national.c 4.1 KB

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  1. /*
  2. * drivers/net/phy/national.c
  3. *
  4. * Driver for National Semiconductor PHYs
  5. *
  6. * Author: Stuart Menefy <stuart.menefy@st.com>
  7. * Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  8. *
  9. * Copyright (c) 2008 STMicroelectronics Limited
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. *
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/kernel.h>
  19. #include <linux/module.h>
  20. #include <linux/mii.h>
  21. #include <linux/ethtool.h>
  22. #include <linux/phy.h>
  23. #include <linux/netdevice.h>
  24. #define DEBUG
  25. /* DP83865 phy identifier values */
  26. #define DP83865_PHY_ID 0x20005c7a
  27. #define DP83865_INT_STATUS 0x14
  28. #define DP83865_INT_MASK 0x15
  29. #define DP83865_INT_CLEAR 0x17
  30. #define DP83865_INT_REMOTE_FAULT 0x0008
  31. #define DP83865_INT_ANE_COMPLETED 0x0010
  32. #define DP83865_INT_LINK_CHANGE 0xe000
  33. #define DP83865_INT_MASK_DEFAULT (DP83865_INT_REMOTE_FAULT | \
  34. DP83865_INT_ANE_COMPLETED | \
  35. DP83865_INT_LINK_CHANGE)
  36. /* Advanced proprietary configuration */
  37. #define NS_EXP_MEM_CTL 0x16
  38. #define NS_EXP_MEM_DATA 0x1d
  39. #define NS_EXP_MEM_ADD 0x1e
  40. #define LED_CTRL_REG 0x13
  41. #define AN_FALLBACK_AN 0x0001
  42. #define AN_FALLBACK_CRC 0x0002
  43. #define AN_FALLBACK_IE 0x0004
  44. #define ALL_FALLBACK_ON (AN_FALLBACK_AN | AN_FALLBACK_CRC | AN_FALLBACK_IE)
  45. enum hdx_loopback {
  46. hdx_loopback_on = 0,
  47. hdx_loopback_off = 1,
  48. };
  49. static u8 ns_exp_read(struct phy_device *phydev, u16 reg)
  50. {
  51. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  52. return phy_read(phydev, NS_EXP_MEM_DATA);
  53. }
  54. static void ns_exp_write(struct phy_device *phydev, u16 reg, u8 data)
  55. {
  56. phy_write(phydev, NS_EXP_MEM_ADD, reg);
  57. phy_write(phydev, NS_EXP_MEM_DATA, data);
  58. }
  59. static int ns_config_intr(struct phy_device *phydev)
  60. {
  61. int err;
  62. if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
  63. err = phy_write(phydev, DP83865_INT_MASK,
  64. DP83865_INT_MASK_DEFAULT);
  65. else
  66. err = phy_write(phydev, DP83865_INT_MASK, 0);
  67. return err;
  68. }
  69. static int ns_ack_interrupt(struct phy_device *phydev)
  70. {
  71. int ret = phy_read(phydev, DP83865_INT_STATUS);
  72. if (ret < 0)
  73. return ret;
  74. /* Clear the interrupt status bit by writing a “1”
  75. * to the corresponding bit in INT_CLEAR (2:0 are reserved) */
  76. ret = phy_write(phydev, DP83865_INT_CLEAR, ret & ~0x7);
  77. return ret;
  78. }
  79. static void ns_giga_speed_fallback(struct phy_device *phydev, int mode)
  80. {
  81. int bmcr = phy_read(phydev, MII_BMCR);
  82. phy_write(phydev, MII_BMCR, (bmcr | BMCR_PDOWN));
  83. /* Enable 8 bit expended memory read/write (no auto increment) */
  84. phy_write(phydev, NS_EXP_MEM_CTL, 0);
  85. phy_write(phydev, NS_EXP_MEM_ADD, 0x1C0);
  86. phy_write(phydev, NS_EXP_MEM_DATA, 0x0008);
  87. phy_write(phydev, MII_BMCR, (bmcr & ~BMCR_PDOWN));
  88. phy_write(phydev, LED_CTRL_REG, mode);
  89. }
  90. static void ns_10_base_t_hdx_loopack(struct phy_device *phydev, int disable)
  91. {
  92. if (disable)
  93. ns_exp_write(phydev, 0x1c0, ns_exp_read(phydev, 0x1c0) | 1);
  94. else
  95. ns_exp_write(phydev, 0x1c0,
  96. ns_exp_read(phydev, 0x1c0) & 0xfffe);
  97. pr_debug("10BASE-T HDX loopback %s\n",
  98. (ns_exp_read(phydev, 0x1c0) & 0x0001) ? "off" : "on");
  99. }
  100. static int ns_config_init(struct phy_device *phydev)
  101. {
  102. ns_giga_speed_fallback(phydev, ALL_FALLBACK_ON);
  103. /* In the latest MAC or switches design, the 10 Mbps loopback
  104. is desired to be turned off. */
  105. ns_10_base_t_hdx_loopack(phydev, hdx_loopback_off);
  106. return ns_ack_interrupt(phydev);
  107. }
  108. static struct phy_driver dp83865_driver[] = { {
  109. .phy_id = DP83865_PHY_ID,
  110. .phy_id_mask = 0xfffffff0,
  111. .name = "NatSemi DP83865",
  112. .features = PHY_GBIT_FEATURES | SUPPORTED_Pause | SUPPORTED_Asym_Pause,
  113. .flags = PHY_HAS_INTERRUPT,
  114. .config_init = ns_config_init,
  115. .config_aneg = genphy_config_aneg,
  116. .read_status = genphy_read_status,
  117. .ack_interrupt = ns_ack_interrupt,
  118. .config_intr = ns_config_intr,
  119. .driver = {.owner = THIS_MODULE,}
  120. } };
  121. module_phy_driver(dp83865_driver);
  122. MODULE_DESCRIPTION("NatSemi PHY driver");
  123. MODULE_AUTHOR("Stuart Menefy");
  124. MODULE_LICENSE("GPL");
  125. static struct mdio_device_id __maybe_unused ns_tbl[] = {
  126. { DP83865_PHY_ID, 0xfffffff0 },
  127. { }
  128. };
  129. MODULE_DEVICE_TABLE(mdio, ns_tbl);