asix_devices.c 29 KB

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  1. /*
  2. * ASIX AX8817X based USB 2.0 Ethernet Devices
  3. * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
  4. * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
  5. * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
  6. * Copyright (c) 2002-2003 TiVo Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  20. */
  21. #include "asix.h"
  22. #define PHY_MODE_MARVELL 0x0000
  23. #define MII_MARVELL_LED_CTRL 0x0018
  24. #define MII_MARVELL_STATUS 0x001b
  25. #define MII_MARVELL_CTRL 0x0014
  26. #define MARVELL_LED_MANUAL 0x0019
  27. #define MARVELL_STATUS_HWCFG 0x0004
  28. #define MARVELL_CTRL_TXDELAY 0x0002
  29. #define MARVELL_CTRL_RXDELAY 0x0080
  30. #define PHY_MODE_RTL8211CL 0x000C
  31. struct ax88172_int_data {
  32. __le16 res1;
  33. u8 link;
  34. __le16 res2;
  35. u8 status;
  36. __le16 res3;
  37. } __packed;
  38. static void asix_status(struct usbnet *dev, struct urb *urb)
  39. {
  40. struct ax88172_int_data *event;
  41. int link;
  42. if (urb->actual_length < 8)
  43. return;
  44. event = urb->transfer_buffer;
  45. link = event->link & 0x01;
  46. if (netif_carrier_ok(dev->net) != link) {
  47. usbnet_link_change(dev, link, 1);
  48. netdev_dbg(dev->net, "Link Status is: %d\n", link);
  49. }
  50. }
  51. static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
  52. {
  53. if (is_valid_ether_addr(addr)) {
  54. memcpy(dev->net->dev_addr, addr, ETH_ALEN);
  55. } else {
  56. netdev_info(dev->net, "invalid hw address, using random\n");
  57. eth_hw_addr_random(dev->net);
  58. }
  59. }
  60. /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
  61. static u32 asix_get_phyid(struct usbnet *dev)
  62. {
  63. int phy_reg;
  64. u32 phy_id;
  65. int i;
  66. /* Poll for the rare case the FW or phy isn't ready yet. */
  67. for (i = 0; i < 100; i++) {
  68. phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
  69. if (phy_reg != 0 && phy_reg != 0xFFFF)
  70. break;
  71. mdelay(1);
  72. }
  73. if (phy_reg <= 0 || phy_reg == 0xFFFF)
  74. return 0;
  75. phy_id = (phy_reg & 0xffff) << 16;
  76. phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
  77. if (phy_reg < 0)
  78. return 0;
  79. phy_id |= (phy_reg & 0xffff);
  80. return phy_id;
  81. }
  82. static u32 asix_get_link(struct net_device *net)
  83. {
  84. struct usbnet *dev = netdev_priv(net);
  85. return mii_link_ok(&dev->mii);
  86. }
  87. static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
  88. {
  89. struct usbnet *dev = netdev_priv(net);
  90. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  91. }
  92. /* We need to override some ethtool_ops so we require our
  93. own structure so we don't interfere with other usbnet
  94. devices that may be connected at the same time. */
  95. static const struct ethtool_ops ax88172_ethtool_ops = {
  96. .get_drvinfo = asix_get_drvinfo,
  97. .get_link = asix_get_link,
  98. .get_msglevel = usbnet_get_msglevel,
  99. .set_msglevel = usbnet_set_msglevel,
  100. .get_wol = asix_get_wol,
  101. .set_wol = asix_set_wol,
  102. .get_eeprom_len = asix_get_eeprom_len,
  103. .get_eeprom = asix_get_eeprom,
  104. .set_eeprom = asix_set_eeprom,
  105. .get_settings = usbnet_get_settings,
  106. .set_settings = usbnet_set_settings,
  107. .nway_reset = usbnet_nway_reset,
  108. };
  109. static void ax88172_set_multicast(struct net_device *net)
  110. {
  111. struct usbnet *dev = netdev_priv(net);
  112. struct asix_data *data = (struct asix_data *)&dev->data;
  113. u8 rx_ctl = 0x8c;
  114. if (net->flags & IFF_PROMISC) {
  115. rx_ctl |= 0x01;
  116. } else if (net->flags & IFF_ALLMULTI ||
  117. netdev_mc_count(net) > AX_MAX_MCAST) {
  118. rx_ctl |= 0x02;
  119. } else if (netdev_mc_empty(net)) {
  120. /* just broadcast and directed */
  121. } else {
  122. /* We use the 20 byte dev->data
  123. * for our 8 byte filter buffer
  124. * to avoid allocating memory that
  125. * is tricky to free later */
  126. struct netdev_hw_addr *ha;
  127. u32 crc_bits;
  128. memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
  129. /* Build the multicast hash filter. */
  130. netdev_for_each_mc_addr(ha, net) {
  131. crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
  132. data->multi_filter[crc_bits >> 3] |=
  133. 1 << (crc_bits & 7);
  134. }
  135. asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
  136. AX_MCAST_FILTER_SIZE, data->multi_filter);
  137. rx_ctl |= 0x10;
  138. }
  139. asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
  140. }
  141. static int ax88172_link_reset(struct usbnet *dev)
  142. {
  143. u8 mode;
  144. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  145. mii_check_media(&dev->mii, 1, 1);
  146. mii_ethtool_gset(&dev->mii, &ecmd);
  147. mode = AX88172_MEDIUM_DEFAULT;
  148. if (ecmd.duplex != DUPLEX_FULL)
  149. mode |= ~AX88172_MEDIUM_FD;
  150. netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  151. ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
  152. asix_write_medium_mode(dev, mode);
  153. return 0;
  154. }
  155. static const struct net_device_ops ax88172_netdev_ops = {
  156. .ndo_open = usbnet_open,
  157. .ndo_stop = usbnet_stop,
  158. .ndo_start_xmit = usbnet_start_xmit,
  159. .ndo_tx_timeout = usbnet_tx_timeout,
  160. .ndo_change_mtu = usbnet_change_mtu,
  161. .ndo_set_mac_address = eth_mac_addr,
  162. .ndo_validate_addr = eth_validate_addr,
  163. .ndo_do_ioctl = asix_ioctl,
  164. .ndo_set_rx_mode = ax88172_set_multicast,
  165. };
  166. static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
  167. {
  168. int ret = 0;
  169. u8 buf[ETH_ALEN];
  170. int i;
  171. unsigned long gpio_bits = dev->driver_info->data;
  172. usbnet_get_endpoints(dev,intf);
  173. /* Toggle the GPIOs in a manufacturer/model specific way */
  174. for (i = 2; i >= 0; i--) {
  175. ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
  176. (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL);
  177. if (ret < 0)
  178. goto out;
  179. msleep(5);
  180. }
  181. ret = asix_write_rx_ctl(dev, 0x80);
  182. if (ret < 0)
  183. goto out;
  184. /* Get the MAC address */
  185. ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  186. if (ret < 0) {
  187. netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
  188. ret);
  189. goto out;
  190. }
  191. asix_set_netdev_dev_addr(dev, buf);
  192. /* Initialize MII structure */
  193. dev->mii.dev = dev->net;
  194. dev->mii.mdio_read = asix_mdio_read;
  195. dev->mii.mdio_write = asix_mdio_write;
  196. dev->mii.phy_id_mask = 0x3f;
  197. dev->mii.reg_num_mask = 0x1f;
  198. dev->mii.phy_id = asix_get_phy_addr(dev);
  199. dev->net->netdev_ops = &ax88172_netdev_ops;
  200. dev->net->ethtool_ops = &ax88172_ethtool_ops;
  201. dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
  202. dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
  203. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  204. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  205. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  206. mii_nway_restart(&dev->mii);
  207. return 0;
  208. out:
  209. return ret;
  210. }
  211. static const struct ethtool_ops ax88772_ethtool_ops = {
  212. .get_drvinfo = asix_get_drvinfo,
  213. .get_link = asix_get_link,
  214. .get_msglevel = usbnet_get_msglevel,
  215. .set_msglevel = usbnet_set_msglevel,
  216. .get_wol = asix_get_wol,
  217. .set_wol = asix_set_wol,
  218. .get_eeprom_len = asix_get_eeprom_len,
  219. .get_eeprom = asix_get_eeprom,
  220. .set_eeprom = asix_set_eeprom,
  221. .get_settings = usbnet_get_settings,
  222. .set_settings = usbnet_set_settings,
  223. .nway_reset = usbnet_nway_reset,
  224. };
  225. static int ax88772_link_reset(struct usbnet *dev)
  226. {
  227. u16 mode;
  228. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  229. mii_check_media(&dev->mii, 1, 1);
  230. mii_ethtool_gset(&dev->mii, &ecmd);
  231. mode = AX88772_MEDIUM_DEFAULT;
  232. if (ethtool_cmd_speed(&ecmd) != SPEED_100)
  233. mode &= ~AX_MEDIUM_PS;
  234. if (ecmd.duplex != DUPLEX_FULL)
  235. mode &= ~AX_MEDIUM_FD;
  236. netdev_dbg(dev->net, "ax88772_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  237. ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
  238. asix_write_medium_mode(dev, mode);
  239. return 0;
  240. }
  241. static int ax88772_reset(struct usbnet *dev)
  242. {
  243. struct asix_data *data = (struct asix_data *)&dev->data;
  244. int ret, embd_phy;
  245. u16 rx_ctl;
  246. ret = asix_write_gpio(dev,
  247. AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
  248. if (ret < 0)
  249. goto out;
  250. embd_phy = ((asix_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0);
  251. ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
  252. if (ret < 0) {
  253. netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
  254. goto out;
  255. }
  256. ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL);
  257. if (ret < 0)
  258. goto out;
  259. msleep(150);
  260. ret = asix_sw_reset(dev, AX_SWRESET_CLEAR);
  261. if (ret < 0)
  262. goto out;
  263. msleep(150);
  264. if (embd_phy) {
  265. ret = asix_sw_reset(dev, AX_SWRESET_IPRL);
  266. if (ret < 0)
  267. goto out;
  268. } else {
  269. ret = asix_sw_reset(dev, AX_SWRESET_PRTE);
  270. if (ret < 0)
  271. goto out;
  272. }
  273. msleep(150);
  274. rx_ctl = asix_read_rx_ctl(dev);
  275. netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl);
  276. ret = asix_write_rx_ctl(dev, 0x0000);
  277. if (ret < 0)
  278. goto out;
  279. rx_ctl = asix_read_rx_ctl(dev);
  280. netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl);
  281. ret = asix_sw_reset(dev, AX_SWRESET_PRL);
  282. if (ret < 0)
  283. goto out;
  284. msleep(150);
  285. ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL);
  286. if (ret < 0)
  287. goto out;
  288. msleep(150);
  289. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  290. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  291. ADVERTISE_ALL | ADVERTISE_CSMA);
  292. mii_nway_restart(&dev->mii);
  293. ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT);
  294. if (ret < 0)
  295. goto out;
  296. ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
  297. AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
  298. AX88772_IPG2_DEFAULT, 0, NULL);
  299. if (ret < 0) {
  300. netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
  301. goto out;
  302. }
  303. /* Rewrite MAC address */
  304. memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
  305. ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
  306. data->mac_addr);
  307. if (ret < 0)
  308. goto out;
  309. /* Set RX_CTL to default values with 2k buffer, and enable cactus */
  310. ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
  311. if (ret < 0)
  312. goto out;
  313. rx_ctl = asix_read_rx_ctl(dev);
  314. netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
  315. rx_ctl);
  316. rx_ctl = asix_read_medium_status(dev);
  317. netdev_dbg(dev->net,
  318. "Medium Status is 0x%04x after all initializations\n",
  319. rx_ctl);
  320. return 0;
  321. out:
  322. return ret;
  323. }
  324. static const struct net_device_ops ax88772_netdev_ops = {
  325. .ndo_open = usbnet_open,
  326. .ndo_stop = usbnet_stop,
  327. .ndo_start_xmit = usbnet_start_xmit,
  328. .ndo_tx_timeout = usbnet_tx_timeout,
  329. .ndo_change_mtu = usbnet_change_mtu,
  330. .ndo_set_mac_address = asix_set_mac_address,
  331. .ndo_validate_addr = eth_validate_addr,
  332. .ndo_do_ioctl = asix_ioctl,
  333. .ndo_set_rx_mode = asix_set_multicast,
  334. };
  335. static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
  336. {
  337. int ret, embd_phy, i;
  338. u8 buf[ETH_ALEN];
  339. u32 phyid;
  340. usbnet_get_endpoints(dev,intf);
  341. /* Get the MAC address */
  342. if (dev->driver_info->data & FLAG_EEPROM_MAC) {
  343. for (i = 0; i < (ETH_ALEN >> 1); i++) {
  344. ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x04 + i,
  345. 0, 2, buf + i * 2);
  346. if (ret < 0)
  347. break;
  348. }
  349. } else {
  350. ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
  351. 0, 0, ETH_ALEN, buf);
  352. }
  353. if (ret < 0) {
  354. netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
  355. return ret;
  356. }
  357. asix_set_netdev_dev_addr(dev, buf);
  358. /* Initialize MII structure */
  359. dev->mii.dev = dev->net;
  360. dev->mii.mdio_read = asix_mdio_read;
  361. dev->mii.mdio_write = asix_mdio_write;
  362. dev->mii.phy_id_mask = 0x1f;
  363. dev->mii.reg_num_mask = 0x1f;
  364. dev->mii.phy_id = asix_get_phy_addr(dev);
  365. dev->net->netdev_ops = &ax88772_netdev_ops;
  366. dev->net->ethtool_ops = &ax88772_ethtool_ops;
  367. dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
  368. dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
  369. embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);
  370. /* Reset the PHY to normal operation mode */
  371. ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL);
  372. if (ret < 0) {
  373. netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
  374. return ret;
  375. }
  376. ax88772_reset(dev);
  377. /* Read PHYID register *AFTER* the PHY was reset properly */
  378. phyid = asix_get_phyid(dev);
  379. netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
  380. /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
  381. if (dev->driver_info->flags & FLAG_FRAMING_AX) {
  382. /* hard_mtu is still the default - the device does not support
  383. jumbo eth frames */
  384. dev->rx_urb_size = 2048;
  385. }
  386. dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
  387. if (!dev->driver_priv)
  388. return -ENOMEM;
  389. return 0;
  390. }
  391. static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
  392. {
  393. kfree(dev->driver_priv);
  394. }
  395. static const struct ethtool_ops ax88178_ethtool_ops = {
  396. .get_drvinfo = asix_get_drvinfo,
  397. .get_link = asix_get_link,
  398. .get_msglevel = usbnet_get_msglevel,
  399. .set_msglevel = usbnet_set_msglevel,
  400. .get_wol = asix_get_wol,
  401. .set_wol = asix_set_wol,
  402. .get_eeprom_len = asix_get_eeprom_len,
  403. .get_eeprom = asix_get_eeprom,
  404. .set_eeprom = asix_set_eeprom,
  405. .get_settings = usbnet_get_settings,
  406. .set_settings = usbnet_set_settings,
  407. .nway_reset = usbnet_nway_reset,
  408. };
  409. static int marvell_phy_init(struct usbnet *dev)
  410. {
  411. struct asix_data *data = (struct asix_data *)&dev->data;
  412. u16 reg;
  413. netdev_dbg(dev->net, "marvell_phy_init()\n");
  414. reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
  415. netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
  416. asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
  417. MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
  418. if (data->ledmode) {
  419. reg = asix_mdio_read(dev->net, dev->mii.phy_id,
  420. MII_MARVELL_LED_CTRL);
  421. netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
  422. reg &= 0xf8ff;
  423. reg |= (1 + 0x0100);
  424. asix_mdio_write(dev->net, dev->mii.phy_id,
  425. MII_MARVELL_LED_CTRL, reg);
  426. reg = asix_mdio_read(dev->net, dev->mii.phy_id,
  427. MII_MARVELL_LED_CTRL);
  428. netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
  429. reg &= 0xfc0f;
  430. }
  431. return 0;
  432. }
  433. static int rtl8211cl_phy_init(struct usbnet *dev)
  434. {
  435. struct asix_data *data = (struct asix_data *)&dev->data;
  436. netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
  437. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
  438. asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
  439. asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
  440. asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
  441. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
  442. if (data->ledmode == 12) {
  443. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
  444. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
  445. asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
  446. }
  447. return 0;
  448. }
  449. static int marvell_led_status(struct usbnet *dev, u16 speed)
  450. {
  451. u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
  452. netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
  453. /* Clear out the center LED bits - 0x03F0 */
  454. reg &= 0xfc0f;
  455. switch (speed) {
  456. case SPEED_1000:
  457. reg |= 0x03e0;
  458. break;
  459. case SPEED_100:
  460. reg |= 0x03b0;
  461. break;
  462. default:
  463. reg |= 0x02f0;
  464. }
  465. netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
  466. asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
  467. return 0;
  468. }
  469. static int ax88178_reset(struct usbnet *dev)
  470. {
  471. struct asix_data *data = (struct asix_data *)&dev->data;
  472. int ret;
  473. __le16 eeprom;
  474. u8 status;
  475. int gpio0 = 0;
  476. u32 phyid;
  477. asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status);
  478. netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
  479. asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL);
  480. asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom);
  481. asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL);
  482. netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
  483. if (eeprom == cpu_to_le16(0xffff)) {
  484. data->phymode = PHY_MODE_MARVELL;
  485. data->ledmode = 0;
  486. gpio0 = 1;
  487. } else {
  488. data->phymode = le16_to_cpu(eeprom) & 0x7F;
  489. data->ledmode = le16_to_cpu(eeprom) >> 8;
  490. gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
  491. }
  492. netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
  493. /* Power up external GigaPHY through AX88178 GPIO pin */
  494. asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 | AX_GPIO_GPO1EN, 40);
  495. if ((le16_to_cpu(eeprom) >> 8) != 1) {
  496. asix_write_gpio(dev, 0x003c, 30);
  497. asix_write_gpio(dev, 0x001c, 300);
  498. asix_write_gpio(dev, 0x003c, 30);
  499. } else {
  500. netdev_dbg(dev->net, "gpio phymode == 1 path\n");
  501. asix_write_gpio(dev, AX_GPIO_GPO1EN, 30);
  502. asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30);
  503. }
  504. /* Read PHYID register *AFTER* powering up PHY */
  505. phyid = asix_get_phyid(dev);
  506. netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
  507. /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
  508. asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL);
  509. asix_sw_reset(dev, 0);
  510. msleep(150);
  511. asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
  512. msleep(150);
  513. asix_write_rx_ctl(dev, 0);
  514. if (data->phymode == PHY_MODE_MARVELL) {
  515. marvell_phy_init(dev);
  516. msleep(60);
  517. } else if (data->phymode == PHY_MODE_RTL8211CL)
  518. rtl8211cl_phy_init(dev);
  519. asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR,
  520. BMCR_RESET | BMCR_ANENABLE);
  521. asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  522. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
  523. asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
  524. ADVERTISE_1000FULL);
  525. mii_nway_restart(&dev->mii);
  526. ret = asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT);
  527. if (ret < 0)
  528. return ret;
  529. /* Rewrite MAC address */
  530. memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
  531. ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
  532. data->mac_addr);
  533. if (ret < 0)
  534. return ret;
  535. ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL);
  536. if (ret < 0)
  537. return ret;
  538. return 0;
  539. }
  540. static int ax88178_link_reset(struct usbnet *dev)
  541. {
  542. u16 mode;
  543. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  544. struct asix_data *data = (struct asix_data *)&dev->data;
  545. u32 speed;
  546. netdev_dbg(dev->net, "ax88178_link_reset()\n");
  547. mii_check_media(&dev->mii, 1, 1);
  548. mii_ethtool_gset(&dev->mii, &ecmd);
  549. mode = AX88178_MEDIUM_DEFAULT;
  550. speed = ethtool_cmd_speed(&ecmd);
  551. if (speed == SPEED_1000)
  552. mode |= AX_MEDIUM_GM;
  553. else if (speed == SPEED_100)
  554. mode |= AX_MEDIUM_PS;
  555. else
  556. mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
  557. mode |= AX_MEDIUM_ENCK;
  558. if (ecmd.duplex == DUPLEX_FULL)
  559. mode |= AX_MEDIUM_FD;
  560. else
  561. mode &= ~AX_MEDIUM_FD;
  562. netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
  563. speed, ecmd.duplex, mode);
  564. asix_write_medium_mode(dev, mode);
  565. if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
  566. marvell_led_status(dev, speed);
  567. return 0;
  568. }
  569. static void ax88178_set_mfb(struct usbnet *dev)
  570. {
  571. u16 mfb = AX_RX_CTL_MFB_16384;
  572. u16 rxctl;
  573. u16 medium;
  574. int old_rx_urb_size = dev->rx_urb_size;
  575. if (dev->hard_mtu < 2048) {
  576. dev->rx_urb_size = 2048;
  577. mfb = AX_RX_CTL_MFB_2048;
  578. } else if (dev->hard_mtu < 4096) {
  579. dev->rx_urb_size = 4096;
  580. mfb = AX_RX_CTL_MFB_4096;
  581. } else if (dev->hard_mtu < 8192) {
  582. dev->rx_urb_size = 8192;
  583. mfb = AX_RX_CTL_MFB_8192;
  584. } else if (dev->hard_mtu < 16384) {
  585. dev->rx_urb_size = 16384;
  586. mfb = AX_RX_CTL_MFB_16384;
  587. }
  588. rxctl = asix_read_rx_ctl(dev);
  589. asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb);
  590. medium = asix_read_medium_status(dev);
  591. if (dev->net->mtu > 1500)
  592. medium |= AX_MEDIUM_JFE;
  593. else
  594. medium &= ~AX_MEDIUM_JFE;
  595. asix_write_medium_mode(dev, medium);
  596. if (dev->rx_urb_size > old_rx_urb_size)
  597. usbnet_unlink_rx_urbs(dev);
  598. }
  599. static int ax88178_change_mtu(struct net_device *net, int new_mtu)
  600. {
  601. struct usbnet *dev = netdev_priv(net);
  602. int ll_mtu = new_mtu + net->hard_header_len + 4;
  603. netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
  604. if (new_mtu <= 0 || ll_mtu > 16384)
  605. return -EINVAL;
  606. if ((ll_mtu % dev->maxpacket) == 0)
  607. return -EDOM;
  608. net->mtu = new_mtu;
  609. dev->hard_mtu = net->mtu + net->hard_header_len;
  610. ax88178_set_mfb(dev);
  611. /* max qlen depend on hard_mtu and rx_urb_size */
  612. usbnet_update_max_qlen(dev);
  613. return 0;
  614. }
  615. static const struct net_device_ops ax88178_netdev_ops = {
  616. .ndo_open = usbnet_open,
  617. .ndo_stop = usbnet_stop,
  618. .ndo_start_xmit = usbnet_start_xmit,
  619. .ndo_tx_timeout = usbnet_tx_timeout,
  620. .ndo_set_mac_address = asix_set_mac_address,
  621. .ndo_validate_addr = eth_validate_addr,
  622. .ndo_set_rx_mode = asix_set_multicast,
  623. .ndo_do_ioctl = asix_ioctl,
  624. .ndo_change_mtu = ax88178_change_mtu,
  625. };
  626. static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
  627. {
  628. int ret;
  629. u8 buf[ETH_ALEN];
  630. usbnet_get_endpoints(dev,intf);
  631. /* Get the MAC address */
  632. ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf);
  633. if (ret < 0) {
  634. netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
  635. return ret;
  636. }
  637. asix_set_netdev_dev_addr(dev, buf);
  638. /* Initialize MII structure */
  639. dev->mii.dev = dev->net;
  640. dev->mii.mdio_read = asix_mdio_read;
  641. dev->mii.mdio_write = asix_mdio_write;
  642. dev->mii.phy_id_mask = 0x1f;
  643. dev->mii.reg_num_mask = 0xff;
  644. dev->mii.supports_gmii = 1;
  645. dev->mii.phy_id = asix_get_phy_addr(dev);
  646. dev->net->netdev_ops = &ax88178_netdev_ops;
  647. dev->net->ethtool_ops = &ax88178_ethtool_ops;
  648. /* Blink LEDS so users know driver saw dongle */
  649. asix_sw_reset(dev, 0);
  650. msleep(150);
  651. asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD);
  652. msleep(150);
  653. /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
  654. if (dev->driver_info->flags & FLAG_FRAMING_AX) {
  655. /* hard_mtu is still the default - the device does not support
  656. jumbo eth frames */
  657. dev->rx_urb_size = 2048;
  658. }
  659. dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
  660. if (!dev->driver_priv)
  661. return -ENOMEM;
  662. return 0;
  663. }
  664. static const struct driver_info ax8817x_info = {
  665. .description = "ASIX AX8817x USB 2.0 Ethernet",
  666. .bind = ax88172_bind,
  667. .status = asix_status,
  668. .link_reset = ax88172_link_reset,
  669. .reset = ax88172_link_reset,
  670. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  671. .data = 0x00130103,
  672. };
  673. static const struct driver_info dlink_dub_e100_info = {
  674. .description = "DLink DUB-E100 USB Ethernet",
  675. .bind = ax88172_bind,
  676. .status = asix_status,
  677. .link_reset = ax88172_link_reset,
  678. .reset = ax88172_link_reset,
  679. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  680. .data = 0x009f9d9f,
  681. };
  682. static const struct driver_info netgear_fa120_info = {
  683. .description = "Netgear FA-120 USB Ethernet",
  684. .bind = ax88172_bind,
  685. .status = asix_status,
  686. .link_reset = ax88172_link_reset,
  687. .reset = ax88172_link_reset,
  688. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  689. .data = 0x00130103,
  690. };
  691. static const struct driver_info hawking_uf200_info = {
  692. .description = "Hawking UF200 USB Ethernet",
  693. .bind = ax88172_bind,
  694. .status = asix_status,
  695. .link_reset = ax88172_link_reset,
  696. .reset = ax88172_link_reset,
  697. .flags = FLAG_ETHER | FLAG_LINK_INTR,
  698. .data = 0x001f1d1f,
  699. };
  700. static const struct driver_info ax88772_info = {
  701. .description = "ASIX AX88772 USB 2.0 Ethernet",
  702. .bind = ax88772_bind,
  703. .unbind = ax88772_unbind,
  704. .status = asix_status,
  705. .link_reset = ax88772_link_reset,
  706. .reset = ax88772_link_reset,
  707. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
  708. .rx_fixup = asix_rx_fixup_common,
  709. .tx_fixup = asix_tx_fixup,
  710. };
  711. static const struct driver_info ax88772b_info = {
  712. .description = "ASIX AX88772B USB 2.0 Ethernet",
  713. .bind = ax88772_bind,
  714. .unbind = ax88772_unbind,
  715. .status = asix_status,
  716. .link_reset = ax88772_link_reset,
  717. .reset = ax88772_reset,
  718. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
  719. FLAG_MULTI_PACKET,
  720. .rx_fixup = asix_rx_fixup_common,
  721. .tx_fixup = asix_tx_fixup,
  722. .data = FLAG_EEPROM_MAC,
  723. };
  724. static const struct driver_info ax88178_info = {
  725. .description = "ASIX AX88178 USB 2.0 Ethernet",
  726. .bind = ax88178_bind,
  727. .unbind = ax88772_unbind,
  728. .status = asix_status,
  729. .link_reset = ax88178_link_reset,
  730. .reset = ax88178_reset,
  731. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
  732. FLAG_MULTI_PACKET,
  733. .rx_fixup = asix_rx_fixup_common,
  734. .tx_fixup = asix_tx_fixup,
  735. };
  736. /*
  737. * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
  738. * no-name packaging.
  739. * USB device strings are:
  740. * 1: Manufacturer: USBLINK
  741. * 2: Product: HG20F9 USB2.0
  742. * 3: Serial: 000003
  743. * Appears to be compatible with Asix 88772B.
  744. */
  745. static const struct driver_info hg20f9_info = {
  746. .description = "HG20F9 USB 2.0 Ethernet",
  747. .bind = ax88772_bind,
  748. .unbind = ax88772_unbind,
  749. .status = asix_status,
  750. .link_reset = ax88772_link_reset,
  751. .reset = ax88772_reset,
  752. .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
  753. FLAG_MULTI_PACKET,
  754. .rx_fixup = asix_rx_fixup_common,
  755. .tx_fixup = asix_tx_fixup,
  756. .data = FLAG_EEPROM_MAC,
  757. };
  758. static const struct usb_device_id products [] = {
  759. {
  760. // Linksys USB200M
  761. USB_DEVICE (0x077b, 0x2226),
  762. .driver_info = (unsigned long) &ax8817x_info,
  763. }, {
  764. // Netgear FA120
  765. USB_DEVICE (0x0846, 0x1040),
  766. .driver_info = (unsigned long) &netgear_fa120_info,
  767. }, {
  768. // DLink DUB-E100
  769. USB_DEVICE (0x2001, 0x1a00),
  770. .driver_info = (unsigned long) &dlink_dub_e100_info,
  771. }, {
  772. // Intellinet, ST Lab USB Ethernet
  773. USB_DEVICE (0x0b95, 0x1720),
  774. .driver_info = (unsigned long) &ax8817x_info,
  775. }, {
  776. // Hawking UF200, TrendNet TU2-ET100
  777. USB_DEVICE (0x07b8, 0x420a),
  778. .driver_info = (unsigned long) &hawking_uf200_info,
  779. }, {
  780. // Billionton Systems, USB2AR
  781. USB_DEVICE (0x08dd, 0x90ff),
  782. .driver_info = (unsigned long) &ax8817x_info,
  783. }, {
  784. // Billionton Systems, GUSB2AM-1G-B
  785. USB_DEVICE(0x08dd, 0x0114),
  786. .driver_info = (unsigned long) &ax88178_info,
  787. }, {
  788. // ATEN UC210T
  789. USB_DEVICE (0x0557, 0x2009),
  790. .driver_info = (unsigned long) &ax8817x_info,
  791. }, {
  792. // Buffalo LUA-U2-KTX
  793. USB_DEVICE (0x0411, 0x003d),
  794. .driver_info = (unsigned long) &ax8817x_info,
  795. }, {
  796. // Buffalo LUA-U2-GT 10/100/1000
  797. USB_DEVICE (0x0411, 0x006e),
  798. .driver_info = (unsigned long) &ax88178_info,
  799. }, {
  800. // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
  801. USB_DEVICE (0x6189, 0x182d),
  802. .driver_info = (unsigned long) &ax8817x_info,
  803. }, {
  804. // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
  805. USB_DEVICE (0x0df6, 0x0056),
  806. .driver_info = (unsigned long) &ax88178_info,
  807. }, {
  808. // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
  809. USB_DEVICE (0x0df6, 0x061c),
  810. .driver_info = (unsigned long) &ax88178_info,
  811. }, {
  812. // corega FEther USB2-TX
  813. USB_DEVICE (0x07aa, 0x0017),
  814. .driver_info = (unsigned long) &ax8817x_info,
  815. }, {
  816. // Surecom EP-1427X-2
  817. USB_DEVICE (0x1189, 0x0893),
  818. .driver_info = (unsigned long) &ax8817x_info,
  819. }, {
  820. // goodway corp usb gwusb2e
  821. USB_DEVICE (0x1631, 0x6200),
  822. .driver_info = (unsigned long) &ax8817x_info,
  823. }, {
  824. // JVC MP-PRX1 Port Replicator
  825. USB_DEVICE (0x04f1, 0x3008),
  826. .driver_info = (unsigned long) &ax8817x_info,
  827. }, {
  828. // Lenovo U2L100P 10/100
  829. USB_DEVICE (0x17ef, 0x7203),
  830. .driver_info = (unsigned long) &ax88772_info,
  831. }, {
  832. // ASIX AX88772B 10/100
  833. USB_DEVICE (0x0b95, 0x772b),
  834. .driver_info = (unsigned long) &ax88772b_info,
  835. }, {
  836. // ASIX AX88772 10/100
  837. USB_DEVICE (0x0b95, 0x7720),
  838. .driver_info = (unsigned long) &ax88772_info,
  839. }, {
  840. // ASIX AX88178 10/100/1000
  841. USB_DEVICE (0x0b95, 0x1780),
  842. .driver_info = (unsigned long) &ax88178_info,
  843. }, {
  844. // Logitec LAN-GTJ/U2A
  845. USB_DEVICE (0x0789, 0x0160),
  846. .driver_info = (unsigned long) &ax88178_info,
  847. }, {
  848. // Linksys USB200M Rev 2
  849. USB_DEVICE (0x13b1, 0x0018),
  850. .driver_info = (unsigned long) &ax88772_info,
  851. }, {
  852. // 0Q0 cable ethernet
  853. USB_DEVICE (0x1557, 0x7720),
  854. .driver_info = (unsigned long) &ax88772_info,
  855. }, {
  856. // DLink DUB-E100 H/W Ver B1
  857. USB_DEVICE (0x07d1, 0x3c05),
  858. .driver_info = (unsigned long) &ax88772_info,
  859. }, {
  860. // DLink DUB-E100 H/W Ver B1 Alternate
  861. USB_DEVICE (0x2001, 0x3c05),
  862. .driver_info = (unsigned long) &ax88772_info,
  863. }, {
  864. // DLink DUB-E100 H/W Ver C1
  865. USB_DEVICE (0x2001, 0x1a02),
  866. .driver_info = (unsigned long) &ax88772_info,
  867. }, {
  868. // Linksys USB1000
  869. USB_DEVICE (0x1737, 0x0039),
  870. .driver_info = (unsigned long) &ax88178_info,
  871. }, {
  872. // IO-DATA ETG-US2
  873. USB_DEVICE (0x04bb, 0x0930),
  874. .driver_info = (unsigned long) &ax88178_info,
  875. }, {
  876. // Belkin F5D5055
  877. USB_DEVICE(0x050d, 0x5055),
  878. .driver_info = (unsigned long) &ax88178_info,
  879. }, {
  880. // Apple USB Ethernet Adapter
  881. USB_DEVICE(0x05ac, 0x1402),
  882. .driver_info = (unsigned long) &ax88772_info,
  883. }, {
  884. // Cables-to-Go USB Ethernet Adapter
  885. USB_DEVICE(0x0b95, 0x772a),
  886. .driver_info = (unsigned long) &ax88772_info,
  887. }, {
  888. // ABOCOM for pci
  889. USB_DEVICE(0x14ea, 0xab11),
  890. .driver_info = (unsigned long) &ax88178_info,
  891. }, {
  892. // ASIX 88772a
  893. USB_DEVICE(0x0db0, 0xa877),
  894. .driver_info = (unsigned long) &ax88772_info,
  895. }, {
  896. // Asus USB Ethernet Adapter
  897. USB_DEVICE (0x0b95, 0x7e2b),
  898. .driver_info = (unsigned long) &ax88772_info,
  899. }, {
  900. /* ASIX 88172a demo board */
  901. USB_DEVICE(0x0b95, 0x172a),
  902. .driver_info = (unsigned long) &ax88172a_info,
  903. }, {
  904. /*
  905. * USBLINK HG20F9 "USB 2.0 LAN"
  906. * Appears to have gazumped Linksys's manufacturer ID but
  907. * doesn't (yet) conflict with any known Linksys product.
  908. */
  909. USB_DEVICE(0x066b, 0x20f9),
  910. .driver_info = (unsigned long) &hg20f9_info,
  911. },
  912. { }, // END
  913. };
  914. MODULE_DEVICE_TABLE(usb, products);
  915. static struct usb_driver asix_driver = {
  916. .name = DRIVER_NAME,
  917. .id_table = products,
  918. .probe = usbnet_probe,
  919. .suspend = usbnet_suspend,
  920. .resume = usbnet_resume,
  921. .disconnect = usbnet_disconnect,
  922. .supports_autosuspend = 1,
  923. .disable_hub_initiated_lpm = 1,
  924. };
  925. module_usb_driver(asix_driver);
  926. MODULE_AUTHOR("David Hollis");
  927. MODULE_VERSION(DRIVER_VERSION);
  928. MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
  929. MODULE_LICENSE("GPL");