ax88179_178a.c 44 KB

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  1. /*
  2. * ASIX AX88179/178A USB 3.0/2.0 to Gigabit Ethernet Devices
  3. *
  4. * Copyright (C) 2011-2013 ASIX
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version 2
  9. * of the License, or (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #include <linux/module.h>
  20. #include <linux/etherdevice.h>
  21. #include <linux/mii.h>
  22. #include <linux/usb.h>
  23. #include <linux/crc32.h>
  24. #include <linux/usb/usbnet.h>
  25. #include <uapi/linux/mdio.h>
  26. #include <linux/mdio.h>
  27. #define AX88179_PHY_ID 0x03
  28. #define AX_EEPROM_LEN 0x100
  29. #define AX88179_EEPROM_MAGIC 0x17900b95
  30. #define AX_MCAST_FLTSIZE 8
  31. #define AX_MAX_MCAST 64
  32. #define AX_INT_PPLS_LINK ((u32)BIT(16))
  33. #define AX_RXHDR_L4_TYPE_MASK 0x1c
  34. #define AX_RXHDR_L4_TYPE_UDP 4
  35. #define AX_RXHDR_L4_TYPE_TCP 16
  36. #define AX_RXHDR_L3CSUM_ERR 2
  37. #define AX_RXHDR_L4CSUM_ERR 1
  38. #define AX_RXHDR_CRC_ERR ((u32)BIT(29))
  39. #define AX_RXHDR_DROP_ERR ((u32)BIT(31))
  40. #define AX_ACCESS_MAC 0x01
  41. #define AX_ACCESS_PHY 0x02
  42. #define AX_ACCESS_EEPROM 0x04
  43. #define AX_ACCESS_EFUS 0x05
  44. #define AX_PAUSE_WATERLVL_HIGH 0x54
  45. #define AX_PAUSE_WATERLVL_LOW 0x55
  46. #define PHYSICAL_LINK_STATUS 0x02
  47. #define AX_USB_SS 0x04
  48. #define AX_USB_HS 0x02
  49. #define GENERAL_STATUS 0x03
  50. /* Check AX88179 version. UA1:Bit2 = 0, UA2:Bit2 = 1 */
  51. #define AX_SECLD 0x04
  52. #define AX_SROM_ADDR 0x07
  53. #define AX_SROM_CMD 0x0a
  54. #define EEP_RD 0x04
  55. #define EEP_BUSY 0x10
  56. #define AX_SROM_DATA_LOW 0x08
  57. #define AX_SROM_DATA_HIGH 0x09
  58. #define AX_RX_CTL 0x0b
  59. #define AX_RX_CTL_DROPCRCERR 0x0100
  60. #define AX_RX_CTL_IPE 0x0200
  61. #define AX_RX_CTL_START 0x0080
  62. #define AX_RX_CTL_AP 0x0020
  63. #define AX_RX_CTL_AM 0x0010
  64. #define AX_RX_CTL_AB 0x0008
  65. #define AX_RX_CTL_AMALL 0x0002
  66. #define AX_RX_CTL_PRO 0x0001
  67. #define AX_RX_CTL_STOP 0x0000
  68. #define AX_NODE_ID 0x10
  69. #define AX_MULFLTARY 0x16
  70. #define AX_MEDIUM_STATUS_MODE 0x22
  71. #define AX_MEDIUM_GIGAMODE 0x01
  72. #define AX_MEDIUM_FULL_DUPLEX 0x02
  73. #define AX_MEDIUM_EN_125MHZ 0x08
  74. #define AX_MEDIUM_RXFLOW_CTRLEN 0x10
  75. #define AX_MEDIUM_TXFLOW_CTRLEN 0x20
  76. #define AX_MEDIUM_RECEIVE_EN 0x100
  77. #define AX_MEDIUM_PS 0x200
  78. #define AX_MEDIUM_JUMBO_EN 0x8040
  79. #define AX_MONITOR_MOD 0x24
  80. #define AX_MONITOR_MODE_RWLC 0x02
  81. #define AX_MONITOR_MODE_RWMP 0x04
  82. #define AX_MONITOR_MODE_PMEPOL 0x20
  83. #define AX_MONITOR_MODE_PMETYPE 0x40
  84. #define AX_GPIO_CTRL 0x25
  85. #define AX_GPIO_CTRL_GPIO3EN 0x80
  86. #define AX_GPIO_CTRL_GPIO2EN 0x40
  87. #define AX_GPIO_CTRL_GPIO1EN 0x20
  88. #define AX_PHYPWR_RSTCTL 0x26
  89. #define AX_PHYPWR_RSTCTL_BZ 0x0010
  90. #define AX_PHYPWR_RSTCTL_IPRL 0x0020
  91. #define AX_PHYPWR_RSTCTL_AT 0x1000
  92. #define AX_RX_BULKIN_QCTRL 0x2e
  93. #define AX_CLK_SELECT 0x33
  94. #define AX_CLK_SELECT_BCS 0x01
  95. #define AX_CLK_SELECT_ACS 0x02
  96. #define AX_CLK_SELECT_ULR 0x08
  97. #define AX_RXCOE_CTL 0x34
  98. #define AX_RXCOE_IP 0x01
  99. #define AX_RXCOE_TCP 0x02
  100. #define AX_RXCOE_UDP 0x04
  101. #define AX_RXCOE_TCPV6 0x20
  102. #define AX_RXCOE_UDPV6 0x40
  103. #define AX_TXCOE_CTL 0x35
  104. #define AX_TXCOE_IP 0x01
  105. #define AX_TXCOE_TCP 0x02
  106. #define AX_TXCOE_UDP 0x04
  107. #define AX_TXCOE_TCPV6 0x20
  108. #define AX_TXCOE_UDPV6 0x40
  109. #define AX_LEDCTRL 0x73
  110. #define GMII_PHY_PHYSR 0x11
  111. #define GMII_PHY_PHYSR_SMASK 0xc000
  112. #define GMII_PHY_PHYSR_GIGA 0x8000
  113. #define GMII_PHY_PHYSR_100 0x4000
  114. #define GMII_PHY_PHYSR_FULL 0x2000
  115. #define GMII_PHY_PHYSR_LINK 0x400
  116. #define GMII_LED_ACT 0x1a
  117. #define GMII_LED_ACTIVE_MASK 0xff8f
  118. #define GMII_LED0_ACTIVE BIT(4)
  119. #define GMII_LED1_ACTIVE BIT(5)
  120. #define GMII_LED2_ACTIVE BIT(6)
  121. #define GMII_LED_LINK 0x1c
  122. #define GMII_LED_LINK_MASK 0xf888
  123. #define GMII_LED0_LINK_10 BIT(0)
  124. #define GMII_LED0_LINK_100 BIT(1)
  125. #define GMII_LED0_LINK_1000 BIT(2)
  126. #define GMII_LED1_LINK_10 BIT(4)
  127. #define GMII_LED1_LINK_100 BIT(5)
  128. #define GMII_LED1_LINK_1000 BIT(6)
  129. #define GMII_LED2_LINK_10 BIT(8)
  130. #define GMII_LED2_LINK_100 BIT(9)
  131. #define GMII_LED2_LINK_1000 BIT(10)
  132. #define LED0_ACTIVE BIT(0)
  133. #define LED0_LINK_10 BIT(1)
  134. #define LED0_LINK_100 BIT(2)
  135. #define LED0_LINK_1000 BIT(3)
  136. #define LED0_FD BIT(4)
  137. #define LED0_USB3_MASK 0x001f
  138. #define LED1_ACTIVE BIT(5)
  139. #define LED1_LINK_10 BIT(6)
  140. #define LED1_LINK_100 BIT(7)
  141. #define LED1_LINK_1000 BIT(8)
  142. #define LED1_FD BIT(9)
  143. #define LED1_USB3_MASK 0x03e0
  144. #define LED2_ACTIVE BIT(10)
  145. #define LED2_LINK_1000 BIT(13)
  146. #define LED2_LINK_100 BIT(12)
  147. #define LED2_LINK_10 BIT(11)
  148. #define LED2_FD BIT(14)
  149. #define LED_VALID BIT(15)
  150. #define LED2_USB3_MASK 0x7c00
  151. #define GMII_PHYPAGE 0x1e
  152. #define GMII_PHY_PAGE_SELECT 0x1f
  153. #define GMII_PHY_PGSEL_EXT 0x0007
  154. #define GMII_PHY_PGSEL_PAGE0 0x0000
  155. #define GMII_PHY_PGSEL_PAGE3 0x0003
  156. #define GMII_PHY_PGSEL_PAGE5 0x0005
  157. struct ax88179_data {
  158. u8 eee_enabled;
  159. u8 eee_active;
  160. u16 rxctl;
  161. u16 reserved;
  162. };
  163. struct ax88179_int_data {
  164. __le32 intdata1;
  165. __le32 intdata2;
  166. };
  167. static const struct {
  168. unsigned char ctrl, timer_l, timer_h, size, ifg;
  169. } AX88179_BULKIN_SIZE[] = {
  170. {7, 0x4f, 0, 0x12, 0xff},
  171. {7, 0x20, 3, 0x16, 0xff},
  172. {7, 0xae, 7, 0x18, 0xff},
  173. {7, 0xcc, 0x4c, 0x18, 8},
  174. };
  175. static int __ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  176. u16 size, void *data, int in_pm)
  177. {
  178. int ret;
  179. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  180. BUG_ON(!dev);
  181. if (!in_pm)
  182. fn = usbnet_read_cmd;
  183. else
  184. fn = usbnet_read_cmd_nopm;
  185. ret = fn(dev, cmd, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  186. value, index, data, size);
  187. if (unlikely(ret < 0))
  188. netdev_warn(dev->net, "Failed to read reg index 0x%04x: %d\n",
  189. index, ret);
  190. return ret;
  191. }
  192. static int __ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  193. u16 size, void *data, int in_pm)
  194. {
  195. int ret;
  196. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  197. BUG_ON(!dev);
  198. if (!in_pm)
  199. fn = usbnet_write_cmd;
  200. else
  201. fn = usbnet_write_cmd_nopm;
  202. ret = fn(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  203. value, index, data, size);
  204. if (unlikely(ret < 0))
  205. netdev_warn(dev->net, "Failed to write reg index 0x%04x: %d\n",
  206. index, ret);
  207. return ret;
  208. }
  209. static void ax88179_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value,
  210. u16 index, u16 size, void *data)
  211. {
  212. u16 buf;
  213. if (2 == size) {
  214. buf = *((u16 *)data);
  215. cpu_to_le16s(&buf);
  216. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  217. USB_RECIP_DEVICE, value, index, &buf,
  218. size);
  219. } else {
  220. usbnet_write_cmd_async(dev, cmd, USB_DIR_OUT | USB_TYPE_VENDOR |
  221. USB_RECIP_DEVICE, value, index, data,
  222. size);
  223. }
  224. }
  225. static int ax88179_read_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  226. u16 index, u16 size, void *data)
  227. {
  228. int ret;
  229. if (2 == size) {
  230. u16 buf;
  231. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  232. le16_to_cpus(&buf);
  233. *((u16 *)data) = buf;
  234. } else if (4 == size) {
  235. u32 buf;
  236. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 1);
  237. le32_to_cpus(&buf);
  238. *((u32 *)data) = buf;
  239. } else {
  240. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 1);
  241. }
  242. return ret;
  243. }
  244. static int ax88179_write_cmd_nopm(struct usbnet *dev, u8 cmd, u16 value,
  245. u16 index, u16 size, void *data)
  246. {
  247. int ret;
  248. if (2 == size) {
  249. u16 buf;
  250. buf = *((u16 *)data);
  251. cpu_to_le16s(&buf);
  252. ret = __ax88179_write_cmd(dev, cmd, value, index,
  253. size, &buf, 1);
  254. } else {
  255. ret = __ax88179_write_cmd(dev, cmd, value, index,
  256. size, data, 1);
  257. }
  258. return ret;
  259. }
  260. static int ax88179_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  261. u16 size, void *data)
  262. {
  263. int ret;
  264. if (2 == size) {
  265. u16 buf;
  266. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  267. le16_to_cpus(&buf);
  268. *((u16 *)data) = buf;
  269. } else if (4 == size) {
  270. u32 buf;
  271. ret = __ax88179_read_cmd(dev, cmd, value, index, size, &buf, 0);
  272. le32_to_cpus(&buf);
  273. *((u32 *)data) = buf;
  274. } else {
  275. ret = __ax88179_read_cmd(dev, cmd, value, index, size, data, 0);
  276. }
  277. return ret;
  278. }
  279. static int ax88179_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index,
  280. u16 size, void *data)
  281. {
  282. int ret;
  283. if (2 == size) {
  284. u16 buf;
  285. buf = *((u16 *)data);
  286. cpu_to_le16s(&buf);
  287. ret = __ax88179_write_cmd(dev, cmd, value, index,
  288. size, &buf, 0);
  289. } else {
  290. ret = __ax88179_write_cmd(dev, cmd, value, index,
  291. size, data, 0);
  292. }
  293. return ret;
  294. }
  295. static void ax88179_status(struct usbnet *dev, struct urb *urb)
  296. {
  297. struct ax88179_int_data *event;
  298. u32 link;
  299. if (urb->actual_length < 8)
  300. return;
  301. event = urb->transfer_buffer;
  302. le32_to_cpus((void *)&event->intdata1);
  303. link = (((__force u32)event->intdata1) & AX_INT_PPLS_LINK) >> 16;
  304. if (netif_carrier_ok(dev->net) != link) {
  305. usbnet_link_change(dev, link, 1);
  306. netdev_info(dev->net, "ax88179 - Link status is: %d\n", link);
  307. }
  308. }
  309. static int ax88179_mdio_read(struct net_device *netdev, int phy_id, int loc)
  310. {
  311. struct usbnet *dev = netdev_priv(netdev);
  312. u16 res;
  313. ax88179_read_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  314. return res;
  315. }
  316. static void ax88179_mdio_write(struct net_device *netdev, int phy_id, int loc,
  317. int val)
  318. {
  319. struct usbnet *dev = netdev_priv(netdev);
  320. u16 res = (u16) val;
  321. ax88179_write_cmd(dev, AX_ACCESS_PHY, phy_id, (__u16)loc, 2, &res);
  322. }
  323. static inline int ax88179_phy_mmd_indirect(struct usbnet *dev, u16 prtad,
  324. u16 devad)
  325. {
  326. u16 tmp16;
  327. int ret;
  328. tmp16 = devad;
  329. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  330. MII_MMD_CTRL, 2, &tmp16);
  331. tmp16 = prtad;
  332. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  333. MII_MMD_DATA, 2, &tmp16);
  334. tmp16 = devad | MII_MMD_CTRL_NOINCR;
  335. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  336. MII_MMD_CTRL, 2, &tmp16);
  337. return ret;
  338. }
  339. static int
  340. ax88179_phy_read_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad)
  341. {
  342. int ret;
  343. u16 tmp16;
  344. ax88179_phy_mmd_indirect(dev, prtad, devad);
  345. ret = ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  346. MII_MMD_DATA, 2, &tmp16);
  347. if (ret < 0)
  348. return ret;
  349. return tmp16;
  350. }
  351. static int
  352. ax88179_phy_write_mmd_indirect(struct usbnet *dev, u16 prtad, u16 devad,
  353. u16 data)
  354. {
  355. int ret;
  356. ax88179_phy_mmd_indirect(dev, prtad, devad);
  357. ret = ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  358. MII_MMD_DATA, 2, &data);
  359. if (ret < 0)
  360. return ret;
  361. return 0;
  362. }
  363. static int ax88179_suspend(struct usb_interface *intf, pm_message_t message)
  364. {
  365. struct usbnet *dev = usb_get_intfdata(intf);
  366. u16 tmp16;
  367. u8 tmp8;
  368. usbnet_suspend(intf, message);
  369. /* Disable RX path */
  370. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  371. 2, 2, &tmp16);
  372. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  373. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  374. 2, 2, &tmp16);
  375. /* Force bulk-in zero length */
  376. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  377. 2, 2, &tmp16);
  378. tmp16 |= AX_PHYPWR_RSTCTL_BZ | AX_PHYPWR_RSTCTL_IPRL;
  379. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  380. 2, 2, &tmp16);
  381. /* change clock */
  382. tmp8 = 0;
  383. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  384. /* Configure RX control register => stop operation */
  385. tmp16 = AX_RX_CTL_STOP;
  386. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  387. return 0;
  388. }
  389. /* This function is used to enable the autodetach function. */
  390. /* This function is determined by offset 0x43 of EEPROM */
  391. static int ax88179_auto_detach(struct usbnet *dev, int in_pm)
  392. {
  393. u16 tmp16;
  394. u8 tmp8;
  395. int (*fnr)(struct usbnet *, u8, u16, u16, u16, void *);
  396. int (*fnw)(struct usbnet *, u8, u16, u16, u16, void *);
  397. if (!in_pm) {
  398. fnr = ax88179_read_cmd;
  399. fnw = ax88179_write_cmd;
  400. } else {
  401. fnr = ax88179_read_cmd_nopm;
  402. fnw = ax88179_write_cmd_nopm;
  403. }
  404. if (fnr(dev, AX_ACCESS_EEPROM, 0x43, 1, 2, &tmp16) < 0)
  405. return 0;
  406. if ((tmp16 == 0xFFFF) || (!(tmp16 & 0x0100)))
  407. return 0;
  408. /* Enable Auto Detach bit */
  409. tmp8 = 0;
  410. fnr(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  411. tmp8 |= AX_CLK_SELECT_ULR;
  412. fnw(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  413. fnr(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  414. tmp16 |= AX_PHYPWR_RSTCTL_AT;
  415. fnw(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  416. return 0;
  417. }
  418. static int ax88179_resume(struct usb_interface *intf)
  419. {
  420. struct usbnet *dev = usb_get_intfdata(intf);
  421. u16 tmp16;
  422. u8 tmp8;
  423. usbnet_link_change(dev, 0, 0);
  424. /* Power up ethernet PHY */
  425. tmp16 = 0;
  426. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  427. 2, 2, &tmp16);
  428. udelay(1000);
  429. tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  430. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL,
  431. 2, 2, &tmp16);
  432. msleep(200);
  433. /* Ethernet PHY Auto Detach*/
  434. ax88179_auto_detach(dev, 1);
  435. /* Enable clock */
  436. ax88179_read_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  437. tmp8 |= AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  438. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp8);
  439. msleep(100);
  440. /* Configure RX control register => start operation */
  441. tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  442. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  443. ax88179_write_cmd_nopm(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  444. return usbnet_resume(intf);
  445. }
  446. static void
  447. ax88179_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  448. {
  449. struct usbnet *dev = netdev_priv(net);
  450. u8 opt;
  451. if (ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  452. 1, 1, &opt) < 0) {
  453. wolinfo->supported = 0;
  454. wolinfo->wolopts = 0;
  455. return;
  456. }
  457. wolinfo->supported = WAKE_PHY | WAKE_MAGIC;
  458. wolinfo->wolopts = 0;
  459. if (opt & AX_MONITOR_MODE_RWLC)
  460. wolinfo->wolopts |= WAKE_PHY;
  461. if (opt & AX_MONITOR_MODE_RWMP)
  462. wolinfo->wolopts |= WAKE_MAGIC;
  463. }
  464. static int
  465. ax88179_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo)
  466. {
  467. struct usbnet *dev = netdev_priv(net);
  468. u8 opt = 0;
  469. if (wolinfo->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
  470. return -EINVAL;
  471. if (wolinfo->wolopts & WAKE_PHY)
  472. opt |= AX_MONITOR_MODE_RWLC;
  473. if (wolinfo->wolopts & WAKE_MAGIC)
  474. opt |= AX_MONITOR_MODE_RWMP;
  475. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD,
  476. 1, 1, &opt) < 0)
  477. return -EINVAL;
  478. return 0;
  479. }
  480. static int ax88179_get_eeprom_len(struct net_device *net)
  481. {
  482. return AX_EEPROM_LEN;
  483. }
  484. static int
  485. ax88179_get_eeprom(struct net_device *net, struct ethtool_eeprom *eeprom,
  486. u8 *data)
  487. {
  488. struct usbnet *dev = netdev_priv(net);
  489. u16 *eeprom_buff;
  490. int first_word, last_word;
  491. int i, ret;
  492. if (eeprom->len == 0)
  493. return -EINVAL;
  494. eeprom->magic = AX88179_EEPROM_MAGIC;
  495. first_word = eeprom->offset >> 1;
  496. last_word = (eeprom->offset + eeprom->len - 1) >> 1;
  497. eeprom_buff = kmalloc(sizeof(u16) * (last_word - first_word + 1),
  498. GFP_KERNEL);
  499. if (!eeprom_buff)
  500. return -ENOMEM;
  501. /* ax88179/178A returns 2 bytes from eeprom on read */
  502. for (i = first_word; i <= last_word; i++) {
  503. ret = __ax88179_read_cmd(dev, AX_ACCESS_EEPROM, i, 1, 2,
  504. &eeprom_buff[i - first_word],
  505. 0);
  506. if (ret < 0) {
  507. kfree(eeprom_buff);
  508. return -EIO;
  509. }
  510. }
  511. memcpy(data, (u8 *)eeprom_buff + (eeprom->offset & 1), eeprom->len);
  512. kfree(eeprom_buff);
  513. return 0;
  514. }
  515. static int ax88179_get_settings(struct net_device *net, struct ethtool_cmd *cmd)
  516. {
  517. struct usbnet *dev = netdev_priv(net);
  518. return mii_ethtool_gset(&dev->mii, cmd);
  519. }
  520. static int ax88179_set_settings(struct net_device *net, struct ethtool_cmd *cmd)
  521. {
  522. struct usbnet *dev = netdev_priv(net);
  523. return mii_ethtool_sset(&dev->mii, cmd);
  524. }
  525. static int
  526. ax88179_ethtool_get_eee(struct usbnet *dev, struct ethtool_eee *data)
  527. {
  528. int val;
  529. /* Get Supported EEE */
  530. val = ax88179_phy_read_mmd_indirect(dev, MDIO_PCS_EEE_ABLE,
  531. MDIO_MMD_PCS);
  532. if (val < 0)
  533. return val;
  534. data->supported = mmd_eee_cap_to_ethtool_sup_t(val);
  535. /* Get advertisement EEE */
  536. val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_ADV,
  537. MDIO_MMD_AN);
  538. if (val < 0)
  539. return val;
  540. data->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  541. /* Get LP advertisement EEE */
  542. val = ax88179_phy_read_mmd_indirect(dev, MDIO_AN_EEE_LPABLE,
  543. MDIO_MMD_AN);
  544. if (val < 0)
  545. return val;
  546. data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
  547. return 0;
  548. }
  549. static int
  550. ax88179_ethtool_set_eee(struct usbnet *dev, struct ethtool_eee *data)
  551. {
  552. u16 tmp16 = ethtool_adv_to_mmd_eee_adv_t(data->advertised);
  553. return ax88179_phy_write_mmd_indirect(dev, MDIO_AN_EEE_ADV,
  554. MDIO_MMD_AN, tmp16);
  555. }
  556. static int ax88179_chk_eee(struct usbnet *dev)
  557. {
  558. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  559. struct ax88179_data *priv = (struct ax88179_data *)dev->data;
  560. mii_ethtool_gset(&dev->mii, &ecmd);
  561. if (ecmd.duplex & DUPLEX_FULL) {
  562. int eee_lp, eee_cap, eee_adv;
  563. u32 lp, cap, adv, supported = 0;
  564. eee_cap = ax88179_phy_read_mmd_indirect(dev,
  565. MDIO_PCS_EEE_ABLE,
  566. MDIO_MMD_PCS);
  567. if (eee_cap < 0) {
  568. priv->eee_active = 0;
  569. return false;
  570. }
  571. cap = mmd_eee_cap_to_ethtool_sup_t(eee_cap);
  572. if (!cap) {
  573. priv->eee_active = 0;
  574. return false;
  575. }
  576. eee_lp = ax88179_phy_read_mmd_indirect(dev,
  577. MDIO_AN_EEE_LPABLE,
  578. MDIO_MMD_AN);
  579. if (eee_lp < 0) {
  580. priv->eee_active = 0;
  581. return false;
  582. }
  583. eee_adv = ax88179_phy_read_mmd_indirect(dev,
  584. MDIO_AN_EEE_ADV,
  585. MDIO_MMD_AN);
  586. if (eee_adv < 0) {
  587. priv->eee_active = 0;
  588. return false;
  589. }
  590. adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv);
  591. lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp);
  592. supported = (ecmd.speed == SPEED_1000) ?
  593. SUPPORTED_1000baseT_Full :
  594. SUPPORTED_100baseT_Full;
  595. if (!(lp & adv & supported)) {
  596. priv->eee_active = 0;
  597. return false;
  598. }
  599. priv->eee_active = 1;
  600. return true;
  601. }
  602. priv->eee_active = 0;
  603. return false;
  604. }
  605. static void ax88179_disable_eee(struct usbnet *dev)
  606. {
  607. u16 tmp16;
  608. tmp16 = GMII_PHY_PGSEL_PAGE3;
  609. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  610. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  611. tmp16 = 0x3246;
  612. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  613. MII_PHYADDR, 2, &tmp16);
  614. tmp16 = GMII_PHY_PGSEL_PAGE0;
  615. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  616. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  617. }
  618. static void ax88179_enable_eee(struct usbnet *dev)
  619. {
  620. u16 tmp16;
  621. tmp16 = GMII_PHY_PGSEL_PAGE3;
  622. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  623. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  624. tmp16 = 0x3247;
  625. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  626. MII_PHYADDR, 2, &tmp16);
  627. tmp16 = GMII_PHY_PGSEL_PAGE5;
  628. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  629. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  630. tmp16 = 0x0680;
  631. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  632. MII_BMSR, 2, &tmp16);
  633. tmp16 = GMII_PHY_PGSEL_PAGE0;
  634. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  635. GMII_PHY_PAGE_SELECT, 2, &tmp16);
  636. }
  637. static int ax88179_get_eee(struct net_device *net, struct ethtool_eee *edata)
  638. {
  639. struct usbnet *dev = netdev_priv(net);
  640. struct ax88179_data *priv = (struct ax88179_data *)dev->data;
  641. edata->eee_enabled = priv->eee_enabled;
  642. edata->eee_active = priv->eee_active;
  643. return ax88179_ethtool_get_eee(dev, edata);
  644. }
  645. static int ax88179_set_eee(struct net_device *net, struct ethtool_eee *edata)
  646. {
  647. struct usbnet *dev = netdev_priv(net);
  648. struct ax88179_data *priv = (struct ax88179_data *)dev->data;
  649. int ret = -EOPNOTSUPP;
  650. priv->eee_enabled = edata->eee_enabled;
  651. if (!priv->eee_enabled) {
  652. ax88179_disable_eee(dev);
  653. } else {
  654. priv->eee_enabled = ax88179_chk_eee(dev);
  655. if (!priv->eee_enabled)
  656. return -EOPNOTSUPP;
  657. ax88179_enable_eee(dev);
  658. }
  659. ret = ax88179_ethtool_set_eee(dev, edata);
  660. if (ret)
  661. return ret;
  662. mii_nway_restart(&dev->mii);
  663. usbnet_link_change(dev, 0, 0);
  664. return ret;
  665. }
  666. static int ax88179_ioctl(struct net_device *net, struct ifreq *rq, int cmd)
  667. {
  668. struct usbnet *dev = netdev_priv(net);
  669. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  670. }
  671. static const struct ethtool_ops ax88179_ethtool_ops = {
  672. .get_link = ethtool_op_get_link,
  673. .get_msglevel = usbnet_get_msglevel,
  674. .set_msglevel = usbnet_set_msglevel,
  675. .get_wol = ax88179_get_wol,
  676. .set_wol = ax88179_set_wol,
  677. .get_eeprom_len = ax88179_get_eeprom_len,
  678. .get_eeprom = ax88179_get_eeprom,
  679. .get_settings = ax88179_get_settings,
  680. .set_settings = ax88179_set_settings,
  681. .get_eee = ax88179_get_eee,
  682. .set_eee = ax88179_set_eee,
  683. .nway_reset = usbnet_nway_reset,
  684. };
  685. static void ax88179_set_multicast(struct net_device *net)
  686. {
  687. struct usbnet *dev = netdev_priv(net);
  688. struct ax88179_data *data = (struct ax88179_data *)dev->data;
  689. u8 *m_filter = ((u8 *)dev->data) + 12;
  690. data->rxctl = (AX_RX_CTL_START | AX_RX_CTL_AB | AX_RX_CTL_IPE);
  691. if (net->flags & IFF_PROMISC) {
  692. data->rxctl |= AX_RX_CTL_PRO;
  693. } else if (net->flags & IFF_ALLMULTI ||
  694. netdev_mc_count(net) > AX_MAX_MCAST) {
  695. data->rxctl |= AX_RX_CTL_AMALL;
  696. } else if (netdev_mc_empty(net)) {
  697. /* just broadcast and directed */
  698. } else {
  699. /* We use the 20 byte dev->data for our 8 byte filter buffer
  700. * to avoid allocating memory that is tricky to free later
  701. */
  702. u32 crc_bits;
  703. struct netdev_hw_addr *ha;
  704. memset(m_filter, 0, AX_MCAST_FLTSIZE);
  705. netdev_for_each_mc_addr(ha, net) {
  706. crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
  707. *(m_filter + (crc_bits >> 3)) |= (1 << (crc_bits & 7));
  708. }
  709. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_MULFLTARY,
  710. AX_MCAST_FLTSIZE, AX_MCAST_FLTSIZE,
  711. m_filter);
  712. data->rxctl |= AX_RX_CTL_AM;
  713. }
  714. ax88179_write_cmd_async(dev, AX_ACCESS_MAC, AX_RX_CTL,
  715. 2, 2, &data->rxctl);
  716. }
  717. static int
  718. ax88179_set_features(struct net_device *net, netdev_features_t features)
  719. {
  720. u8 tmp;
  721. struct usbnet *dev = netdev_priv(net);
  722. netdev_features_t changed = net->features ^ features;
  723. if (changed & NETIF_F_IP_CSUM) {
  724. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  725. tmp ^= AX_TXCOE_TCP | AX_TXCOE_UDP;
  726. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  727. }
  728. if (changed & NETIF_F_IPV6_CSUM) {
  729. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  730. tmp ^= AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  731. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, &tmp);
  732. }
  733. if (changed & NETIF_F_RXCSUM) {
  734. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  735. tmp ^= AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  736. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  737. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, &tmp);
  738. }
  739. return 0;
  740. }
  741. static int ax88179_change_mtu(struct net_device *net, int new_mtu)
  742. {
  743. struct usbnet *dev = netdev_priv(net);
  744. u16 tmp16;
  745. if (new_mtu <= 0 || new_mtu > 4088)
  746. return -EINVAL;
  747. net->mtu = new_mtu;
  748. dev->hard_mtu = net->mtu + net->hard_header_len;
  749. if (net->mtu > 1500) {
  750. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  751. 2, 2, &tmp16);
  752. tmp16 |= AX_MEDIUM_JUMBO_EN;
  753. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  754. 2, 2, &tmp16);
  755. } else {
  756. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  757. 2, 2, &tmp16);
  758. tmp16 &= ~AX_MEDIUM_JUMBO_EN;
  759. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  760. 2, 2, &tmp16);
  761. }
  762. /* max qlen depend on hard_mtu and rx_urb_size */
  763. usbnet_update_max_qlen(dev);
  764. return 0;
  765. }
  766. static int ax88179_set_mac_addr(struct net_device *net, void *p)
  767. {
  768. struct usbnet *dev = netdev_priv(net);
  769. struct sockaddr *addr = p;
  770. int ret;
  771. if (netif_running(net))
  772. return -EBUSY;
  773. if (!is_valid_ether_addr(addr->sa_data))
  774. return -EADDRNOTAVAIL;
  775. memcpy(net->dev_addr, addr->sa_data, ETH_ALEN);
  776. /* Set the MAC address */
  777. ret = ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  778. ETH_ALEN, net->dev_addr);
  779. if (ret < 0)
  780. return ret;
  781. return 0;
  782. }
  783. static const struct net_device_ops ax88179_netdev_ops = {
  784. .ndo_open = usbnet_open,
  785. .ndo_stop = usbnet_stop,
  786. .ndo_start_xmit = usbnet_start_xmit,
  787. .ndo_tx_timeout = usbnet_tx_timeout,
  788. .ndo_change_mtu = ax88179_change_mtu,
  789. .ndo_set_mac_address = ax88179_set_mac_addr,
  790. .ndo_validate_addr = eth_validate_addr,
  791. .ndo_do_ioctl = ax88179_ioctl,
  792. .ndo_set_rx_mode = ax88179_set_multicast,
  793. .ndo_set_features = ax88179_set_features,
  794. };
  795. static int ax88179_check_eeprom(struct usbnet *dev)
  796. {
  797. u8 i, buf, eeprom[20];
  798. u16 csum, delay = HZ / 10;
  799. unsigned long jtimeout;
  800. /* Read EEPROM content */
  801. for (i = 0; i < 6; i++) {
  802. buf = i;
  803. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  804. 1, 1, &buf) < 0)
  805. return -EINVAL;
  806. buf = EEP_RD;
  807. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  808. 1, 1, &buf) < 0)
  809. return -EINVAL;
  810. jtimeout = jiffies + delay;
  811. do {
  812. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  813. 1, 1, &buf);
  814. if (time_after(jiffies, jtimeout))
  815. return -EINVAL;
  816. } while (buf & EEP_BUSY);
  817. __ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  818. 2, 2, &eeprom[i * 2], 0);
  819. if ((i == 0) && (eeprom[0] == 0xFF))
  820. return -EINVAL;
  821. }
  822. csum = eeprom[6] + eeprom[7] + eeprom[8] + eeprom[9];
  823. csum = (csum >> 8) + (csum & 0xff);
  824. if ((csum + eeprom[10]) != 0xff)
  825. return -EINVAL;
  826. return 0;
  827. }
  828. static int ax88179_check_efuse(struct usbnet *dev, u16 *ledmode)
  829. {
  830. u8 i;
  831. u8 efuse[64];
  832. u16 csum = 0;
  833. if (ax88179_read_cmd(dev, AX_ACCESS_EFUS, 0, 64, 64, efuse) < 0)
  834. return -EINVAL;
  835. if (*efuse == 0xFF)
  836. return -EINVAL;
  837. for (i = 0; i < 64; i++)
  838. csum = csum + efuse[i];
  839. while (csum > 255)
  840. csum = (csum & 0x00FF) + ((csum >> 8) & 0x00FF);
  841. if (csum != 0xFF)
  842. return -EINVAL;
  843. *ledmode = (efuse[51] << 8) | efuse[52];
  844. return 0;
  845. }
  846. static int ax88179_convert_old_led(struct usbnet *dev, u16 *ledvalue)
  847. {
  848. u16 led;
  849. /* Loaded the old eFuse LED Mode */
  850. if (ax88179_read_cmd(dev, AX_ACCESS_EEPROM, 0x3C, 1, 2, &led) < 0)
  851. return -EINVAL;
  852. led >>= 8;
  853. switch (led) {
  854. case 0xFF:
  855. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  856. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  857. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  858. break;
  859. case 0xFE:
  860. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 | LED_VALID;
  861. break;
  862. case 0xFD:
  863. led = LED0_ACTIVE | LED1_LINK_1000 | LED2_LINK_100 |
  864. LED2_LINK_10 | LED_VALID;
  865. break;
  866. case 0xFC:
  867. led = LED0_ACTIVE | LED1_ACTIVE | LED1_LINK_1000 | LED2_ACTIVE |
  868. LED2_LINK_100 | LED2_LINK_10 | LED_VALID;
  869. break;
  870. default:
  871. led = LED0_ACTIVE | LED1_LINK_10 | LED1_LINK_100 |
  872. LED1_LINK_1000 | LED2_ACTIVE | LED2_LINK_10 |
  873. LED2_LINK_100 | LED2_LINK_1000 | LED_VALID;
  874. break;
  875. }
  876. *ledvalue = led;
  877. return 0;
  878. }
  879. static int ax88179_led_setting(struct usbnet *dev)
  880. {
  881. u8 ledfd, value = 0;
  882. u16 tmp, ledact, ledlink, ledvalue = 0, delay = HZ / 10;
  883. unsigned long jtimeout;
  884. /* Check AX88179 version. UA1 or UA2*/
  885. ax88179_read_cmd(dev, AX_ACCESS_MAC, GENERAL_STATUS, 1, 1, &value);
  886. if (!(value & AX_SECLD)) { /* UA1 */
  887. value = AX_GPIO_CTRL_GPIO3EN | AX_GPIO_CTRL_GPIO2EN |
  888. AX_GPIO_CTRL_GPIO1EN;
  889. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_GPIO_CTRL,
  890. 1, 1, &value) < 0)
  891. return -EINVAL;
  892. }
  893. /* Check EEPROM */
  894. if (!ax88179_check_eeprom(dev)) {
  895. value = 0x42;
  896. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_ADDR,
  897. 1, 1, &value) < 0)
  898. return -EINVAL;
  899. value = EEP_RD;
  900. if (ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  901. 1, 1, &value) < 0)
  902. return -EINVAL;
  903. jtimeout = jiffies + delay;
  904. do {
  905. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_CMD,
  906. 1, 1, &value);
  907. if (time_after(jiffies, jtimeout))
  908. return -EINVAL;
  909. } while (value & EEP_BUSY);
  910. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_HIGH,
  911. 1, 1, &value);
  912. ledvalue = (value << 8);
  913. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_SROM_DATA_LOW,
  914. 1, 1, &value);
  915. ledvalue |= value;
  916. /* load internal ROM for defaule setting */
  917. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  918. ax88179_convert_old_led(dev, &ledvalue);
  919. } else if (!ax88179_check_efuse(dev, &ledvalue)) {
  920. if ((ledvalue == 0xFFFF) || ((ledvalue & LED_VALID) == 0))
  921. ax88179_convert_old_led(dev, &ledvalue);
  922. } else {
  923. ax88179_convert_old_led(dev, &ledvalue);
  924. }
  925. tmp = GMII_PHY_PGSEL_EXT;
  926. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  927. GMII_PHY_PAGE_SELECT, 2, &tmp);
  928. tmp = 0x2c;
  929. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  930. GMII_PHYPAGE, 2, &tmp);
  931. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  932. GMII_LED_ACT, 2, &ledact);
  933. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  934. GMII_LED_LINK, 2, &ledlink);
  935. ledact &= GMII_LED_ACTIVE_MASK;
  936. ledlink &= GMII_LED_LINK_MASK;
  937. if (ledvalue & LED0_ACTIVE)
  938. ledact |= GMII_LED0_ACTIVE;
  939. if (ledvalue & LED1_ACTIVE)
  940. ledact |= GMII_LED1_ACTIVE;
  941. if (ledvalue & LED2_ACTIVE)
  942. ledact |= GMII_LED2_ACTIVE;
  943. if (ledvalue & LED0_LINK_10)
  944. ledlink |= GMII_LED0_LINK_10;
  945. if (ledvalue & LED1_LINK_10)
  946. ledlink |= GMII_LED1_LINK_10;
  947. if (ledvalue & LED2_LINK_10)
  948. ledlink |= GMII_LED2_LINK_10;
  949. if (ledvalue & LED0_LINK_100)
  950. ledlink |= GMII_LED0_LINK_100;
  951. if (ledvalue & LED1_LINK_100)
  952. ledlink |= GMII_LED1_LINK_100;
  953. if (ledvalue & LED2_LINK_100)
  954. ledlink |= GMII_LED2_LINK_100;
  955. if (ledvalue & LED0_LINK_1000)
  956. ledlink |= GMII_LED0_LINK_1000;
  957. if (ledvalue & LED1_LINK_1000)
  958. ledlink |= GMII_LED1_LINK_1000;
  959. if (ledvalue & LED2_LINK_1000)
  960. ledlink |= GMII_LED2_LINK_1000;
  961. tmp = ledact;
  962. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  963. GMII_LED_ACT, 2, &tmp);
  964. tmp = ledlink;
  965. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  966. GMII_LED_LINK, 2, &tmp);
  967. tmp = GMII_PHY_PGSEL_PAGE0;
  968. ax88179_write_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  969. GMII_PHY_PAGE_SELECT, 2, &tmp);
  970. /* LED full duplex setting */
  971. ledfd = 0;
  972. if (ledvalue & LED0_FD)
  973. ledfd |= 0x01;
  974. else if ((ledvalue & LED0_USB3_MASK) == 0)
  975. ledfd |= 0x02;
  976. if (ledvalue & LED1_FD)
  977. ledfd |= 0x04;
  978. else if ((ledvalue & LED1_USB3_MASK) == 0)
  979. ledfd |= 0x08;
  980. if (ledvalue & LED2_FD)
  981. ledfd |= 0x10;
  982. else if ((ledvalue & LED2_USB3_MASK) == 0)
  983. ledfd |= 0x20;
  984. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_LEDCTRL, 1, 1, &ledfd);
  985. return 0;
  986. }
  987. static int ax88179_bind(struct usbnet *dev, struct usb_interface *intf)
  988. {
  989. u8 buf[5];
  990. u16 *tmp16;
  991. u8 *tmp;
  992. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  993. struct ethtool_eee eee_data;
  994. usbnet_get_endpoints(dev, intf);
  995. tmp16 = (u16 *)buf;
  996. tmp = (u8 *)buf;
  997. memset(ax179_data, 0, sizeof(*ax179_data));
  998. /* Power up ethernet PHY */
  999. *tmp16 = 0;
  1000. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1001. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  1002. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1003. msleep(200);
  1004. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  1005. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  1006. msleep(100);
  1007. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN,
  1008. ETH_ALEN, dev->net->dev_addr);
  1009. memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN);
  1010. /* RX bulk configuration */
  1011. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1012. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1013. dev->rx_urb_size = 1024 * 20;
  1014. *tmp = 0x34;
  1015. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  1016. *tmp = 0x52;
  1017. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  1018. 1, 1, tmp);
  1019. dev->net->netdev_ops = &ax88179_netdev_ops;
  1020. dev->net->ethtool_ops = &ax88179_ethtool_ops;
  1021. dev->net->needed_headroom = 8;
  1022. /* Initialize MII structure */
  1023. dev->mii.dev = dev->net;
  1024. dev->mii.mdio_read = ax88179_mdio_read;
  1025. dev->mii.mdio_write = ax88179_mdio_write;
  1026. dev->mii.phy_id_mask = 0xff;
  1027. dev->mii.reg_num_mask = 0xff;
  1028. dev->mii.phy_id = 0x03;
  1029. dev->mii.supports_gmii = 1;
  1030. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1031. NETIF_F_RXCSUM;
  1032. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1033. NETIF_F_RXCSUM;
  1034. /* Enable checksum offload */
  1035. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  1036. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  1037. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  1038. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  1039. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  1040. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  1041. /* Configure RX control register => start operation */
  1042. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  1043. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  1044. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  1045. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  1046. AX_MONITOR_MODE_RWMP;
  1047. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  1048. /* Configure default medium type => giga */
  1049. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1050. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  1051. AX_MEDIUM_GIGAMODE;
  1052. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1053. 2, 2, tmp16);
  1054. ax88179_led_setting(dev);
  1055. ax179_data->eee_enabled = 0;
  1056. ax179_data->eee_active = 0;
  1057. ax88179_disable_eee(dev);
  1058. ax88179_ethtool_get_eee(dev, &eee_data);
  1059. eee_data.advertised = 0;
  1060. ax88179_ethtool_set_eee(dev, &eee_data);
  1061. /* Restart autoneg */
  1062. mii_nway_restart(&dev->mii);
  1063. usbnet_link_change(dev, 0, 0);
  1064. return 0;
  1065. }
  1066. static void ax88179_unbind(struct usbnet *dev, struct usb_interface *intf)
  1067. {
  1068. u16 tmp16;
  1069. /* Configure RX control register => stop operation */
  1070. tmp16 = AX_RX_CTL_STOP;
  1071. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &tmp16);
  1072. tmp16 = 0;
  1073. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, &tmp16);
  1074. /* Power down ethernet PHY */
  1075. tmp16 = 0;
  1076. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, &tmp16);
  1077. }
  1078. static void
  1079. ax88179_rx_checksum(struct sk_buff *skb, u32 *pkt_hdr)
  1080. {
  1081. skb->ip_summed = CHECKSUM_NONE;
  1082. /* checksum error bit is set */
  1083. if ((*pkt_hdr & AX_RXHDR_L3CSUM_ERR) ||
  1084. (*pkt_hdr & AX_RXHDR_L4CSUM_ERR))
  1085. return;
  1086. /* It must be a TCP or UDP packet with a valid checksum */
  1087. if (((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_TCP) ||
  1088. ((*pkt_hdr & AX_RXHDR_L4_TYPE_MASK) == AX_RXHDR_L4_TYPE_UDP))
  1089. skb->ip_summed = CHECKSUM_UNNECESSARY;
  1090. }
  1091. static int ax88179_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1092. {
  1093. struct sk_buff *ax_skb;
  1094. int pkt_cnt;
  1095. u32 rx_hdr;
  1096. u16 hdr_off;
  1097. u32 *pkt_hdr;
  1098. /* This check is no longer done by usbnet */
  1099. if (skb->len < dev->net->hard_header_len)
  1100. return 0;
  1101. skb_trim(skb, skb->len - 4);
  1102. memcpy(&rx_hdr, skb_tail_pointer(skb), 4);
  1103. le32_to_cpus(&rx_hdr);
  1104. pkt_cnt = (u16)rx_hdr;
  1105. hdr_off = (u16)(rx_hdr >> 16);
  1106. pkt_hdr = (u32 *)(skb->data + hdr_off);
  1107. while (pkt_cnt--) {
  1108. u16 pkt_len;
  1109. le32_to_cpus(pkt_hdr);
  1110. pkt_len = (*pkt_hdr >> 16) & 0x1fff;
  1111. /* Check CRC or runt packet */
  1112. if ((*pkt_hdr & AX_RXHDR_CRC_ERR) ||
  1113. (*pkt_hdr & AX_RXHDR_DROP_ERR)) {
  1114. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  1115. pkt_hdr++;
  1116. continue;
  1117. }
  1118. if (pkt_cnt == 0) {
  1119. /* Skip IP alignment psudo header */
  1120. skb_pull(skb, 2);
  1121. skb->len = pkt_len;
  1122. skb_set_tail_pointer(skb, pkt_len);
  1123. skb->truesize = pkt_len + sizeof(struct sk_buff);
  1124. ax88179_rx_checksum(skb, pkt_hdr);
  1125. return 1;
  1126. }
  1127. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1128. if (ax_skb) {
  1129. ax_skb->len = pkt_len;
  1130. ax_skb->data = skb->data + 2;
  1131. skb_set_tail_pointer(ax_skb, pkt_len);
  1132. ax_skb->truesize = pkt_len + sizeof(struct sk_buff);
  1133. ax88179_rx_checksum(ax_skb, pkt_hdr);
  1134. usbnet_skb_return(dev, ax_skb);
  1135. } else {
  1136. return 0;
  1137. }
  1138. skb_pull(skb, (pkt_len + 7) & 0xFFF8);
  1139. pkt_hdr++;
  1140. }
  1141. return 1;
  1142. }
  1143. static struct sk_buff *
  1144. ax88179_tx_fixup(struct usbnet *dev, struct sk_buff *skb, gfp_t flags)
  1145. {
  1146. u32 tx_hdr1, tx_hdr2;
  1147. int frame_size = dev->maxpacket;
  1148. int mss = skb_shinfo(skb)->gso_size;
  1149. int headroom;
  1150. tx_hdr1 = skb->len;
  1151. tx_hdr2 = mss;
  1152. if (((skb->len + 8) % frame_size) == 0)
  1153. tx_hdr2 |= 0x80008000; /* Enable padding */
  1154. headroom = skb_headroom(skb) - 8;
  1155. if ((skb_header_cloned(skb) || headroom < 0) &&
  1156. pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
  1157. dev_kfree_skb_any(skb);
  1158. return NULL;
  1159. }
  1160. skb_push(skb, 4);
  1161. cpu_to_le32s(&tx_hdr2);
  1162. skb_copy_to_linear_data(skb, &tx_hdr2, 4);
  1163. skb_push(skb, 4);
  1164. cpu_to_le32s(&tx_hdr1);
  1165. skb_copy_to_linear_data(skb, &tx_hdr1, 4);
  1166. return skb;
  1167. }
  1168. static int ax88179_link_reset(struct usbnet *dev)
  1169. {
  1170. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  1171. u8 tmp[5], link_sts;
  1172. u16 mode, tmp16, delay = HZ / 10;
  1173. u32 tmp32 = 0x40000000;
  1174. unsigned long jtimeout;
  1175. jtimeout = jiffies + delay;
  1176. while (tmp32 & 0x40000000) {
  1177. mode = 0;
  1178. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, &mode);
  1179. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2,
  1180. &ax179_data->rxctl);
  1181. /*link up, check the usb device control TX FIFO full or empty*/
  1182. ax88179_read_cmd(dev, 0x81, 0x8c, 0, 4, &tmp32);
  1183. if (time_after(jiffies, jtimeout))
  1184. return 0;
  1185. }
  1186. mode = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1187. AX_MEDIUM_RXFLOW_CTRLEN;
  1188. ax88179_read_cmd(dev, AX_ACCESS_MAC, PHYSICAL_LINK_STATUS,
  1189. 1, 1, &link_sts);
  1190. ax88179_read_cmd(dev, AX_ACCESS_PHY, AX88179_PHY_ID,
  1191. GMII_PHY_PHYSR, 2, &tmp16);
  1192. if (!(tmp16 & GMII_PHY_PHYSR_LINK)) {
  1193. return 0;
  1194. } else if (GMII_PHY_PHYSR_GIGA == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  1195. mode |= AX_MEDIUM_GIGAMODE | AX_MEDIUM_EN_125MHZ;
  1196. if (dev->net->mtu > 1500)
  1197. mode |= AX_MEDIUM_JUMBO_EN;
  1198. if (link_sts & AX_USB_SS)
  1199. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1200. else if (link_sts & AX_USB_HS)
  1201. memcpy(tmp, &AX88179_BULKIN_SIZE[1], 5);
  1202. else
  1203. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1204. } else if (GMII_PHY_PHYSR_100 == (tmp16 & GMII_PHY_PHYSR_SMASK)) {
  1205. mode |= AX_MEDIUM_PS;
  1206. if (link_sts & (AX_USB_SS | AX_USB_HS))
  1207. memcpy(tmp, &AX88179_BULKIN_SIZE[2], 5);
  1208. else
  1209. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1210. } else {
  1211. memcpy(tmp, &AX88179_BULKIN_SIZE[3], 5);
  1212. }
  1213. /* RX bulk configuration */
  1214. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1215. dev->rx_urb_size = (1024 * (tmp[3] + 2));
  1216. if (tmp16 & GMII_PHY_PHYSR_FULL)
  1217. mode |= AX_MEDIUM_FULL_DUPLEX;
  1218. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1219. 2, 2, &mode);
  1220. ax179_data->eee_enabled = ax88179_chk_eee(dev);
  1221. netif_carrier_on(dev->net);
  1222. return 0;
  1223. }
  1224. static int ax88179_reset(struct usbnet *dev)
  1225. {
  1226. u8 buf[5];
  1227. u16 *tmp16;
  1228. u8 *tmp;
  1229. struct ax88179_data *ax179_data = (struct ax88179_data *)dev->data;
  1230. struct ethtool_eee eee_data;
  1231. tmp16 = (u16 *)buf;
  1232. tmp = (u8 *)buf;
  1233. /* Power up ethernet PHY */
  1234. *tmp16 = 0;
  1235. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1236. *tmp16 = AX_PHYPWR_RSTCTL_IPRL;
  1237. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PHYPWR_RSTCTL, 2, 2, tmp16);
  1238. msleep(200);
  1239. *tmp = AX_CLK_SELECT_ACS | AX_CLK_SELECT_BCS;
  1240. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_CLK_SELECT, 1, 1, tmp);
  1241. msleep(100);
  1242. /* Ethernet PHY Auto Detach*/
  1243. ax88179_auto_detach(dev, 0);
  1244. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_NODE_ID, ETH_ALEN, ETH_ALEN,
  1245. dev->net->dev_addr);
  1246. memcpy(dev->net->perm_addr, dev->net->dev_addr, ETH_ALEN);
  1247. /* RX bulk configuration */
  1248. memcpy(tmp, &AX88179_BULKIN_SIZE[0], 5);
  1249. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_BULKIN_QCTRL, 5, 5, tmp);
  1250. dev->rx_urb_size = 1024 * 20;
  1251. *tmp = 0x34;
  1252. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_LOW, 1, 1, tmp);
  1253. *tmp = 0x52;
  1254. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_PAUSE_WATERLVL_HIGH,
  1255. 1, 1, tmp);
  1256. dev->net->features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1257. NETIF_F_RXCSUM;
  1258. dev->net->hw_features |= NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
  1259. NETIF_F_RXCSUM;
  1260. /* Enable checksum offload */
  1261. *tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
  1262. AX_RXCOE_TCPV6 | AX_RXCOE_UDPV6;
  1263. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RXCOE_CTL, 1, 1, tmp);
  1264. *tmp = AX_TXCOE_IP | AX_TXCOE_TCP | AX_TXCOE_UDP |
  1265. AX_TXCOE_TCPV6 | AX_TXCOE_UDPV6;
  1266. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_TXCOE_CTL, 1, 1, tmp);
  1267. /* Configure RX control register => start operation */
  1268. *tmp16 = AX_RX_CTL_DROPCRCERR | AX_RX_CTL_IPE | AX_RX_CTL_START |
  1269. AX_RX_CTL_AP | AX_RX_CTL_AMALL | AX_RX_CTL_AB;
  1270. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_RX_CTL, 2, 2, tmp16);
  1271. *tmp = AX_MONITOR_MODE_PMETYPE | AX_MONITOR_MODE_PMEPOL |
  1272. AX_MONITOR_MODE_RWMP;
  1273. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MONITOR_MOD, 1, 1, tmp);
  1274. /* Configure default medium type => giga */
  1275. *tmp16 = AX_MEDIUM_RECEIVE_EN | AX_MEDIUM_TXFLOW_CTRLEN |
  1276. AX_MEDIUM_RXFLOW_CTRLEN | AX_MEDIUM_FULL_DUPLEX |
  1277. AX_MEDIUM_GIGAMODE;
  1278. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1279. 2, 2, tmp16);
  1280. ax88179_led_setting(dev);
  1281. ax179_data->eee_enabled = 0;
  1282. ax179_data->eee_active = 0;
  1283. ax88179_disable_eee(dev);
  1284. ax88179_ethtool_get_eee(dev, &eee_data);
  1285. eee_data.advertised = 0;
  1286. ax88179_ethtool_set_eee(dev, &eee_data);
  1287. /* Restart autoneg */
  1288. mii_nway_restart(&dev->mii);
  1289. usbnet_link_change(dev, 0, 0);
  1290. return 0;
  1291. }
  1292. static int ax88179_stop(struct usbnet *dev)
  1293. {
  1294. u16 tmp16;
  1295. ax88179_read_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1296. 2, 2, &tmp16);
  1297. tmp16 &= ~AX_MEDIUM_RECEIVE_EN;
  1298. ax88179_write_cmd(dev, AX_ACCESS_MAC, AX_MEDIUM_STATUS_MODE,
  1299. 2, 2, &tmp16);
  1300. return 0;
  1301. }
  1302. static const struct driver_info ax88179_info = {
  1303. .description = "ASIX AX88179 USB 3.0 Gigabit Ethernet",
  1304. .bind = ax88179_bind,
  1305. .unbind = ax88179_unbind,
  1306. .status = ax88179_status,
  1307. .link_reset = ax88179_link_reset,
  1308. .reset = ax88179_reset,
  1309. .stop = ax88179_stop,
  1310. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1311. .rx_fixup = ax88179_rx_fixup,
  1312. .tx_fixup = ax88179_tx_fixup,
  1313. };
  1314. static const struct driver_info ax88178a_info = {
  1315. .description = "ASIX AX88178A USB 2.0 Gigabit Ethernet",
  1316. .bind = ax88179_bind,
  1317. .unbind = ax88179_unbind,
  1318. .status = ax88179_status,
  1319. .link_reset = ax88179_link_reset,
  1320. .reset = ax88179_reset,
  1321. .stop = ax88179_stop,
  1322. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1323. .rx_fixup = ax88179_rx_fixup,
  1324. .tx_fixup = ax88179_tx_fixup,
  1325. };
  1326. static const struct driver_info dlink_dub1312_info = {
  1327. .description = "D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter",
  1328. .bind = ax88179_bind,
  1329. .unbind = ax88179_unbind,
  1330. .status = ax88179_status,
  1331. .link_reset = ax88179_link_reset,
  1332. .reset = ax88179_reset,
  1333. .stop = ax88179_stop,
  1334. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1335. .rx_fixup = ax88179_rx_fixup,
  1336. .tx_fixup = ax88179_tx_fixup,
  1337. };
  1338. static const struct driver_info sitecom_info = {
  1339. .description = "Sitecom USB 3.0 to Gigabit Adapter",
  1340. .bind = ax88179_bind,
  1341. .unbind = ax88179_unbind,
  1342. .status = ax88179_status,
  1343. .link_reset = ax88179_link_reset,
  1344. .reset = ax88179_reset,
  1345. .stop = ax88179_stop,
  1346. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1347. .rx_fixup = ax88179_rx_fixup,
  1348. .tx_fixup = ax88179_tx_fixup,
  1349. };
  1350. static const struct driver_info samsung_info = {
  1351. .description = "Samsung USB Ethernet Adapter",
  1352. .bind = ax88179_bind,
  1353. .unbind = ax88179_unbind,
  1354. .status = ax88179_status,
  1355. .link_reset = ax88179_link_reset,
  1356. .reset = ax88179_reset,
  1357. .stop = ax88179_stop,
  1358. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1359. .rx_fixup = ax88179_rx_fixup,
  1360. .tx_fixup = ax88179_tx_fixup,
  1361. };
  1362. static const struct driver_info lenovo_info = {
  1363. .description = "Lenovo OneLinkDock Gigabit LAN",
  1364. .bind = ax88179_bind,
  1365. .unbind = ax88179_unbind,
  1366. .status = ax88179_status,
  1367. .link_reset = ax88179_link_reset,
  1368. .reset = ax88179_reset,
  1369. .stop = ax88179_stop,
  1370. .flags = FLAG_ETHER | FLAG_FRAMING_AX,
  1371. .rx_fixup = ax88179_rx_fixup,
  1372. .tx_fixup = ax88179_tx_fixup,
  1373. };
  1374. static const struct usb_device_id products[] = {
  1375. {
  1376. /* ASIX AX88179 10/100/1000 */
  1377. USB_DEVICE(0x0b95, 0x1790),
  1378. .driver_info = (unsigned long)&ax88179_info,
  1379. }, {
  1380. /* ASIX AX88178A 10/100/1000 */
  1381. USB_DEVICE(0x0b95, 0x178a),
  1382. .driver_info = (unsigned long)&ax88178a_info,
  1383. }, {
  1384. /* D-Link DUB-1312 USB 3.0 to Gigabit Ethernet Adapter */
  1385. USB_DEVICE(0x2001, 0x4a00),
  1386. .driver_info = (unsigned long)&dlink_dub1312_info,
  1387. }, {
  1388. /* Sitecom USB 3.0 to Gigabit Adapter */
  1389. USB_DEVICE(0x0df6, 0x0072),
  1390. .driver_info = (unsigned long)&sitecom_info,
  1391. }, {
  1392. /* Samsung USB Ethernet Adapter */
  1393. USB_DEVICE(0x04e8, 0xa100),
  1394. .driver_info = (unsigned long)&samsung_info,
  1395. }, {
  1396. /* Lenovo OneLinkDock Gigabit LAN */
  1397. USB_DEVICE(0x17ef, 0x304b),
  1398. .driver_info = (unsigned long)&lenovo_info,
  1399. },
  1400. { },
  1401. };
  1402. MODULE_DEVICE_TABLE(usb, products);
  1403. static struct usb_driver ax88179_178a_driver = {
  1404. .name = "ax88179_178a",
  1405. .id_table = products,
  1406. .probe = usbnet_probe,
  1407. .suspend = ax88179_suspend,
  1408. .resume = ax88179_resume,
  1409. .reset_resume = ax88179_resume,
  1410. .disconnect = usbnet_disconnect,
  1411. .supports_autosuspend = 1,
  1412. .disable_hub_initiated_lpm = 1,
  1413. };
  1414. module_usb_driver(ax88179_178a_driver);
  1415. MODULE_DESCRIPTION("ASIX AX88179/178A based USB 3.0/2.0 Gigabit Ethernet Devices");
  1416. MODULE_LICENSE("GPL");