ch9200.c 9.5 KB

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  1. /*
  2. * USB 10M/100M ethernet adapter
  3. *
  4. * This file is licensed under the terms of the GNU General Public License
  5. * version 2. This program is licensed "as is" without any warranty of any
  6. * kind, whether express or implied
  7. *
  8. */
  9. #include <linux/kernel.h>
  10. #include <linux/module.h>
  11. #include <linux/sched.h>
  12. #include <linux/stddef.h>
  13. #include <linux/init.h>
  14. #include <linux/netdevice.h>
  15. #include <linux/etherdevice.h>
  16. #include <linux/ethtool.h>
  17. #include <linux/mii.h>
  18. #include <linux/usb.h>
  19. #include <linux/crc32.h>
  20. #include <linux/usb/usbnet.h>
  21. #include <linux/slab.h>
  22. #define CH9200_VID 0x1A86
  23. #define CH9200_PID_E092 0xE092
  24. #define CTRL_TIMEOUT_MS 1000
  25. #define CONTROL_TIMEOUT_MS 1000
  26. #define REQUEST_READ 0x0E
  27. #define REQUEST_WRITE 0x0F
  28. /* Address space:
  29. * 00-63 : MII
  30. * 64-128: MAC
  31. *
  32. * Note: all accesses must be 16-bit
  33. */
  34. #define MAC_REG_CTRL 64
  35. #define MAC_REG_STATUS 66
  36. #define MAC_REG_INTERRUPT_MASK 68
  37. #define MAC_REG_PHY_COMMAND 70
  38. #define MAC_REG_PHY_DATA 72
  39. #define MAC_REG_STATION_L 74
  40. #define MAC_REG_STATION_M 76
  41. #define MAC_REG_STATION_H 78
  42. #define MAC_REG_HASH_L 80
  43. #define MAC_REG_HASH_M1 82
  44. #define MAC_REG_HASH_M2 84
  45. #define MAC_REG_HASH_H 86
  46. #define MAC_REG_THRESHOLD 88
  47. #define MAC_REG_FIFO_DEPTH 90
  48. #define MAC_REG_PAUSE 92
  49. #define MAC_REG_FLOW_CONTROL 94
  50. /* Control register bits
  51. *
  52. * Note: bits 13 and 15 are reserved
  53. */
  54. #define LOOPBACK (0x01 << 14)
  55. #define BASE100X (0x01 << 12)
  56. #define MBPS_10 (0x01 << 11)
  57. #define DUPLEX_MODE (0x01 << 10)
  58. #define PAUSE_FRAME (0x01 << 9)
  59. #define PROMISCUOUS (0x01 << 8)
  60. #define MULTICAST (0x01 << 7)
  61. #define BROADCAST (0x01 << 6)
  62. #define HASH (0x01 << 5)
  63. #define APPEND_PAD (0x01 << 4)
  64. #define APPEND_CRC (0x01 << 3)
  65. #define TRANSMITTER_ACTION (0x01 << 2)
  66. #define RECEIVER_ACTION (0x01 << 1)
  67. #define DMA_ACTION (0x01 << 0)
  68. /* Status register bits
  69. *
  70. * Note: bits 7-15 are reserved
  71. */
  72. #define ALIGNMENT (0x01 << 6)
  73. #define FIFO_OVER_RUN (0x01 << 5)
  74. #define FIFO_UNDER_RUN (0x01 << 4)
  75. #define RX_ERROR (0x01 << 3)
  76. #define RX_COMPLETE (0x01 << 2)
  77. #define TX_ERROR (0x01 << 1)
  78. #define TX_COMPLETE (0x01 << 0)
  79. /* FIFO depth register bits
  80. *
  81. * Note: bits 6 and 14 are reserved
  82. */
  83. #define ETH_TXBD (0x01 << 15)
  84. #define ETN_TX_FIFO_DEPTH (0x01 << 8)
  85. #define ETH_RXBD (0x01 << 7)
  86. #define ETH_RX_FIFO_DEPTH (0x01 << 0)
  87. static int control_read(struct usbnet *dev,
  88. unsigned char request, unsigned short value,
  89. unsigned short index, void *data, unsigned short size,
  90. int timeout)
  91. {
  92. unsigned char *buf = NULL;
  93. unsigned char request_type;
  94. int err = 0;
  95. if (request == REQUEST_READ)
  96. request_type = (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_OTHER);
  97. else
  98. request_type = (USB_DIR_IN | USB_TYPE_VENDOR |
  99. USB_RECIP_DEVICE);
  100. netdev_dbg(dev->net, "Control_read() index=0x%02x size=%d\n",
  101. index, size);
  102. buf = kmalloc(size, GFP_KERNEL);
  103. if (!buf) {
  104. err = -ENOMEM;
  105. goto err_out;
  106. }
  107. err = usb_control_msg(dev->udev,
  108. usb_rcvctrlpipe(dev->udev, 0),
  109. request, request_type, value, index, buf, size,
  110. timeout);
  111. if (err == size)
  112. memcpy(data, buf, size);
  113. else if (err >= 0)
  114. err = -EINVAL;
  115. kfree(buf);
  116. return err;
  117. err_out:
  118. return err;
  119. }
  120. static int control_write(struct usbnet *dev, unsigned char request,
  121. unsigned short value, unsigned short index,
  122. void *data, unsigned short size, int timeout)
  123. {
  124. unsigned char *buf = NULL;
  125. unsigned char request_type;
  126. int err = 0;
  127. if (request == REQUEST_WRITE)
  128. request_type = (USB_DIR_OUT | USB_TYPE_VENDOR |
  129. USB_RECIP_OTHER);
  130. else
  131. request_type = (USB_DIR_OUT | USB_TYPE_VENDOR |
  132. USB_RECIP_DEVICE);
  133. netdev_dbg(dev->net, "Control_write() index=0x%02x size=%d\n",
  134. index, size);
  135. if (data) {
  136. buf = kmalloc(size, GFP_KERNEL);
  137. if (!buf) {
  138. err = -ENOMEM;
  139. goto err_out;
  140. }
  141. memcpy(buf, data, size);
  142. }
  143. err = usb_control_msg(dev->udev,
  144. usb_sndctrlpipe(dev->udev, 0),
  145. request, request_type, value, index, buf, size,
  146. timeout);
  147. if (err >= 0 && err < size)
  148. err = -EINVAL;
  149. kfree(buf);
  150. return 0;
  151. err_out:
  152. return err;
  153. }
  154. static int ch9200_mdio_read(struct net_device *netdev, int phy_id, int loc)
  155. {
  156. struct usbnet *dev = netdev_priv(netdev);
  157. unsigned char buff[2];
  158. netdev_dbg(netdev, "ch9200_mdio_read phy_id:%02x loc:%02x\n",
  159. phy_id, loc);
  160. if (phy_id != 0)
  161. return -ENODEV;
  162. control_read(dev, REQUEST_READ, 0, loc * 2, buff, 0x02,
  163. CONTROL_TIMEOUT_MS);
  164. return (buff[0] | buff[1] << 8);
  165. }
  166. static void ch9200_mdio_write(struct net_device *netdev,
  167. int phy_id, int loc, int val)
  168. {
  169. struct usbnet *dev = netdev_priv(netdev);
  170. unsigned char buff[2];
  171. netdev_dbg(netdev, "ch9200_mdio_write() phy_id=%02x loc:%02x\n",
  172. phy_id, loc);
  173. if (phy_id != 0)
  174. return;
  175. buff[0] = (unsigned char)val;
  176. buff[1] = (unsigned char)(val >> 8);
  177. control_write(dev, REQUEST_WRITE, 0, loc * 2, buff, 0x02,
  178. CONTROL_TIMEOUT_MS);
  179. }
  180. static int ch9200_link_reset(struct usbnet *dev)
  181. {
  182. struct ethtool_cmd ecmd;
  183. mii_check_media(&dev->mii, 1, 1);
  184. mii_ethtool_gset(&dev->mii, &ecmd);
  185. netdev_dbg(dev->net, "link_reset() speed:%d duplex:%d\n",
  186. ecmd.speed, ecmd.duplex);
  187. return 0;
  188. }
  189. static void ch9200_status(struct usbnet *dev, struct urb *urb)
  190. {
  191. int link;
  192. unsigned char *buf;
  193. if (urb->actual_length < 16)
  194. return;
  195. buf = urb->transfer_buffer;
  196. link = !!(buf[0] & 0x01);
  197. if (link) {
  198. netif_carrier_on(dev->net);
  199. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  200. } else {
  201. netif_carrier_off(dev->net);
  202. }
  203. }
  204. static struct sk_buff *ch9200_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
  205. gfp_t flags)
  206. {
  207. int i = 0;
  208. int len = 0;
  209. int tx_overhead = 0;
  210. tx_overhead = 0x40;
  211. len = skb->len;
  212. if (skb_cow_head(skb, tx_overhead)) {
  213. dev_kfree_skb_any(skb);
  214. return NULL;
  215. }
  216. __skb_push(skb, tx_overhead);
  217. /* usbnet adds padding if length is a multiple of packet size
  218. * if so, adjust length value in header
  219. */
  220. if ((skb->len % dev->maxpacket) == 0)
  221. len++;
  222. skb->data[0] = len;
  223. skb->data[1] = len >> 8;
  224. skb->data[2] = 0x00;
  225. skb->data[3] = 0x80;
  226. for (i = 4; i < 48; i++)
  227. skb->data[i] = 0x00;
  228. skb->data[48] = len;
  229. skb->data[49] = len >> 8;
  230. skb->data[50] = 0x00;
  231. skb->data[51] = 0x80;
  232. for (i = 52; i < 64; i++)
  233. skb->data[i] = 0x00;
  234. return skb;
  235. }
  236. static int ch9200_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  237. {
  238. int len = 0;
  239. int rx_overhead = 0;
  240. rx_overhead = 64;
  241. if (unlikely(skb->len < rx_overhead)) {
  242. dev_err(&dev->udev->dev, "unexpected tiny rx frame\n");
  243. return 0;
  244. }
  245. len = (skb->data[skb->len - 16] | skb->data[skb->len - 15] << 8);
  246. skb_trim(skb, len);
  247. return 1;
  248. }
  249. static int get_mac_address(struct usbnet *dev, unsigned char *data)
  250. {
  251. int err = 0;
  252. unsigned char mac_addr[0x06];
  253. int rd_mac_len = 0;
  254. netdev_dbg(dev->net, "get_mac_address:\n\tusbnet VID:%0x PID:%0x\n",
  255. dev->udev->descriptor.idVendor,
  256. dev->udev->descriptor.idProduct);
  257. memset(mac_addr, 0, sizeof(mac_addr));
  258. rd_mac_len = control_read(dev, REQUEST_READ, 0,
  259. MAC_REG_STATION_L, mac_addr, 0x02,
  260. CONTROL_TIMEOUT_MS);
  261. rd_mac_len += control_read(dev, REQUEST_READ, 0, MAC_REG_STATION_M,
  262. mac_addr + 2, 0x02, CONTROL_TIMEOUT_MS);
  263. rd_mac_len += control_read(dev, REQUEST_READ, 0, MAC_REG_STATION_H,
  264. mac_addr + 4, 0x02, CONTROL_TIMEOUT_MS);
  265. if (rd_mac_len != ETH_ALEN)
  266. err = -EINVAL;
  267. data[0] = mac_addr[5];
  268. data[1] = mac_addr[4];
  269. data[2] = mac_addr[3];
  270. data[3] = mac_addr[2];
  271. data[4] = mac_addr[1];
  272. data[5] = mac_addr[0];
  273. return err;
  274. }
  275. static int ch9200_bind(struct usbnet *dev, struct usb_interface *intf)
  276. {
  277. int retval = 0;
  278. unsigned char data[2];
  279. retval = usbnet_get_endpoints(dev, intf);
  280. if (retval)
  281. return retval;
  282. dev->mii.dev = dev->net;
  283. dev->mii.mdio_read = ch9200_mdio_read;
  284. dev->mii.mdio_write = ch9200_mdio_write;
  285. dev->mii.reg_num_mask = 0x1f;
  286. dev->mii.phy_id_mask = 0x1f;
  287. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  288. dev->rx_urb_size = 24 * 64 + 16;
  289. mii_nway_restart(&dev->mii);
  290. data[0] = 0x01;
  291. data[1] = 0x0F;
  292. retval = control_write(dev, REQUEST_WRITE, 0, MAC_REG_THRESHOLD, data,
  293. 0x02, CONTROL_TIMEOUT_MS);
  294. data[0] = 0xA0;
  295. data[1] = 0x90;
  296. retval = control_write(dev, REQUEST_WRITE, 0, MAC_REG_FIFO_DEPTH, data,
  297. 0x02, CONTROL_TIMEOUT_MS);
  298. data[0] = 0x30;
  299. data[1] = 0x00;
  300. retval = control_write(dev, REQUEST_WRITE, 0, MAC_REG_PAUSE, data,
  301. 0x02, CONTROL_TIMEOUT_MS);
  302. data[0] = 0x17;
  303. data[1] = 0xD8;
  304. retval = control_write(dev, REQUEST_WRITE, 0, MAC_REG_FLOW_CONTROL,
  305. data, 0x02, CONTROL_TIMEOUT_MS);
  306. /* Undocumented register */
  307. data[0] = 0x01;
  308. data[1] = 0x00;
  309. retval = control_write(dev, REQUEST_WRITE, 0, 254, data, 0x02,
  310. CONTROL_TIMEOUT_MS);
  311. data[0] = 0x5F;
  312. data[1] = 0x0D;
  313. retval = control_write(dev, REQUEST_WRITE, 0, MAC_REG_CTRL, data, 0x02,
  314. CONTROL_TIMEOUT_MS);
  315. retval = get_mac_address(dev, dev->net->dev_addr);
  316. return retval;
  317. }
  318. static const struct driver_info ch9200_info = {
  319. .description = "CH9200 USB to Network Adaptor",
  320. .flags = FLAG_ETHER,
  321. .bind = ch9200_bind,
  322. .rx_fixup = ch9200_rx_fixup,
  323. .tx_fixup = ch9200_tx_fixup,
  324. .status = ch9200_status,
  325. .link_reset = ch9200_link_reset,
  326. .reset = ch9200_link_reset,
  327. };
  328. static const struct usb_device_id ch9200_products[] = {
  329. {
  330. USB_DEVICE(0x1A86, 0xE092),
  331. .driver_info = (unsigned long)&ch9200_info,
  332. },
  333. {},
  334. };
  335. MODULE_DEVICE_TABLE(usb, ch9200_products);
  336. static struct usb_driver ch9200_driver = {
  337. .name = "ch9200",
  338. .id_table = ch9200_products,
  339. .probe = usbnet_probe,
  340. .disconnect = usbnet_disconnect,
  341. .suspend = usbnet_suspend,
  342. .resume = usbnet_resume,
  343. };
  344. module_usb_driver(ch9200_driver);
  345. MODULE_DESCRIPTION("QinHeng CH9200 USB Network device");
  346. MODULE_LICENSE("GPL");