r8152.c 100 KB

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  1. /*
  2. * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License
  6. * version 2 as published by the Free Software Foundation.
  7. *
  8. */
  9. #include <linux/signal.h>
  10. #include <linux/slab.h>
  11. #include <linux/module.h>
  12. #include <linux/netdevice.h>
  13. #include <linux/etherdevice.h>
  14. #include <linux/mii.h>
  15. #include <linux/ethtool.h>
  16. #include <linux/usb.h>
  17. #include <linux/crc32.h>
  18. #include <linux/if_vlan.h>
  19. #include <linux/uaccess.h>
  20. #include <linux/list.h>
  21. #include <linux/ip.h>
  22. #include <linux/ipv6.h>
  23. #include <net/ip6_checksum.h>
  24. #include <uapi/linux/mdio.h>
  25. #include <linux/mdio.h>
  26. #include <linux/usb/cdc.h>
  27. #include <linux/suspend.h>
  28. /* Information for net-next */
  29. #define NETNEXT_VERSION "08"
  30. /* Information for net */
  31. #define NET_VERSION "3"
  32. #define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION
  33. #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  34. #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  35. #define MODULENAME "r8152"
  36. #define R8152_PHY_ID 32
  37. #define PLA_IDR 0xc000
  38. #define PLA_RCR 0xc010
  39. #define PLA_RMS 0xc016
  40. #define PLA_RXFIFO_CTRL0 0xc0a0
  41. #define PLA_RXFIFO_CTRL1 0xc0a4
  42. #define PLA_RXFIFO_CTRL2 0xc0a8
  43. #define PLA_DMY_REG0 0xc0b0
  44. #define PLA_FMC 0xc0b4
  45. #define PLA_CFG_WOL 0xc0b6
  46. #define PLA_TEREDO_CFG 0xc0bc
  47. #define PLA_MAR 0xcd00
  48. #define PLA_BACKUP 0xd000
  49. #define PAL_BDC_CR 0xd1a0
  50. #define PLA_TEREDO_TIMER 0xd2cc
  51. #define PLA_REALWOW_TIMER 0xd2e8
  52. #define PLA_LEDSEL 0xdd90
  53. #define PLA_LED_FEATURE 0xdd92
  54. #define PLA_PHYAR 0xde00
  55. #define PLA_BOOT_CTRL 0xe004
  56. #define PLA_GPHY_INTR_IMR 0xe022
  57. #define PLA_EEE_CR 0xe040
  58. #define PLA_EEEP_CR 0xe080
  59. #define PLA_MAC_PWR_CTRL 0xe0c0
  60. #define PLA_MAC_PWR_CTRL2 0xe0ca
  61. #define PLA_MAC_PWR_CTRL3 0xe0cc
  62. #define PLA_MAC_PWR_CTRL4 0xe0ce
  63. #define PLA_WDT6_CTRL 0xe428
  64. #define PLA_TCR0 0xe610
  65. #define PLA_TCR1 0xe612
  66. #define PLA_MTPS 0xe615
  67. #define PLA_TXFIFO_CTRL 0xe618
  68. #define PLA_RSTTALLY 0xe800
  69. #define PLA_CR 0xe813
  70. #define PLA_CRWECR 0xe81c
  71. #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
  72. #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
  73. #define PLA_CONFIG5 0xe822
  74. #define PLA_PHY_PWR 0xe84c
  75. #define PLA_OOB_CTRL 0xe84f
  76. #define PLA_CPCR 0xe854
  77. #define PLA_MISC_0 0xe858
  78. #define PLA_MISC_1 0xe85a
  79. #define PLA_OCP_GPHY_BASE 0xe86c
  80. #define PLA_TALLYCNT 0xe890
  81. #define PLA_SFF_STS_7 0xe8de
  82. #define PLA_PHYSTATUS 0xe908
  83. #define PLA_BP_BA 0xfc26
  84. #define PLA_BP_0 0xfc28
  85. #define PLA_BP_1 0xfc2a
  86. #define PLA_BP_2 0xfc2c
  87. #define PLA_BP_3 0xfc2e
  88. #define PLA_BP_4 0xfc30
  89. #define PLA_BP_5 0xfc32
  90. #define PLA_BP_6 0xfc34
  91. #define PLA_BP_7 0xfc36
  92. #define PLA_BP_EN 0xfc38
  93. #define USB_USB2PHY 0xb41e
  94. #define USB_SSPHYLINK2 0xb428
  95. #define USB_U2P3_CTRL 0xb460
  96. #define USB_CSR_DUMMY1 0xb464
  97. #define USB_CSR_DUMMY2 0xb466
  98. #define USB_DEV_STAT 0xb808
  99. #define USB_CONNECT_TIMER 0xcbf8
  100. #define USB_BURST_SIZE 0xcfc0
  101. #define USB_USB_CTRL 0xd406
  102. #define USB_PHY_CTRL 0xd408
  103. #define USB_TX_AGG 0xd40a
  104. #define USB_RX_BUF_TH 0xd40c
  105. #define USB_USB_TIMER 0xd428
  106. #define USB_RX_EARLY_TIMEOUT 0xd42c
  107. #define USB_RX_EARLY_SIZE 0xd42e
  108. #define USB_PM_CTRL_STATUS 0xd432
  109. #define USB_TX_DMA 0xd434
  110. #define USB_TOLERANCE 0xd490
  111. #define USB_LPM_CTRL 0xd41a
  112. #define USB_UPS_CTRL 0xd800
  113. #define USB_MISC_0 0xd81a
  114. #define USB_POWER_CUT 0xd80a
  115. #define USB_AFE_CTRL2 0xd824
  116. #define USB_WDT11_CTRL 0xe43c
  117. #define USB_BP_BA 0xfc26
  118. #define USB_BP_0 0xfc28
  119. #define USB_BP_1 0xfc2a
  120. #define USB_BP_2 0xfc2c
  121. #define USB_BP_3 0xfc2e
  122. #define USB_BP_4 0xfc30
  123. #define USB_BP_5 0xfc32
  124. #define USB_BP_6 0xfc34
  125. #define USB_BP_7 0xfc36
  126. #define USB_BP_EN 0xfc38
  127. /* OCP Registers */
  128. #define OCP_ALDPS_CONFIG 0x2010
  129. #define OCP_EEE_CONFIG1 0x2080
  130. #define OCP_EEE_CONFIG2 0x2092
  131. #define OCP_EEE_CONFIG3 0x2094
  132. #define OCP_BASE_MII 0xa400
  133. #define OCP_EEE_AR 0xa41a
  134. #define OCP_EEE_DATA 0xa41c
  135. #define OCP_PHY_STATUS 0xa420
  136. #define OCP_POWER_CFG 0xa430
  137. #define OCP_EEE_CFG 0xa432
  138. #define OCP_SRAM_ADDR 0xa436
  139. #define OCP_SRAM_DATA 0xa438
  140. #define OCP_DOWN_SPEED 0xa442
  141. #define OCP_EEE_ABLE 0xa5c4
  142. #define OCP_EEE_ADV 0xa5d0
  143. #define OCP_EEE_LPABLE 0xa5d2
  144. #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
  145. #define OCP_ADC_CFG 0xbc06
  146. /* SRAM Register */
  147. #define SRAM_LPF_CFG 0x8012
  148. #define SRAM_10M_AMP1 0x8080
  149. #define SRAM_10M_AMP2 0x8082
  150. #define SRAM_IMPEDANCE 0x8084
  151. /* PLA_RCR */
  152. #define RCR_AAP 0x00000001
  153. #define RCR_APM 0x00000002
  154. #define RCR_AM 0x00000004
  155. #define RCR_AB 0x00000008
  156. #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
  157. /* PLA_RXFIFO_CTRL0 */
  158. #define RXFIFO_THR1_NORMAL 0x00080002
  159. #define RXFIFO_THR1_OOB 0x01800003
  160. /* PLA_RXFIFO_CTRL1 */
  161. #define RXFIFO_THR2_FULL 0x00000060
  162. #define RXFIFO_THR2_HIGH 0x00000038
  163. #define RXFIFO_THR2_OOB 0x0000004a
  164. #define RXFIFO_THR2_NORMAL 0x00a0
  165. /* PLA_RXFIFO_CTRL2 */
  166. #define RXFIFO_THR3_FULL 0x00000078
  167. #define RXFIFO_THR3_HIGH 0x00000048
  168. #define RXFIFO_THR3_OOB 0x0000005a
  169. #define RXFIFO_THR3_NORMAL 0x0110
  170. /* PLA_TXFIFO_CTRL */
  171. #define TXFIFO_THR_NORMAL 0x00400008
  172. #define TXFIFO_THR_NORMAL2 0x01000008
  173. /* PLA_DMY_REG0 */
  174. #define ECM_ALDPS 0x0002
  175. /* PLA_FMC */
  176. #define FMC_FCR_MCU_EN 0x0001
  177. /* PLA_EEEP_CR */
  178. #define EEEP_CR_EEEP_TX 0x0002
  179. /* PLA_WDT6_CTRL */
  180. #define WDT6_SET_MODE 0x0010
  181. /* PLA_TCR0 */
  182. #define TCR0_TX_EMPTY 0x0800
  183. #define TCR0_AUTO_FIFO 0x0080
  184. /* PLA_TCR1 */
  185. #define VERSION_MASK 0x7cf0
  186. /* PLA_MTPS */
  187. #define MTPS_JUMBO (12 * 1024 / 64)
  188. #define MTPS_DEFAULT (6 * 1024 / 64)
  189. /* PLA_RSTTALLY */
  190. #define TALLY_RESET 0x0001
  191. /* PLA_CR */
  192. #define CR_RST 0x10
  193. #define CR_RE 0x08
  194. #define CR_TE 0x04
  195. /* PLA_CRWECR */
  196. #define CRWECR_NORAML 0x00
  197. #define CRWECR_CONFIG 0xc0
  198. /* PLA_OOB_CTRL */
  199. #define NOW_IS_OOB 0x80
  200. #define TXFIFO_EMPTY 0x20
  201. #define RXFIFO_EMPTY 0x10
  202. #define LINK_LIST_READY 0x02
  203. #define DIS_MCU_CLROOB 0x01
  204. #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
  205. /* PLA_MISC_1 */
  206. #define RXDY_GATED_EN 0x0008
  207. /* PLA_SFF_STS_7 */
  208. #define RE_INIT_LL 0x8000
  209. #define MCU_BORW_EN 0x4000
  210. /* PLA_CPCR */
  211. #define CPCR_RX_VLAN 0x0040
  212. /* PLA_CFG_WOL */
  213. #define MAGIC_EN 0x0001
  214. /* PLA_TEREDO_CFG */
  215. #define TEREDO_SEL 0x8000
  216. #define TEREDO_WAKE_MASK 0x7f00
  217. #define TEREDO_RS_EVENT_MASK 0x00fe
  218. #define OOB_TEREDO_EN 0x0001
  219. /* PAL_BDC_CR */
  220. #define ALDPS_PROXY_MODE 0x0001
  221. /* PLA_CONFIG34 */
  222. #define LINK_ON_WAKE_EN 0x0010
  223. #define LINK_OFF_WAKE_EN 0x0008
  224. /* PLA_CONFIG5 */
  225. #define BWF_EN 0x0040
  226. #define MWF_EN 0x0020
  227. #define UWF_EN 0x0010
  228. #define LAN_WAKE_EN 0x0002
  229. /* PLA_LED_FEATURE */
  230. #define LED_MODE_MASK 0x0700
  231. /* PLA_PHY_PWR */
  232. #define TX_10M_IDLE_EN 0x0080
  233. #define PFM_PWM_SWITCH 0x0040
  234. /* PLA_MAC_PWR_CTRL */
  235. #define D3_CLK_GATED_EN 0x00004000
  236. #define MCU_CLK_RATIO 0x07010f07
  237. #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
  238. #define ALDPS_SPDWN_RATIO 0x0f87
  239. /* PLA_MAC_PWR_CTRL2 */
  240. #define EEE_SPDWN_RATIO 0x8007
  241. /* PLA_MAC_PWR_CTRL3 */
  242. #define PKT_AVAIL_SPDWN_EN 0x0100
  243. #define SUSPEND_SPDWN_EN 0x0004
  244. #define U1U2_SPDWN_EN 0x0002
  245. #define L1_SPDWN_EN 0x0001
  246. /* PLA_MAC_PWR_CTRL4 */
  247. #define PWRSAVE_SPDWN_EN 0x1000
  248. #define RXDV_SPDWN_EN 0x0800
  249. #define TX10MIDLE_EN 0x0100
  250. #define TP100_SPDWN_EN 0x0020
  251. #define TP500_SPDWN_EN 0x0010
  252. #define TP1000_SPDWN_EN 0x0008
  253. #define EEE_SPDWN_EN 0x0001
  254. /* PLA_GPHY_INTR_IMR */
  255. #define GPHY_STS_MSK 0x0001
  256. #define SPEED_DOWN_MSK 0x0002
  257. #define SPDWN_RXDV_MSK 0x0004
  258. #define SPDWN_LINKCHG_MSK 0x0008
  259. /* PLA_PHYAR */
  260. #define PHYAR_FLAG 0x80000000
  261. /* PLA_EEE_CR */
  262. #define EEE_RX_EN 0x0001
  263. #define EEE_TX_EN 0x0002
  264. /* PLA_BOOT_CTRL */
  265. #define AUTOLOAD_DONE 0x0002
  266. /* USB_USB2PHY */
  267. #define USB2PHY_SUSPEND 0x0001
  268. #define USB2PHY_L1 0x0002
  269. /* USB_SSPHYLINK2 */
  270. #define pwd_dn_scale_mask 0x3ffe
  271. #define pwd_dn_scale(x) ((x) << 1)
  272. /* USB_CSR_DUMMY1 */
  273. #define DYNAMIC_BURST 0x0001
  274. /* USB_CSR_DUMMY2 */
  275. #define EP4_FULL_FC 0x0001
  276. /* USB_DEV_STAT */
  277. #define STAT_SPEED_MASK 0x0006
  278. #define STAT_SPEED_HIGH 0x0000
  279. #define STAT_SPEED_FULL 0x0002
  280. /* USB_TX_AGG */
  281. #define TX_AGG_MAX_THRESHOLD 0x03
  282. /* USB_RX_BUF_TH */
  283. #define RX_THR_SUPPER 0x0c350180
  284. #define RX_THR_HIGH 0x7a120180
  285. #define RX_THR_SLOW 0xffff0180
  286. /* USB_TX_DMA */
  287. #define TEST_MODE_DISABLE 0x00000001
  288. #define TX_SIZE_ADJUST1 0x00000100
  289. /* USB_UPS_CTRL */
  290. #define POWER_CUT 0x0100
  291. /* USB_PM_CTRL_STATUS */
  292. #define RESUME_INDICATE 0x0001
  293. /* USB_USB_CTRL */
  294. #define RX_AGG_DISABLE 0x0010
  295. #define RX_ZERO_EN 0x0080
  296. /* USB_U2P3_CTRL */
  297. #define U2P3_ENABLE 0x0001
  298. /* USB_POWER_CUT */
  299. #define PWR_EN 0x0001
  300. #define PHASE2_EN 0x0008
  301. /* USB_MISC_0 */
  302. #define PCUT_STATUS 0x0001
  303. /* USB_RX_EARLY_TIMEOUT */
  304. #define COALESCE_SUPER 85000U
  305. #define COALESCE_HIGH 250000U
  306. #define COALESCE_SLOW 524280U
  307. /* USB_WDT11_CTRL */
  308. #define TIMER11_EN 0x0001
  309. /* USB_LPM_CTRL */
  310. /* bit 4 ~ 5: fifo empty boundary */
  311. #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
  312. /* bit 2 ~ 3: LMP timer */
  313. #define LPM_TIMER_MASK 0x0c
  314. #define LPM_TIMER_500MS 0x04 /* 500 ms */
  315. #define LPM_TIMER_500US 0x0c /* 500 us */
  316. #define ROK_EXIT_LPM 0x02
  317. /* USB_AFE_CTRL2 */
  318. #define SEN_VAL_MASK 0xf800
  319. #define SEN_VAL_NORMAL 0xa000
  320. #define SEL_RXIDLE 0x0100
  321. /* OCP_ALDPS_CONFIG */
  322. #define ENPWRSAVE 0x8000
  323. #define ENPDNPS 0x0200
  324. #define LINKENA 0x0100
  325. #define DIS_SDSAVE 0x0010
  326. /* OCP_PHY_STATUS */
  327. #define PHY_STAT_MASK 0x0007
  328. #define PHY_STAT_LAN_ON 3
  329. #define PHY_STAT_PWRDN 5
  330. /* OCP_POWER_CFG */
  331. #define EEE_CLKDIV_EN 0x8000
  332. #define EN_ALDPS 0x0004
  333. #define EN_10M_PLLOFF 0x0001
  334. /* OCP_EEE_CONFIG1 */
  335. #define RG_TXLPI_MSK_HFDUP 0x8000
  336. #define RG_MATCLR_EN 0x4000
  337. #define EEE_10_CAP 0x2000
  338. #define EEE_NWAY_EN 0x1000
  339. #define TX_QUIET_EN 0x0200
  340. #define RX_QUIET_EN 0x0100
  341. #define sd_rise_time_mask 0x0070
  342. #define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */
  343. #define RG_RXLPI_MSK_HFDUP 0x0008
  344. #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
  345. /* OCP_EEE_CONFIG2 */
  346. #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
  347. #define RG_DACQUIET_EN 0x0400
  348. #define RG_LDVQUIET_EN 0x0200
  349. #define RG_CKRSEL 0x0020
  350. #define RG_EEEPRG_EN 0x0010
  351. /* OCP_EEE_CONFIG3 */
  352. #define fast_snr_mask 0xff80
  353. #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
  354. #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
  355. #define MSK_PH 0x0006 /* bit 0 ~ 3 */
  356. /* OCP_EEE_AR */
  357. /* bit[15:14] function */
  358. #define FUN_ADDR 0x0000
  359. #define FUN_DATA 0x4000
  360. /* bit[4:0] device addr */
  361. /* OCP_EEE_CFG */
  362. #define CTAP_SHORT_EN 0x0040
  363. #define EEE10_EN 0x0010
  364. /* OCP_DOWN_SPEED */
  365. #define EN_10M_BGOFF 0x0080
  366. /* OCP_PHY_STATE */
  367. #define TXDIS_STATE 0x01
  368. #define ABD_STATE 0x02
  369. /* OCP_ADC_CFG */
  370. #define CKADSEL_L 0x0100
  371. #define ADC_EN 0x0080
  372. #define EN_EMI_L 0x0040
  373. /* SRAM_LPF_CFG */
  374. #define LPF_AUTO_TUNE 0x8000
  375. /* SRAM_10M_AMP1 */
  376. #define GDAC_IB_UPALL 0x0008
  377. /* SRAM_10M_AMP2 */
  378. #define AMP_DN 0x0200
  379. /* SRAM_IMPEDANCE */
  380. #define RX_DRIVING_MASK 0x6000
  381. enum rtl_register_content {
  382. _1000bps = 0x10,
  383. _100bps = 0x08,
  384. _10bps = 0x04,
  385. LINK_STATUS = 0x02,
  386. FULL_DUP = 0x01,
  387. };
  388. #define RTL8152_MAX_TX 4
  389. #define RTL8152_MAX_RX 10
  390. #define INTBUFSIZE 2
  391. #define CRC_SIZE 4
  392. #define TX_ALIGN 4
  393. #define RX_ALIGN 8
  394. #define INTR_LINK 0x0004
  395. #define RTL8152_REQT_READ 0xc0
  396. #define RTL8152_REQT_WRITE 0x40
  397. #define RTL8152_REQ_GET_REGS 0x05
  398. #define RTL8152_REQ_SET_REGS 0x05
  399. #define BYTE_EN_DWORD 0xff
  400. #define BYTE_EN_WORD 0x33
  401. #define BYTE_EN_BYTE 0x11
  402. #define BYTE_EN_SIX_BYTES 0x3f
  403. #define BYTE_EN_START_MASK 0x0f
  404. #define BYTE_EN_END_MASK 0xf0
  405. #define RTL8153_MAX_PACKET 9216 /* 9K */
  406. #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
  407. #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
  408. #define RTL8153_RMS RTL8153_MAX_PACKET
  409. #define RTL8152_TX_TIMEOUT (5 * HZ)
  410. #define RTL8152_NAPI_WEIGHT 64
  411. /* rtl8152 flags */
  412. enum rtl8152_flags {
  413. RTL8152_UNPLUG = 0,
  414. RTL8152_SET_RX_MODE,
  415. WORK_ENABLE,
  416. RTL8152_LINK_CHG,
  417. SELECTIVE_SUSPEND,
  418. PHY_RESET,
  419. SCHEDULE_NAPI,
  420. };
  421. /* Define these values to match your device */
  422. #define VENDOR_ID_REALTEK 0x0bda
  423. #define VENDOR_ID_SAMSUNG 0x04e8
  424. #define VENDOR_ID_LENOVO 0x17ef
  425. #define VENDOR_ID_LINKSYS 0x13b1
  426. #define VENDOR_ID_NVIDIA 0x0955
  427. #define MCU_TYPE_PLA 0x0100
  428. #define MCU_TYPE_USB 0x0000
  429. struct tally_counter {
  430. __le64 tx_packets;
  431. __le64 rx_packets;
  432. __le64 tx_errors;
  433. __le32 rx_errors;
  434. __le16 rx_missed;
  435. __le16 align_errors;
  436. __le32 tx_one_collision;
  437. __le32 tx_multi_collision;
  438. __le64 rx_unicast;
  439. __le64 rx_broadcast;
  440. __le32 rx_multicast;
  441. __le16 tx_aborted;
  442. __le16 tx_underrun;
  443. };
  444. struct rx_desc {
  445. __le32 opts1;
  446. #define RX_LEN_MASK 0x7fff
  447. __le32 opts2;
  448. #define RD_UDP_CS BIT(23)
  449. #define RD_TCP_CS BIT(22)
  450. #define RD_IPV6_CS BIT(20)
  451. #define RD_IPV4_CS BIT(19)
  452. __le32 opts3;
  453. #define IPF BIT(23) /* IP checksum fail */
  454. #define UDPF BIT(22) /* UDP checksum fail */
  455. #define TCPF BIT(21) /* TCP checksum fail */
  456. #define RX_VLAN_TAG BIT(16)
  457. __le32 opts4;
  458. __le32 opts5;
  459. __le32 opts6;
  460. };
  461. struct tx_desc {
  462. __le32 opts1;
  463. #define TX_FS BIT(31) /* First segment of a packet */
  464. #define TX_LS BIT(30) /* Final segment of a packet */
  465. #define GTSENDV4 BIT(28)
  466. #define GTSENDV6 BIT(27)
  467. #define GTTCPHO_SHIFT 18
  468. #define GTTCPHO_MAX 0x7fU
  469. #define TX_LEN_MAX 0x3ffffU
  470. __le32 opts2;
  471. #define UDP_CS BIT(31) /* Calculate UDP/IP checksum */
  472. #define TCP_CS BIT(30) /* Calculate TCP/IP checksum */
  473. #define IPV4_CS BIT(29) /* Calculate IPv4 checksum */
  474. #define IPV6_CS BIT(28) /* Calculate IPv6 checksum */
  475. #define MSS_SHIFT 17
  476. #define MSS_MAX 0x7ffU
  477. #define TCPHO_SHIFT 17
  478. #define TCPHO_MAX 0x7ffU
  479. #define TX_VLAN_TAG BIT(16)
  480. };
  481. struct r8152;
  482. struct rx_agg {
  483. struct list_head list;
  484. struct urb *urb;
  485. struct r8152 *context;
  486. void *buffer;
  487. void *head;
  488. };
  489. struct tx_agg {
  490. struct list_head list;
  491. struct urb *urb;
  492. struct r8152 *context;
  493. void *buffer;
  494. void *head;
  495. u32 skb_num;
  496. u32 skb_len;
  497. };
  498. struct r8152 {
  499. unsigned long flags;
  500. struct usb_device *udev;
  501. struct napi_struct napi;
  502. struct usb_interface *intf;
  503. struct net_device *netdev;
  504. struct urb *intr_urb;
  505. struct tx_agg tx_info[RTL8152_MAX_TX];
  506. struct rx_agg rx_info[RTL8152_MAX_RX];
  507. struct list_head rx_done, tx_free;
  508. struct sk_buff_head tx_queue, rx_queue;
  509. spinlock_t rx_lock, tx_lock;
  510. struct delayed_work schedule;
  511. struct mii_if_info mii;
  512. struct mutex control; /* use for hw setting */
  513. #ifdef CONFIG_PM_SLEEP
  514. struct notifier_block pm_notifier;
  515. #endif
  516. struct rtl_ops {
  517. void (*init)(struct r8152 *);
  518. int (*enable)(struct r8152 *);
  519. void (*disable)(struct r8152 *);
  520. void (*up)(struct r8152 *);
  521. void (*down)(struct r8152 *);
  522. void (*unload)(struct r8152 *);
  523. int (*eee_get)(struct r8152 *, struct ethtool_eee *);
  524. int (*eee_set)(struct r8152 *, struct ethtool_eee *);
  525. bool (*in_nway)(struct r8152 *);
  526. } rtl_ops;
  527. int intr_interval;
  528. u32 saved_wolopts;
  529. u32 msg_enable;
  530. u32 tx_qlen;
  531. u32 coalesce;
  532. u16 ocp_base;
  533. u8 *intr_buff;
  534. u8 version;
  535. };
  536. enum rtl_version {
  537. RTL_VER_UNKNOWN = 0,
  538. RTL_VER_01,
  539. RTL_VER_02,
  540. RTL_VER_03,
  541. RTL_VER_04,
  542. RTL_VER_05,
  543. RTL_VER_06,
  544. RTL_VER_MAX
  545. };
  546. enum tx_csum_stat {
  547. TX_CSUM_SUCCESS = 0,
  548. TX_CSUM_TSO,
  549. TX_CSUM_NONE
  550. };
  551. /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  552. * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  553. */
  554. static const int multicast_filter_limit = 32;
  555. static unsigned int agg_buf_sz = 16384;
  556. #define RTL_LIMITED_TSO_SIZE (agg_buf_sz - sizeof(struct tx_desc) - \
  557. VLAN_ETH_HLEN - VLAN_HLEN)
  558. static
  559. int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  560. {
  561. int ret;
  562. void *tmp;
  563. tmp = kmalloc(size, GFP_KERNEL);
  564. if (!tmp)
  565. return -ENOMEM;
  566. ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
  567. RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
  568. value, index, tmp, size, 500);
  569. memcpy(data, tmp, size);
  570. kfree(tmp);
  571. return ret;
  572. }
  573. static
  574. int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
  575. {
  576. int ret;
  577. void *tmp;
  578. tmp = kmemdup(data, size, GFP_KERNEL);
  579. if (!tmp)
  580. return -ENOMEM;
  581. ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
  582. RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
  583. value, index, tmp, size, 500);
  584. kfree(tmp);
  585. return ret;
  586. }
  587. static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
  588. void *data, u16 type)
  589. {
  590. u16 limit = 64;
  591. int ret = 0;
  592. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  593. return -ENODEV;
  594. /* both size and indix must be 4 bytes align */
  595. if ((size & 3) || !size || (index & 3) || !data)
  596. return -EPERM;
  597. if ((u32)index + (u32)size > 0xffff)
  598. return -EPERM;
  599. while (size) {
  600. if (size > limit) {
  601. ret = get_registers(tp, index, type, limit, data);
  602. if (ret < 0)
  603. break;
  604. index += limit;
  605. data += limit;
  606. size -= limit;
  607. } else {
  608. ret = get_registers(tp, index, type, size, data);
  609. if (ret < 0)
  610. break;
  611. index += size;
  612. data += size;
  613. size = 0;
  614. break;
  615. }
  616. }
  617. if (ret == -ENODEV)
  618. set_bit(RTL8152_UNPLUG, &tp->flags);
  619. return ret;
  620. }
  621. static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
  622. u16 size, void *data, u16 type)
  623. {
  624. int ret;
  625. u16 byteen_start, byteen_end, byen;
  626. u16 limit = 512;
  627. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  628. return -ENODEV;
  629. /* both size and indix must be 4 bytes align */
  630. if ((size & 3) || !size || (index & 3) || !data)
  631. return -EPERM;
  632. if ((u32)index + (u32)size > 0xffff)
  633. return -EPERM;
  634. byteen_start = byteen & BYTE_EN_START_MASK;
  635. byteen_end = byteen & BYTE_EN_END_MASK;
  636. byen = byteen_start | (byteen_start << 4);
  637. ret = set_registers(tp, index, type | byen, 4, data);
  638. if (ret < 0)
  639. goto error1;
  640. index += 4;
  641. data += 4;
  642. size -= 4;
  643. if (size) {
  644. size -= 4;
  645. while (size) {
  646. if (size > limit) {
  647. ret = set_registers(tp, index,
  648. type | BYTE_EN_DWORD,
  649. limit, data);
  650. if (ret < 0)
  651. goto error1;
  652. index += limit;
  653. data += limit;
  654. size -= limit;
  655. } else {
  656. ret = set_registers(tp, index,
  657. type | BYTE_EN_DWORD,
  658. size, data);
  659. if (ret < 0)
  660. goto error1;
  661. index += size;
  662. data += size;
  663. size = 0;
  664. break;
  665. }
  666. }
  667. byen = byteen_end | (byteen_end >> 4);
  668. ret = set_registers(tp, index, type | byen, 4, data);
  669. if (ret < 0)
  670. goto error1;
  671. }
  672. error1:
  673. if (ret == -ENODEV)
  674. set_bit(RTL8152_UNPLUG, &tp->flags);
  675. return ret;
  676. }
  677. static inline
  678. int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  679. {
  680. return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
  681. }
  682. static inline
  683. int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  684. {
  685. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
  686. }
  687. static inline
  688. int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
  689. {
  690. return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
  691. }
  692. static inline
  693. int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
  694. {
  695. return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
  696. }
  697. static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
  698. {
  699. __le32 data;
  700. generic_ocp_read(tp, index, sizeof(data), &data, type);
  701. return __le32_to_cpu(data);
  702. }
  703. static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
  704. {
  705. __le32 tmp = __cpu_to_le32(data);
  706. generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
  707. }
  708. static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
  709. {
  710. u32 data;
  711. __le32 tmp;
  712. u8 shift = index & 2;
  713. index &= ~3;
  714. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  715. data = __le32_to_cpu(tmp);
  716. data >>= (shift * 8);
  717. data &= 0xffff;
  718. return (u16)data;
  719. }
  720. static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
  721. {
  722. u32 mask = 0xffff;
  723. __le32 tmp;
  724. u16 byen = BYTE_EN_WORD;
  725. u8 shift = index & 2;
  726. data &= mask;
  727. if (index & 2) {
  728. byen <<= shift;
  729. mask <<= (shift * 8);
  730. data <<= (shift * 8);
  731. index &= ~3;
  732. }
  733. tmp = __cpu_to_le32(data);
  734. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  735. }
  736. static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
  737. {
  738. u32 data;
  739. __le32 tmp;
  740. u8 shift = index & 3;
  741. index &= ~3;
  742. generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
  743. data = __le32_to_cpu(tmp);
  744. data >>= (shift * 8);
  745. data &= 0xff;
  746. return (u8)data;
  747. }
  748. static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
  749. {
  750. u32 mask = 0xff;
  751. __le32 tmp;
  752. u16 byen = BYTE_EN_BYTE;
  753. u8 shift = index & 3;
  754. data &= mask;
  755. if (index & 3) {
  756. byen <<= shift;
  757. mask <<= (shift * 8);
  758. data <<= (shift * 8);
  759. index &= ~3;
  760. }
  761. tmp = __cpu_to_le32(data);
  762. generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
  763. }
  764. static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
  765. {
  766. u16 ocp_base, ocp_index;
  767. ocp_base = addr & 0xf000;
  768. if (ocp_base != tp->ocp_base) {
  769. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  770. tp->ocp_base = ocp_base;
  771. }
  772. ocp_index = (addr & 0x0fff) | 0xb000;
  773. return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
  774. }
  775. static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
  776. {
  777. u16 ocp_base, ocp_index;
  778. ocp_base = addr & 0xf000;
  779. if (ocp_base != tp->ocp_base) {
  780. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
  781. tp->ocp_base = ocp_base;
  782. }
  783. ocp_index = (addr & 0x0fff) | 0xb000;
  784. ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
  785. }
  786. static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
  787. {
  788. ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
  789. }
  790. static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
  791. {
  792. return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
  793. }
  794. static void sram_write(struct r8152 *tp, u16 addr, u16 data)
  795. {
  796. ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
  797. ocp_reg_write(tp, OCP_SRAM_DATA, data);
  798. }
  799. static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
  800. {
  801. struct r8152 *tp = netdev_priv(netdev);
  802. int ret;
  803. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  804. return -ENODEV;
  805. if (phy_id != R8152_PHY_ID)
  806. return -EINVAL;
  807. ret = r8152_mdio_read(tp, reg);
  808. return ret;
  809. }
  810. static
  811. void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
  812. {
  813. struct r8152 *tp = netdev_priv(netdev);
  814. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  815. return;
  816. if (phy_id != R8152_PHY_ID)
  817. return;
  818. r8152_mdio_write(tp, reg, val);
  819. }
  820. static int
  821. r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
  822. static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
  823. {
  824. struct r8152 *tp = netdev_priv(netdev);
  825. struct sockaddr *addr = p;
  826. int ret = -EADDRNOTAVAIL;
  827. if (!is_valid_ether_addr(addr->sa_data))
  828. goto out1;
  829. ret = usb_autopm_get_interface(tp->intf);
  830. if (ret < 0)
  831. goto out1;
  832. mutex_lock(&tp->control);
  833. memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
  834. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  835. pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
  836. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  837. mutex_unlock(&tp->control);
  838. usb_autopm_put_interface(tp->intf);
  839. out1:
  840. return ret;
  841. }
  842. static int set_ethernet_addr(struct r8152 *tp)
  843. {
  844. struct net_device *dev = tp->netdev;
  845. struct sockaddr sa;
  846. int ret;
  847. if (tp->version == RTL_VER_01)
  848. ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
  849. else
  850. ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
  851. if (ret < 0) {
  852. netif_err(tp, probe, dev, "Get ether addr fail\n");
  853. } else if (!is_valid_ether_addr(sa.sa_data)) {
  854. netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
  855. sa.sa_data);
  856. eth_hw_addr_random(dev);
  857. ether_addr_copy(sa.sa_data, dev->dev_addr);
  858. ret = rtl8152_set_mac_address(dev, &sa);
  859. netif_info(tp, probe, dev, "Random ether addr %pM\n",
  860. sa.sa_data);
  861. } else {
  862. if (tp->version == RTL_VER_01)
  863. ether_addr_copy(dev->dev_addr, sa.sa_data);
  864. else
  865. ret = rtl8152_set_mac_address(dev, &sa);
  866. }
  867. return ret;
  868. }
  869. static void read_bulk_callback(struct urb *urb)
  870. {
  871. struct net_device *netdev;
  872. int status = urb->status;
  873. struct rx_agg *agg;
  874. struct r8152 *tp;
  875. agg = urb->context;
  876. if (!agg)
  877. return;
  878. tp = agg->context;
  879. if (!tp)
  880. return;
  881. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  882. return;
  883. if (!test_bit(WORK_ENABLE, &tp->flags))
  884. return;
  885. netdev = tp->netdev;
  886. /* When link down, the driver would cancel all bulks. */
  887. /* This avoid the re-submitting bulk */
  888. if (!netif_carrier_ok(netdev))
  889. return;
  890. usb_mark_last_busy(tp->udev);
  891. switch (status) {
  892. case 0:
  893. if (urb->actual_length < ETH_ZLEN)
  894. break;
  895. spin_lock(&tp->rx_lock);
  896. list_add_tail(&agg->list, &tp->rx_done);
  897. spin_unlock(&tp->rx_lock);
  898. napi_schedule(&tp->napi);
  899. return;
  900. case -ESHUTDOWN:
  901. set_bit(RTL8152_UNPLUG, &tp->flags);
  902. netif_device_detach(tp->netdev);
  903. return;
  904. case -ENOENT:
  905. return; /* the urb is in unlink state */
  906. case -ETIME:
  907. if (net_ratelimit())
  908. netdev_warn(netdev, "maybe reset is needed?\n");
  909. break;
  910. default:
  911. if (net_ratelimit())
  912. netdev_warn(netdev, "Rx status %d\n", status);
  913. break;
  914. }
  915. r8152_submit_rx(tp, agg, GFP_ATOMIC);
  916. }
  917. static void write_bulk_callback(struct urb *urb)
  918. {
  919. struct net_device_stats *stats;
  920. struct net_device *netdev;
  921. struct tx_agg *agg;
  922. struct r8152 *tp;
  923. int status = urb->status;
  924. agg = urb->context;
  925. if (!agg)
  926. return;
  927. tp = agg->context;
  928. if (!tp)
  929. return;
  930. netdev = tp->netdev;
  931. stats = &netdev->stats;
  932. if (status) {
  933. if (net_ratelimit())
  934. netdev_warn(netdev, "Tx status %d\n", status);
  935. stats->tx_errors += agg->skb_num;
  936. } else {
  937. stats->tx_packets += agg->skb_num;
  938. stats->tx_bytes += agg->skb_len;
  939. }
  940. spin_lock(&tp->tx_lock);
  941. list_add_tail(&agg->list, &tp->tx_free);
  942. spin_unlock(&tp->tx_lock);
  943. usb_autopm_put_interface_async(tp->intf);
  944. if (!netif_carrier_ok(netdev))
  945. return;
  946. if (!test_bit(WORK_ENABLE, &tp->flags))
  947. return;
  948. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  949. return;
  950. if (!skb_queue_empty(&tp->tx_queue))
  951. napi_schedule(&tp->napi);
  952. }
  953. static void intr_callback(struct urb *urb)
  954. {
  955. struct r8152 *tp;
  956. __le16 *d;
  957. int status = urb->status;
  958. int res;
  959. tp = urb->context;
  960. if (!tp)
  961. return;
  962. if (!test_bit(WORK_ENABLE, &tp->flags))
  963. return;
  964. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  965. return;
  966. switch (status) {
  967. case 0: /* success */
  968. break;
  969. case -ECONNRESET: /* unlink */
  970. case -ESHUTDOWN:
  971. netif_device_detach(tp->netdev);
  972. case -ENOENT:
  973. case -EPROTO:
  974. netif_info(tp, intr, tp->netdev,
  975. "Stop submitting intr, status %d\n", status);
  976. return;
  977. case -EOVERFLOW:
  978. netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
  979. goto resubmit;
  980. /* -EPIPE: should clear the halt */
  981. default:
  982. netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
  983. goto resubmit;
  984. }
  985. d = urb->transfer_buffer;
  986. if (INTR_LINK & __le16_to_cpu(d[0])) {
  987. if (!netif_carrier_ok(tp->netdev)) {
  988. set_bit(RTL8152_LINK_CHG, &tp->flags);
  989. schedule_delayed_work(&tp->schedule, 0);
  990. }
  991. } else {
  992. if (netif_carrier_ok(tp->netdev)) {
  993. netif_stop_queue(tp->netdev);
  994. set_bit(RTL8152_LINK_CHG, &tp->flags);
  995. schedule_delayed_work(&tp->schedule, 0);
  996. }
  997. }
  998. resubmit:
  999. res = usb_submit_urb(urb, GFP_ATOMIC);
  1000. if (res == -ENODEV) {
  1001. set_bit(RTL8152_UNPLUG, &tp->flags);
  1002. netif_device_detach(tp->netdev);
  1003. } else if (res) {
  1004. netif_err(tp, intr, tp->netdev,
  1005. "can't resubmit intr, status %d\n", res);
  1006. }
  1007. }
  1008. static inline void *rx_agg_align(void *data)
  1009. {
  1010. return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
  1011. }
  1012. static inline void *tx_agg_align(void *data)
  1013. {
  1014. return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
  1015. }
  1016. static void free_all_mem(struct r8152 *tp)
  1017. {
  1018. int i;
  1019. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1020. usb_free_urb(tp->rx_info[i].urb);
  1021. tp->rx_info[i].urb = NULL;
  1022. kfree(tp->rx_info[i].buffer);
  1023. tp->rx_info[i].buffer = NULL;
  1024. tp->rx_info[i].head = NULL;
  1025. }
  1026. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1027. usb_free_urb(tp->tx_info[i].urb);
  1028. tp->tx_info[i].urb = NULL;
  1029. kfree(tp->tx_info[i].buffer);
  1030. tp->tx_info[i].buffer = NULL;
  1031. tp->tx_info[i].head = NULL;
  1032. }
  1033. usb_free_urb(tp->intr_urb);
  1034. tp->intr_urb = NULL;
  1035. kfree(tp->intr_buff);
  1036. tp->intr_buff = NULL;
  1037. }
  1038. static int alloc_all_mem(struct r8152 *tp)
  1039. {
  1040. struct net_device *netdev = tp->netdev;
  1041. struct usb_interface *intf = tp->intf;
  1042. struct usb_host_interface *alt = intf->cur_altsetting;
  1043. struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
  1044. struct urb *urb;
  1045. int node, i;
  1046. u8 *buf;
  1047. node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
  1048. spin_lock_init(&tp->rx_lock);
  1049. spin_lock_init(&tp->tx_lock);
  1050. INIT_LIST_HEAD(&tp->tx_free);
  1051. INIT_LIST_HEAD(&tp->rx_done);
  1052. skb_queue_head_init(&tp->tx_queue);
  1053. skb_queue_head_init(&tp->rx_queue);
  1054. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1055. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1056. if (!buf)
  1057. goto err1;
  1058. if (buf != rx_agg_align(buf)) {
  1059. kfree(buf);
  1060. buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
  1061. node);
  1062. if (!buf)
  1063. goto err1;
  1064. }
  1065. urb = usb_alloc_urb(0, GFP_KERNEL);
  1066. if (!urb) {
  1067. kfree(buf);
  1068. goto err1;
  1069. }
  1070. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1071. tp->rx_info[i].context = tp;
  1072. tp->rx_info[i].urb = urb;
  1073. tp->rx_info[i].buffer = buf;
  1074. tp->rx_info[i].head = rx_agg_align(buf);
  1075. }
  1076. for (i = 0; i < RTL8152_MAX_TX; i++) {
  1077. buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
  1078. if (!buf)
  1079. goto err1;
  1080. if (buf != tx_agg_align(buf)) {
  1081. kfree(buf);
  1082. buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
  1083. node);
  1084. if (!buf)
  1085. goto err1;
  1086. }
  1087. urb = usb_alloc_urb(0, GFP_KERNEL);
  1088. if (!urb) {
  1089. kfree(buf);
  1090. goto err1;
  1091. }
  1092. INIT_LIST_HEAD(&tp->tx_info[i].list);
  1093. tp->tx_info[i].context = tp;
  1094. tp->tx_info[i].urb = urb;
  1095. tp->tx_info[i].buffer = buf;
  1096. tp->tx_info[i].head = tx_agg_align(buf);
  1097. list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
  1098. }
  1099. tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
  1100. if (!tp->intr_urb)
  1101. goto err1;
  1102. tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
  1103. if (!tp->intr_buff)
  1104. goto err1;
  1105. tp->intr_interval = (int)ep_intr->desc.bInterval;
  1106. usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
  1107. tp->intr_buff, INTBUFSIZE, intr_callback,
  1108. tp, tp->intr_interval);
  1109. return 0;
  1110. err1:
  1111. free_all_mem(tp);
  1112. return -ENOMEM;
  1113. }
  1114. static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
  1115. {
  1116. struct tx_agg *agg = NULL;
  1117. unsigned long flags;
  1118. if (list_empty(&tp->tx_free))
  1119. return NULL;
  1120. spin_lock_irqsave(&tp->tx_lock, flags);
  1121. if (!list_empty(&tp->tx_free)) {
  1122. struct list_head *cursor;
  1123. cursor = tp->tx_free.next;
  1124. list_del_init(cursor);
  1125. agg = list_entry(cursor, struct tx_agg, list);
  1126. }
  1127. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1128. return agg;
  1129. }
  1130. /* r8152_csum_workaround()
  1131. * The hw limites the value the transport offset. When the offset is out of the
  1132. * range, calculate the checksum by sw.
  1133. */
  1134. static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
  1135. struct sk_buff_head *list)
  1136. {
  1137. if (skb_shinfo(skb)->gso_size) {
  1138. netdev_features_t features = tp->netdev->features;
  1139. struct sk_buff_head seg_list;
  1140. struct sk_buff *segs, *nskb;
  1141. features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
  1142. segs = skb_gso_segment(skb, features);
  1143. if (IS_ERR(segs) || !segs)
  1144. goto drop;
  1145. __skb_queue_head_init(&seg_list);
  1146. do {
  1147. nskb = segs;
  1148. segs = segs->next;
  1149. nskb->next = NULL;
  1150. __skb_queue_tail(&seg_list, nskb);
  1151. } while (segs);
  1152. skb_queue_splice(&seg_list, list);
  1153. dev_kfree_skb(skb);
  1154. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1155. if (skb_checksum_help(skb) < 0)
  1156. goto drop;
  1157. __skb_queue_head(list, skb);
  1158. } else {
  1159. struct net_device_stats *stats;
  1160. drop:
  1161. stats = &tp->netdev->stats;
  1162. stats->tx_dropped++;
  1163. dev_kfree_skb(skb);
  1164. }
  1165. }
  1166. /* msdn_giant_send_check()
  1167. * According to the document of microsoft, the TCP Pseudo Header excludes the
  1168. * packet length for IPv6 TCP large packets.
  1169. */
  1170. static int msdn_giant_send_check(struct sk_buff *skb)
  1171. {
  1172. const struct ipv6hdr *ipv6h;
  1173. struct tcphdr *th;
  1174. int ret;
  1175. ret = skb_cow_head(skb, 0);
  1176. if (ret)
  1177. return ret;
  1178. ipv6h = ipv6_hdr(skb);
  1179. th = tcp_hdr(skb);
  1180. th->check = 0;
  1181. th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
  1182. return ret;
  1183. }
  1184. static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
  1185. {
  1186. if (skb_vlan_tag_present(skb)) {
  1187. u32 opts2;
  1188. opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
  1189. desc->opts2 |= cpu_to_le32(opts2);
  1190. }
  1191. }
  1192. static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
  1193. {
  1194. u32 opts2 = le32_to_cpu(desc->opts2);
  1195. if (opts2 & RX_VLAN_TAG)
  1196. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
  1197. swab16(opts2 & 0xffff));
  1198. }
  1199. static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
  1200. struct sk_buff *skb, u32 len, u32 transport_offset)
  1201. {
  1202. u32 mss = skb_shinfo(skb)->gso_size;
  1203. u32 opts1, opts2 = 0;
  1204. int ret = TX_CSUM_SUCCESS;
  1205. WARN_ON_ONCE(len > TX_LEN_MAX);
  1206. opts1 = len | TX_FS | TX_LS;
  1207. if (mss) {
  1208. if (transport_offset > GTTCPHO_MAX) {
  1209. netif_warn(tp, tx_err, tp->netdev,
  1210. "Invalid transport offset 0x%x for TSO\n",
  1211. transport_offset);
  1212. ret = TX_CSUM_TSO;
  1213. goto unavailable;
  1214. }
  1215. switch (vlan_get_protocol(skb)) {
  1216. case htons(ETH_P_IP):
  1217. opts1 |= GTSENDV4;
  1218. break;
  1219. case htons(ETH_P_IPV6):
  1220. if (msdn_giant_send_check(skb)) {
  1221. ret = TX_CSUM_TSO;
  1222. goto unavailable;
  1223. }
  1224. opts1 |= GTSENDV6;
  1225. break;
  1226. default:
  1227. WARN_ON_ONCE(1);
  1228. break;
  1229. }
  1230. opts1 |= transport_offset << GTTCPHO_SHIFT;
  1231. opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
  1232. } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
  1233. u8 ip_protocol;
  1234. if (transport_offset > TCPHO_MAX) {
  1235. netif_warn(tp, tx_err, tp->netdev,
  1236. "Invalid transport offset 0x%x\n",
  1237. transport_offset);
  1238. ret = TX_CSUM_NONE;
  1239. goto unavailable;
  1240. }
  1241. switch (vlan_get_protocol(skb)) {
  1242. case htons(ETH_P_IP):
  1243. opts2 |= IPV4_CS;
  1244. ip_protocol = ip_hdr(skb)->protocol;
  1245. break;
  1246. case htons(ETH_P_IPV6):
  1247. opts2 |= IPV6_CS;
  1248. ip_protocol = ipv6_hdr(skb)->nexthdr;
  1249. break;
  1250. default:
  1251. ip_protocol = IPPROTO_RAW;
  1252. break;
  1253. }
  1254. if (ip_protocol == IPPROTO_TCP)
  1255. opts2 |= TCP_CS;
  1256. else if (ip_protocol == IPPROTO_UDP)
  1257. opts2 |= UDP_CS;
  1258. else
  1259. WARN_ON_ONCE(1);
  1260. opts2 |= transport_offset << TCPHO_SHIFT;
  1261. }
  1262. desc->opts2 = cpu_to_le32(opts2);
  1263. desc->opts1 = cpu_to_le32(opts1);
  1264. unavailable:
  1265. return ret;
  1266. }
  1267. static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
  1268. {
  1269. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1270. int remain, ret;
  1271. u8 *tx_data;
  1272. __skb_queue_head_init(&skb_head);
  1273. spin_lock(&tx_queue->lock);
  1274. skb_queue_splice_init(tx_queue, &skb_head);
  1275. spin_unlock(&tx_queue->lock);
  1276. tx_data = agg->head;
  1277. agg->skb_num = 0;
  1278. agg->skb_len = 0;
  1279. remain = agg_buf_sz;
  1280. while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
  1281. struct tx_desc *tx_desc;
  1282. struct sk_buff *skb;
  1283. unsigned int len;
  1284. u32 offset;
  1285. skb = __skb_dequeue(&skb_head);
  1286. if (!skb)
  1287. break;
  1288. len = skb->len + sizeof(*tx_desc);
  1289. if (len > remain) {
  1290. __skb_queue_head(&skb_head, skb);
  1291. break;
  1292. }
  1293. tx_data = tx_agg_align(tx_data);
  1294. tx_desc = (struct tx_desc *)tx_data;
  1295. offset = (u32)skb_transport_offset(skb);
  1296. if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
  1297. r8152_csum_workaround(tp, skb, &skb_head);
  1298. continue;
  1299. }
  1300. rtl_tx_vlan_tag(tx_desc, skb);
  1301. tx_data += sizeof(*tx_desc);
  1302. len = skb->len;
  1303. if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
  1304. struct net_device_stats *stats = &tp->netdev->stats;
  1305. stats->tx_dropped++;
  1306. dev_kfree_skb_any(skb);
  1307. tx_data -= sizeof(*tx_desc);
  1308. continue;
  1309. }
  1310. tx_data += len;
  1311. agg->skb_len += len;
  1312. agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
  1313. dev_kfree_skb_any(skb);
  1314. remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
  1315. }
  1316. if (!skb_queue_empty(&skb_head)) {
  1317. spin_lock(&tx_queue->lock);
  1318. skb_queue_splice(&skb_head, tx_queue);
  1319. spin_unlock(&tx_queue->lock);
  1320. }
  1321. netif_tx_lock(tp->netdev);
  1322. if (netif_queue_stopped(tp->netdev) &&
  1323. skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
  1324. netif_wake_queue(tp->netdev);
  1325. netif_tx_unlock(tp->netdev);
  1326. ret = usb_autopm_get_interface_async(tp->intf);
  1327. if (ret < 0)
  1328. goto out_tx_fill;
  1329. usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
  1330. agg->head, (int)(tx_data - (u8 *)agg->head),
  1331. (usb_complete_t)write_bulk_callback, agg);
  1332. ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
  1333. if (ret < 0)
  1334. usb_autopm_put_interface_async(tp->intf);
  1335. out_tx_fill:
  1336. return ret;
  1337. }
  1338. static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
  1339. {
  1340. u8 checksum = CHECKSUM_NONE;
  1341. u32 opts2, opts3;
  1342. if (!(tp->netdev->features & NETIF_F_RXCSUM))
  1343. goto return_result;
  1344. opts2 = le32_to_cpu(rx_desc->opts2);
  1345. opts3 = le32_to_cpu(rx_desc->opts3);
  1346. if (opts2 & RD_IPV4_CS) {
  1347. if (opts3 & IPF)
  1348. checksum = CHECKSUM_NONE;
  1349. else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
  1350. checksum = CHECKSUM_NONE;
  1351. else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
  1352. checksum = CHECKSUM_NONE;
  1353. else
  1354. checksum = CHECKSUM_UNNECESSARY;
  1355. } else if (RD_IPV6_CS) {
  1356. if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
  1357. checksum = CHECKSUM_UNNECESSARY;
  1358. else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
  1359. checksum = CHECKSUM_UNNECESSARY;
  1360. }
  1361. return_result:
  1362. return checksum;
  1363. }
  1364. static int rx_bottom(struct r8152 *tp, int budget)
  1365. {
  1366. unsigned long flags;
  1367. struct list_head *cursor, *next, rx_queue;
  1368. int ret = 0, work_done = 0;
  1369. if (!skb_queue_empty(&tp->rx_queue)) {
  1370. while (work_done < budget) {
  1371. struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
  1372. struct net_device *netdev = tp->netdev;
  1373. struct net_device_stats *stats = &netdev->stats;
  1374. unsigned int pkt_len;
  1375. if (!skb)
  1376. break;
  1377. pkt_len = skb->len;
  1378. napi_gro_receive(&tp->napi, skb);
  1379. work_done++;
  1380. stats->rx_packets++;
  1381. stats->rx_bytes += pkt_len;
  1382. }
  1383. }
  1384. if (list_empty(&tp->rx_done))
  1385. goto out1;
  1386. INIT_LIST_HEAD(&rx_queue);
  1387. spin_lock_irqsave(&tp->rx_lock, flags);
  1388. list_splice_init(&tp->rx_done, &rx_queue);
  1389. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1390. list_for_each_safe(cursor, next, &rx_queue) {
  1391. struct rx_desc *rx_desc;
  1392. struct rx_agg *agg;
  1393. int len_used = 0;
  1394. struct urb *urb;
  1395. u8 *rx_data;
  1396. list_del_init(cursor);
  1397. agg = list_entry(cursor, struct rx_agg, list);
  1398. urb = agg->urb;
  1399. if (urb->actual_length < ETH_ZLEN)
  1400. goto submit;
  1401. rx_desc = agg->head;
  1402. rx_data = agg->head;
  1403. len_used += sizeof(struct rx_desc);
  1404. while (urb->actual_length > len_used) {
  1405. struct net_device *netdev = tp->netdev;
  1406. struct net_device_stats *stats = &netdev->stats;
  1407. unsigned int pkt_len;
  1408. struct sk_buff *skb;
  1409. pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
  1410. if (pkt_len < ETH_ZLEN)
  1411. break;
  1412. len_used += pkt_len;
  1413. if (urb->actual_length < len_used)
  1414. break;
  1415. pkt_len -= CRC_SIZE;
  1416. rx_data += sizeof(struct rx_desc);
  1417. skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
  1418. if (!skb) {
  1419. stats->rx_dropped++;
  1420. goto find_next_rx;
  1421. }
  1422. skb->ip_summed = r8152_rx_csum(tp, rx_desc);
  1423. memcpy(skb->data, rx_data, pkt_len);
  1424. skb_put(skb, pkt_len);
  1425. skb->protocol = eth_type_trans(skb, netdev);
  1426. rtl_rx_vlan_tag(rx_desc, skb);
  1427. if (work_done < budget) {
  1428. napi_gro_receive(&tp->napi, skb);
  1429. work_done++;
  1430. stats->rx_packets++;
  1431. stats->rx_bytes += pkt_len;
  1432. } else {
  1433. __skb_queue_tail(&tp->rx_queue, skb);
  1434. }
  1435. find_next_rx:
  1436. rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
  1437. rx_desc = (struct rx_desc *)rx_data;
  1438. len_used = (int)(rx_data - (u8 *)agg->head);
  1439. len_used += sizeof(struct rx_desc);
  1440. }
  1441. submit:
  1442. if (!ret) {
  1443. ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
  1444. } else {
  1445. urb->actual_length = 0;
  1446. list_add_tail(&agg->list, next);
  1447. }
  1448. }
  1449. if (!list_empty(&rx_queue)) {
  1450. spin_lock_irqsave(&tp->rx_lock, flags);
  1451. list_splice_tail(&rx_queue, &tp->rx_done);
  1452. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1453. }
  1454. out1:
  1455. return work_done;
  1456. }
  1457. static void tx_bottom(struct r8152 *tp)
  1458. {
  1459. int res;
  1460. do {
  1461. struct tx_agg *agg;
  1462. if (skb_queue_empty(&tp->tx_queue))
  1463. break;
  1464. agg = r8152_get_tx_agg(tp);
  1465. if (!agg)
  1466. break;
  1467. res = r8152_tx_agg_fill(tp, agg);
  1468. if (res) {
  1469. struct net_device *netdev = tp->netdev;
  1470. if (res == -ENODEV) {
  1471. set_bit(RTL8152_UNPLUG, &tp->flags);
  1472. netif_device_detach(netdev);
  1473. } else {
  1474. struct net_device_stats *stats = &netdev->stats;
  1475. unsigned long flags;
  1476. netif_warn(tp, tx_err, netdev,
  1477. "failed tx_urb %d\n", res);
  1478. stats->tx_dropped += agg->skb_num;
  1479. spin_lock_irqsave(&tp->tx_lock, flags);
  1480. list_add_tail(&agg->list, &tp->tx_free);
  1481. spin_unlock_irqrestore(&tp->tx_lock, flags);
  1482. }
  1483. }
  1484. } while (res == 0);
  1485. }
  1486. static void bottom_half(struct r8152 *tp)
  1487. {
  1488. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1489. return;
  1490. if (!test_bit(WORK_ENABLE, &tp->flags))
  1491. return;
  1492. /* When link down, the driver would cancel all bulks. */
  1493. /* This avoid the re-submitting bulk */
  1494. if (!netif_carrier_ok(tp->netdev))
  1495. return;
  1496. clear_bit(SCHEDULE_NAPI, &tp->flags);
  1497. tx_bottom(tp);
  1498. }
  1499. static int r8152_poll(struct napi_struct *napi, int budget)
  1500. {
  1501. struct r8152 *tp = container_of(napi, struct r8152, napi);
  1502. int work_done;
  1503. work_done = rx_bottom(tp, budget);
  1504. bottom_half(tp);
  1505. if (work_done < budget) {
  1506. napi_complete(napi);
  1507. if (!list_empty(&tp->rx_done))
  1508. napi_schedule(napi);
  1509. else if (!skb_queue_empty(&tp->tx_queue) &&
  1510. !list_empty(&tp->tx_free))
  1511. napi_schedule(napi);
  1512. }
  1513. return work_done;
  1514. }
  1515. static
  1516. int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
  1517. {
  1518. int ret;
  1519. /* The rx would be stopped, so skip submitting */
  1520. if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
  1521. !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
  1522. return 0;
  1523. usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
  1524. agg->head, agg_buf_sz,
  1525. (usb_complete_t)read_bulk_callback, agg);
  1526. ret = usb_submit_urb(agg->urb, mem_flags);
  1527. if (ret == -ENODEV) {
  1528. set_bit(RTL8152_UNPLUG, &tp->flags);
  1529. netif_device_detach(tp->netdev);
  1530. } else if (ret) {
  1531. struct urb *urb = agg->urb;
  1532. unsigned long flags;
  1533. urb->actual_length = 0;
  1534. spin_lock_irqsave(&tp->rx_lock, flags);
  1535. list_add_tail(&agg->list, &tp->rx_done);
  1536. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1537. netif_err(tp, rx_err, tp->netdev,
  1538. "Couldn't submit rx[%p], ret = %d\n", agg, ret);
  1539. napi_schedule(&tp->napi);
  1540. }
  1541. return ret;
  1542. }
  1543. static void rtl_drop_queued_tx(struct r8152 *tp)
  1544. {
  1545. struct net_device_stats *stats = &tp->netdev->stats;
  1546. struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
  1547. struct sk_buff *skb;
  1548. if (skb_queue_empty(tx_queue))
  1549. return;
  1550. __skb_queue_head_init(&skb_head);
  1551. spin_lock_bh(&tx_queue->lock);
  1552. skb_queue_splice_init(tx_queue, &skb_head);
  1553. spin_unlock_bh(&tx_queue->lock);
  1554. while ((skb = __skb_dequeue(&skb_head))) {
  1555. dev_kfree_skb(skb);
  1556. stats->tx_dropped++;
  1557. }
  1558. }
  1559. static void rtl8152_tx_timeout(struct net_device *netdev)
  1560. {
  1561. struct r8152 *tp = netdev_priv(netdev);
  1562. netif_warn(tp, tx_err, netdev, "Tx timeout\n");
  1563. usb_queue_reset_device(tp->intf);
  1564. }
  1565. static void rtl8152_set_rx_mode(struct net_device *netdev)
  1566. {
  1567. struct r8152 *tp = netdev_priv(netdev);
  1568. if (netif_carrier_ok(netdev)) {
  1569. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  1570. schedule_delayed_work(&tp->schedule, 0);
  1571. }
  1572. }
  1573. static void _rtl8152_set_rx_mode(struct net_device *netdev)
  1574. {
  1575. struct r8152 *tp = netdev_priv(netdev);
  1576. u32 mc_filter[2]; /* Multicast hash filter */
  1577. __le32 tmp[2];
  1578. u32 ocp_data;
  1579. netif_stop_queue(netdev);
  1580. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1581. ocp_data &= ~RCR_ACPT_ALL;
  1582. ocp_data |= RCR_AB | RCR_APM;
  1583. if (netdev->flags & IFF_PROMISC) {
  1584. /* Unconditionally log net taps. */
  1585. netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
  1586. ocp_data |= RCR_AM | RCR_AAP;
  1587. mc_filter[1] = 0xffffffff;
  1588. mc_filter[0] = 0xffffffff;
  1589. } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
  1590. (netdev->flags & IFF_ALLMULTI)) {
  1591. /* Too many to filter perfectly -- accept all multicasts. */
  1592. ocp_data |= RCR_AM;
  1593. mc_filter[1] = 0xffffffff;
  1594. mc_filter[0] = 0xffffffff;
  1595. } else {
  1596. struct netdev_hw_addr *ha;
  1597. mc_filter[1] = 0;
  1598. mc_filter[0] = 0;
  1599. netdev_for_each_mc_addr(ha, netdev) {
  1600. int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
  1601. mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  1602. ocp_data |= RCR_AM;
  1603. }
  1604. }
  1605. tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
  1606. tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
  1607. pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
  1608. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1609. netif_wake_queue(netdev);
  1610. }
  1611. static netdev_features_t
  1612. rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
  1613. netdev_features_t features)
  1614. {
  1615. u32 mss = skb_shinfo(skb)->gso_size;
  1616. int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
  1617. int offset = skb_transport_offset(skb);
  1618. if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
  1619. features &= ~(NETIF_F_ALL_CSUM | NETIF_F_GSO_MASK);
  1620. else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
  1621. features &= ~NETIF_F_GSO_MASK;
  1622. return features;
  1623. }
  1624. static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
  1625. struct net_device *netdev)
  1626. {
  1627. struct r8152 *tp = netdev_priv(netdev);
  1628. skb_tx_timestamp(skb);
  1629. skb_queue_tail(&tp->tx_queue, skb);
  1630. if (!list_empty(&tp->tx_free)) {
  1631. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  1632. set_bit(SCHEDULE_NAPI, &tp->flags);
  1633. schedule_delayed_work(&tp->schedule, 0);
  1634. } else {
  1635. usb_mark_last_busy(tp->udev);
  1636. napi_schedule(&tp->napi);
  1637. }
  1638. } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
  1639. netif_stop_queue(netdev);
  1640. }
  1641. return NETDEV_TX_OK;
  1642. }
  1643. static void r8152b_reset_packet_filter(struct r8152 *tp)
  1644. {
  1645. u32 ocp_data;
  1646. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
  1647. ocp_data &= ~FMC_FCR_MCU_EN;
  1648. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1649. ocp_data |= FMC_FCR_MCU_EN;
  1650. ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
  1651. }
  1652. static void rtl8152_nic_reset(struct r8152 *tp)
  1653. {
  1654. int i;
  1655. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
  1656. for (i = 0; i < 1000; i++) {
  1657. if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
  1658. break;
  1659. usleep_range(100, 400);
  1660. }
  1661. }
  1662. static void set_tx_qlen(struct r8152 *tp)
  1663. {
  1664. struct net_device *netdev = tp->netdev;
  1665. tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
  1666. sizeof(struct tx_desc));
  1667. }
  1668. static inline u8 rtl8152_get_speed(struct r8152 *tp)
  1669. {
  1670. return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
  1671. }
  1672. static void rtl_set_eee_plus(struct r8152 *tp)
  1673. {
  1674. u32 ocp_data;
  1675. u8 speed;
  1676. speed = rtl8152_get_speed(tp);
  1677. if (speed & _10bps) {
  1678. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1679. ocp_data |= EEEP_CR_EEEP_TX;
  1680. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1681. } else {
  1682. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
  1683. ocp_data &= ~EEEP_CR_EEEP_TX;
  1684. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
  1685. }
  1686. }
  1687. static void rxdy_gated_en(struct r8152 *tp, bool enable)
  1688. {
  1689. u32 ocp_data;
  1690. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
  1691. if (enable)
  1692. ocp_data |= RXDY_GATED_EN;
  1693. else
  1694. ocp_data &= ~RXDY_GATED_EN;
  1695. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
  1696. }
  1697. static int rtl_start_rx(struct r8152 *tp)
  1698. {
  1699. int i, ret = 0;
  1700. INIT_LIST_HEAD(&tp->rx_done);
  1701. for (i = 0; i < RTL8152_MAX_RX; i++) {
  1702. INIT_LIST_HEAD(&tp->rx_info[i].list);
  1703. ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
  1704. if (ret)
  1705. break;
  1706. }
  1707. if (ret && ++i < RTL8152_MAX_RX) {
  1708. struct list_head rx_queue;
  1709. unsigned long flags;
  1710. INIT_LIST_HEAD(&rx_queue);
  1711. do {
  1712. struct rx_agg *agg = &tp->rx_info[i++];
  1713. struct urb *urb = agg->urb;
  1714. urb->actual_length = 0;
  1715. list_add_tail(&agg->list, &rx_queue);
  1716. } while (i < RTL8152_MAX_RX);
  1717. spin_lock_irqsave(&tp->rx_lock, flags);
  1718. list_splice_tail(&rx_queue, &tp->rx_done);
  1719. spin_unlock_irqrestore(&tp->rx_lock, flags);
  1720. }
  1721. return ret;
  1722. }
  1723. static int rtl_stop_rx(struct r8152 *tp)
  1724. {
  1725. int i;
  1726. for (i = 0; i < RTL8152_MAX_RX; i++)
  1727. usb_kill_urb(tp->rx_info[i].urb);
  1728. while (!skb_queue_empty(&tp->rx_queue))
  1729. dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
  1730. return 0;
  1731. }
  1732. static int rtl_enable(struct r8152 *tp)
  1733. {
  1734. u32 ocp_data;
  1735. r8152b_reset_packet_filter(tp);
  1736. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
  1737. ocp_data |= CR_RE | CR_TE;
  1738. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
  1739. rxdy_gated_en(tp, false);
  1740. return 0;
  1741. }
  1742. static int rtl8152_enable(struct r8152 *tp)
  1743. {
  1744. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1745. return -ENODEV;
  1746. set_tx_qlen(tp);
  1747. rtl_set_eee_plus(tp);
  1748. return rtl_enable(tp);
  1749. }
  1750. static void r8153_set_rx_early_timeout(struct r8152 *tp)
  1751. {
  1752. u32 ocp_data = tp->coalesce / 8;
  1753. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, ocp_data);
  1754. }
  1755. static void r8153_set_rx_early_size(struct r8152 *tp)
  1756. {
  1757. u32 mtu = tp->netdev->mtu;
  1758. u32 ocp_data = (agg_buf_sz - mtu - VLAN_ETH_HLEN - VLAN_HLEN) / 4;
  1759. ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, ocp_data);
  1760. }
  1761. static int rtl8153_enable(struct r8152 *tp)
  1762. {
  1763. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  1764. return -ENODEV;
  1765. usb_disable_lpm(tp->udev);
  1766. set_tx_qlen(tp);
  1767. rtl_set_eee_plus(tp);
  1768. r8153_set_rx_early_timeout(tp);
  1769. r8153_set_rx_early_size(tp);
  1770. return rtl_enable(tp);
  1771. }
  1772. static void rtl_disable(struct r8152 *tp)
  1773. {
  1774. u32 ocp_data;
  1775. int i;
  1776. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  1777. rtl_drop_queued_tx(tp);
  1778. return;
  1779. }
  1780. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  1781. ocp_data &= ~RCR_ACPT_ALL;
  1782. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  1783. rtl_drop_queued_tx(tp);
  1784. for (i = 0; i < RTL8152_MAX_TX; i++)
  1785. usb_kill_urb(tp->tx_info[i].urb);
  1786. rxdy_gated_en(tp, true);
  1787. for (i = 0; i < 1000; i++) {
  1788. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  1789. if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
  1790. break;
  1791. usleep_range(1000, 2000);
  1792. }
  1793. for (i = 0; i < 1000; i++) {
  1794. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
  1795. break;
  1796. usleep_range(1000, 2000);
  1797. }
  1798. rtl_stop_rx(tp);
  1799. rtl8152_nic_reset(tp);
  1800. }
  1801. static void r8152_power_cut_en(struct r8152 *tp, bool enable)
  1802. {
  1803. u32 ocp_data;
  1804. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
  1805. if (enable)
  1806. ocp_data |= POWER_CUT;
  1807. else
  1808. ocp_data &= ~POWER_CUT;
  1809. ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
  1810. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
  1811. ocp_data &= ~RESUME_INDICATE;
  1812. ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
  1813. }
  1814. static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
  1815. {
  1816. u32 ocp_data;
  1817. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
  1818. if (enable)
  1819. ocp_data |= CPCR_RX_VLAN;
  1820. else
  1821. ocp_data &= ~CPCR_RX_VLAN;
  1822. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
  1823. }
  1824. static int rtl8152_set_features(struct net_device *dev,
  1825. netdev_features_t features)
  1826. {
  1827. netdev_features_t changed = features ^ dev->features;
  1828. struct r8152 *tp = netdev_priv(dev);
  1829. int ret;
  1830. ret = usb_autopm_get_interface(tp->intf);
  1831. if (ret < 0)
  1832. goto out;
  1833. mutex_lock(&tp->control);
  1834. if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
  1835. if (features & NETIF_F_HW_VLAN_CTAG_RX)
  1836. rtl_rx_vlan_en(tp, true);
  1837. else
  1838. rtl_rx_vlan_en(tp, false);
  1839. }
  1840. mutex_unlock(&tp->control);
  1841. usb_autopm_put_interface(tp->intf);
  1842. out:
  1843. return ret;
  1844. }
  1845. #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
  1846. static u32 __rtl_get_wol(struct r8152 *tp)
  1847. {
  1848. u32 ocp_data;
  1849. u32 wolopts = 0;
  1850. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1851. if (!(ocp_data & LAN_WAKE_EN))
  1852. return 0;
  1853. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1854. if (ocp_data & LINK_ON_WAKE_EN)
  1855. wolopts |= WAKE_PHY;
  1856. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1857. if (ocp_data & UWF_EN)
  1858. wolopts |= WAKE_UCAST;
  1859. if (ocp_data & BWF_EN)
  1860. wolopts |= WAKE_BCAST;
  1861. if (ocp_data & MWF_EN)
  1862. wolopts |= WAKE_MCAST;
  1863. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1864. if (ocp_data & MAGIC_EN)
  1865. wolopts |= WAKE_MAGIC;
  1866. return wolopts;
  1867. }
  1868. static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
  1869. {
  1870. u32 ocp_data;
  1871. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1872. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1873. ocp_data &= ~LINK_ON_WAKE_EN;
  1874. if (wolopts & WAKE_PHY)
  1875. ocp_data |= LINK_ON_WAKE_EN;
  1876. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1877. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
  1878. ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
  1879. if (wolopts & WAKE_UCAST)
  1880. ocp_data |= UWF_EN;
  1881. if (wolopts & WAKE_BCAST)
  1882. ocp_data |= BWF_EN;
  1883. if (wolopts & WAKE_MCAST)
  1884. ocp_data |= MWF_EN;
  1885. if (wolopts & WAKE_ANY)
  1886. ocp_data |= LAN_WAKE_EN;
  1887. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
  1888. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1889. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
  1890. ocp_data &= ~MAGIC_EN;
  1891. if (wolopts & WAKE_MAGIC)
  1892. ocp_data |= MAGIC_EN;
  1893. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
  1894. if (wolopts & WAKE_ANY)
  1895. device_set_wakeup_enable(&tp->udev->dev, true);
  1896. else
  1897. device_set_wakeup_enable(&tp->udev->dev, false);
  1898. }
  1899. static void r8153_u1u2en(struct r8152 *tp, bool enable)
  1900. {
  1901. u8 u1u2[8];
  1902. if (enable)
  1903. memset(u1u2, 0xff, sizeof(u1u2));
  1904. else
  1905. memset(u1u2, 0x00, sizeof(u1u2));
  1906. usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
  1907. }
  1908. static void r8153_u2p3en(struct r8152 *tp, bool enable)
  1909. {
  1910. u32 ocp_data;
  1911. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
  1912. if (enable && tp->version != RTL_VER_03 && tp->version != RTL_VER_04)
  1913. ocp_data |= U2P3_ENABLE;
  1914. else
  1915. ocp_data &= ~U2P3_ENABLE;
  1916. ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
  1917. }
  1918. static void r8153_power_cut_en(struct r8152 *tp, bool enable)
  1919. {
  1920. u32 ocp_data;
  1921. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
  1922. if (enable)
  1923. ocp_data |= PWR_EN | PHASE2_EN;
  1924. else
  1925. ocp_data &= ~(PWR_EN | PHASE2_EN);
  1926. ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
  1927. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
  1928. ocp_data &= ~PCUT_STATUS;
  1929. ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
  1930. }
  1931. static bool rtl_can_wakeup(struct r8152 *tp)
  1932. {
  1933. struct usb_device *udev = tp->udev;
  1934. return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
  1935. }
  1936. static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
  1937. {
  1938. if (enable) {
  1939. u32 ocp_data;
  1940. r8153_u1u2en(tp, false);
  1941. r8153_u2p3en(tp, false);
  1942. __rtl_set_wol(tp, WAKE_ANY);
  1943. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
  1944. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
  1945. ocp_data |= LINK_OFF_WAKE_EN;
  1946. ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
  1947. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  1948. } else {
  1949. __rtl_set_wol(tp, tp->saved_wolopts);
  1950. r8153_u2p3en(tp, true);
  1951. r8153_u1u2en(tp, true);
  1952. }
  1953. }
  1954. static void rtl_phy_reset(struct r8152 *tp)
  1955. {
  1956. u16 data;
  1957. int i;
  1958. data = r8152_mdio_read(tp, MII_BMCR);
  1959. /* don't reset again before the previous one complete */
  1960. if (data & BMCR_RESET)
  1961. return;
  1962. data |= BMCR_RESET;
  1963. r8152_mdio_write(tp, MII_BMCR, data);
  1964. for (i = 0; i < 50; i++) {
  1965. msleep(20);
  1966. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  1967. break;
  1968. }
  1969. }
  1970. static void r8153_teredo_off(struct r8152 *tp)
  1971. {
  1972. u32 ocp_data;
  1973. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  1974. ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
  1975. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  1976. ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
  1977. ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
  1978. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
  1979. }
  1980. static void r8152_aldps_en(struct r8152 *tp, bool enable)
  1981. {
  1982. if (enable) {
  1983. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
  1984. LINKENA | DIS_SDSAVE);
  1985. } else {
  1986. ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
  1987. DIS_SDSAVE);
  1988. msleep(20);
  1989. }
  1990. }
  1991. static void rtl8152_disable(struct r8152 *tp)
  1992. {
  1993. r8152_aldps_en(tp, false);
  1994. rtl_disable(tp);
  1995. r8152_aldps_en(tp, true);
  1996. }
  1997. static void r8152b_hw_phy_cfg(struct r8152 *tp)
  1998. {
  1999. u16 data;
  2000. data = r8152_mdio_read(tp, MII_BMCR);
  2001. if (data & BMCR_PDOWN) {
  2002. data &= ~BMCR_PDOWN;
  2003. r8152_mdio_write(tp, MII_BMCR, data);
  2004. }
  2005. set_bit(PHY_RESET, &tp->flags);
  2006. }
  2007. static void r8152b_exit_oob(struct r8152 *tp)
  2008. {
  2009. u32 ocp_data;
  2010. int i;
  2011. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2012. ocp_data &= ~RCR_ACPT_ALL;
  2013. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2014. rxdy_gated_en(tp, true);
  2015. r8153_teredo_off(tp);
  2016. r8152b_hw_phy_cfg(tp);
  2017. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
  2018. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
  2019. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2020. ocp_data &= ~NOW_IS_OOB;
  2021. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2022. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2023. ocp_data &= ~MCU_BORW_EN;
  2024. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2025. for (i = 0; i < 1000; i++) {
  2026. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2027. if (ocp_data & LINK_LIST_READY)
  2028. break;
  2029. usleep_range(1000, 2000);
  2030. }
  2031. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2032. ocp_data |= RE_INIT_LL;
  2033. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2034. for (i = 0; i < 1000; i++) {
  2035. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2036. if (ocp_data & LINK_LIST_READY)
  2037. break;
  2038. usleep_range(1000, 2000);
  2039. }
  2040. rtl8152_nic_reset(tp);
  2041. /* rx share fifo credit full threshold */
  2042. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2043. if (tp->udev->speed == USB_SPEED_FULL ||
  2044. tp->udev->speed == USB_SPEED_LOW) {
  2045. /* rx share fifo credit near full threshold */
  2046. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2047. RXFIFO_THR2_FULL);
  2048. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2049. RXFIFO_THR3_FULL);
  2050. } else {
  2051. /* rx share fifo credit near full threshold */
  2052. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
  2053. RXFIFO_THR2_HIGH);
  2054. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
  2055. RXFIFO_THR3_HIGH);
  2056. }
  2057. /* TX share fifo free credit full threshold */
  2058. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
  2059. ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
  2060. ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
  2061. ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
  2062. TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
  2063. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2064. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2065. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2066. ocp_data |= TCR0_AUTO_FIFO;
  2067. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2068. }
  2069. static void r8152b_enter_oob(struct r8152 *tp)
  2070. {
  2071. u32 ocp_data;
  2072. int i;
  2073. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2074. ocp_data &= ~NOW_IS_OOB;
  2075. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2076. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
  2077. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
  2078. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
  2079. rtl_disable(tp);
  2080. for (i = 0; i < 1000; i++) {
  2081. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2082. if (ocp_data & LINK_LIST_READY)
  2083. break;
  2084. usleep_range(1000, 2000);
  2085. }
  2086. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2087. ocp_data |= RE_INIT_LL;
  2088. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2089. for (i = 0; i < 1000; i++) {
  2090. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2091. if (ocp_data & LINK_LIST_READY)
  2092. break;
  2093. usleep_range(1000, 2000);
  2094. }
  2095. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
  2096. rtl_rx_vlan_en(tp, true);
  2097. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2098. ocp_data |= ALDPS_PROXY_MODE;
  2099. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2100. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2101. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2102. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2103. rxdy_gated_en(tp, false);
  2104. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2105. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2106. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2107. }
  2108. static void r8153_hw_phy_cfg(struct r8152 *tp)
  2109. {
  2110. u32 ocp_data;
  2111. u16 data;
  2112. if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
  2113. tp->version == RTL_VER_05)
  2114. ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
  2115. data = r8152_mdio_read(tp, MII_BMCR);
  2116. if (data & BMCR_PDOWN) {
  2117. data &= ~BMCR_PDOWN;
  2118. r8152_mdio_write(tp, MII_BMCR, data);
  2119. }
  2120. if (tp->version == RTL_VER_03) {
  2121. data = ocp_reg_read(tp, OCP_EEE_CFG);
  2122. data &= ~CTAP_SHORT_EN;
  2123. ocp_reg_write(tp, OCP_EEE_CFG, data);
  2124. }
  2125. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2126. data |= EEE_CLKDIV_EN;
  2127. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2128. data = ocp_reg_read(tp, OCP_DOWN_SPEED);
  2129. data |= EN_10M_BGOFF;
  2130. ocp_reg_write(tp, OCP_DOWN_SPEED, data);
  2131. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2132. data |= EN_10M_PLLOFF;
  2133. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2134. sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
  2135. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2136. ocp_data |= PFM_PWM_SWITCH;
  2137. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2138. /* Enable LPF corner auto tune */
  2139. sram_write(tp, SRAM_LPF_CFG, 0xf70f);
  2140. /* Adjust 10M Amplitude */
  2141. sram_write(tp, SRAM_10M_AMP1, 0x00af);
  2142. sram_write(tp, SRAM_10M_AMP2, 0x0208);
  2143. set_bit(PHY_RESET, &tp->flags);
  2144. }
  2145. static void r8153_first_init(struct r8152 *tp)
  2146. {
  2147. u32 ocp_data;
  2148. int i;
  2149. rxdy_gated_en(tp, true);
  2150. r8153_teredo_off(tp);
  2151. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2152. ocp_data &= ~RCR_ACPT_ALL;
  2153. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2154. r8153_hw_phy_cfg(tp);
  2155. rtl8152_nic_reset(tp);
  2156. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2157. ocp_data &= ~NOW_IS_OOB;
  2158. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2159. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2160. ocp_data &= ~MCU_BORW_EN;
  2161. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2162. for (i = 0; i < 1000; i++) {
  2163. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2164. if (ocp_data & LINK_LIST_READY)
  2165. break;
  2166. usleep_range(1000, 2000);
  2167. }
  2168. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2169. ocp_data |= RE_INIT_LL;
  2170. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2171. for (i = 0; i < 1000; i++) {
  2172. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2173. if (ocp_data & LINK_LIST_READY)
  2174. break;
  2175. usleep_range(1000, 2000);
  2176. }
  2177. rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
  2178. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2179. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
  2180. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
  2181. ocp_data |= TCR0_AUTO_FIFO;
  2182. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
  2183. rtl8152_nic_reset(tp);
  2184. /* rx share fifo credit full threshold */
  2185. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
  2186. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
  2187. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
  2188. /* TX share fifo free credit full threshold */
  2189. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
  2190. /* rx aggregation */
  2191. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2192. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2193. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2194. }
  2195. static void r8153_enter_oob(struct r8152 *tp)
  2196. {
  2197. u32 ocp_data;
  2198. int i;
  2199. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2200. ocp_data &= ~NOW_IS_OOB;
  2201. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2202. rtl_disable(tp);
  2203. for (i = 0; i < 1000; i++) {
  2204. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2205. if (ocp_data & LINK_LIST_READY)
  2206. break;
  2207. usleep_range(1000, 2000);
  2208. }
  2209. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
  2210. ocp_data |= RE_INIT_LL;
  2211. ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
  2212. for (i = 0; i < 1000; i++) {
  2213. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2214. if (ocp_data & LINK_LIST_READY)
  2215. break;
  2216. usleep_range(1000, 2000);
  2217. }
  2218. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
  2219. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
  2220. ocp_data &= ~TEREDO_WAKE_MASK;
  2221. ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
  2222. rtl_rx_vlan_en(tp, true);
  2223. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
  2224. ocp_data |= ALDPS_PROXY_MODE;
  2225. ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
  2226. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
  2227. ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
  2228. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
  2229. rxdy_gated_en(tp, false);
  2230. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2231. ocp_data |= RCR_APM | RCR_AM | RCR_AB;
  2232. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2233. }
  2234. static void r8153_aldps_en(struct r8152 *tp, bool enable)
  2235. {
  2236. u16 data;
  2237. data = ocp_reg_read(tp, OCP_POWER_CFG);
  2238. if (enable) {
  2239. data |= EN_ALDPS;
  2240. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2241. } else {
  2242. data &= ~EN_ALDPS;
  2243. ocp_reg_write(tp, OCP_POWER_CFG, data);
  2244. msleep(20);
  2245. }
  2246. }
  2247. static void rtl8153_disable(struct r8152 *tp)
  2248. {
  2249. r8153_aldps_en(tp, false);
  2250. rtl_disable(tp);
  2251. r8153_aldps_en(tp, true);
  2252. usb_enable_lpm(tp->udev);
  2253. }
  2254. static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
  2255. {
  2256. u16 bmcr, anar, gbcr;
  2257. int ret = 0;
  2258. cancel_delayed_work_sync(&tp->schedule);
  2259. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2260. anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
  2261. ADVERTISE_100HALF | ADVERTISE_100FULL);
  2262. if (tp->mii.supports_gmii) {
  2263. gbcr = r8152_mdio_read(tp, MII_CTRL1000);
  2264. gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
  2265. } else {
  2266. gbcr = 0;
  2267. }
  2268. if (autoneg == AUTONEG_DISABLE) {
  2269. if (speed == SPEED_10) {
  2270. bmcr = 0;
  2271. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2272. } else if (speed == SPEED_100) {
  2273. bmcr = BMCR_SPEED100;
  2274. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2275. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2276. bmcr = BMCR_SPEED1000;
  2277. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2278. } else {
  2279. ret = -EINVAL;
  2280. goto out;
  2281. }
  2282. if (duplex == DUPLEX_FULL)
  2283. bmcr |= BMCR_FULLDPLX;
  2284. } else {
  2285. if (speed == SPEED_10) {
  2286. if (duplex == DUPLEX_FULL)
  2287. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2288. else
  2289. anar |= ADVERTISE_10HALF;
  2290. } else if (speed == SPEED_100) {
  2291. if (duplex == DUPLEX_FULL) {
  2292. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2293. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2294. } else {
  2295. anar |= ADVERTISE_10HALF;
  2296. anar |= ADVERTISE_100HALF;
  2297. }
  2298. } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
  2299. if (duplex == DUPLEX_FULL) {
  2300. anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
  2301. anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
  2302. gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
  2303. } else {
  2304. anar |= ADVERTISE_10HALF;
  2305. anar |= ADVERTISE_100HALF;
  2306. gbcr |= ADVERTISE_1000HALF;
  2307. }
  2308. } else {
  2309. ret = -EINVAL;
  2310. goto out;
  2311. }
  2312. bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
  2313. }
  2314. if (test_bit(PHY_RESET, &tp->flags))
  2315. bmcr |= BMCR_RESET;
  2316. if (tp->mii.supports_gmii)
  2317. r8152_mdio_write(tp, MII_CTRL1000, gbcr);
  2318. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2319. r8152_mdio_write(tp, MII_BMCR, bmcr);
  2320. if (test_and_clear_bit(PHY_RESET, &tp->flags)) {
  2321. int i;
  2322. for (i = 0; i < 50; i++) {
  2323. msleep(20);
  2324. if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
  2325. break;
  2326. }
  2327. }
  2328. out:
  2329. return ret;
  2330. }
  2331. static void rtl8152_up(struct r8152 *tp)
  2332. {
  2333. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2334. return;
  2335. r8152_aldps_en(tp, false);
  2336. r8152b_exit_oob(tp);
  2337. r8152_aldps_en(tp, true);
  2338. }
  2339. static void rtl8152_down(struct r8152 *tp)
  2340. {
  2341. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2342. rtl_drop_queued_tx(tp);
  2343. return;
  2344. }
  2345. r8152_power_cut_en(tp, false);
  2346. r8152_aldps_en(tp, false);
  2347. r8152b_enter_oob(tp);
  2348. r8152_aldps_en(tp, true);
  2349. }
  2350. static void rtl8153_up(struct r8152 *tp)
  2351. {
  2352. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2353. return;
  2354. r8153_u1u2en(tp, false);
  2355. r8153_aldps_en(tp, false);
  2356. r8153_first_init(tp);
  2357. r8153_aldps_en(tp, true);
  2358. r8153_u2p3en(tp, true);
  2359. r8153_u1u2en(tp, true);
  2360. usb_enable_lpm(tp->udev);
  2361. }
  2362. static void rtl8153_down(struct r8152 *tp)
  2363. {
  2364. if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2365. rtl_drop_queued_tx(tp);
  2366. return;
  2367. }
  2368. r8153_u1u2en(tp, false);
  2369. r8153_u2p3en(tp, false);
  2370. r8153_power_cut_en(tp, false);
  2371. r8153_aldps_en(tp, false);
  2372. r8153_enter_oob(tp);
  2373. r8153_aldps_en(tp, true);
  2374. }
  2375. static bool rtl8152_in_nway(struct r8152 *tp)
  2376. {
  2377. u16 nway_state;
  2378. ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
  2379. tp->ocp_base = 0x2000;
  2380. ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */
  2381. nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
  2382. /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
  2383. if (nway_state & 0xc000)
  2384. return false;
  2385. else
  2386. return true;
  2387. }
  2388. static bool rtl8153_in_nway(struct r8152 *tp)
  2389. {
  2390. u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
  2391. if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
  2392. return false;
  2393. else
  2394. return true;
  2395. }
  2396. static void set_carrier(struct r8152 *tp)
  2397. {
  2398. struct net_device *netdev = tp->netdev;
  2399. u8 speed;
  2400. speed = rtl8152_get_speed(tp);
  2401. if (speed & LINK_STATUS) {
  2402. if (!netif_carrier_ok(netdev)) {
  2403. tp->rtl_ops.enable(tp);
  2404. set_bit(RTL8152_SET_RX_MODE, &tp->flags);
  2405. netif_stop_queue(netdev);
  2406. napi_disable(&tp->napi);
  2407. netif_carrier_on(netdev);
  2408. rtl_start_rx(tp);
  2409. napi_enable(&tp->napi);
  2410. netif_wake_queue(netdev);
  2411. netif_info(tp, link, netdev, "carrier on\n");
  2412. } else if (netif_queue_stopped(netdev) &&
  2413. skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
  2414. netif_wake_queue(netdev);
  2415. }
  2416. } else {
  2417. if (netif_carrier_ok(netdev)) {
  2418. netif_carrier_off(netdev);
  2419. napi_disable(&tp->napi);
  2420. tp->rtl_ops.disable(tp);
  2421. napi_enable(&tp->napi);
  2422. netif_info(tp, link, netdev, "carrier off\n");
  2423. }
  2424. }
  2425. }
  2426. static void rtl_work_func_t(struct work_struct *work)
  2427. {
  2428. struct r8152 *tp = container_of(work, struct r8152, schedule.work);
  2429. /* If the device is unplugged or !netif_running(), the workqueue
  2430. * doesn't need to wake the device, and could return directly.
  2431. */
  2432. if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
  2433. return;
  2434. if (usb_autopm_get_interface(tp->intf) < 0)
  2435. return;
  2436. if (!test_bit(WORK_ENABLE, &tp->flags))
  2437. goto out1;
  2438. if (!mutex_trylock(&tp->control)) {
  2439. schedule_delayed_work(&tp->schedule, 0);
  2440. goto out1;
  2441. }
  2442. if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
  2443. set_carrier(tp);
  2444. if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
  2445. _rtl8152_set_rx_mode(tp->netdev);
  2446. /* don't schedule napi before linking */
  2447. if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
  2448. netif_carrier_ok(tp->netdev))
  2449. napi_schedule(&tp->napi);
  2450. if (test_and_clear_bit(PHY_RESET, &tp->flags))
  2451. rtl_phy_reset(tp);
  2452. mutex_unlock(&tp->control);
  2453. out1:
  2454. usb_autopm_put_interface(tp->intf);
  2455. }
  2456. #ifdef CONFIG_PM_SLEEP
  2457. static int rtl_notifier(struct notifier_block *nb, unsigned long action,
  2458. void *data)
  2459. {
  2460. struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
  2461. switch (action) {
  2462. case PM_HIBERNATION_PREPARE:
  2463. case PM_SUSPEND_PREPARE:
  2464. usb_autopm_get_interface(tp->intf);
  2465. break;
  2466. case PM_POST_HIBERNATION:
  2467. case PM_POST_SUSPEND:
  2468. usb_autopm_put_interface(tp->intf);
  2469. break;
  2470. case PM_POST_RESTORE:
  2471. case PM_RESTORE_PREPARE:
  2472. default:
  2473. break;
  2474. }
  2475. return NOTIFY_DONE;
  2476. }
  2477. #endif
  2478. static int rtl8152_open(struct net_device *netdev)
  2479. {
  2480. struct r8152 *tp = netdev_priv(netdev);
  2481. int res = 0;
  2482. res = alloc_all_mem(tp);
  2483. if (res)
  2484. goto out;
  2485. netif_carrier_off(netdev);
  2486. res = usb_autopm_get_interface(tp->intf);
  2487. if (res < 0) {
  2488. free_all_mem(tp);
  2489. goto out;
  2490. }
  2491. mutex_lock(&tp->control);
  2492. tp->rtl_ops.up(tp);
  2493. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2494. tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
  2495. DUPLEX_FULL);
  2496. netif_carrier_off(netdev);
  2497. netif_start_queue(netdev);
  2498. set_bit(WORK_ENABLE, &tp->flags);
  2499. res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2500. if (res) {
  2501. if (res == -ENODEV)
  2502. netif_device_detach(tp->netdev);
  2503. netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
  2504. res);
  2505. free_all_mem(tp);
  2506. } else {
  2507. napi_enable(&tp->napi);
  2508. }
  2509. mutex_unlock(&tp->control);
  2510. usb_autopm_put_interface(tp->intf);
  2511. #ifdef CONFIG_PM_SLEEP
  2512. tp->pm_notifier.notifier_call = rtl_notifier;
  2513. register_pm_notifier(&tp->pm_notifier);
  2514. #endif
  2515. out:
  2516. return res;
  2517. }
  2518. static int rtl8152_close(struct net_device *netdev)
  2519. {
  2520. struct r8152 *tp = netdev_priv(netdev);
  2521. int res = 0;
  2522. #ifdef CONFIG_PM_SLEEP
  2523. unregister_pm_notifier(&tp->pm_notifier);
  2524. #endif
  2525. if (!test_bit(RTL8152_UNPLUG, &tp->flags))
  2526. napi_disable(&tp->napi);
  2527. clear_bit(WORK_ENABLE, &tp->flags);
  2528. usb_kill_urb(tp->intr_urb);
  2529. cancel_delayed_work_sync(&tp->schedule);
  2530. netif_stop_queue(netdev);
  2531. res = usb_autopm_get_interface(tp->intf);
  2532. if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
  2533. rtl_drop_queued_tx(tp);
  2534. rtl_stop_rx(tp);
  2535. } else {
  2536. mutex_lock(&tp->control);
  2537. tp->rtl_ops.down(tp);
  2538. mutex_unlock(&tp->control);
  2539. usb_autopm_put_interface(tp->intf);
  2540. }
  2541. free_all_mem(tp);
  2542. return res;
  2543. }
  2544. static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
  2545. {
  2546. ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
  2547. ocp_reg_write(tp, OCP_EEE_DATA, reg);
  2548. ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
  2549. }
  2550. static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
  2551. {
  2552. u16 data;
  2553. r8152_mmd_indirect(tp, dev, reg);
  2554. data = ocp_reg_read(tp, OCP_EEE_DATA);
  2555. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2556. return data;
  2557. }
  2558. static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
  2559. {
  2560. r8152_mmd_indirect(tp, dev, reg);
  2561. ocp_reg_write(tp, OCP_EEE_DATA, data);
  2562. ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
  2563. }
  2564. static void r8152_eee_en(struct r8152 *tp, bool enable)
  2565. {
  2566. u16 config1, config2, config3;
  2567. u32 ocp_data;
  2568. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2569. config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
  2570. config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
  2571. config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
  2572. if (enable) {
  2573. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2574. config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
  2575. config1 |= sd_rise_time(1);
  2576. config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
  2577. config3 |= fast_snr(42);
  2578. } else {
  2579. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2580. config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
  2581. RX_QUIET_EN);
  2582. config1 |= sd_rise_time(7);
  2583. config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
  2584. config3 |= fast_snr(511);
  2585. }
  2586. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2587. ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
  2588. ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
  2589. ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
  2590. }
  2591. static void r8152b_enable_eee(struct r8152 *tp)
  2592. {
  2593. r8152_eee_en(tp, true);
  2594. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
  2595. }
  2596. static void r8153_eee_en(struct r8152 *tp, bool enable)
  2597. {
  2598. u32 ocp_data;
  2599. u16 config;
  2600. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  2601. config = ocp_reg_read(tp, OCP_EEE_CFG);
  2602. if (enable) {
  2603. ocp_data |= EEE_RX_EN | EEE_TX_EN;
  2604. config |= EEE10_EN;
  2605. } else {
  2606. ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
  2607. config &= ~EEE10_EN;
  2608. }
  2609. ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
  2610. ocp_reg_write(tp, OCP_EEE_CFG, config);
  2611. }
  2612. static void r8153_enable_eee(struct r8152 *tp)
  2613. {
  2614. r8153_eee_en(tp, true);
  2615. ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
  2616. }
  2617. static void r8152b_enable_fc(struct r8152 *tp)
  2618. {
  2619. u16 anar;
  2620. anar = r8152_mdio_read(tp, MII_ADVERTISE);
  2621. anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
  2622. r8152_mdio_write(tp, MII_ADVERTISE, anar);
  2623. }
  2624. static void rtl_tally_reset(struct r8152 *tp)
  2625. {
  2626. u32 ocp_data;
  2627. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
  2628. ocp_data |= TALLY_RESET;
  2629. ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  2630. }
  2631. static void r8152b_init(struct r8152 *tp)
  2632. {
  2633. u32 ocp_data;
  2634. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2635. return;
  2636. r8152_aldps_en(tp, false);
  2637. if (tp->version == RTL_VER_01) {
  2638. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2639. ocp_data &= ~LED_MODE_MASK;
  2640. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2641. }
  2642. r8152_power_cut_en(tp, false);
  2643. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
  2644. ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
  2645. ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
  2646. ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
  2647. ocp_data &= ~MCU_CLK_RATIO_MASK;
  2648. ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
  2649. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
  2650. ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
  2651. SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
  2652. ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
  2653. r8152b_enable_eee(tp);
  2654. r8152_aldps_en(tp, true);
  2655. r8152b_enable_fc(tp);
  2656. rtl_tally_reset(tp);
  2657. /* enable rx aggregation */
  2658. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  2659. ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  2660. ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
  2661. }
  2662. static void r8153_init(struct r8152 *tp)
  2663. {
  2664. u32 ocp_data;
  2665. int i;
  2666. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  2667. return;
  2668. r8153_aldps_en(tp, false);
  2669. r8153_u1u2en(tp, false);
  2670. for (i = 0; i < 500; i++) {
  2671. if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
  2672. AUTOLOAD_DONE)
  2673. break;
  2674. msleep(20);
  2675. }
  2676. for (i = 0; i < 500; i++) {
  2677. ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
  2678. if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
  2679. break;
  2680. msleep(20);
  2681. }
  2682. usb_disable_lpm(tp->udev);
  2683. r8153_u2p3en(tp, false);
  2684. if (tp->version == RTL_VER_04) {
  2685. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
  2686. ocp_data &= ~pwd_dn_scale_mask;
  2687. ocp_data |= pwd_dn_scale(96);
  2688. ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
  2689. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
  2690. ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
  2691. ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
  2692. } else if (tp->version == RTL_VER_05) {
  2693. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
  2694. ocp_data &= ~ECM_ALDPS;
  2695. ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
  2696. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2697. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2698. ocp_data &= ~DYNAMIC_BURST;
  2699. else
  2700. ocp_data |= DYNAMIC_BURST;
  2701. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2702. } else if (tp->version == RTL_VER_06) {
  2703. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
  2704. if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
  2705. ocp_data &= ~DYNAMIC_BURST;
  2706. else
  2707. ocp_data |= DYNAMIC_BURST;
  2708. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
  2709. }
  2710. ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
  2711. ocp_data |= EP4_FULL_FC;
  2712. ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
  2713. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
  2714. ocp_data &= ~TIMER11_EN;
  2715. ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
  2716. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
  2717. ocp_data &= ~LED_MODE_MASK;
  2718. ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
  2719. ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
  2720. if (tp->version == RTL_VER_04 && tp->udev->speed != USB_SPEED_SUPER)
  2721. ocp_data |= LPM_TIMER_500MS;
  2722. else
  2723. ocp_data |= LPM_TIMER_500US;
  2724. ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
  2725. ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
  2726. ocp_data &= ~SEN_VAL_MASK;
  2727. ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
  2728. ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
  2729. ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
  2730. r8153_power_cut_en(tp, false);
  2731. r8153_u1u2en(tp, true);
  2732. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
  2733. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
  2734. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
  2735. PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
  2736. U1U2_SPDWN_EN | L1_SPDWN_EN);
  2737. ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
  2738. PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
  2739. TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
  2740. EEE_SPDWN_EN);
  2741. r8153_enable_eee(tp);
  2742. r8153_aldps_en(tp, true);
  2743. r8152b_enable_fc(tp);
  2744. rtl_tally_reset(tp);
  2745. r8153_u2p3en(tp, true);
  2746. }
  2747. static int rtl8152_pre_reset(struct usb_interface *intf)
  2748. {
  2749. struct r8152 *tp = usb_get_intfdata(intf);
  2750. struct net_device *netdev;
  2751. if (!tp)
  2752. return 0;
  2753. netdev = tp->netdev;
  2754. if (!netif_running(netdev))
  2755. return 0;
  2756. netif_stop_queue(netdev);
  2757. napi_disable(&tp->napi);
  2758. clear_bit(WORK_ENABLE, &tp->flags);
  2759. usb_kill_urb(tp->intr_urb);
  2760. cancel_delayed_work_sync(&tp->schedule);
  2761. if (netif_carrier_ok(netdev)) {
  2762. mutex_lock(&tp->control);
  2763. tp->rtl_ops.disable(tp);
  2764. mutex_unlock(&tp->control);
  2765. }
  2766. return 0;
  2767. }
  2768. static int rtl8152_post_reset(struct usb_interface *intf)
  2769. {
  2770. struct r8152 *tp = usb_get_intfdata(intf);
  2771. struct net_device *netdev;
  2772. if (!tp)
  2773. return 0;
  2774. netdev = tp->netdev;
  2775. if (!netif_running(netdev))
  2776. return 0;
  2777. set_bit(WORK_ENABLE, &tp->flags);
  2778. if (netif_carrier_ok(netdev)) {
  2779. mutex_lock(&tp->control);
  2780. tp->rtl_ops.enable(tp);
  2781. rtl_start_rx(tp);
  2782. rtl8152_set_rx_mode(netdev);
  2783. mutex_unlock(&tp->control);
  2784. }
  2785. napi_enable(&tp->napi);
  2786. netif_wake_queue(netdev);
  2787. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2788. return 0;
  2789. }
  2790. static bool delay_autosuspend(struct r8152 *tp)
  2791. {
  2792. bool sw_linking = !!netif_carrier_ok(tp->netdev);
  2793. bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
  2794. /* This means a linking change occurs and the driver doesn't detect it,
  2795. * yet. If the driver has disabled tx/rx and hw is linking on, the
  2796. * device wouldn't wake up by receiving any packet.
  2797. */
  2798. if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
  2799. return true;
  2800. /* If the linking down is occurred by nway, the device may miss the
  2801. * linking change event. And it wouldn't wake when linking on.
  2802. */
  2803. if (!sw_linking && tp->rtl_ops.in_nway(tp))
  2804. return true;
  2805. else if (!skb_queue_empty(&tp->tx_queue))
  2806. return true;
  2807. else
  2808. return false;
  2809. }
  2810. static int rtl8152_rumtime_suspend(struct r8152 *tp)
  2811. {
  2812. struct net_device *netdev = tp->netdev;
  2813. int ret = 0;
  2814. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2815. u32 rcr = 0;
  2816. if (delay_autosuspend(tp)) {
  2817. ret = -EBUSY;
  2818. goto out1;
  2819. }
  2820. if (netif_carrier_ok(netdev)) {
  2821. u32 ocp_data;
  2822. rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
  2823. ocp_data = rcr & ~RCR_ACPT_ALL;
  2824. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
  2825. rxdy_gated_en(tp, true);
  2826. ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
  2827. PLA_OOB_CTRL);
  2828. if (!(ocp_data & RXFIFO_EMPTY)) {
  2829. rxdy_gated_en(tp, false);
  2830. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  2831. ret = -EBUSY;
  2832. goto out1;
  2833. }
  2834. }
  2835. clear_bit(WORK_ENABLE, &tp->flags);
  2836. usb_kill_urb(tp->intr_urb);
  2837. rtl_runtime_suspend_enable(tp, true);
  2838. if (netif_carrier_ok(netdev)) {
  2839. napi_disable(&tp->napi);
  2840. rtl_stop_rx(tp);
  2841. rxdy_gated_en(tp, false);
  2842. ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
  2843. napi_enable(&tp->napi);
  2844. }
  2845. }
  2846. set_bit(SELECTIVE_SUSPEND, &tp->flags);
  2847. out1:
  2848. return ret;
  2849. }
  2850. static int rtl8152_system_suspend(struct r8152 *tp)
  2851. {
  2852. struct net_device *netdev = tp->netdev;
  2853. int ret = 0;
  2854. netif_device_detach(netdev);
  2855. if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
  2856. clear_bit(WORK_ENABLE, &tp->flags);
  2857. usb_kill_urb(tp->intr_urb);
  2858. napi_disable(&tp->napi);
  2859. cancel_delayed_work_sync(&tp->schedule);
  2860. tp->rtl_ops.down(tp);
  2861. napi_enable(&tp->napi);
  2862. }
  2863. return ret;
  2864. }
  2865. static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
  2866. {
  2867. struct r8152 *tp = usb_get_intfdata(intf);
  2868. int ret;
  2869. mutex_lock(&tp->control);
  2870. if (PMSG_IS_AUTO(message))
  2871. ret = rtl8152_rumtime_suspend(tp);
  2872. else
  2873. ret = rtl8152_system_suspend(tp);
  2874. mutex_unlock(&tp->control);
  2875. return ret;
  2876. }
  2877. static int rtl8152_resume(struct usb_interface *intf)
  2878. {
  2879. struct r8152 *tp = usb_get_intfdata(intf);
  2880. mutex_lock(&tp->control);
  2881. if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2882. tp->rtl_ops.init(tp);
  2883. netif_device_attach(tp->netdev);
  2884. }
  2885. if (netif_running(tp->netdev) && tp->netdev->flags & IFF_UP) {
  2886. if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2887. rtl_runtime_suspend_enable(tp, false);
  2888. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2889. napi_disable(&tp->napi);
  2890. set_bit(WORK_ENABLE, &tp->flags);
  2891. if (netif_carrier_ok(tp->netdev)) {
  2892. if (rtl8152_get_speed(tp) & LINK_STATUS) {
  2893. rtl_start_rx(tp);
  2894. } else {
  2895. netif_carrier_off(tp->netdev);
  2896. tp->rtl_ops.disable(tp);
  2897. netif_info(tp, link, tp->netdev,
  2898. "linking down\n");
  2899. }
  2900. }
  2901. napi_enable(&tp->napi);
  2902. } else {
  2903. tp->rtl_ops.up(tp);
  2904. rtl8152_set_speed(tp, AUTONEG_ENABLE,
  2905. tp->mii.supports_gmii ?
  2906. SPEED_1000 : SPEED_100,
  2907. DUPLEX_FULL);
  2908. netif_carrier_off(tp->netdev);
  2909. set_bit(WORK_ENABLE, &tp->flags);
  2910. }
  2911. usb_submit_urb(tp->intr_urb, GFP_KERNEL);
  2912. } else if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
  2913. if (tp->netdev->flags & IFF_UP)
  2914. rtl_runtime_suspend_enable(tp, false);
  2915. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2916. }
  2917. mutex_unlock(&tp->control);
  2918. return 0;
  2919. }
  2920. static int rtl8152_reset_resume(struct usb_interface *intf)
  2921. {
  2922. struct r8152 *tp = usb_get_intfdata(intf);
  2923. clear_bit(SELECTIVE_SUSPEND, &tp->flags);
  2924. return rtl8152_resume(intf);
  2925. }
  2926. static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2927. {
  2928. struct r8152 *tp = netdev_priv(dev);
  2929. if (usb_autopm_get_interface(tp->intf) < 0)
  2930. return;
  2931. if (!rtl_can_wakeup(tp)) {
  2932. wol->supported = 0;
  2933. wol->wolopts = 0;
  2934. } else {
  2935. mutex_lock(&tp->control);
  2936. wol->supported = WAKE_ANY;
  2937. wol->wolopts = __rtl_get_wol(tp);
  2938. mutex_unlock(&tp->control);
  2939. }
  2940. usb_autopm_put_interface(tp->intf);
  2941. }
  2942. static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
  2943. {
  2944. struct r8152 *tp = netdev_priv(dev);
  2945. int ret;
  2946. if (!rtl_can_wakeup(tp))
  2947. return -EOPNOTSUPP;
  2948. if (wol->wolopts & ~WAKE_ANY)
  2949. return -EINVAL;
  2950. ret = usb_autopm_get_interface(tp->intf);
  2951. if (ret < 0)
  2952. goto out_set_wol;
  2953. mutex_lock(&tp->control);
  2954. __rtl_set_wol(tp, wol->wolopts);
  2955. tp->saved_wolopts = wol->wolopts & WAKE_ANY;
  2956. mutex_unlock(&tp->control);
  2957. usb_autopm_put_interface(tp->intf);
  2958. out_set_wol:
  2959. return ret;
  2960. }
  2961. static u32 rtl8152_get_msglevel(struct net_device *dev)
  2962. {
  2963. struct r8152 *tp = netdev_priv(dev);
  2964. return tp->msg_enable;
  2965. }
  2966. static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
  2967. {
  2968. struct r8152 *tp = netdev_priv(dev);
  2969. tp->msg_enable = value;
  2970. }
  2971. static void rtl8152_get_drvinfo(struct net_device *netdev,
  2972. struct ethtool_drvinfo *info)
  2973. {
  2974. struct r8152 *tp = netdev_priv(netdev);
  2975. strlcpy(info->driver, MODULENAME, sizeof(info->driver));
  2976. strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
  2977. usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
  2978. }
  2979. static
  2980. int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
  2981. {
  2982. struct r8152 *tp = netdev_priv(netdev);
  2983. int ret;
  2984. if (!tp->mii.mdio_read)
  2985. return -EOPNOTSUPP;
  2986. ret = usb_autopm_get_interface(tp->intf);
  2987. if (ret < 0)
  2988. goto out;
  2989. mutex_lock(&tp->control);
  2990. ret = mii_ethtool_gset(&tp->mii, cmd);
  2991. mutex_unlock(&tp->control);
  2992. usb_autopm_put_interface(tp->intf);
  2993. out:
  2994. return ret;
  2995. }
  2996. static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
  2997. {
  2998. struct r8152 *tp = netdev_priv(dev);
  2999. int ret;
  3000. ret = usb_autopm_get_interface(tp->intf);
  3001. if (ret < 0)
  3002. goto out;
  3003. mutex_lock(&tp->control);
  3004. ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
  3005. mutex_unlock(&tp->control);
  3006. usb_autopm_put_interface(tp->intf);
  3007. out:
  3008. return ret;
  3009. }
  3010. static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
  3011. "tx_packets",
  3012. "rx_packets",
  3013. "tx_errors",
  3014. "rx_errors",
  3015. "rx_missed",
  3016. "align_errors",
  3017. "tx_single_collisions",
  3018. "tx_multi_collisions",
  3019. "rx_unicast",
  3020. "rx_broadcast",
  3021. "rx_multicast",
  3022. "tx_aborted",
  3023. "tx_underrun",
  3024. };
  3025. static int rtl8152_get_sset_count(struct net_device *dev, int sset)
  3026. {
  3027. switch (sset) {
  3028. case ETH_SS_STATS:
  3029. return ARRAY_SIZE(rtl8152_gstrings);
  3030. default:
  3031. return -EOPNOTSUPP;
  3032. }
  3033. }
  3034. static void rtl8152_get_ethtool_stats(struct net_device *dev,
  3035. struct ethtool_stats *stats, u64 *data)
  3036. {
  3037. struct r8152 *tp = netdev_priv(dev);
  3038. struct tally_counter tally;
  3039. if (usb_autopm_get_interface(tp->intf) < 0)
  3040. return;
  3041. generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
  3042. usb_autopm_put_interface(tp->intf);
  3043. data[0] = le64_to_cpu(tally.tx_packets);
  3044. data[1] = le64_to_cpu(tally.rx_packets);
  3045. data[2] = le64_to_cpu(tally.tx_errors);
  3046. data[3] = le32_to_cpu(tally.rx_errors);
  3047. data[4] = le16_to_cpu(tally.rx_missed);
  3048. data[5] = le16_to_cpu(tally.align_errors);
  3049. data[6] = le32_to_cpu(tally.tx_one_collision);
  3050. data[7] = le32_to_cpu(tally.tx_multi_collision);
  3051. data[8] = le64_to_cpu(tally.rx_unicast);
  3052. data[9] = le64_to_cpu(tally.rx_broadcast);
  3053. data[10] = le32_to_cpu(tally.rx_multicast);
  3054. data[11] = le16_to_cpu(tally.tx_aborted);
  3055. data[12] = le16_to_cpu(tally.tx_underrun);
  3056. }
  3057. static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
  3058. {
  3059. switch (stringset) {
  3060. case ETH_SS_STATS:
  3061. memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
  3062. break;
  3063. }
  3064. }
  3065. static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3066. {
  3067. u32 ocp_data, lp, adv, supported = 0;
  3068. u16 val;
  3069. val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
  3070. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3071. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
  3072. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3073. val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
  3074. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3075. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3076. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3077. eee->eee_enabled = !!ocp_data;
  3078. eee->eee_active = !!(supported & adv & lp);
  3079. eee->supported = supported;
  3080. eee->advertised = adv;
  3081. eee->lp_advertised = lp;
  3082. return 0;
  3083. }
  3084. static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3085. {
  3086. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3087. r8152_eee_en(tp, eee->eee_enabled);
  3088. if (!eee->eee_enabled)
  3089. val = 0;
  3090. r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
  3091. return 0;
  3092. }
  3093. static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3094. {
  3095. u32 ocp_data, lp, adv, supported = 0;
  3096. u16 val;
  3097. val = ocp_reg_read(tp, OCP_EEE_ABLE);
  3098. supported = mmd_eee_cap_to_ethtool_sup_t(val);
  3099. val = ocp_reg_read(tp, OCP_EEE_ADV);
  3100. adv = mmd_eee_adv_to_ethtool_adv_t(val);
  3101. val = ocp_reg_read(tp, OCP_EEE_LPABLE);
  3102. lp = mmd_eee_adv_to_ethtool_adv_t(val);
  3103. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
  3104. ocp_data &= EEE_RX_EN | EEE_TX_EN;
  3105. eee->eee_enabled = !!ocp_data;
  3106. eee->eee_active = !!(supported & adv & lp);
  3107. eee->supported = supported;
  3108. eee->advertised = adv;
  3109. eee->lp_advertised = lp;
  3110. return 0;
  3111. }
  3112. static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
  3113. {
  3114. u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
  3115. r8153_eee_en(tp, eee->eee_enabled);
  3116. if (!eee->eee_enabled)
  3117. val = 0;
  3118. ocp_reg_write(tp, OCP_EEE_ADV, val);
  3119. return 0;
  3120. }
  3121. static int
  3122. rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
  3123. {
  3124. struct r8152 *tp = netdev_priv(net);
  3125. int ret;
  3126. ret = usb_autopm_get_interface(tp->intf);
  3127. if (ret < 0)
  3128. goto out;
  3129. mutex_lock(&tp->control);
  3130. ret = tp->rtl_ops.eee_get(tp, edata);
  3131. mutex_unlock(&tp->control);
  3132. usb_autopm_put_interface(tp->intf);
  3133. out:
  3134. return ret;
  3135. }
  3136. static int
  3137. rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
  3138. {
  3139. struct r8152 *tp = netdev_priv(net);
  3140. int ret;
  3141. ret = usb_autopm_get_interface(tp->intf);
  3142. if (ret < 0)
  3143. goto out;
  3144. mutex_lock(&tp->control);
  3145. ret = tp->rtl_ops.eee_set(tp, edata);
  3146. if (!ret)
  3147. ret = mii_nway_restart(&tp->mii);
  3148. mutex_unlock(&tp->control);
  3149. usb_autopm_put_interface(tp->intf);
  3150. out:
  3151. return ret;
  3152. }
  3153. static int rtl8152_nway_reset(struct net_device *dev)
  3154. {
  3155. struct r8152 *tp = netdev_priv(dev);
  3156. int ret;
  3157. ret = usb_autopm_get_interface(tp->intf);
  3158. if (ret < 0)
  3159. goto out;
  3160. mutex_lock(&tp->control);
  3161. ret = mii_nway_restart(&tp->mii);
  3162. mutex_unlock(&tp->control);
  3163. usb_autopm_put_interface(tp->intf);
  3164. out:
  3165. return ret;
  3166. }
  3167. static int rtl8152_get_coalesce(struct net_device *netdev,
  3168. struct ethtool_coalesce *coalesce)
  3169. {
  3170. struct r8152 *tp = netdev_priv(netdev);
  3171. switch (tp->version) {
  3172. case RTL_VER_01:
  3173. case RTL_VER_02:
  3174. return -EOPNOTSUPP;
  3175. default:
  3176. break;
  3177. }
  3178. coalesce->rx_coalesce_usecs = tp->coalesce;
  3179. return 0;
  3180. }
  3181. static int rtl8152_set_coalesce(struct net_device *netdev,
  3182. struct ethtool_coalesce *coalesce)
  3183. {
  3184. struct r8152 *tp = netdev_priv(netdev);
  3185. int ret;
  3186. switch (tp->version) {
  3187. case RTL_VER_01:
  3188. case RTL_VER_02:
  3189. return -EOPNOTSUPP;
  3190. default:
  3191. break;
  3192. }
  3193. if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
  3194. return -EINVAL;
  3195. ret = usb_autopm_get_interface(tp->intf);
  3196. if (ret < 0)
  3197. return ret;
  3198. mutex_lock(&tp->control);
  3199. if (tp->coalesce != coalesce->rx_coalesce_usecs) {
  3200. tp->coalesce = coalesce->rx_coalesce_usecs;
  3201. if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
  3202. r8153_set_rx_early_timeout(tp);
  3203. }
  3204. mutex_unlock(&tp->control);
  3205. usb_autopm_put_interface(tp->intf);
  3206. return ret;
  3207. }
  3208. static struct ethtool_ops ops = {
  3209. .get_drvinfo = rtl8152_get_drvinfo,
  3210. .get_settings = rtl8152_get_settings,
  3211. .set_settings = rtl8152_set_settings,
  3212. .get_link = ethtool_op_get_link,
  3213. .nway_reset = rtl8152_nway_reset,
  3214. .get_msglevel = rtl8152_get_msglevel,
  3215. .set_msglevel = rtl8152_set_msglevel,
  3216. .get_wol = rtl8152_get_wol,
  3217. .set_wol = rtl8152_set_wol,
  3218. .get_strings = rtl8152_get_strings,
  3219. .get_sset_count = rtl8152_get_sset_count,
  3220. .get_ethtool_stats = rtl8152_get_ethtool_stats,
  3221. .get_coalesce = rtl8152_get_coalesce,
  3222. .set_coalesce = rtl8152_set_coalesce,
  3223. .get_eee = rtl_ethtool_get_eee,
  3224. .set_eee = rtl_ethtool_set_eee,
  3225. };
  3226. static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  3227. {
  3228. struct r8152 *tp = netdev_priv(netdev);
  3229. struct mii_ioctl_data *data = if_mii(rq);
  3230. int res;
  3231. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3232. return -ENODEV;
  3233. res = usb_autopm_get_interface(tp->intf);
  3234. if (res < 0)
  3235. goto out;
  3236. switch (cmd) {
  3237. case SIOCGMIIPHY:
  3238. data->phy_id = R8152_PHY_ID; /* Internal PHY */
  3239. break;
  3240. case SIOCGMIIREG:
  3241. mutex_lock(&tp->control);
  3242. data->val_out = r8152_mdio_read(tp, data->reg_num);
  3243. mutex_unlock(&tp->control);
  3244. break;
  3245. case SIOCSMIIREG:
  3246. if (!capable(CAP_NET_ADMIN)) {
  3247. res = -EPERM;
  3248. break;
  3249. }
  3250. mutex_lock(&tp->control);
  3251. r8152_mdio_write(tp, data->reg_num, data->val_in);
  3252. mutex_unlock(&tp->control);
  3253. break;
  3254. default:
  3255. res = -EOPNOTSUPP;
  3256. }
  3257. usb_autopm_put_interface(tp->intf);
  3258. out:
  3259. return res;
  3260. }
  3261. static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
  3262. {
  3263. struct r8152 *tp = netdev_priv(dev);
  3264. int ret;
  3265. switch (tp->version) {
  3266. case RTL_VER_01:
  3267. case RTL_VER_02:
  3268. return eth_change_mtu(dev, new_mtu);
  3269. default:
  3270. break;
  3271. }
  3272. if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
  3273. return -EINVAL;
  3274. ret = usb_autopm_get_interface(tp->intf);
  3275. if (ret < 0)
  3276. return ret;
  3277. mutex_lock(&tp->control);
  3278. dev->mtu = new_mtu;
  3279. if (netif_running(dev) && netif_carrier_ok(dev))
  3280. r8153_set_rx_early_size(tp);
  3281. mutex_unlock(&tp->control);
  3282. usb_autopm_put_interface(tp->intf);
  3283. return ret;
  3284. }
  3285. static const struct net_device_ops rtl8152_netdev_ops = {
  3286. .ndo_open = rtl8152_open,
  3287. .ndo_stop = rtl8152_close,
  3288. .ndo_do_ioctl = rtl8152_ioctl,
  3289. .ndo_start_xmit = rtl8152_start_xmit,
  3290. .ndo_tx_timeout = rtl8152_tx_timeout,
  3291. .ndo_set_features = rtl8152_set_features,
  3292. .ndo_set_rx_mode = rtl8152_set_rx_mode,
  3293. .ndo_set_mac_address = rtl8152_set_mac_address,
  3294. .ndo_change_mtu = rtl8152_change_mtu,
  3295. .ndo_validate_addr = eth_validate_addr,
  3296. .ndo_features_check = rtl8152_features_check,
  3297. };
  3298. static void r8152b_get_version(struct r8152 *tp)
  3299. {
  3300. u32 ocp_data;
  3301. u16 version;
  3302. ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
  3303. version = (u16)(ocp_data & VERSION_MASK);
  3304. switch (version) {
  3305. case 0x4c00:
  3306. tp->version = RTL_VER_01;
  3307. break;
  3308. case 0x4c10:
  3309. tp->version = RTL_VER_02;
  3310. break;
  3311. case 0x5c00:
  3312. tp->version = RTL_VER_03;
  3313. tp->mii.supports_gmii = 1;
  3314. break;
  3315. case 0x5c10:
  3316. tp->version = RTL_VER_04;
  3317. tp->mii.supports_gmii = 1;
  3318. break;
  3319. case 0x5c20:
  3320. tp->version = RTL_VER_05;
  3321. tp->mii.supports_gmii = 1;
  3322. break;
  3323. case 0x5c30:
  3324. tp->version = RTL_VER_06;
  3325. tp->mii.supports_gmii = 1;
  3326. break;
  3327. default:
  3328. netif_info(tp, probe, tp->netdev,
  3329. "Unknown version 0x%04x\n", version);
  3330. break;
  3331. }
  3332. }
  3333. static void rtl8152_unload(struct r8152 *tp)
  3334. {
  3335. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3336. return;
  3337. if (tp->version != RTL_VER_01)
  3338. r8152_power_cut_en(tp, true);
  3339. }
  3340. static void rtl8153_unload(struct r8152 *tp)
  3341. {
  3342. if (test_bit(RTL8152_UNPLUG, &tp->flags))
  3343. return;
  3344. r8153_power_cut_en(tp, false);
  3345. }
  3346. static int rtl_ops_init(struct r8152 *tp)
  3347. {
  3348. struct rtl_ops *ops = &tp->rtl_ops;
  3349. int ret = 0;
  3350. switch (tp->version) {
  3351. case RTL_VER_01:
  3352. case RTL_VER_02:
  3353. ops->init = r8152b_init;
  3354. ops->enable = rtl8152_enable;
  3355. ops->disable = rtl8152_disable;
  3356. ops->up = rtl8152_up;
  3357. ops->down = rtl8152_down;
  3358. ops->unload = rtl8152_unload;
  3359. ops->eee_get = r8152_get_eee;
  3360. ops->eee_set = r8152_set_eee;
  3361. ops->in_nway = rtl8152_in_nway;
  3362. break;
  3363. case RTL_VER_03:
  3364. case RTL_VER_04:
  3365. case RTL_VER_05:
  3366. case RTL_VER_06:
  3367. ops->init = r8153_init;
  3368. ops->enable = rtl8153_enable;
  3369. ops->disable = rtl8153_disable;
  3370. ops->up = rtl8153_up;
  3371. ops->down = rtl8153_down;
  3372. ops->unload = rtl8153_unload;
  3373. ops->eee_get = r8153_get_eee;
  3374. ops->eee_set = r8153_set_eee;
  3375. ops->in_nway = rtl8153_in_nway;
  3376. break;
  3377. default:
  3378. ret = -ENODEV;
  3379. netif_err(tp, probe, tp->netdev, "Unknown Device\n");
  3380. break;
  3381. }
  3382. return ret;
  3383. }
  3384. static int rtl8152_probe(struct usb_interface *intf,
  3385. const struct usb_device_id *id)
  3386. {
  3387. struct usb_device *udev = interface_to_usbdev(intf);
  3388. struct r8152 *tp;
  3389. struct net_device *netdev;
  3390. int ret;
  3391. if (udev->actconfig->desc.bConfigurationValue != 1) {
  3392. usb_driver_set_configuration(udev, 1);
  3393. return -ENODEV;
  3394. }
  3395. usb_reset_device(udev);
  3396. netdev = alloc_etherdev(sizeof(struct r8152));
  3397. if (!netdev) {
  3398. dev_err(&intf->dev, "Out of memory\n");
  3399. return -ENOMEM;
  3400. }
  3401. SET_NETDEV_DEV(netdev, &intf->dev);
  3402. tp = netdev_priv(netdev);
  3403. tp->msg_enable = 0x7FFF;
  3404. tp->udev = udev;
  3405. tp->netdev = netdev;
  3406. tp->intf = intf;
  3407. r8152b_get_version(tp);
  3408. ret = rtl_ops_init(tp);
  3409. if (ret)
  3410. goto out;
  3411. mutex_init(&tp->control);
  3412. INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
  3413. netdev->netdev_ops = &rtl8152_netdev_ops;
  3414. netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
  3415. netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3416. NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
  3417. NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
  3418. NETIF_F_HW_VLAN_CTAG_TX;
  3419. netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
  3420. NETIF_F_TSO | NETIF_F_FRAGLIST |
  3421. NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
  3422. NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
  3423. netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
  3424. NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
  3425. NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
  3426. if (tp->version == RTL_VER_01) {
  3427. netdev->features &= ~NETIF_F_RXCSUM;
  3428. netdev->hw_features &= ~NETIF_F_RXCSUM;
  3429. }
  3430. netdev->ethtool_ops = &ops;
  3431. netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
  3432. tp->mii.dev = netdev;
  3433. tp->mii.mdio_read = read_mii_word;
  3434. tp->mii.mdio_write = write_mii_word;
  3435. tp->mii.phy_id_mask = 0x3f;
  3436. tp->mii.reg_num_mask = 0x1f;
  3437. tp->mii.phy_id = R8152_PHY_ID;
  3438. switch (udev->speed) {
  3439. case USB_SPEED_SUPER:
  3440. tp->coalesce = COALESCE_SUPER;
  3441. break;
  3442. case USB_SPEED_HIGH:
  3443. tp->coalesce = COALESCE_HIGH;
  3444. break;
  3445. default:
  3446. tp->coalesce = COALESCE_SLOW;
  3447. break;
  3448. }
  3449. intf->needs_remote_wakeup = 1;
  3450. tp->rtl_ops.init(tp);
  3451. set_ethernet_addr(tp);
  3452. usb_set_intfdata(intf, tp);
  3453. netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
  3454. ret = register_netdev(netdev);
  3455. if (ret != 0) {
  3456. netif_err(tp, probe, netdev, "couldn't register the device\n");
  3457. goto out1;
  3458. }
  3459. if (!rtl_can_wakeup(tp))
  3460. __rtl_set_wol(tp, 0);
  3461. tp->saved_wolopts = __rtl_get_wol(tp);
  3462. if (tp->saved_wolopts)
  3463. device_set_wakeup_enable(&udev->dev, true);
  3464. else
  3465. device_set_wakeup_enable(&udev->dev, false);
  3466. netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
  3467. return 0;
  3468. out1:
  3469. netif_napi_del(&tp->napi);
  3470. usb_set_intfdata(intf, NULL);
  3471. out:
  3472. free_netdev(netdev);
  3473. return ret;
  3474. }
  3475. static void rtl8152_disconnect(struct usb_interface *intf)
  3476. {
  3477. struct r8152 *tp = usb_get_intfdata(intf);
  3478. usb_set_intfdata(intf, NULL);
  3479. if (tp) {
  3480. struct usb_device *udev = tp->udev;
  3481. if (udev->state == USB_STATE_NOTATTACHED)
  3482. set_bit(RTL8152_UNPLUG, &tp->flags);
  3483. netif_napi_del(&tp->napi);
  3484. unregister_netdev(tp->netdev);
  3485. tp->rtl_ops.unload(tp);
  3486. free_netdev(tp->netdev);
  3487. }
  3488. }
  3489. #define REALTEK_USB_DEVICE(vend, prod) \
  3490. .match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
  3491. USB_DEVICE_ID_MATCH_INT_CLASS, \
  3492. .idVendor = (vend), \
  3493. .idProduct = (prod), \
  3494. .bInterfaceClass = USB_CLASS_VENDOR_SPEC \
  3495. }, \
  3496. { \
  3497. .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
  3498. USB_DEVICE_ID_MATCH_DEVICE, \
  3499. .idVendor = (vend), \
  3500. .idProduct = (prod), \
  3501. .bInterfaceClass = USB_CLASS_COMM, \
  3502. .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
  3503. .bInterfaceProtocol = USB_CDC_PROTO_NONE
  3504. /* table of devices that work with this driver */
  3505. static struct usb_device_id rtl8152_table[] = {
  3506. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
  3507. {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
  3508. {REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
  3509. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x7205)},
  3510. {REALTEK_USB_DEVICE(VENDOR_ID_LENOVO, 0x304f)},
  3511. {REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
  3512. {REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff)},
  3513. {}
  3514. };
  3515. MODULE_DEVICE_TABLE(usb, rtl8152_table);
  3516. static struct usb_driver rtl8152_driver = {
  3517. .name = MODULENAME,
  3518. .id_table = rtl8152_table,
  3519. .probe = rtl8152_probe,
  3520. .disconnect = rtl8152_disconnect,
  3521. .suspend = rtl8152_suspend,
  3522. .resume = rtl8152_resume,
  3523. .reset_resume = rtl8152_reset_resume,
  3524. .pre_reset = rtl8152_pre_reset,
  3525. .post_reset = rtl8152_post_reset,
  3526. .supports_autosuspend = 1,
  3527. .disable_hub_initiated_lpm = 1,
  3528. };
  3529. module_usb_driver(rtl8152_driver);
  3530. MODULE_AUTHOR(DRIVER_AUTHOR);
  3531. MODULE_DESCRIPTION(DRIVER_DESC);
  3532. MODULE_LICENSE("GPL");