smsc95xx.c 50 KB

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  1. /***************************************************************************
  2. *
  3. * Copyright (C) 2007-2008 SMSC
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version 2
  8. * of the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, see <http://www.gnu.org/licenses/>.
  17. *
  18. *****************************************************************************/
  19. #include <linux/module.h>
  20. #include <linux/kmod.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/etherdevice.h>
  23. #include <linux/ethtool.h>
  24. #include <linux/mii.h>
  25. #include <linux/usb.h>
  26. #include <linux/bitrev.h>
  27. #include <linux/crc16.h>
  28. #include <linux/crc32.h>
  29. #include <linux/usb/usbnet.h>
  30. #include <linux/slab.h>
  31. #include "smsc95xx.h"
  32. #define SMSC_CHIPNAME "smsc95xx"
  33. #define SMSC_DRIVER_VERSION "1.0.4"
  34. #define HS_USB_PKT_SIZE (512)
  35. #define FS_USB_PKT_SIZE (64)
  36. #define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
  37. #define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
  38. #define DEFAULT_BULK_IN_DELAY (0x00002000)
  39. #define MAX_SINGLE_PACKET_SIZE (2048)
  40. #define LAN95XX_EEPROM_MAGIC (0x9500)
  41. #define EEPROM_MAC_OFFSET (0x01)
  42. #define DEFAULT_TX_CSUM_ENABLE (true)
  43. #define DEFAULT_RX_CSUM_ENABLE (true)
  44. #define SMSC95XX_INTERNAL_PHY_ID (1)
  45. #define SMSC95XX_TX_OVERHEAD (8)
  46. #define SMSC95XX_TX_OVERHEAD_CSUM (12)
  47. #define SUPPORTED_WAKE (WAKE_PHY | WAKE_UCAST | WAKE_BCAST | \
  48. WAKE_MCAST | WAKE_ARP | WAKE_MAGIC)
  49. #define FEATURE_8_WAKEUP_FILTERS (0x01)
  50. #define FEATURE_PHY_NLP_CROSSOVER (0x02)
  51. #define FEATURE_REMOTE_WAKEUP (0x04)
  52. #define SUSPEND_SUSPEND0 (0x01)
  53. #define SUSPEND_SUSPEND1 (0x02)
  54. #define SUSPEND_SUSPEND2 (0x04)
  55. #define SUSPEND_SUSPEND3 (0x08)
  56. #define SUSPEND_ALLMODES (SUSPEND_SUSPEND0 | SUSPEND_SUSPEND1 | \
  57. SUSPEND_SUSPEND2 | SUSPEND_SUSPEND3)
  58. struct smsc95xx_priv {
  59. u32 mac_cr;
  60. u32 hash_hi;
  61. u32 hash_lo;
  62. u32 wolopts;
  63. spinlock_t mac_cr_lock;
  64. u8 features;
  65. u8 suspend_flags;
  66. };
  67. static bool turbo_mode = true;
  68. module_param(turbo_mode, bool, 0644);
  69. MODULE_PARM_DESC(turbo_mode, "Enable multiple frames per Rx transaction");
  70. static int __must_check __smsc95xx_read_reg(struct usbnet *dev, u32 index,
  71. u32 *data, int in_pm)
  72. {
  73. u32 buf;
  74. int ret;
  75. int (*fn)(struct usbnet *, u8, u8, u16, u16, void *, u16);
  76. BUG_ON(!dev);
  77. if (!in_pm)
  78. fn = usbnet_read_cmd;
  79. else
  80. fn = usbnet_read_cmd_nopm;
  81. ret = fn(dev, USB_VENDOR_REQUEST_READ_REGISTER, USB_DIR_IN
  82. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  83. 0, index, &buf, 4);
  84. if (unlikely(ret < 0))
  85. netdev_warn(dev->net, "Failed to read reg index 0x%08x: %d\n",
  86. index, ret);
  87. le32_to_cpus(&buf);
  88. *data = buf;
  89. return ret;
  90. }
  91. static int __must_check __smsc95xx_write_reg(struct usbnet *dev, u32 index,
  92. u32 data, int in_pm)
  93. {
  94. u32 buf;
  95. int ret;
  96. int (*fn)(struct usbnet *, u8, u8, u16, u16, const void *, u16);
  97. BUG_ON(!dev);
  98. if (!in_pm)
  99. fn = usbnet_write_cmd;
  100. else
  101. fn = usbnet_write_cmd_nopm;
  102. buf = data;
  103. cpu_to_le32s(&buf);
  104. ret = fn(dev, USB_VENDOR_REQUEST_WRITE_REGISTER, USB_DIR_OUT
  105. | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
  106. 0, index, &buf, 4);
  107. if (unlikely(ret < 0))
  108. netdev_warn(dev->net, "Failed to write reg index 0x%08x: %d\n",
  109. index, ret);
  110. return ret;
  111. }
  112. static int __must_check smsc95xx_read_reg_nopm(struct usbnet *dev, u32 index,
  113. u32 *data)
  114. {
  115. return __smsc95xx_read_reg(dev, index, data, 1);
  116. }
  117. static int __must_check smsc95xx_write_reg_nopm(struct usbnet *dev, u32 index,
  118. u32 data)
  119. {
  120. return __smsc95xx_write_reg(dev, index, data, 1);
  121. }
  122. static int __must_check smsc95xx_read_reg(struct usbnet *dev, u32 index,
  123. u32 *data)
  124. {
  125. return __smsc95xx_read_reg(dev, index, data, 0);
  126. }
  127. static int __must_check smsc95xx_write_reg(struct usbnet *dev, u32 index,
  128. u32 data)
  129. {
  130. return __smsc95xx_write_reg(dev, index, data, 0);
  131. }
  132. /* Loop until the read is completed with timeout
  133. * called with phy_mutex held */
  134. static int __must_check __smsc95xx_phy_wait_not_busy(struct usbnet *dev,
  135. int in_pm)
  136. {
  137. unsigned long start_time = jiffies;
  138. u32 val;
  139. int ret;
  140. do {
  141. ret = __smsc95xx_read_reg(dev, MII_ADDR, &val, in_pm);
  142. if (ret < 0) {
  143. netdev_warn(dev->net, "Error reading MII_ACCESS\n");
  144. return ret;
  145. }
  146. if (!(val & MII_BUSY_))
  147. return 0;
  148. } while (!time_after(jiffies, start_time + HZ));
  149. return -EIO;
  150. }
  151. static int __smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx,
  152. int in_pm)
  153. {
  154. struct usbnet *dev = netdev_priv(netdev);
  155. u32 val, addr;
  156. int ret;
  157. mutex_lock(&dev->phy_mutex);
  158. /* confirm MII not busy */
  159. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  160. if (ret < 0) {
  161. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_read\n");
  162. goto done;
  163. }
  164. /* set the address, index & direction (read from PHY) */
  165. phy_id &= dev->mii.phy_id_mask;
  166. idx &= dev->mii.reg_num_mask;
  167. addr = (phy_id << 11) | (idx << 6) | MII_READ_ | MII_BUSY_;
  168. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  169. if (ret < 0) {
  170. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  171. goto done;
  172. }
  173. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  174. if (ret < 0) {
  175. netdev_warn(dev->net, "Timed out reading MII reg %02X\n", idx);
  176. goto done;
  177. }
  178. ret = __smsc95xx_read_reg(dev, MII_DATA, &val, in_pm);
  179. if (ret < 0) {
  180. netdev_warn(dev->net, "Error reading MII_DATA\n");
  181. goto done;
  182. }
  183. ret = (u16)(val & 0xFFFF);
  184. done:
  185. mutex_unlock(&dev->phy_mutex);
  186. return ret;
  187. }
  188. static void __smsc95xx_mdio_write(struct net_device *netdev, int phy_id,
  189. int idx, int regval, int in_pm)
  190. {
  191. struct usbnet *dev = netdev_priv(netdev);
  192. u32 val, addr;
  193. int ret;
  194. mutex_lock(&dev->phy_mutex);
  195. /* confirm MII not busy */
  196. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  197. if (ret < 0) {
  198. netdev_warn(dev->net, "MII is busy in smsc95xx_mdio_write\n");
  199. goto done;
  200. }
  201. val = regval;
  202. ret = __smsc95xx_write_reg(dev, MII_DATA, val, in_pm);
  203. if (ret < 0) {
  204. netdev_warn(dev->net, "Error writing MII_DATA\n");
  205. goto done;
  206. }
  207. /* set the address, index & direction (write to PHY) */
  208. phy_id &= dev->mii.phy_id_mask;
  209. idx &= dev->mii.reg_num_mask;
  210. addr = (phy_id << 11) | (idx << 6) | MII_WRITE_ | MII_BUSY_;
  211. ret = __smsc95xx_write_reg(dev, MII_ADDR, addr, in_pm);
  212. if (ret < 0) {
  213. netdev_warn(dev->net, "Error writing MII_ADDR\n");
  214. goto done;
  215. }
  216. ret = __smsc95xx_phy_wait_not_busy(dev, in_pm);
  217. if (ret < 0) {
  218. netdev_warn(dev->net, "Timed out writing MII reg %02X\n", idx);
  219. goto done;
  220. }
  221. done:
  222. mutex_unlock(&dev->phy_mutex);
  223. }
  224. static int smsc95xx_mdio_read_nopm(struct net_device *netdev, int phy_id,
  225. int idx)
  226. {
  227. return __smsc95xx_mdio_read(netdev, phy_id, idx, 1);
  228. }
  229. static void smsc95xx_mdio_write_nopm(struct net_device *netdev, int phy_id,
  230. int idx, int regval)
  231. {
  232. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 1);
  233. }
  234. static int smsc95xx_mdio_read(struct net_device *netdev, int phy_id, int idx)
  235. {
  236. return __smsc95xx_mdio_read(netdev, phy_id, idx, 0);
  237. }
  238. static void smsc95xx_mdio_write(struct net_device *netdev, int phy_id, int idx,
  239. int regval)
  240. {
  241. __smsc95xx_mdio_write(netdev, phy_id, idx, regval, 0);
  242. }
  243. static int __must_check smsc95xx_wait_eeprom(struct usbnet *dev)
  244. {
  245. unsigned long start_time = jiffies;
  246. u32 val;
  247. int ret;
  248. do {
  249. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  250. if (ret < 0) {
  251. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  252. return ret;
  253. }
  254. if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
  255. break;
  256. udelay(40);
  257. } while (!time_after(jiffies, start_time + HZ));
  258. if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
  259. netdev_warn(dev->net, "EEPROM read operation timeout\n");
  260. return -EIO;
  261. }
  262. return 0;
  263. }
  264. static int __must_check smsc95xx_eeprom_confirm_not_busy(struct usbnet *dev)
  265. {
  266. unsigned long start_time = jiffies;
  267. u32 val;
  268. int ret;
  269. do {
  270. ret = smsc95xx_read_reg(dev, E2P_CMD, &val);
  271. if (ret < 0) {
  272. netdev_warn(dev->net, "Error reading E2P_CMD\n");
  273. return ret;
  274. }
  275. if (!(val & E2P_CMD_BUSY_))
  276. return 0;
  277. udelay(40);
  278. } while (!time_after(jiffies, start_time + HZ));
  279. netdev_warn(dev->net, "EEPROM is busy\n");
  280. return -EIO;
  281. }
  282. static int smsc95xx_read_eeprom(struct usbnet *dev, u32 offset, u32 length,
  283. u8 *data)
  284. {
  285. u32 val;
  286. int i, ret;
  287. BUG_ON(!dev);
  288. BUG_ON(!data);
  289. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  290. if (ret)
  291. return ret;
  292. for (i = 0; i < length; i++) {
  293. val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
  294. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  295. if (ret < 0) {
  296. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  297. return ret;
  298. }
  299. ret = smsc95xx_wait_eeprom(dev);
  300. if (ret < 0)
  301. return ret;
  302. ret = smsc95xx_read_reg(dev, E2P_DATA, &val);
  303. if (ret < 0) {
  304. netdev_warn(dev->net, "Error reading E2P_DATA\n");
  305. return ret;
  306. }
  307. data[i] = val & 0xFF;
  308. offset++;
  309. }
  310. return 0;
  311. }
  312. static int smsc95xx_write_eeprom(struct usbnet *dev, u32 offset, u32 length,
  313. u8 *data)
  314. {
  315. u32 val;
  316. int i, ret;
  317. BUG_ON(!dev);
  318. BUG_ON(!data);
  319. ret = smsc95xx_eeprom_confirm_not_busy(dev);
  320. if (ret)
  321. return ret;
  322. /* Issue write/erase enable command */
  323. val = E2P_CMD_BUSY_ | E2P_CMD_EWEN_;
  324. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  325. if (ret < 0) {
  326. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  327. return ret;
  328. }
  329. ret = smsc95xx_wait_eeprom(dev);
  330. if (ret < 0)
  331. return ret;
  332. for (i = 0; i < length; i++) {
  333. /* Fill data register */
  334. val = data[i];
  335. ret = smsc95xx_write_reg(dev, E2P_DATA, val);
  336. if (ret < 0) {
  337. netdev_warn(dev->net, "Error writing E2P_DATA\n");
  338. return ret;
  339. }
  340. /* Send "write" command */
  341. val = E2P_CMD_BUSY_ | E2P_CMD_WRITE_ | (offset & E2P_CMD_ADDR_);
  342. ret = smsc95xx_write_reg(dev, E2P_CMD, val);
  343. if (ret < 0) {
  344. netdev_warn(dev->net, "Error writing E2P_CMD\n");
  345. return ret;
  346. }
  347. ret = smsc95xx_wait_eeprom(dev);
  348. if (ret < 0)
  349. return ret;
  350. offset++;
  351. }
  352. return 0;
  353. }
  354. static int __must_check smsc95xx_write_reg_async(struct usbnet *dev, u16 index,
  355. u32 data)
  356. {
  357. const u16 size = 4;
  358. u32 buf;
  359. int ret;
  360. buf = data;
  361. cpu_to_le32s(&buf);
  362. ret = usbnet_write_cmd_async(dev, USB_VENDOR_REQUEST_WRITE_REGISTER,
  363. USB_DIR_OUT | USB_TYPE_VENDOR |
  364. USB_RECIP_DEVICE,
  365. 0, index, &buf, size);
  366. if (ret < 0)
  367. netdev_warn(dev->net, "Error write async cmd, sts=%d\n",
  368. ret);
  369. return ret;
  370. }
  371. /* returns hash bit number for given MAC address
  372. * example:
  373. * 01 00 5E 00 00 01 -> returns bit number 31 */
  374. static unsigned int smsc95xx_hash(char addr[ETH_ALEN])
  375. {
  376. return (ether_crc(ETH_ALEN, addr) >> 26) & 0x3f;
  377. }
  378. static void smsc95xx_set_multicast(struct net_device *netdev)
  379. {
  380. struct usbnet *dev = netdev_priv(netdev);
  381. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  382. unsigned long flags;
  383. int ret;
  384. pdata->hash_hi = 0;
  385. pdata->hash_lo = 0;
  386. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  387. if (dev->net->flags & IFF_PROMISC) {
  388. netif_dbg(dev, drv, dev->net, "promiscuous mode enabled\n");
  389. pdata->mac_cr |= MAC_CR_PRMS_;
  390. pdata->mac_cr &= ~(MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  391. } else if (dev->net->flags & IFF_ALLMULTI) {
  392. netif_dbg(dev, drv, dev->net, "receive all multicast enabled\n");
  393. pdata->mac_cr |= MAC_CR_MCPAS_;
  394. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_HPFILT_);
  395. } else if (!netdev_mc_empty(dev->net)) {
  396. struct netdev_hw_addr *ha;
  397. pdata->mac_cr |= MAC_CR_HPFILT_;
  398. pdata->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_);
  399. netdev_for_each_mc_addr(ha, netdev) {
  400. u32 bitnum = smsc95xx_hash(ha->addr);
  401. u32 mask = 0x01 << (bitnum & 0x1F);
  402. if (bitnum & 0x20)
  403. pdata->hash_hi |= mask;
  404. else
  405. pdata->hash_lo |= mask;
  406. }
  407. netif_dbg(dev, drv, dev->net, "HASHH=0x%08X, HASHL=0x%08X\n",
  408. pdata->hash_hi, pdata->hash_lo);
  409. } else {
  410. netif_dbg(dev, drv, dev->net, "receive own packets only\n");
  411. pdata->mac_cr &=
  412. ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
  413. }
  414. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  415. /* Initiate async writes, as we can't wait for completion here */
  416. ret = smsc95xx_write_reg_async(dev, HASHH, pdata->hash_hi);
  417. if (ret < 0)
  418. netdev_warn(dev->net, "failed to initiate async write to HASHH\n");
  419. ret = smsc95xx_write_reg_async(dev, HASHL, pdata->hash_lo);
  420. if (ret < 0)
  421. netdev_warn(dev->net, "failed to initiate async write to HASHL\n");
  422. ret = smsc95xx_write_reg_async(dev, MAC_CR, pdata->mac_cr);
  423. if (ret < 0)
  424. netdev_warn(dev->net, "failed to initiate async write to MAC_CR\n");
  425. }
  426. static int smsc95xx_phy_update_flowcontrol(struct usbnet *dev, u8 duplex,
  427. u16 lcladv, u16 rmtadv)
  428. {
  429. u32 flow, afc_cfg = 0;
  430. int ret = smsc95xx_read_reg(dev, AFC_CFG, &afc_cfg);
  431. if (ret < 0)
  432. return ret;
  433. if (duplex == DUPLEX_FULL) {
  434. u8 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
  435. if (cap & FLOW_CTRL_RX)
  436. flow = 0xFFFF0002;
  437. else
  438. flow = 0;
  439. if (cap & FLOW_CTRL_TX)
  440. afc_cfg |= 0xF;
  441. else
  442. afc_cfg &= ~0xF;
  443. netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s\n",
  444. cap & FLOW_CTRL_RX ? "enabled" : "disabled",
  445. cap & FLOW_CTRL_TX ? "enabled" : "disabled");
  446. } else {
  447. netif_dbg(dev, link, dev->net, "half duplex\n");
  448. flow = 0;
  449. afc_cfg |= 0xF;
  450. }
  451. ret = smsc95xx_write_reg(dev, FLOW, flow);
  452. if (ret < 0)
  453. return ret;
  454. return smsc95xx_write_reg(dev, AFC_CFG, afc_cfg);
  455. }
  456. static int smsc95xx_link_reset(struct usbnet *dev)
  457. {
  458. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  459. struct mii_if_info *mii = &dev->mii;
  460. struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
  461. unsigned long flags;
  462. u16 lcladv, rmtadv;
  463. int ret;
  464. /* clear interrupt status */
  465. ret = smsc95xx_mdio_read(dev->net, mii->phy_id, PHY_INT_SRC);
  466. if (ret < 0)
  467. return ret;
  468. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  469. if (ret < 0)
  470. return ret;
  471. mii_check_media(mii, 1, 1);
  472. mii_ethtool_gset(&dev->mii, &ecmd);
  473. lcladv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_ADVERTISE);
  474. rmtadv = smsc95xx_mdio_read(dev->net, mii->phy_id, MII_LPA);
  475. netif_dbg(dev, link, dev->net,
  476. "speed: %u duplex: %d lcladv: %04x rmtadv: %04x\n",
  477. ethtool_cmd_speed(&ecmd), ecmd.duplex, lcladv, rmtadv);
  478. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  479. if (ecmd.duplex != DUPLEX_FULL) {
  480. pdata->mac_cr &= ~MAC_CR_FDPX_;
  481. pdata->mac_cr |= MAC_CR_RCVOWN_;
  482. } else {
  483. pdata->mac_cr &= ~MAC_CR_RCVOWN_;
  484. pdata->mac_cr |= MAC_CR_FDPX_;
  485. }
  486. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  487. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  488. if (ret < 0)
  489. return ret;
  490. ret = smsc95xx_phy_update_flowcontrol(dev, ecmd.duplex, lcladv, rmtadv);
  491. if (ret < 0)
  492. netdev_warn(dev->net, "Error updating PHY flow control\n");
  493. return ret;
  494. }
  495. static void smsc95xx_status(struct usbnet *dev, struct urb *urb)
  496. {
  497. u32 intdata;
  498. if (urb->actual_length != 4) {
  499. netdev_warn(dev->net, "unexpected urb length %d\n",
  500. urb->actual_length);
  501. return;
  502. }
  503. memcpy(&intdata, urb->transfer_buffer, 4);
  504. le32_to_cpus(&intdata);
  505. netif_dbg(dev, link, dev->net, "intdata: 0x%08X\n", intdata);
  506. if (intdata & INT_ENP_PHY_INT_)
  507. usbnet_defer_kevent(dev, EVENT_LINK_RESET);
  508. else
  509. netdev_warn(dev->net, "unexpected interrupt, intdata=0x%08X\n",
  510. intdata);
  511. }
  512. /* Enable or disable Tx & Rx checksum offload engines */
  513. static int smsc95xx_set_features(struct net_device *netdev,
  514. netdev_features_t features)
  515. {
  516. struct usbnet *dev = netdev_priv(netdev);
  517. u32 read_buf;
  518. int ret;
  519. ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
  520. if (ret < 0)
  521. return ret;
  522. if (features & NETIF_F_HW_CSUM)
  523. read_buf |= Tx_COE_EN_;
  524. else
  525. read_buf &= ~Tx_COE_EN_;
  526. if (features & NETIF_F_RXCSUM)
  527. read_buf |= Rx_COE_EN_;
  528. else
  529. read_buf &= ~Rx_COE_EN_;
  530. ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
  531. if (ret < 0)
  532. return ret;
  533. netif_dbg(dev, hw, dev->net, "COE_CR = 0x%08x\n", read_buf);
  534. return 0;
  535. }
  536. static int smsc95xx_ethtool_get_eeprom_len(struct net_device *net)
  537. {
  538. return MAX_EEPROM_SIZE;
  539. }
  540. static int smsc95xx_ethtool_get_eeprom(struct net_device *netdev,
  541. struct ethtool_eeprom *ee, u8 *data)
  542. {
  543. struct usbnet *dev = netdev_priv(netdev);
  544. ee->magic = LAN95XX_EEPROM_MAGIC;
  545. return smsc95xx_read_eeprom(dev, ee->offset, ee->len, data);
  546. }
  547. static int smsc95xx_ethtool_set_eeprom(struct net_device *netdev,
  548. struct ethtool_eeprom *ee, u8 *data)
  549. {
  550. struct usbnet *dev = netdev_priv(netdev);
  551. if (ee->magic != LAN95XX_EEPROM_MAGIC) {
  552. netdev_warn(dev->net, "EEPROM: magic value mismatch, magic = 0x%x\n",
  553. ee->magic);
  554. return -EINVAL;
  555. }
  556. return smsc95xx_write_eeprom(dev, ee->offset, ee->len, data);
  557. }
  558. static int smsc95xx_ethtool_getregslen(struct net_device *netdev)
  559. {
  560. /* all smsc95xx registers */
  561. return COE_CR - ID_REV + sizeof(u32);
  562. }
  563. static void
  564. smsc95xx_ethtool_getregs(struct net_device *netdev, struct ethtool_regs *regs,
  565. void *buf)
  566. {
  567. struct usbnet *dev = netdev_priv(netdev);
  568. unsigned int i, j;
  569. int retval;
  570. u32 *data = buf;
  571. retval = smsc95xx_read_reg(dev, ID_REV, &regs->version);
  572. if (retval < 0) {
  573. netdev_warn(netdev, "REGS: cannot read ID_REV\n");
  574. return;
  575. }
  576. for (i = ID_REV, j = 0; i <= COE_CR; i += (sizeof(u32)), j++) {
  577. retval = smsc95xx_read_reg(dev, i, &data[j]);
  578. if (retval < 0) {
  579. netdev_warn(netdev, "REGS: cannot read reg[%x]\n", i);
  580. return;
  581. }
  582. }
  583. }
  584. static void smsc95xx_ethtool_get_wol(struct net_device *net,
  585. struct ethtool_wolinfo *wolinfo)
  586. {
  587. struct usbnet *dev = netdev_priv(net);
  588. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  589. wolinfo->supported = SUPPORTED_WAKE;
  590. wolinfo->wolopts = pdata->wolopts;
  591. }
  592. static int smsc95xx_ethtool_set_wol(struct net_device *net,
  593. struct ethtool_wolinfo *wolinfo)
  594. {
  595. struct usbnet *dev = netdev_priv(net);
  596. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  597. int ret;
  598. if (wolinfo->wolopts & ~SUPPORTED_WAKE)
  599. return -EINVAL;
  600. pdata->wolopts = wolinfo->wolopts & SUPPORTED_WAKE;
  601. ret = device_set_wakeup_enable(&dev->udev->dev, pdata->wolopts);
  602. if (ret < 0)
  603. netdev_warn(dev->net, "device_set_wakeup_enable error %d\n", ret);
  604. return ret;
  605. }
  606. static const struct ethtool_ops smsc95xx_ethtool_ops = {
  607. .get_link = usbnet_get_link,
  608. .nway_reset = usbnet_nway_reset,
  609. .get_drvinfo = usbnet_get_drvinfo,
  610. .get_msglevel = usbnet_get_msglevel,
  611. .set_msglevel = usbnet_set_msglevel,
  612. .get_settings = usbnet_get_settings,
  613. .set_settings = usbnet_set_settings,
  614. .get_eeprom_len = smsc95xx_ethtool_get_eeprom_len,
  615. .get_eeprom = smsc95xx_ethtool_get_eeprom,
  616. .set_eeprom = smsc95xx_ethtool_set_eeprom,
  617. .get_regs_len = smsc95xx_ethtool_getregslen,
  618. .get_regs = smsc95xx_ethtool_getregs,
  619. .get_wol = smsc95xx_ethtool_get_wol,
  620. .set_wol = smsc95xx_ethtool_set_wol,
  621. };
  622. static int smsc95xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
  623. {
  624. struct usbnet *dev = netdev_priv(netdev);
  625. if (!netif_running(netdev))
  626. return -EINVAL;
  627. return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
  628. }
  629. static void smsc95xx_init_mac_address(struct usbnet *dev)
  630. {
  631. /* try reading mac address from EEPROM */
  632. if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
  633. dev->net->dev_addr) == 0) {
  634. if (is_valid_ether_addr(dev->net->dev_addr)) {
  635. /* eeprom values are valid so use them */
  636. netif_dbg(dev, ifup, dev->net, "MAC address read from EEPROM\n");
  637. return;
  638. }
  639. }
  640. /* no eeprom, or eeprom values are invalid. generate random MAC */
  641. eth_hw_addr_random(dev->net);
  642. netif_dbg(dev, ifup, dev->net, "MAC address set to eth_random_addr\n");
  643. }
  644. static int smsc95xx_set_mac_address(struct usbnet *dev)
  645. {
  646. u32 addr_lo = dev->net->dev_addr[0] | dev->net->dev_addr[1] << 8 |
  647. dev->net->dev_addr[2] << 16 | dev->net->dev_addr[3] << 24;
  648. u32 addr_hi = dev->net->dev_addr[4] | dev->net->dev_addr[5] << 8;
  649. int ret;
  650. ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
  651. if (ret < 0)
  652. return ret;
  653. return smsc95xx_write_reg(dev, ADDRH, addr_hi);
  654. }
  655. /* starts the TX path */
  656. static int smsc95xx_start_tx_path(struct usbnet *dev)
  657. {
  658. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  659. unsigned long flags;
  660. int ret;
  661. /* Enable Tx at MAC */
  662. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  663. pdata->mac_cr |= MAC_CR_TXEN_;
  664. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  665. ret = smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr);
  666. if (ret < 0)
  667. return ret;
  668. /* Enable Tx at SCSRs */
  669. return smsc95xx_write_reg(dev, TX_CFG, TX_CFG_ON_);
  670. }
  671. /* Starts the Receive path */
  672. static int smsc95xx_start_rx_path(struct usbnet *dev, int in_pm)
  673. {
  674. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  675. unsigned long flags;
  676. spin_lock_irqsave(&pdata->mac_cr_lock, flags);
  677. pdata->mac_cr |= MAC_CR_RXEN_;
  678. spin_unlock_irqrestore(&pdata->mac_cr_lock, flags);
  679. return __smsc95xx_write_reg(dev, MAC_CR, pdata->mac_cr, in_pm);
  680. }
  681. static int smsc95xx_phy_initialize(struct usbnet *dev)
  682. {
  683. int bmcr, ret, timeout = 0;
  684. /* Initialize MII structure */
  685. dev->mii.dev = dev->net;
  686. dev->mii.mdio_read = smsc95xx_mdio_read;
  687. dev->mii.mdio_write = smsc95xx_mdio_write;
  688. dev->mii.phy_id_mask = 0x1f;
  689. dev->mii.reg_num_mask = 0x1f;
  690. dev->mii.phy_id = SMSC95XX_INTERNAL_PHY_ID;
  691. /* reset phy and wait for reset to complete */
  692. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET);
  693. do {
  694. msleep(10);
  695. bmcr = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR);
  696. timeout++;
  697. } while ((bmcr & BMCR_RESET) && (timeout < 100));
  698. if (timeout >= 100) {
  699. netdev_warn(dev->net, "timeout on PHY Reset");
  700. return -EIO;
  701. }
  702. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
  703. ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
  704. ADVERTISE_PAUSE_ASYM);
  705. /* read to clear */
  706. ret = smsc95xx_mdio_read(dev->net, dev->mii.phy_id, PHY_INT_SRC);
  707. if (ret < 0) {
  708. netdev_warn(dev->net, "Failed to read PHY_INT_SRC during init\n");
  709. return ret;
  710. }
  711. smsc95xx_mdio_write(dev->net, dev->mii.phy_id, PHY_INT_MASK,
  712. PHY_INT_MASK_DEFAULT_);
  713. mii_nway_restart(&dev->mii);
  714. netif_dbg(dev, ifup, dev->net, "phy initialised successfully\n");
  715. return 0;
  716. }
  717. static int smsc95xx_reset(struct usbnet *dev)
  718. {
  719. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  720. u32 read_buf, write_buf, burst_cap;
  721. int ret = 0, timeout;
  722. netif_dbg(dev, ifup, dev->net, "entering smsc95xx_reset\n");
  723. ret = smsc95xx_write_reg(dev, HW_CFG, HW_CFG_LRST_);
  724. if (ret < 0)
  725. return ret;
  726. timeout = 0;
  727. do {
  728. msleep(10);
  729. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  730. if (ret < 0)
  731. return ret;
  732. timeout++;
  733. } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
  734. if (timeout >= 100) {
  735. netdev_warn(dev->net, "timeout waiting for completion of Lite Reset\n");
  736. return ret;
  737. }
  738. ret = smsc95xx_write_reg(dev, PM_CTRL, PM_CTL_PHY_RST_);
  739. if (ret < 0)
  740. return ret;
  741. timeout = 0;
  742. do {
  743. msleep(10);
  744. ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
  745. if (ret < 0)
  746. return ret;
  747. timeout++;
  748. } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
  749. if (timeout >= 100) {
  750. netdev_warn(dev->net, "timeout waiting for PHY Reset\n");
  751. return ret;
  752. }
  753. ret = smsc95xx_set_mac_address(dev);
  754. if (ret < 0)
  755. return ret;
  756. netif_dbg(dev, ifup, dev->net, "MAC Address: %pM\n",
  757. dev->net->dev_addr);
  758. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  759. if (ret < 0)
  760. return ret;
  761. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG : 0x%08x\n",
  762. read_buf);
  763. read_buf |= HW_CFG_BIR_;
  764. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  765. if (ret < 0)
  766. return ret;
  767. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  768. if (ret < 0)
  769. return ret;
  770. netif_dbg(dev, ifup, dev->net,
  771. "Read Value from HW_CFG after writing HW_CFG_BIR_: 0x%08x\n",
  772. read_buf);
  773. if (!turbo_mode) {
  774. burst_cap = 0;
  775. dev->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
  776. } else if (dev->udev->speed == USB_SPEED_HIGH) {
  777. burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
  778. dev->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
  779. } else {
  780. burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
  781. dev->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
  782. }
  783. netif_dbg(dev, ifup, dev->net, "rx_urb_size=%ld\n",
  784. (ulong)dev->rx_urb_size);
  785. ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
  786. if (ret < 0)
  787. return ret;
  788. ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
  789. if (ret < 0)
  790. return ret;
  791. netif_dbg(dev, ifup, dev->net,
  792. "Read Value from BURST_CAP after writing: 0x%08x\n",
  793. read_buf);
  794. ret = smsc95xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
  795. if (ret < 0)
  796. return ret;
  797. ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
  798. if (ret < 0)
  799. return ret;
  800. netif_dbg(dev, ifup, dev->net,
  801. "Read Value from BULK_IN_DLY after writing: 0x%08x\n",
  802. read_buf);
  803. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  804. if (ret < 0)
  805. return ret;
  806. netif_dbg(dev, ifup, dev->net, "Read Value from HW_CFG: 0x%08x\n",
  807. read_buf);
  808. if (turbo_mode)
  809. read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
  810. read_buf &= ~HW_CFG_RXDOFF_;
  811. /* set Rx data offset=2, Make IP header aligns on word boundary. */
  812. read_buf |= NET_IP_ALIGN << 9;
  813. ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
  814. if (ret < 0)
  815. return ret;
  816. ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
  817. if (ret < 0)
  818. return ret;
  819. netif_dbg(dev, ifup, dev->net,
  820. "Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
  821. ret = smsc95xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
  822. if (ret < 0)
  823. return ret;
  824. ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
  825. if (ret < 0)
  826. return ret;
  827. netif_dbg(dev, ifup, dev->net, "ID_REV = 0x%08x\n", read_buf);
  828. /* Configure GPIO pins as LED outputs */
  829. write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
  830. LED_GPIO_CFG_FDX_LED;
  831. ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
  832. if (ret < 0)
  833. return ret;
  834. /* Init Tx */
  835. ret = smsc95xx_write_reg(dev, FLOW, 0);
  836. if (ret < 0)
  837. return ret;
  838. ret = smsc95xx_write_reg(dev, AFC_CFG, AFC_CFG_DEFAULT);
  839. if (ret < 0)
  840. return ret;
  841. /* Don't need mac_cr_lock during initialisation */
  842. ret = smsc95xx_read_reg(dev, MAC_CR, &pdata->mac_cr);
  843. if (ret < 0)
  844. return ret;
  845. /* Init Rx */
  846. /* Set Vlan */
  847. ret = smsc95xx_write_reg(dev, VLAN1, (u32)ETH_P_8021Q);
  848. if (ret < 0)
  849. return ret;
  850. /* Enable or disable checksum offload engines */
  851. ret = smsc95xx_set_features(dev->net, dev->net->features);
  852. if (ret < 0) {
  853. netdev_warn(dev->net, "Failed to set checksum offload features\n");
  854. return ret;
  855. }
  856. smsc95xx_set_multicast(dev->net);
  857. ret = smsc95xx_phy_initialize(dev);
  858. if (ret < 0) {
  859. netdev_warn(dev->net, "Failed to init PHY\n");
  860. return ret;
  861. }
  862. ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
  863. if (ret < 0)
  864. return ret;
  865. /* enable PHY interrupts */
  866. read_buf |= INT_EP_CTL_PHY_INT_;
  867. ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
  868. if (ret < 0)
  869. return ret;
  870. ret = smsc95xx_start_tx_path(dev);
  871. if (ret < 0) {
  872. netdev_warn(dev->net, "Failed to start TX path\n");
  873. return ret;
  874. }
  875. ret = smsc95xx_start_rx_path(dev, 0);
  876. if (ret < 0) {
  877. netdev_warn(dev->net, "Failed to start RX path\n");
  878. return ret;
  879. }
  880. netif_dbg(dev, ifup, dev->net, "smsc95xx_reset, return 0\n");
  881. return 0;
  882. }
  883. static const struct net_device_ops smsc95xx_netdev_ops = {
  884. .ndo_open = usbnet_open,
  885. .ndo_stop = usbnet_stop,
  886. .ndo_start_xmit = usbnet_start_xmit,
  887. .ndo_tx_timeout = usbnet_tx_timeout,
  888. .ndo_change_mtu = usbnet_change_mtu,
  889. .ndo_set_mac_address = eth_mac_addr,
  890. .ndo_validate_addr = eth_validate_addr,
  891. .ndo_do_ioctl = smsc95xx_ioctl,
  892. .ndo_set_rx_mode = smsc95xx_set_multicast,
  893. .ndo_set_features = smsc95xx_set_features,
  894. };
  895. static int smsc95xx_bind(struct usbnet *dev, struct usb_interface *intf)
  896. {
  897. struct smsc95xx_priv *pdata = NULL;
  898. u32 val;
  899. int ret;
  900. printk(KERN_INFO SMSC_CHIPNAME " v" SMSC_DRIVER_VERSION "\n");
  901. ret = usbnet_get_endpoints(dev, intf);
  902. if (ret < 0) {
  903. netdev_warn(dev->net, "usbnet_get_endpoints failed: %d\n", ret);
  904. return ret;
  905. }
  906. dev->data[0] = (unsigned long)kzalloc(sizeof(struct smsc95xx_priv),
  907. GFP_KERNEL);
  908. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  909. if (!pdata)
  910. return -ENOMEM;
  911. spin_lock_init(&pdata->mac_cr_lock);
  912. if (DEFAULT_TX_CSUM_ENABLE)
  913. dev->net->features |= NETIF_F_HW_CSUM;
  914. if (DEFAULT_RX_CSUM_ENABLE)
  915. dev->net->features |= NETIF_F_RXCSUM;
  916. dev->net->hw_features = NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
  917. smsc95xx_init_mac_address(dev);
  918. /* Init all registers */
  919. ret = smsc95xx_reset(dev);
  920. /* detect device revision as different features may be available */
  921. ret = smsc95xx_read_reg(dev, ID_REV, &val);
  922. if (ret < 0)
  923. return ret;
  924. val >>= 16;
  925. if ((val == ID_REV_CHIP_ID_9500A_) || (val == ID_REV_CHIP_ID_9530_) ||
  926. (val == ID_REV_CHIP_ID_89530_) || (val == ID_REV_CHIP_ID_9730_))
  927. pdata->features = (FEATURE_8_WAKEUP_FILTERS |
  928. FEATURE_PHY_NLP_CROSSOVER |
  929. FEATURE_REMOTE_WAKEUP);
  930. else if (val == ID_REV_CHIP_ID_9512_)
  931. pdata->features = FEATURE_8_WAKEUP_FILTERS;
  932. dev->net->netdev_ops = &smsc95xx_netdev_ops;
  933. dev->net->ethtool_ops = &smsc95xx_ethtool_ops;
  934. dev->net->flags |= IFF_MULTICAST;
  935. dev->net->hard_header_len += SMSC95XX_TX_OVERHEAD_CSUM;
  936. dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
  937. return 0;
  938. }
  939. static void smsc95xx_unbind(struct usbnet *dev, struct usb_interface *intf)
  940. {
  941. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  942. if (pdata) {
  943. netif_dbg(dev, ifdown, dev->net, "free pdata\n");
  944. kfree(pdata);
  945. pdata = NULL;
  946. dev->data[0] = 0;
  947. }
  948. }
  949. static u32 smsc_crc(const u8 *buffer, size_t len, int filter)
  950. {
  951. u32 crc = bitrev16(crc16(0xFFFF, buffer, len));
  952. return crc << ((filter % 2) * 16);
  953. }
  954. static int smsc95xx_enable_phy_wakeup_interrupts(struct usbnet *dev, u16 mask)
  955. {
  956. struct mii_if_info *mii = &dev->mii;
  957. int ret;
  958. netdev_dbg(dev->net, "enabling PHY wakeup interrupts\n");
  959. /* read to clear */
  960. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_SRC);
  961. if (ret < 0)
  962. return ret;
  963. /* enable interrupt source */
  964. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_INT_MASK);
  965. if (ret < 0)
  966. return ret;
  967. ret |= mask;
  968. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_INT_MASK, ret);
  969. return 0;
  970. }
  971. static int smsc95xx_link_ok_nopm(struct usbnet *dev)
  972. {
  973. struct mii_if_info *mii = &dev->mii;
  974. int ret;
  975. /* first, a dummy read, needed to latch some MII phys */
  976. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  977. if (ret < 0)
  978. return ret;
  979. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, MII_BMSR);
  980. if (ret < 0)
  981. return ret;
  982. return !!(ret & BMSR_LSTATUS);
  983. }
  984. static int smsc95xx_enter_suspend0(struct usbnet *dev)
  985. {
  986. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  987. u32 val;
  988. int ret;
  989. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  990. if (ret < 0)
  991. return ret;
  992. val &= (~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_));
  993. val |= PM_CTL_SUS_MODE_0;
  994. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  995. if (ret < 0)
  996. return ret;
  997. /* clear wol status */
  998. val &= ~PM_CTL_WUPS_;
  999. val |= PM_CTL_WUPS_WOL_;
  1000. /* enable energy detection */
  1001. if (pdata->wolopts & WAKE_PHY)
  1002. val |= PM_CTL_WUPS_ED_;
  1003. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1004. if (ret < 0)
  1005. return ret;
  1006. /* read back PM_CTRL */
  1007. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1008. if (ret < 0)
  1009. return ret;
  1010. pdata->suspend_flags |= SUSPEND_SUSPEND0;
  1011. return 0;
  1012. }
  1013. static int smsc95xx_enter_suspend1(struct usbnet *dev)
  1014. {
  1015. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1016. struct mii_if_info *mii = &dev->mii;
  1017. u32 val;
  1018. int ret;
  1019. /* reconfigure link pulse detection timing for
  1020. * compatibility with non-standard link partners
  1021. */
  1022. if (pdata->features & FEATURE_PHY_NLP_CROSSOVER)
  1023. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_EDPD_CONFIG,
  1024. PHY_EDPD_CONFIG_DEFAULT);
  1025. /* enable energy detect power-down mode */
  1026. ret = smsc95xx_mdio_read_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS);
  1027. if (ret < 0)
  1028. return ret;
  1029. ret |= MODE_CTRL_STS_EDPWRDOWN_;
  1030. smsc95xx_mdio_write_nopm(dev->net, mii->phy_id, PHY_MODE_CTRL_STS, ret);
  1031. /* enter SUSPEND1 mode */
  1032. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1033. if (ret < 0)
  1034. return ret;
  1035. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1036. val |= PM_CTL_SUS_MODE_1;
  1037. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1038. if (ret < 0)
  1039. return ret;
  1040. /* clear wol status, enable energy detection */
  1041. val &= ~PM_CTL_WUPS_;
  1042. val |= (PM_CTL_WUPS_ED_ | PM_CTL_ED_EN_);
  1043. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1044. if (ret < 0)
  1045. return ret;
  1046. pdata->suspend_flags |= SUSPEND_SUSPEND1;
  1047. return 0;
  1048. }
  1049. static int smsc95xx_enter_suspend2(struct usbnet *dev)
  1050. {
  1051. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1052. u32 val;
  1053. int ret;
  1054. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1055. if (ret < 0)
  1056. return ret;
  1057. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1058. val |= PM_CTL_SUS_MODE_2;
  1059. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1060. if (ret < 0)
  1061. return ret;
  1062. pdata->suspend_flags |= SUSPEND_SUSPEND2;
  1063. return 0;
  1064. }
  1065. static int smsc95xx_enter_suspend3(struct usbnet *dev)
  1066. {
  1067. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1068. u32 val;
  1069. int ret;
  1070. ret = smsc95xx_read_reg_nopm(dev, RX_FIFO_INF, &val);
  1071. if (ret < 0)
  1072. return ret;
  1073. if (val & 0xFFFF) {
  1074. netdev_info(dev->net, "rx fifo not empty in autosuspend\n");
  1075. return -EBUSY;
  1076. }
  1077. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1078. if (ret < 0)
  1079. return ret;
  1080. val &= ~(PM_CTL_SUS_MODE_ | PM_CTL_WUPS_ | PM_CTL_PHY_RST_);
  1081. val |= PM_CTL_SUS_MODE_3 | PM_CTL_RES_CLR_WKP_STS;
  1082. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1083. if (ret < 0)
  1084. return ret;
  1085. /* clear wol status */
  1086. val &= ~PM_CTL_WUPS_;
  1087. val |= PM_CTL_WUPS_WOL_;
  1088. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1089. if (ret < 0)
  1090. return ret;
  1091. pdata->suspend_flags |= SUSPEND_SUSPEND3;
  1092. return 0;
  1093. }
  1094. static int smsc95xx_autosuspend(struct usbnet *dev, u32 link_up)
  1095. {
  1096. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1097. int ret;
  1098. if (!netif_running(dev->net)) {
  1099. /* interface is ifconfig down so fully power down hw */
  1100. netdev_dbg(dev->net, "autosuspend entering SUSPEND2\n");
  1101. return smsc95xx_enter_suspend2(dev);
  1102. }
  1103. if (!link_up) {
  1104. /* link is down so enter EDPD mode, but only if device can
  1105. * reliably resume from it. This check should be redundant
  1106. * as current FEATURE_REMOTE_WAKEUP parts also support
  1107. * FEATURE_PHY_NLP_CROSSOVER but it's included for clarity */
  1108. if (!(pdata->features & FEATURE_PHY_NLP_CROSSOVER)) {
  1109. netdev_warn(dev->net, "EDPD not supported\n");
  1110. return -EBUSY;
  1111. }
  1112. netdev_dbg(dev->net, "autosuspend entering SUSPEND1\n");
  1113. /* enable PHY wakeup events for if cable is attached */
  1114. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1115. PHY_INT_MASK_ANEG_COMP_);
  1116. if (ret < 0) {
  1117. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1118. return ret;
  1119. }
  1120. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1121. return smsc95xx_enter_suspend1(dev);
  1122. }
  1123. /* enable PHY wakeup events so we remote wakeup if cable is pulled */
  1124. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1125. PHY_INT_MASK_LINK_DOWN_);
  1126. if (ret < 0) {
  1127. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1128. return ret;
  1129. }
  1130. netdev_dbg(dev->net, "autosuspend entering SUSPEND3\n");
  1131. return smsc95xx_enter_suspend3(dev);
  1132. }
  1133. static int smsc95xx_suspend(struct usb_interface *intf, pm_message_t message)
  1134. {
  1135. struct usbnet *dev = usb_get_intfdata(intf);
  1136. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1137. u32 val, link_up;
  1138. int ret;
  1139. ret = usbnet_suspend(intf, message);
  1140. if (ret < 0) {
  1141. netdev_warn(dev->net, "usbnet_suspend error\n");
  1142. return ret;
  1143. }
  1144. if (pdata->suspend_flags) {
  1145. netdev_warn(dev->net, "error during last resume\n");
  1146. pdata->suspend_flags = 0;
  1147. }
  1148. /* determine if link is up using only _nopm functions */
  1149. link_up = smsc95xx_link_ok_nopm(dev);
  1150. if (message.event == PM_EVENT_AUTO_SUSPEND &&
  1151. (pdata->features & FEATURE_REMOTE_WAKEUP)) {
  1152. ret = smsc95xx_autosuspend(dev, link_up);
  1153. goto done;
  1154. }
  1155. /* if we get this far we're not autosuspending */
  1156. /* if no wol options set, or if link is down and we're not waking on
  1157. * PHY activity, enter lowest power SUSPEND2 mode
  1158. */
  1159. if (!(pdata->wolopts & SUPPORTED_WAKE) ||
  1160. !(link_up || (pdata->wolopts & WAKE_PHY))) {
  1161. netdev_info(dev->net, "entering SUSPEND2 mode\n");
  1162. /* disable energy detect (link up) & wake up events */
  1163. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1164. if (ret < 0)
  1165. goto done;
  1166. val &= ~(WUCSR_MPEN_ | WUCSR_WAKE_EN_);
  1167. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1168. if (ret < 0)
  1169. goto done;
  1170. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1171. if (ret < 0)
  1172. goto done;
  1173. val &= ~(PM_CTL_ED_EN_ | PM_CTL_WOL_EN_);
  1174. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1175. if (ret < 0)
  1176. goto done;
  1177. ret = smsc95xx_enter_suspend2(dev);
  1178. goto done;
  1179. }
  1180. if (pdata->wolopts & WAKE_PHY) {
  1181. ret = smsc95xx_enable_phy_wakeup_interrupts(dev,
  1182. (PHY_INT_MASK_ANEG_COMP_ | PHY_INT_MASK_LINK_DOWN_));
  1183. if (ret < 0) {
  1184. netdev_warn(dev->net, "error enabling PHY wakeup ints\n");
  1185. goto done;
  1186. }
  1187. /* if link is down then configure EDPD and enter SUSPEND1,
  1188. * otherwise enter SUSPEND0 below
  1189. */
  1190. if (!link_up) {
  1191. netdev_info(dev->net, "entering SUSPEND1 mode\n");
  1192. ret = smsc95xx_enter_suspend1(dev);
  1193. goto done;
  1194. }
  1195. }
  1196. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1197. u32 *filter_mask = kzalloc(sizeof(u32) * 32, GFP_KERNEL);
  1198. u32 command[2];
  1199. u32 offset[2];
  1200. u32 crc[4];
  1201. int wuff_filter_count =
  1202. (pdata->features & FEATURE_8_WAKEUP_FILTERS) ?
  1203. LAN9500A_WUFF_NUM : LAN9500_WUFF_NUM;
  1204. int i, filter = 0;
  1205. if (!filter_mask) {
  1206. netdev_warn(dev->net, "Unable to allocate filter_mask\n");
  1207. ret = -ENOMEM;
  1208. goto done;
  1209. }
  1210. memset(command, 0, sizeof(command));
  1211. memset(offset, 0, sizeof(offset));
  1212. memset(crc, 0, sizeof(crc));
  1213. if (pdata->wolopts & WAKE_BCAST) {
  1214. const u8 bcast[] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
  1215. netdev_info(dev->net, "enabling broadcast detection\n");
  1216. filter_mask[filter * 4] = 0x003F;
  1217. filter_mask[filter * 4 + 1] = 0x00;
  1218. filter_mask[filter * 4 + 2] = 0x00;
  1219. filter_mask[filter * 4 + 3] = 0x00;
  1220. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1221. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1222. crc[filter/2] |= smsc_crc(bcast, 6, filter);
  1223. filter++;
  1224. }
  1225. if (pdata->wolopts & WAKE_MCAST) {
  1226. const u8 mcast[] = {0x01, 0x00, 0x5E};
  1227. netdev_info(dev->net, "enabling multicast detection\n");
  1228. filter_mask[filter * 4] = 0x0007;
  1229. filter_mask[filter * 4 + 1] = 0x00;
  1230. filter_mask[filter * 4 + 2] = 0x00;
  1231. filter_mask[filter * 4 + 3] = 0x00;
  1232. command[filter/4] |= 0x09UL << ((filter % 4) * 8);
  1233. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1234. crc[filter/2] |= smsc_crc(mcast, 3, filter);
  1235. filter++;
  1236. }
  1237. if (pdata->wolopts & WAKE_ARP) {
  1238. const u8 arp[] = {0x08, 0x06};
  1239. netdev_info(dev->net, "enabling ARP detection\n");
  1240. filter_mask[filter * 4] = 0x0003;
  1241. filter_mask[filter * 4 + 1] = 0x00;
  1242. filter_mask[filter * 4 + 2] = 0x00;
  1243. filter_mask[filter * 4 + 3] = 0x00;
  1244. command[filter/4] |= 0x05UL << ((filter % 4) * 8);
  1245. offset[filter/4] |= 0x0C << ((filter % 4) * 8);
  1246. crc[filter/2] |= smsc_crc(arp, 2, filter);
  1247. filter++;
  1248. }
  1249. if (pdata->wolopts & WAKE_UCAST) {
  1250. netdev_info(dev->net, "enabling unicast detection\n");
  1251. filter_mask[filter * 4] = 0x003F;
  1252. filter_mask[filter * 4 + 1] = 0x00;
  1253. filter_mask[filter * 4 + 2] = 0x00;
  1254. filter_mask[filter * 4 + 3] = 0x00;
  1255. command[filter/4] |= 0x01UL << ((filter % 4) * 8);
  1256. offset[filter/4] |= 0x00 << ((filter % 4) * 8);
  1257. crc[filter/2] |= smsc_crc(dev->net->dev_addr, ETH_ALEN, filter);
  1258. filter++;
  1259. }
  1260. for (i = 0; i < (wuff_filter_count * 4); i++) {
  1261. ret = smsc95xx_write_reg_nopm(dev, WUFF, filter_mask[i]);
  1262. if (ret < 0) {
  1263. kfree(filter_mask);
  1264. goto done;
  1265. }
  1266. }
  1267. kfree(filter_mask);
  1268. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1269. ret = smsc95xx_write_reg_nopm(dev, WUFF, command[i]);
  1270. if (ret < 0)
  1271. goto done;
  1272. }
  1273. for (i = 0; i < (wuff_filter_count / 4); i++) {
  1274. ret = smsc95xx_write_reg_nopm(dev, WUFF, offset[i]);
  1275. if (ret < 0)
  1276. goto done;
  1277. }
  1278. for (i = 0; i < (wuff_filter_count / 2); i++) {
  1279. ret = smsc95xx_write_reg_nopm(dev, WUFF, crc[i]);
  1280. if (ret < 0)
  1281. goto done;
  1282. }
  1283. /* clear any pending pattern match packet status */
  1284. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1285. if (ret < 0)
  1286. goto done;
  1287. val |= WUCSR_WUFR_;
  1288. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1289. if (ret < 0)
  1290. goto done;
  1291. }
  1292. if (pdata->wolopts & WAKE_MAGIC) {
  1293. /* clear any pending magic packet status */
  1294. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1295. if (ret < 0)
  1296. goto done;
  1297. val |= WUCSR_MPR_;
  1298. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1299. if (ret < 0)
  1300. goto done;
  1301. }
  1302. /* enable/disable wakeup sources */
  1303. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1304. if (ret < 0)
  1305. goto done;
  1306. if (pdata->wolopts & (WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_UCAST)) {
  1307. netdev_info(dev->net, "enabling pattern match wakeup\n");
  1308. val |= WUCSR_WAKE_EN_;
  1309. } else {
  1310. netdev_info(dev->net, "disabling pattern match wakeup\n");
  1311. val &= ~WUCSR_WAKE_EN_;
  1312. }
  1313. if (pdata->wolopts & WAKE_MAGIC) {
  1314. netdev_info(dev->net, "enabling magic packet wakeup\n");
  1315. val |= WUCSR_MPEN_;
  1316. } else {
  1317. netdev_info(dev->net, "disabling magic packet wakeup\n");
  1318. val &= ~WUCSR_MPEN_;
  1319. }
  1320. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1321. if (ret < 0)
  1322. goto done;
  1323. /* enable wol wakeup source */
  1324. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1325. if (ret < 0)
  1326. goto done;
  1327. val |= PM_CTL_WOL_EN_;
  1328. /* phy energy detect wakeup source */
  1329. if (pdata->wolopts & WAKE_PHY)
  1330. val |= PM_CTL_ED_EN_;
  1331. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1332. if (ret < 0)
  1333. goto done;
  1334. /* enable receiver to enable frame reception */
  1335. smsc95xx_start_rx_path(dev, 1);
  1336. /* some wol options are enabled, so enter SUSPEND0 */
  1337. netdev_info(dev->net, "entering SUSPEND0 mode\n");
  1338. ret = smsc95xx_enter_suspend0(dev);
  1339. done:
  1340. /*
  1341. * TODO: resume() might need to handle the suspend failure
  1342. * in system sleep
  1343. */
  1344. if (ret && PMSG_IS_AUTO(message))
  1345. usbnet_resume(intf);
  1346. return ret;
  1347. }
  1348. static int smsc95xx_resume(struct usb_interface *intf)
  1349. {
  1350. struct usbnet *dev = usb_get_intfdata(intf);
  1351. struct smsc95xx_priv *pdata;
  1352. u8 suspend_flags;
  1353. int ret;
  1354. u32 val;
  1355. BUG_ON(!dev);
  1356. pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1357. suspend_flags = pdata->suspend_flags;
  1358. netdev_dbg(dev->net, "resume suspend_flags=0x%02x\n", suspend_flags);
  1359. /* do this first to ensure it's cleared even in error case */
  1360. pdata->suspend_flags = 0;
  1361. if (suspend_flags & SUSPEND_ALLMODES) {
  1362. /* clear wake-up sources */
  1363. ret = smsc95xx_read_reg_nopm(dev, WUCSR, &val);
  1364. if (ret < 0)
  1365. return ret;
  1366. val &= ~(WUCSR_WAKE_EN_ | WUCSR_MPEN_);
  1367. ret = smsc95xx_write_reg_nopm(dev, WUCSR, val);
  1368. if (ret < 0)
  1369. return ret;
  1370. /* clear wake-up status */
  1371. ret = smsc95xx_read_reg_nopm(dev, PM_CTRL, &val);
  1372. if (ret < 0)
  1373. return ret;
  1374. val &= ~PM_CTL_WOL_EN_;
  1375. val |= PM_CTL_WUPS_;
  1376. ret = smsc95xx_write_reg_nopm(dev, PM_CTRL, val);
  1377. if (ret < 0)
  1378. return ret;
  1379. }
  1380. ret = usbnet_resume(intf);
  1381. if (ret < 0)
  1382. netdev_warn(dev->net, "usbnet_resume error\n");
  1383. return ret;
  1384. }
  1385. static int smsc95xx_reset_resume(struct usb_interface *intf)
  1386. {
  1387. struct usbnet *dev = usb_get_intfdata(intf);
  1388. int ret;
  1389. ret = smsc95xx_reset(dev);
  1390. if (ret < 0)
  1391. return ret;
  1392. return smsc95xx_resume(intf);
  1393. }
  1394. static void smsc95xx_rx_csum_offload(struct sk_buff *skb)
  1395. {
  1396. skb->csum = *(u16 *)(skb_tail_pointer(skb) - 2);
  1397. skb->ip_summed = CHECKSUM_COMPLETE;
  1398. skb_trim(skb, skb->len - 2);
  1399. }
  1400. static int smsc95xx_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
  1401. {
  1402. /* This check is no longer done by usbnet */
  1403. if (skb->len < dev->net->hard_header_len)
  1404. return 0;
  1405. while (skb->len > 0) {
  1406. u32 header, align_count;
  1407. struct sk_buff *ax_skb;
  1408. unsigned char *packet;
  1409. u16 size;
  1410. memcpy(&header, skb->data, sizeof(header));
  1411. le32_to_cpus(&header);
  1412. skb_pull(skb, 4 + NET_IP_ALIGN);
  1413. packet = skb->data;
  1414. /* get the packet length */
  1415. size = (u16)((header & RX_STS_FL_) >> 16);
  1416. align_count = (4 - ((size + NET_IP_ALIGN) % 4)) % 4;
  1417. if (unlikely(header & RX_STS_ES_)) {
  1418. netif_dbg(dev, rx_err, dev->net,
  1419. "Error header=0x%08x\n", header);
  1420. dev->net->stats.rx_errors++;
  1421. dev->net->stats.rx_dropped++;
  1422. if (header & RX_STS_CRC_) {
  1423. dev->net->stats.rx_crc_errors++;
  1424. } else {
  1425. if (header & (RX_STS_TL_ | RX_STS_RF_))
  1426. dev->net->stats.rx_frame_errors++;
  1427. if ((header & RX_STS_LE_) &&
  1428. (!(header & RX_STS_FT_)))
  1429. dev->net->stats.rx_length_errors++;
  1430. }
  1431. } else {
  1432. /* ETH_FRAME_LEN + 4(CRC) + 2(COE) + 4(Vlan) */
  1433. if (unlikely(size > (ETH_FRAME_LEN + 12))) {
  1434. netif_dbg(dev, rx_err, dev->net,
  1435. "size err header=0x%08x\n", header);
  1436. return 0;
  1437. }
  1438. /* last frame in this batch */
  1439. if (skb->len == size) {
  1440. if (dev->net->features & NETIF_F_RXCSUM)
  1441. smsc95xx_rx_csum_offload(skb);
  1442. skb_trim(skb, skb->len - 4); /* remove fcs */
  1443. skb->truesize = size + sizeof(struct sk_buff);
  1444. return 1;
  1445. }
  1446. ax_skb = skb_clone(skb, GFP_ATOMIC);
  1447. if (unlikely(!ax_skb)) {
  1448. netdev_warn(dev->net, "Error allocating skb\n");
  1449. return 0;
  1450. }
  1451. ax_skb->len = size;
  1452. ax_skb->data = packet;
  1453. skb_set_tail_pointer(ax_skb, size);
  1454. if (dev->net->features & NETIF_F_RXCSUM)
  1455. smsc95xx_rx_csum_offload(ax_skb);
  1456. skb_trim(ax_skb, ax_skb->len - 4); /* remove fcs */
  1457. ax_skb->truesize = size + sizeof(struct sk_buff);
  1458. usbnet_skb_return(dev, ax_skb);
  1459. }
  1460. skb_pull(skb, size);
  1461. /* padding bytes before the next frame starts */
  1462. if (skb->len)
  1463. skb_pull(skb, align_count);
  1464. }
  1465. return 1;
  1466. }
  1467. static u32 smsc95xx_calc_csum_preamble(struct sk_buff *skb)
  1468. {
  1469. u16 low_16 = (u16)skb_checksum_start_offset(skb);
  1470. u16 high_16 = low_16 + skb->csum_offset;
  1471. return (high_16 << 16) | low_16;
  1472. }
  1473. static struct sk_buff *smsc95xx_tx_fixup(struct usbnet *dev,
  1474. struct sk_buff *skb, gfp_t flags)
  1475. {
  1476. bool csum = skb->ip_summed == CHECKSUM_PARTIAL;
  1477. int overhead = csum ? SMSC95XX_TX_OVERHEAD_CSUM : SMSC95XX_TX_OVERHEAD;
  1478. u32 tx_cmd_a, tx_cmd_b;
  1479. /* We do not advertise SG, so skbs should be already linearized */
  1480. BUG_ON(skb_shinfo(skb)->nr_frags);
  1481. /* Make writable and expand header space by overhead if required */
  1482. if (skb_cow_head(skb, overhead)) {
  1483. /* Must deallocate here as returning NULL to indicate error
  1484. * means the skb won't be deallocated in the caller.
  1485. */
  1486. dev_kfree_skb_any(skb);
  1487. return NULL;
  1488. }
  1489. if (csum) {
  1490. if (skb->len <= 45) {
  1491. /* workaround - hardware tx checksum does not work
  1492. * properly with extremely small packets */
  1493. long csstart = skb_checksum_start_offset(skb);
  1494. __wsum calc = csum_partial(skb->data + csstart,
  1495. skb->len - csstart, 0);
  1496. *((__sum16 *)(skb->data + csstart
  1497. + skb->csum_offset)) = csum_fold(calc);
  1498. csum = false;
  1499. } else {
  1500. u32 csum_preamble = smsc95xx_calc_csum_preamble(skb);
  1501. skb_push(skb, 4);
  1502. cpu_to_le32s(&csum_preamble);
  1503. memcpy(skb->data, &csum_preamble, 4);
  1504. }
  1505. }
  1506. skb_push(skb, 4);
  1507. tx_cmd_b = (u32)(skb->len - 4);
  1508. if (csum)
  1509. tx_cmd_b |= TX_CMD_B_CSUM_ENABLE;
  1510. cpu_to_le32s(&tx_cmd_b);
  1511. memcpy(skb->data, &tx_cmd_b, 4);
  1512. skb_push(skb, 4);
  1513. tx_cmd_a = (u32)(skb->len - 8) | TX_CMD_A_FIRST_SEG_ |
  1514. TX_CMD_A_LAST_SEG_;
  1515. cpu_to_le32s(&tx_cmd_a);
  1516. memcpy(skb->data, &tx_cmd_a, 4);
  1517. return skb;
  1518. }
  1519. static int smsc95xx_manage_power(struct usbnet *dev, int on)
  1520. {
  1521. struct smsc95xx_priv *pdata = (struct smsc95xx_priv *)(dev->data[0]);
  1522. dev->intf->needs_remote_wakeup = on;
  1523. if (pdata->features & FEATURE_REMOTE_WAKEUP)
  1524. return 0;
  1525. /* this chip revision isn't capable of remote wakeup */
  1526. netdev_info(dev->net, "hardware isn't capable of remote wakeup\n");
  1527. if (on)
  1528. usb_autopm_get_interface_no_resume(dev->intf);
  1529. else
  1530. usb_autopm_put_interface(dev->intf);
  1531. return 0;
  1532. }
  1533. static const struct driver_info smsc95xx_info = {
  1534. .description = "smsc95xx USB 2.0 Ethernet",
  1535. .bind = smsc95xx_bind,
  1536. .unbind = smsc95xx_unbind,
  1537. .link_reset = smsc95xx_link_reset,
  1538. .reset = smsc95xx_reset,
  1539. .rx_fixup = smsc95xx_rx_fixup,
  1540. .tx_fixup = smsc95xx_tx_fixup,
  1541. .status = smsc95xx_status,
  1542. .manage_power = smsc95xx_manage_power,
  1543. .flags = FLAG_ETHER | FLAG_SEND_ZLP | FLAG_LINK_INTR,
  1544. };
  1545. static const struct usb_device_id products[] = {
  1546. {
  1547. /* SMSC9500 USB Ethernet Device */
  1548. USB_DEVICE(0x0424, 0x9500),
  1549. .driver_info = (unsigned long) &smsc95xx_info,
  1550. },
  1551. {
  1552. /* SMSC9505 USB Ethernet Device */
  1553. USB_DEVICE(0x0424, 0x9505),
  1554. .driver_info = (unsigned long) &smsc95xx_info,
  1555. },
  1556. {
  1557. /* SMSC9500A USB Ethernet Device */
  1558. USB_DEVICE(0x0424, 0x9E00),
  1559. .driver_info = (unsigned long) &smsc95xx_info,
  1560. },
  1561. {
  1562. /* SMSC9505A USB Ethernet Device */
  1563. USB_DEVICE(0x0424, 0x9E01),
  1564. .driver_info = (unsigned long) &smsc95xx_info,
  1565. },
  1566. {
  1567. /* SMSC9512/9514 USB Hub & Ethernet Device */
  1568. USB_DEVICE(0x0424, 0xec00),
  1569. .driver_info = (unsigned long) &smsc95xx_info,
  1570. },
  1571. {
  1572. /* SMSC9500 USB Ethernet Device (SAL10) */
  1573. USB_DEVICE(0x0424, 0x9900),
  1574. .driver_info = (unsigned long) &smsc95xx_info,
  1575. },
  1576. {
  1577. /* SMSC9505 USB Ethernet Device (SAL10) */
  1578. USB_DEVICE(0x0424, 0x9901),
  1579. .driver_info = (unsigned long) &smsc95xx_info,
  1580. },
  1581. {
  1582. /* SMSC9500A USB Ethernet Device (SAL10) */
  1583. USB_DEVICE(0x0424, 0x9902),
  1584. .driver_info = (unsigned long) &smsc95xx_info,
  1585. },
  1586. {
  1587. /* SMSC9505A USB Ethernet Device (SAL10) */
  1588. USB_DEVICE(0x0424, 0x9903),
  1589. .driver_info = (unsigned long) &smsc95xx_info,
  1590. },
  1591. {
  1592. /* SMSC9512/9514 USB Hub & Ethernet Device (SAL10) */
  1593. USB_DEVICE(0x0424, 0x9904),
  1594. .driver_info = (unsigned long) &smsc95xx_info,
  1595. },
  1596. {
  1597. /* SMSC9500A USB Ethernet Device (HAL) */
  1598. USB_DEVICE(0x0424, 0x9905),
  1599. .driver_info = (unsigned long) &smsc95xx_info,
  1600. },
  1601. {
  1602. /* SMSC9505A USB Ethernet Device (HAL) */
  1603. USB_DEVICE(0x0424, 0x9906),
  1604. .driver_info = (unsigned long) &smsc95xx_info,
  1605. },
  1606. {
  1607. /* SMSC9500 USB Ethernet Device (Alternate ID) */
  1608. USB_DEVICE(0x0424, 0x9907),
  1609. .driver_info = (unsigned long) &smsc95xx_info,
  1610. },
  1611. {
  1612. /* SMSC9500A USB Ethernet Device (Alternate ID) */
  1613. USB_DEVICE(0x0424, 0x9908),
  1614. .driver_info = (unsigned long) &smsc95xx_info,
  1615. },
  1616. {
  1617. /* SMSC9512/9514 USB Hub & Ethernet Device (Alternate ID) */
  1618. USB_DEVICE(0x0424, 0x9909),
  1619. .driver_info = (unsigned long) &smsc95xx_info,
  1620. },
  1621. {
  1622. /* SMSC LAN9530 USB Ethernet Device */
  1623. USB_DEVICE(0x0424, 0x9530),
  1624. .driver_info = (unsigned long) &smsc95xx_info,
  1625. },
  1626. {
  1627. /* SMSC LAN9730 USB Ethernet Device */
  1628. USB_DEVICE(0x0424, 0x9730),
  1629. .driver_info = (unsigned long) &smsc95xx_info,
  1630. },
  1631. {
  1632. /* SMSC LAN89530 USB Ethernet Device */
  1633. USB_DEVICE(0x0424, 0x9E08),
  1634. .driver_info = (unsigned long) &smsc95xx_info,
  1635. },
  1636. { }, /* END */
  1637. };
  1638. MODULE_DEVICE_TABLE(usb, products);
  1639. static struct usb_driver smsc95xx_driver = {
  1640. .name = "smsc95xx",
  1641. .id_table = products,
  1642. .probe = usbnet_probe,
  1643. .suspend = smsc95xx_suspend,
  1644. .resume = smsc95xx_resume,
  1645. .reset_resume = smsc95xx_reset_resume,
  1646. .disconnect = usbnet_disconnect,
  1647. .disable_hub_initiated_lpm = 1,
  1648. .supports_autosuspend = 1,
  1649. };
  1650. module_usb_driver(smsc95xx_driver);
  1651. MODULE_AUTHOR("Nancy Lin");
  1652. MODULE_AUTHOR("Steve Glendinning <steve.glendinning@shawell.net>");
  1653. MODULE_DESCRIPTION("SMSC95XX USB 2.0 Ethernet Devices");
  1654. MODULE_LICENSE("GPL");