core.c 51 KB

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  1. /*
  2. * Copyright (c) 2005-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/firmware.h>
  19. #include <linux/of.h>
  20. #include "core.h"
  21. #include "mac.h"
  22. #include "htc.h"
  23. #include "hif.h"
  24. #include "wmi.h"
  25. #include "bmi.h"
  26. #include "debug.h"
  27. #include "htt.h"
  28. #include "testmode.h"
  29. #include "wmi-ops.h"
  30. unsigned int ath10k_debug_mask;
  31. static unsigned int ath10k_cryptmode_param;
  32. static bool uart_print;
  33. static bool skip_otp;
  34. static bool rawmode;
  35. module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
  36. module_param_named(cryptmode, ath10k_cryptmode_param, uint, 0644);
  37. module_param(uart_print, bool, 0644);
  38. module_param(skip_otp, bool, 0644);
  39. module_param(rawmode, bool, 0644);
  40. MODULE_PARM_DESC(debug_mask, "Debugging mask");
  41. MODULE_PARM_DESC(uart_print, "Uart target debugging");
  42. MODULE_PARM_DESC(skip_otp, "Skip otp failure for calibration in testmode");
  43. MODULE_PARM_DESC(cryptmode, "Crypto mode: 0-hardware, 1-software");
  44. MODULE_PARM_DESC(rawmode, "Use raw 802.11 frame datapath");
  45. static const struct ath10k_hw_params ath10k_hw_params_list[] = {
  46. {
  47. .id = QCA988X_HW_2_0_VERSION,
  48. .dev_id = QCA988X_2_0_DEVICE_ID,
  49. .name = "qca988x hw2.0",
  50. .patch_load_addr = QCA988X_HW_2_0_PATCH_LOAD_ADDR,
  51. .uart_pin = 7,
  52. .has_shifted_cc_wraparound = true,
  53. .otp_exe_param = 0,
  54. .channel_counters_freq_hz = 88000,
  55. .max_probe_resp_desc_thres = 0,
  56. .fw = {
  57. .dir = QCA988X_HW_2_0_FW_DIR,
  58. .fw = QCA988X_HW_2_0_FW_FILE,
  59. .otp = QCA988X_HW_2_0_OTP_FILE,
  60. .board = QCA988X_HW_2_0_BOARD_DATA_FILE,
  61. .board_size = QCA988X_BOARD_DATA_SZ,
  62. .board_ext_size = QCA988X_BOARD_EXT_DATA_SZ,
  63. },
  64. .decap_align_bytes = 4,
  65. },
  66. {
  67. .id = QCA6174_HW_2_1_VERSION,
  68. .dev_id = QCA6164_2_1_DEVICE_ID,
  69. .name = "qca6164 hw2.1",
  70. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  71. .uart_pin = 6,
  72. .otp_exe_param = 0,
  73. .channel_counters_freq_hz = 88000,
  74. .max_probe_resp_desc_thres = 0,
  75. .fw = {
  76. .dir = QCA6174_HW_2_1_FW_DIR,
  77. .fw = QCA6174_HW_2_1_FW_FILE,
  78. .otp = QCA6174_HW_2_1_OTP_FILE,
  79. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  80. .board_size = QCA6174_BOARD_DATA_SZ,
  81. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  82. },
  83. .decap_align_bytes = 4,
  84. },
  85. {
  86. .id = QCA6174_HW_2_1_VERSION,
  87. .dev_id = QCA6174_2_1_DEVICE_ID,
  88. .name = "qca6174 hw2.1",
  89. .patch_load_addr = QCA6174_HW_2_1_PATCH_LOAD_ADDR,
  90. .uart_pin = 6,
  91. .otp_exe_param = 0,
  92. .channel_counters_freq_hz = 88000,
  93. .max_probe_resp_desc_thres = 0,
  94. .fw = {
  95. .dir = QCA6174_HW_2_1_FW_DIR,
  96. .fw = QCA6174_HW_2_1_FW_FILE,
  97. .otp = QCA6174_HW_2_1_OTP_FILE,
  98. .board = QCA6174_HW_2_1_BOARD_DATA_FILE,
  99. .board_size = QCA6174_BOARD_DATA_SZ,
  100. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  101. },
  102. .decap_align_bytes = 4,
  103. },
  104. {
  105. .id = QCA6174_HW_3_0_VERSION,
  106. .dev_id = QCA6174_2_1_DEVICE_ID,
  107. .name = "qca6174 hw3.0",
  108. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  109. .uart_pin = 6,
  110. .otp_exe_param = 0,
  111. .channel_counters_freq_hz = 88000,
  112. .max_probe_resp_desc_thres = 0,
  113. .fw = {
  114. .dir = QCA6174_HW_3_0_FW_DIR,
  115. .fw = QCA6174_HW_3_0_FW_FILE,
  116. .otp = QCA6174_HW_3_0_OTP_FILE,
  117. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  118. .board_size = QCA6174_BOARD_DATA_SZ,
  119. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  120. },
  121. .decap_align_bytes = 4,
  122. },
  123. {
  124. .id = QCA6174_HW_3_2_VERSION,
  125. .dev_id = QCA6174_2_1_DEVICE_ID,
  126. .name = "qca6174 hw3.2",
  127. .patch_load_addr = QCA6174_HW_3_0_PATCH_LOAD_ADDR,
  128. .uart_pin = 6,
  129. .otp_exe_param = 0,
  130. .channel_counters_freq_hz = 88000,
  131. .max_probe_resp_desc_thres = 0,
  132. .fw = {
  133. /* uses same binaries as hw3.0 */
  134. .dir = QCA6174_HW_3_0_FW_DIR,
  135. .fw = QCA6174_HW_3_0_FW_FILE,
  136. .otp = QCA6174_HW_3_0_OTP_FILE,
  137. .board = QCA6174_HW_3_0_BOARD_DATA_FILE,
  138. .board_size = QCA6174_BOARD_DATA_SZ,
  139. .board_ext_size = QCA6174_BOARD_EXT_DATA_SZ,
  140. },
  141. .decap_align_bytes = 4,
  142. },
  143. {
  144. .id = QCA99X0_HW_2_0_DEV_VERSION,
  145. .dev_id = QCA99X0_2_0_DEVICE_ID,
  146. .name = "qca99x0 hw2.0",
  147. .patch_load_addr = QCA99X0_HW_2_0_PATCH_LOAD_ADDR,
  148. .uart_pin = 7,
  149. .otp_exe_param = 0x00000700,
  150. .continuous_frag_desc = true,
  151. .channel_counters_freq_hz = 150000,
  152. .max_probe_resp_desc_thres = 24,
  153. .fw = {
  154. .dir = QCA99X0_HW_2_0_FW_DIR,
  155. .fw = QCA99X0_HW_2_0_FW_FILE,
  156. .otp = QCA99X0_HW_2_0_OTP_FILE,
  157. .board = QCA99X0_HW_2_0_BOARD_DATA_FILE,
  158. .board_size = QCA99X0_BOARD_DATA_SZ,
  159. .board_ext_size = QCA99X0_BOARD_EXT_DATA_SZ,
  160. },
  161. .decap_align_bytes = 1,
  162. },
  163. {
  164. .id = QCA9377_HW_1_0_DEV_VERSION,
  165. .dev_id = QCA9377_1_0_DEVICE_ID,
  166. .name = "qca9377 hw1.0",
  167. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  168. .uart_pin = 6,
  169. .otp_exe_param = 0,
  170. .channel_counters_freq_hz = 88000,
  171. .max_probe_resp_desc_thres = 0,
  172. .fw = {
  173. .dir = QCA9377_HW_1_0_FW_DIR,
  174. .fw = QCA9377_HW_1_0_FW_FILE,
  175. .otp = QCA9377_HW_1_0_OTP_FILE,
  176. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  177. .board_size = QCA9377_BOARD_DATA_SZ,
  178. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  179. },
  180. .decap_align_bytes = 4,
  181. },
  182. {
  183. .id = QCA9377_HW_1_1_DEV_VERSION,
  184. .dev_id = QCA9377_1_0_DEVICE_ID,
  185. .name = "qca9377 hw1.1",
  186. .patch_load_addr = QCA9377_HW_1_0_PATCH_LOAD_ADDR,
  187. .uart_pin = 6,
  188. .otp_exe_param = 0,
  189. .channel_counters_freq_hz = 88000,
  190. .max_probe_resp_desc_thres = 0,
  191. .fw = {
  192. .dir = QCA9377_HW_1_0_FW_DIR,
  193. .fw = QCA9377_HW_1_0_FW_FILE,
  194. .otp = QCA9377_HW_1_0_OTP_FILE,
  195. .board = QCA9377_HW_1_0_BOARD_DATA_FILE,
  196. .board_size = QCA9377_BOARD_DATA_SZ,
  197. .board_ext_size = QCA9377_BOARD_EXT_DATA_SZ,
  198. },
  199. .decap_align_bytes = 4,
  200. },
  201. };
  202. static const char *const ath10k_core_fw_feature_str[] = {
  203. [ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX] = "wmi-mgmt-rx",
  204. [ATH10K_FW_FEATURE_WMI_10X] = "wmi-10.x",
  205. [ATH10K_FW_FEATURE_HAS_WMI_MGMT_TX] = "has-wmi-mgmt-tx",
  206. [ATH10K_FW_FEATURE_NO_P2P] = "no-p2p",
  207. [ATH10K_FW_FEATURE_WMI_10_2] = "wmi-10.2",
  208. [ATH10K_FW_FEATURE_MULTI_VIF_PS_SUPPORT] = "multi-vif-ps",
  209. [ATH10K_FW_FEATURE_WOWLAN_SUPPORT] = "wowlan",
  210. [ATH10K_FW_FEATURE_IGNORE_OTP_RESULT] = "ignore-otp",
  211. [ATH10K_FW_FEATURE_NO_NWIFI_DECAP_4ADDR_PADDING] = "no-4addr-pad",
  212. [ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT] = "skip-clock-init",
  213. [ATH10K_FW_FEATURE_RAW_MODE_SUPPORT] = "raw-mode",
  214. [ATH10K_FW_FEATURE_SUPPORTS_ADAPTIVE_CCA] = "adaptive-cca",
  215. };
  216. static unsigned int ath10k_core_get_fw_feature_str(char *buf,
  217. size_t buf_len,
  218. enum ath10k_fw_features feat)
  219. {
  220. /* make sure that ath10k_core_fw_feature_str[] gets updated */
  221. BUILD_BUG_ON(ARRAY_SIZE(ath10k_core_fw_feature_str) !=
  222. ATH10K_FW_FEATURE_COUNT);
  223. if (feat >= ARRAY_SIZE(ath10k_core_fw_feature_str) ||
  224. WARN_ON(!ath10k_core_fw_feature_str[feat])) {
  225. return scnprintf(buf, buf_len, "bit%d", feat);
  226. }
  227. return scnprintf(buf, buf_len, "%s", ath10k_core_fw_feature_str[feat]);
  228. }
  229. void ath10k_core_get_fw_features_str(struct ath10k *ar,
  230. char *buf,
  231. size_t buf_len)
  232. {
  233. unsigned int len = 0;
  234. int i;
  235. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  236. if (test_bit(i, ar->fw_features)) {
  237. if (len > 0)
  238. len += scnprintf(buf + len, buf_len - len, ",");
  239. len += ath10k_core_get_fw_feature_str(buf + len,
  240. buf_len - len,
  241. i);
  242. }
  243. }
  244. }
  245. static void ath10k_send_suspend_complete(struct ath10k *ar)
  246. {
  247. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot suspend complete\n");
  248. complete(&ar->target_suspend);
  249. }
  250. static int ath10k_init_configure_target(struct ath10k *ar)
  251. {
  252. u32 param_host;
  253. int ret;
  254. /* tell target which HTC version it is used*/
  255. ret = ath10k_bmi_write32(ar, hi_app_host_interest,
  256. HTC_PROTOCOL_VERSION);
  257. if (ret) {
  258. ath10k_err(ar, "settings HTC version failed\n");
  259. return ret;
  260. }
  261. /* set the firmware mode to STA/IBSS/AP */
  262. ret = ath10k_bmi_read32(ar, hi_option_flag, &param_host);
  263. if (ret) {
  264. ath10k_err(ar, "setting firmware mode (1/2) failed\n");
  265. return ret;
  266. }
  267. /* TODO following parameters need to be re-visited. */
  268. /* num_device */
  269. param_host |= (1 << HI_OPTION_NUM_DEV_SHIFT);
  270. /* Firmware mode */
  271. /* FIXME: Why FW_MODE_AP ??.*/
  272. param_host |= (HI_OPTION_FW_MODE_AP << HI_OPTION_FW_MODE_SHIFT);
  273. /* mac_addr_method */
  274. param_host |= (1 << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
  275. /* firmware_bridge */
  276. param_host |= (0 << HI_OPTION_FW_BRIDGE_SHIFT);
  277. /* fwsubmode */
  278. param_host |= (0 << HI_OPTION_FW_SUBMODE_SHIFT);
  279. ret = ath10k_bmi_write32(ar, hi_option_flag, param_host);
  280. if (ret) {
  281. ath10k_err(ar, "setting firmware mode (2/2) failed\n");
  282. return ret;
  283. }
  284. /* We do all byte-swapping on the host */
  285. ret = ath10k_bmi_write32(ar, hi_be, 0);
  286. if (ret) {
  287. ath10k_err(ar, "setting host CPU BE mode failed\n");
  288. return ret;
  289. }
  290. /* FW descriptor/Data swap flags */
  291. ret = ath10k_bmi_write32(ar, hi_fw_swap, 0);
  292. if (ret) {
  293. ath10k_err(ar, "setting FW data/desc swap flags failed\n");
  294. return ret;
  295. }
  296. /* Some devices have a special sanity check that verifies the PCI
  297. * Device ID is written to this host interest var. It is known to be
  298. * required to boot QCA6164.
  299. */
  300. ret = ath10k_bmi_write32(ar, hi_hci_uart_pwr_mgmt_params_ext,
  301. ar->dev_id);
  302. if (ret) {
  303. ath10k_err(ar, "failed to set pwr_mgmt_params: %d\n", ret);
  304. return ret;
  305. }
  306. return 0;
  307. }
  308. static const struct firmware *ath10k_fetch_fw_file(struct ath10k *ar,
  309. const char *dir,
  310. const char *file)
  311. {
  312. char filename[100];
  313. const struct firmware *fw;
  314. int ret;
  315. if (file == NULL)
  316. return ERR_PTR(-ENOENT);
  317. if (dir == NULL)
  318. dir = ".";
  319. snprintf(filename, sizeof(filename), "%s/%s", dir, file);
  320. ret = request_firmware(&fw, filename, ar->dev);
  321. if (ret)
  322. return ERR_PTR(ret);
  323. return fw;
  324. }
  325. static int ath10k_push_board_ext_data(struct ath10k *ar, const void *data,
  326. size_t data_len)
  327. {
  328. u32 board_data_size = ar->hw_params.fw.board_size;
  329. u32 board_ext_data_size = ar->hw_params.fw.board_ext_size;
  330. u32 board_ext_data_addr;
  331. int ret;
  332. ret = ath10k_bmi_read32(ar, hi_board_ext_data, &board_ext_data_addr);
  333. if (ret) {
  334. ath10k_err(ar, "could not read board ext data addr (%d)\n",
  335. ret);
  336. return ret;
  337. }
  338. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  339. "boot push board extended data addr 0x%x\n",
  340. board_ext_data_addr);
  341. if (board_ext_data_addr == 0)
  342. return 0;
  343. if (data_len != (board_data_size + board_ext_data_size)) {
  344. ath10k_err(ar, "invalid board (ext) data sizes %zu != %d+%d\n",
  345. data_len, board_data_size, board_ext_data_size);
  346. return -EINVAL;
  347. }
  348. ret = ath10k_bmi_write_memory(ar, board_ext_data_addr,
  349. data + board_data_size,
  350. board_ext_data_size);
  351. if (ret) {
  352. ath10k_err(ar, "could not write board ext data (%d)\n", ret);
  353. return ret;
  354. }
  355. ret = ath10k_bmi_write32(ar, hi_board_ext_data_config,
  356. (board_ext_data_size << 16) | 1);
  357. if (ret) {
  358. ath10k_err(ar, "could not write board ext data bit (%d)\n",
  359. ret);
  360. return ret;
  361. }
  362. return 0;
  363. }
  364. static int ath10k_download_board_data(struct ath10k *ar, const void *data,
  365. size_t data_len)
  366. {
  367. u32 board_data_size = ar->hw_params.fw.board_size;
  368. u32 address;
  369. int ret;
  370. ret = ath10k_push_board_ext_data(ar, data, data_len);
  371. if (ret) {
  372. ath10k_err(ar, "could not push board ext data (%d)\n", ret);
  373. goto exit;
  374. }
  375. ret = ath10k_bmi_read32(ar, hi_board_data, &address);
  376. if (ret) {
  377. ath10k_err(ar, "could not read board data addr (%d)\n", ret);
  378. goto exit;
  379. }
  380. ret = ath10k_bmi_write_memory(ar, address, data,
  381. min_t(u32, board_data_size,
  382. data_len));
  383. if (ret) {
  384. ath10k_err(ar, "could not write board data (%d)\n", ret);
  385. goto exit;
  386. }
  387. ret = ath10k_bmi_write32(ar, hi_board_data_initialized, 1);
  388. if (ret) {
  389. ath10k_err(ar, "could not write board data bit (%d)\n", ret);
  390. goto exit;
  391. }
  392. exit:
  393. return ret;
  394. }
  395. static int ath10k_download_cal_file(struct ath10k *ar)
  396. {
  397. int ret;
  398. if (!ar->cal_file)
  399. return -ENOENT;
  400. if (IS_ERR(ar->cal_file))
  401. return PTR_ERR(ar->cal_file);
  402. ret = ath10k_download_board_data(ar, ar->cal_file->data,
  403. ar->cal_file->size);
  404. if (ret) {
  405. ath10k_err(ar, "failed to download cal_file data: %d\n", ret);
  406. return ret;
  407. }
  408. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot cal file downloaded\n");
  409. return 0;
  410. }
  411. static int ath10k_download_cal_dt(struct ath10k *ar)
  412. {
  413. struct device_node *node;
  414. int data_len;
  415. void *data;
  416. int ret;
  417. node = ar->dev->of_node;
  418. if (!node)
  419. /* Device Tree is optional, don't print any warnings if
  420. * there's no node for ath10k.
  421. */
  422. return -ENOENT;
  423. if (!of_get_property(node, "qcom,ath10k-calibration-data",
  424. &data_len)) {
  425. /* The calibration data node is optional */
  426. return -ENOENT;
  427. }
  428. if (data_len != QCA988X_CAL_DATA_LEN) {
  429. ath10k_warn(ar, "invalid calibration data length in DT: %d\n",
  430. data_len);
  431. ret = -EMSGSIZE;
  432. goto out;
  433. }
  434. data = kmalloc(data_len, GFP_KERNEL);
  435. if (!data) {
  436. ret = -ENOMEM;
  437. goto out;
  438. }
  439. ret = of_property_read_u8_array(node, "qcom,ath10k-calibration-data",
  440. data, data_len);
  441. if (ret) {
  442. ath10k_warn(ar, "failed to read calibration data from DT: %d\n",
  443. ret);
  444. goto out_free;
  445. }
  446. ret = ath10k_download_board_data(ar, data, data_len);
  447. if (ret) {
  448. ath10k_warn(ar, "failed to download calibration data from Device Tree: %d\n",
  449. ret);
  450. goto out_free;
  451. }
  452. ret = 0;
  453. out_free:
  454. kfree(data);
  455. out:
  456. return ret;
  457. }
  458. static int ath10k_core_get_board_id_from_otp(struct ath10k *ar)
  459. {
  460. u32 result, address;
  461. u8 board_id, chip_id;
  462. int ret;
  463. address = ar->hw_params.patch_load_addr;
  464. if (!ar->otp_data || !ar->otp_len) {
  465. ath10k_warn(ar,
  466. "failed to retrieve board id because of invalid otp\n");
  467. return -ENODATA;
  468. }
  469. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  470. "boot upload otp to 0x%x len %zd for board id\n",
  471. address, ar->otp_len);
  472. ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
  473. if (ret) {
  474. ath10k_err(ar, "could not write otp for board id check: %d\n",
  475. ret);
  476. return ret;
  477. }
  478. ret = ath10k_bmi_execute(ar, address, BMI_PARAM_GET_EEPROM_BOARD_ID,
  479. &result);
  480. if (ret) {
  481. ath10k_err(ar, "could not execute otp for board id check: %d\n",
  482. ret);
  483. return ret;
  484. }
  485. board_id = MS(result, ATH10K_BMI_BOARD_ID_FROM_OTP);
  486. chip_id = MS(result, ATH10K_BMI_CHIP_ID_FROM_OTP);
  487. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  488. "boot get otp board id result 0x%08x board_id %d chip_id %d\n",
  489. result, board_id, chip_id);
  490. if ((result & ATH10K_BMI_BOARD_ID_STATUS_MASK) != 0 ||
  491. (board_id == 0)) {
  492. ath10k_warn(ar, "board id is not exist in otp, ignore it\n");
  493. return -EOPNOTSUPP;
  494. }
  495. ar->id.bmi_ids_valid = true;
  496. ar->id.bmi_board_id = board_id;
  497. ar->id.bmi_chip_id = chip_id;
  498. return 0;
  499. }
  500. static int ath10k_download_and_run_otp(struct ath10k *ar)
  501. {
  502. u32 result, address = ar->hw_params.patch_load_addr;
  503. u32 bmi_otp_exe_param = ar->hw_params.otp_exe_param;
  504. int ret;
  505. ret = ath10k_download_board_data(ar, ar->board_data, ar->board_len);
  506. if (ret) {
  507. ath10k_err(ar, "failed to download board data: %d\n", ret);
  508. return ret;
  509. }
  510. /* OTP is optional */
  511. if (!ar->otp_data || !ar->otp_len) {
  512. ath10k_warn(ar, "Not running otp, calibration will be incorrect (otp-data %p otp_len %zd)!\n",
  513. ar->otp_data, ar->otp_len);
  514. return 0;
  515. }
  516. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot upload otp to 0x%x len %zd\n",
  517. address, ar->otp_len);
  518. ret = ath10k_bmi_fast_download(ar, address, ar->otp_data, ar->otp_len);
  519. if (ret) {
  520. ath10k_err(ar, "could not write otp (%d)\n", ret);
  521. return ret;
  522. }
  523. ret = ath10k_bmi_execute(ar, address, bmi_otp_exe_param, &result);
  524. if (ret) {
  525. ath10k_err(ar, "could not execute otp (%d)\n", ret);
  526. return ret;
  527. }
  528. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot otp execute result %d\n", result);
  529. if (!(skip_otp || test_bit(ATH10K_FW_FEATURE_IGNORE_OTP_RESULT,
  530. ar->fw_features)) &&
  531. result != 0) {
  532. ath10k_err(ar, "otp calibration failed: %d", result);
  533. return -EINVAL;
  534. }
  535. return 0;
  536. }
  537. static int ath10k_download_fw(struct ath10k *ar, enum ath10k_firmware_mode mode)
  538. {
  539. u32 address, data_len;
  540. const char *mode_name;
  541. const void *data;
  542. int ret;
  543. address = ar->hw_params.patch_load_addr;
  544. switch (mode) {
  545. case ATH10K_FIRMWARE_MODE_NORMAL:
  546. data = ar->firmware_data;
  547. data_len = ar->firmware_len;
  548. mode_name = "normal";
  549. ret = ath10k_swap_code_seg_configure(ar,
  550. ATH10K_SWAP_CODE_SEG_BIN_TYPE_FW);
  551. if (ret) {
  552. ath10k_err(ar, "failed to configure fw code swap: %d\n",
  553. ret);
  554. return ret;
  555. }
  556. break;
  557. case ATH10K_FIRMWARE_MODE_UTF:
  558. data = ar->testmode.utf_firmware_data;
  559. data_len = ar->testmode.utf_firmware_len;
  560. mode_name = "utf";
  561. break;
  562. default:
  563. ath10k_err(ar, "unknown firmware mode: %d\n", mode);
  564. return -EINVAL;
  565. }
  566. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  567. "boot uploading firmware image %p len %d mode %s\n",
  568. data, data_len, mode_name);
  569. ret = ath10k_bmi_fast_download(ar, address, data, data_len);
  570. if (ret) {
  571. ath10k_err(ar, "failed to download %s firmware: %d\n",
  572. mode_name, ret);
  573. return ret;
  574. }
  575. return ret;
  576. }
  577. static void ath10k_core_free_board_files(struct ath10k *ar)
  578. {
  579. if (!IS_ERR(ar->board))
  580. release_firmware(ar->board);
  581. ar->board = NULL;
  582. ar->board_data = NULL;
  583. ar->board_len = 0;
  584. }
  585. static void ath10k_core_free_firmware_files(struct ath10k *ar)
  586. {
  587. if (!IS_ERR(ar->otp))
  588. release_firmware(ar->otp);
  589. if (!IS_ERR(ar->firmware))
  590. release_firmware(ar->firmware);
  591. if (!IS_ERR(ar->cal_file))
  592. release_firmware(ar->cal_file);
  593. ath10k_swap_code_seg_release(ar);
  594. ar->otp = NULL;
  595. ar->otp_data = NULL;
  596. ar->otp_len = 0;
  597. ar->firmware = NULL;
  598. ar->firmware_data = NULL;
  599. ar->firmware_len = 0;
  600. ar->cal_file = NULL;
  601. }
  602. static int ath10k_fetch_cal_file(struct ath10k *ar)
  603. {
  604. char filename[100];
  605. /* cal-<bus>-<id>.bin */
  606. scnprintf(filename, sizeof(filename), "cal-%s-%s.bin",
  607. ath10k_bus_str(ar->hif.bus), dev_name(ar->dev));
  608. ar->cal_file = ath10k_fetch_fw_file(ar, ATH10K_FW_DIR, filename);
  609. if (IS_ERR(ar->cal_file))
  610. /* calibration file is optional, don't print any warnings */
  611. return PTR_ERR(ar->cal_file);
  612. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found calibration file %s/%s\n",
  613. ATH10K_FW_DIR, filename);
  614. return 0;
  615. }
  616. static int ath10k_core_fetch_board_data_api_1(struct ath10k *ar)
  617. {
  618. if (!ar->hw_params.fw.board) {
  619. ath10k_err(ar, "failed to find board file fw entry\n");
  620. return -EINVAL;
  621. }
  622. ar->board = ath10k_fetch_fw_file(ar,
  623. ar->hw_params.fw.dir,
  624. ar->hw_params.fw.board);
  625. if (IS_ERR(ar->board))
  626. return PTR_ERR(ar->board);
  627. ar->board_data = ar->board->data;
  628. ar->board_len = ar->board->size;
  629. return 0;
  630. }
  631. static int ath10k_core_parse_bd_ie_board(struct ath10k *ar,
  632. const void *buf, size_t buf_len,
  633. const char *boardname)
  634. {
  635. const struct ath10k_fw_ie *hdr;
  636. bool name_match_found;
  637. int ret, board_ie_id;
  638. size_t board_ie_len;
  639. const void *board_ie_data;
  640. name_match_found = false;
  641. /* go through ATH10K_BD_IE_BOARD_ elements */
  642. while (buf_len > sizeof(struct ath10k_fw_ie)) {
  643. hdr = buf;
  644. board_ie_id = le32_to_cpu(hdr->id);
  645. board_ie_len = le32_to_cpu(hdr->len);
  646. board_ie_data = hdr->data;
  647. buf_len -= sizeof(*hdr);
  648. buf += sizeof(*hdr);
  649. if (buf_len < ALIGN(board_ie_len, 4)) {
  650. ath10k_err(ar, "invalid ATH10K_BD_IE_BOARD length: %zu < %zu\n",
  651. buf_len, ALIGN(board_ie_len, 4));
  652. ret = -EINVAL;
  653. goto out;
  654. }
  655. switch (board_ie_id) {
  656. case ATH10K_BD_IE_BOARD_NAME:
  657. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "board name", "",
  658. board_ie_data, board_ie_len);
  659. if (board_ie_len != strlen(boardname))
  660. break;
  661. ret = memcmp(board_ie_data, boardname, strlen(boardname));
  662. if (ret)
  663. break;
  664. name_match_found = true;
  665. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  666. "boot found match for name '%s'",
  667. boardname);
  668. break;
  669. case ATH10K_BD_IE_BOARD_DATA:
  670. if (!name_match_found)
  671. /* no match found */
  672. break;
  673. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  674. "boot found board data for '%s'",
  675. boardname);
  676. ar->board_data = board_ie_data;
  677. ar->board_len = board_ie_len;
  678. ret = 0;
  679. goto out;
  680. default:
  681. ath10k_warn(ar, "unknown ATH10K_BD_IE_BOARD found: %d\n",
  682. board_ie_id);
  683. break;
  684. }
  685. /* jump over the padding */
  686. board_ie_len = ALIGN(board_ie_len, 4);
  687. buf_len -= board_ie_len;
  688. buf += board_ie_len;
  689. }
  690. /* no match found */
  691. ret = -ENOENT;
  692. out:
  693. return ret;
  694. }
  695. static int ath10k_core_fetch_board_data_api_n(struct ath10k *ar,
  696. const char *boardname,
  697. const char *filename)
  698. {
  699. size_t len, magic_len, ie_len;
  700. struct ath10k_fw_ie *hdr;
  701. const u8 *data;
  702. int ret, ie_id;
  703. ar->board = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, filename);
  704. if (IS_ERR(ar->board))
  705. return PTR_ERR(ar->board);
  706. data = ar->board->data;
  707. len = ar->board->size;
  708. /* magic has extra null byte padded */
  709. magic_len = strlen(ATH10K_BOARD_MAGIC) + 1;
  710. if (len < magic_len) {
  711. ath10k_err(ar, "failed to find magic value in %s/%s, file too short: %zu\n",
  712. ar->hw_params.fw.dir, filename, len);
  713. ret = -EINVAL;
  714. goto err;
  715. }
  716. if (memcmp(data, ATH10K_BOARD_MAGIC, magic_len)) {
  717. ath10k_err(ar, "found invalid board magic\n");
  718. ret = -EINVAL;
  719. goto err;
  720. }
  721. /* magic is padded to 4 bytes */
  722. magic_len = ALIGN(magic_len, 4);
  723. if (len < magic_len) {
  724. ath10k_err(ar, "failed: %s/%s too small to contain board data, len: %zu\n",
  725. ar->hw_params.fw.dir, filename, len);
  726. ret = -EINVAL;
  727. goto err;
  728. }
  729. data += magic_len;
  730. len -= magic_len;
  731. while (len > sizeof(struct ath10k_fw_ie)) {
  732. hdr = (struct ath10k_fw_ie *)data;
  733. ie_id = le32_to_cpu(hdr->id);
  734. ie_len = le32_to_cpu(hdr->len);
  735. len -= sizeof(*hdr);
  736. data = hdr->data;
  737. if (len < ALIGN(ie_len, 4)) {
  738. ath10k_err(ar, "invalid length for board ie_id %d ie_len %zu len %zu\n",
  739. ie_id, ie_len, len);
  740. ret = -EINVAL;
  741. goto err;
  742. }
  743. switch (ie_id) {
  744. case ATH10K_BD_IE_BOARD:
  745. ret = ath10k_core_parse_bd_ie_board(ar, data, ie_len,
  746. boardname);
  747. if (ret == -ENOENT)
  748. /* no match found, continue */
  749. break;
  750. else if (ret)
  751. /* there was an error, bail out */
  752. goto err;
  753. /* board data found */
  754. goto out;
  755. }
  756. /* jump over the padding */
  757. ie_len = ALIGN(ie_len, 4);
  758. len -= ie_len;
  759. data += ie_len;
  760. }
  761. out:
  762. if (!ar->board_data || !ar->board_len) {
  763. ath10k_err(ar,
  764. "failed to fetch board data for %s from %s/%s\n",
  765. ar->hw_params.fw.dir, boardname, filename);
  766. ret = -ENODATA;
  767. goto err;
  768. }
  769. return 0;
  770. err:
  771. ath10k_core_free_board_files(ar);
  772. return ret;
  773. }
  774. static int ath10k_core_create_board_name(struct ath10k *ar, char *name,
  775. size_t name_len)
  776. {
  777. if (ar->id.bmi_ids_valid) {
  778. scnprintf(name, name_len,
  779. "bus=%s,bmi-chip-id=%d,bmi-board-id=%d",
  780. ath10k_bus_str(ar->hif.bus),
  781. ar->id.bmi_chip_id,
  782. ar->id.bmi_board_id);
  783. goto out;
  784. }
  785. scnprintf(name, name_len,
  786. "bus=%s,vendor=%04x,device=%04x,subsystem-vendor=%04x,subsystem-device=%04x",
  787. ath10k_bus_str(ar->hif.bus),
  788. ar->id.vendor, ar->id.device,
  789. ar->id.subsystem_vendor, ar->id.subsystem_device);
  790. out:
  791. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using board name '%s'\n", name);
  792. return 0;
  793. }
  794. static int ath10k_core_fetch_board_file(struct ath10k *ar)
  795. {
  796. char boardname[100];
  797. int ret;
  798. ret = ath10k_core_create_board_name(ar, boardname, sizeof(boardname));
  799. if (ret) {
  800. ath10k_err(ar, "failed to create board name: %d", ret);
  801. return ret;
  802. }
  803. ar->bd_api = 2;
  804. ret = ath10k_core_fetch_board_data_api_n(ar, boardname,
  805. ATH10K_BOARD_API2_FILE);
  806. if (!ret)
  807. goto success;
  808. ar->bd_api = 1;
  809. ret = ath10k_core_fetch_board_data_api_1(ar);
  810. if (ret) {
  811. ath10k_err(ar, "failed to fetch board data\n");
  812. return ret;
  813. }
  814. success:
  815. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using board api %d\n", ar->bd_api);
  816. return 0;
  817. }
  818. static int ath10k_core_fetch_firmware_api_1(struct ath10k *ar)
  819. {
  820. int ret = 0;
  821. if (ar->hw_params.fw.fw == NULL) {
  822. ath10k_err(ar, "firmware file not defined\n");
  823. return -EINVAL;
  824. }
  825. ar->firmware = ath10k_fetch_fw_file(ar,
  826. ar->hw_params.fw.dir,
  827. ar->hw_params.fw.fw);
  828. if (IS_ERR(ar->firmware)) {
  829. ret = PTR_ERR(ar->firmware);
  830. ath10k_err(ar, "could not fetch firmware (%d)\n", ret);
  831. goto err;
  832. }
  833. ar->firmware_data = ar->firmware->data;
  834. ar->firmware_len = ar->firmware->size;
  835. /* OTP may be undefined. If so, don't fetch it at all */
  836. if (ar->hw_params.fw.otp == NULL)
  837. return 0;
  838. ar->otp = ath10k_fetch_fw_file(ar,
  839. ar->hw_params.fw.dir,
  840. ar->hw_params.fw.otp);
  841. if (IS_ERR(ar->otp)) {
  842. ret = PTR_ERR(ar->otp);
  843. ath10k_err(ar, "could not fetch otp (%d)\n", ret);
  844. goto err;
  845. }
  846. ar->otp_data = ar->otp->data;
  847. ar->otp_len = ar->otp->size;
  848. return 0;
  849. err:
  850. ath10k_core_free_firmware_files(ar);
  851. return ret;
  852. }
  853. static int ath10k_core_fetch_firmware_api_n(struct ath10k *ar, const char *name)
  854. {
  855. size_t magic_len, len, ie_len;
  856. int ie_id, i, index, bit, ret;
  857. struct ath10k_fw_ie *hdr;
  858. const u8 *data;
  859. __le32 *timestamp, *version;
  860. /* first fetch the firmware file (firmware-*.bin) */
  861. ar->firmware = ath10k_fetch_fw_file(ar, ar->hw_params.fw.dir, name);
  862. if (IS_ERR(ar->firmware)) {
  863. ath10k_err(ar, "could not fetch firmware file '%s/%s': %ld\n",
  864. ar->hw_params.fw.dir, name, PTR_ERR(ar->firmware));
  865. return PTR_ERR(ar->firmware);
  866. }
  867. data = ar->firmware->data;
  868. len = ar->firmware->size;
  869. /* magic also includes the null byte, check that as well */
  870. magic_len = strlen(ATH10K_FIRMWARE_MAGIC) + 1;
  871. if (len < magic_len) {
  872. ath10k_err(ar, "firmware file '%s/%s' too small to contain magic: %zu\n",
  873. ar->hw_params.fw.dir, name, len);
  874. ret = -EINVAL;
  875. goto err;
  876. }
  877. if (memcmp(data, ATH10K_FIRMWARE_MAGIC, magic_len) != 0) {
  878. ath10k_err(ar, "invalid firmware magic\n");
  879. ret = -EINVAL;
  880. goto err;
  881. }
  882. /* jump over the padding */
  883. magic_len = ALIGN(magic_len, 4);
  884. len -= magic_len;
  885. data += magic_len;
  886. /* loop elements */
  887. while (len > sizeof(struct ath10k_fw_ie)) {
  888. hdr = (struct ath10k_fw_ie *)data;
  889. ie_id = le32_to_cpu(hdr->id);
  890. ie_len = le32_to_cpu(hdr->len);
  891. len -= sizeof(*hdr);
  892. data += sizeof(*hdr);
  893. if (len < ie_len) {
  894. ath10k_err(ar, "invalid length for FW IE %d (%zu < %zu)\n",
  895. ie_id, len, ie_len);
  896. ret = -EINVAL;
  897. goto err;
  898. }
  899. switch (ie_id) {
  900. case ATH10K_FW_IE_FW_VERSION:
  901. if (ie_len > sizeof(ar->hw->wiphy->fw_version) - 1)
  902. break;
  903. memcpy(ar->hw->wiphy->fw_version, data, ie_len);
  904. ar->hw->wiphy->fw_version[ie_len] = '\0';
  905. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  906. "found fw version %s\n",
  907. ar->hw->wiphy->fw_version);
  908. break;
  909. case ATH10K_FW_IE_TIMESTAMP:
  910. if (ie_len != sizeof(u32))
  911. break;
  912. timestamp = (__le32 *)data;
  913. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw timestamp %d\n",
  914. le32_to_cpup(timestamp));
  915. break;
  916. case ATH10K_FW_IE_FEATURES:
  917. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  918. "found firmware features ie (%zd B)\n",
  919. ie_len);
  920. for (i = 0; i < ATH10K_FW_FEATURE_COUNT; i++) {
  921. index = i / 8;
  922. bit = i % 8;
  923. if (index == ie_len)
  924. break;
  925. if (data[index] & (1 << bit)) {
  926. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  927. "Enabling feature bit: %i\n",
  928. i);
  929. __set_bit(i, ar->fw_features);
  930. }
  931. }
  932. ath10k_dbg_dump(ar, ATH10K_DBG_BOOT, "features", "",
  933. ar->fw_features,
  934. sizeof(ar->fw_features));
  935. break;
  936. case ATH10K_FW_IE_FW_IMAGE:
  937. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  938. "found fw image ie (%zd B)\n",
  939. ie_len);
  940. ar->firmware_data = data;
  941. ar->firmware_len = ie_len;
  942. break;
  943. case ATH10K_FW_IE_OTP_IMAGE:
  944. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  945. "found otp image ie (%zd B)\n",
  946. ie_len);
  947. ar->otp_data = data;
  948. ar->otp_len = ie_len;
  949. break;
  950. case ATH10K_FW_IE_WMI_OP_VERSION:
  951. if (ie_len != sizeof(u32))
  952. break;
  953. version = (__le32 *)data;
  954. ar->wmi.op_version = le32_to_cpup(version);
  955. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie wmi op version %d\n",
  956. ar->wmi.op_version);
  957. break;
  958. case ATH10K_FW_IE_HTT_OP_VERSION:
  959. if (ie_len != sizeof(u32))
  960. break;
  961. version = (__le32 *)data;
  962. ar->htt.op_version = le32_to_cpup(version);
  963. ath10k_dbg(ar, ATH10K_DBG_BOOT, "found fw ie htt op version %d\n",
  964. ar->htt.op_version);
  965. break;
  966. case ATH10K_FW_IE_FW_CODE_SWAP_IMAGE:
  967. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  968. "found fw code swap image ie (%zd B)\n",
  969. ie_len);
  970. ar->swap.firmware_codeswap_data = data;
  971. ar->swap.firmware_codeswap_len = ie_len;
  972. break;
  973. default:
  974. ath10k_warn(ar, "Unknown FW IE: %u\n",
  975. le32_to_cpu(hdr->id));
  976. break;
  977. }
  978. /* jump over the padding */
  979. ie_len = ALIGN(ie_len, 4);
  980. len -= ie_len;
  981. data += ie_len;
  982. }
  983. if (!ar->firmware_data || !ar->firmware_len) {
  984. ath10k_warn(ar, "No ATH10K_FW_IE_FW_IMAGE found from '%s/%s', skipping\n",
  985. ar->hw_params.fw.dir, name);
  986. ret = -ENOMEDIUM;
  987. goto err;
  988. }
  989. return 0;
  990. err:
  991. ath10k_core_free_firmware_files(ar);
  992. return ret;
  993. }
  994. static int ath10k_core_fetch_firmware_files(struct ath10k *ar)
  995. {
  996. int ret;
  997. /* calibration file is optional, don't check for any errors */
  998. ath10k_fetch_cal_file(ar);
  999. ar->fw_api = 5;
  1000. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1001. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API5_FILE);
  1002. if (ret == 0)
  1003. goto success;
  1004. ar->fw_api = 4;
  1005. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1006. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API4_FILE);
  1007. if (ret == 0)
  1008. goto success;
  1009. ar->fw_api = 3;
  1010. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1011. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API3_FILE);
  1012. if (ret == 0)
  1013. goto success;
  1014. ar->fw_api = 2;
  1015. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1016. ret = ath10k_core_fetch_firmware_api_n(ar, ATH10K_FW_API2_FILE);
  1017. if (ret == 0)
  1018. goto success;
  1019. ar->fw_api = 1;
  1020. ath10k_dbg(ar, ATH10K_DBG_BOOT, "trying fw api %d\n", ar->fw_api);
  1021. ret = ath10k_core_fetch_firmware_api_1(ar);
  1022. if (ret)
  1023. return ret;
  1024. success:
  1025. ath10k_dbg(ar, ATH10K_DBG_BOOT, "using fw api %d\n", ar->fw_api);
  1026. return 0;
  1027. }
  1028. static int ath10k_download_cal_data(struct ath10k *ar)
  1029. {
  1030. int ret;
  1031. ret = ath10k_download_cal_file(ar);
  1032. if (ret == 0) {
  1033. ar->cal_mode = ATH10K_CAL_MODE_FILE;
  1034. goto done;
  1035. }
  1036. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1037. "boot did not find a calibration file, try DT next: %d\n",
  1038. ret);
  1039. ret = ath10k_download_cal_dt(ar);
  1040. if (ret == 0) {
  1041. ar->cal_mode = ATH10K_CAL_MODE_DT;
  1042. goto done;
  1043. }
  1044. ath10k_dbg(ar, ATH10K_DBG_BOOT,
  1045. "boot did not find DT entry, try OTP next: %d\n",
  1046. ret);
  1047. ret = ath10k_download_and_run_otp(ar);
  1048. if (ret) {
  1049. ath10k_err(ar, "failed to run otp: %d\n", ret);
  1050. return ret;
  1051. }
  1052. ar->cal_mode = ATH10K_CAL_MODE_OTP;
  1053. done:
  1054. ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot using calibration mode %s\n",
  1055. ath10k_cal_mode_str(ar->cal_mode));
  1056. return 0;
  1057. }
  1058. static int ath10k_init_uart(struct ath10k *ar)
  1059. {
  1060. int ret;
  1061. /*
  1062. * Explicitly setting UART prints to zero as target turns it on
  1063. * based on scratch registers.
  1064. */
  1065. ret = ath10k_bmi_write32(ar, hi_serial_enable, 0);
  1066. if (ret) {
  1067. ath10k_warn(ar, "could not disable UART prints (%d)\n", ret);
  1068. return ret;
  1069. }
  1070. if (!uart_print)
  1071. return 0;
  1072. ret = ath10k_bmi_write32(ar, hi_dbg_uart_txpin, ar->hw_params.uart_pin);
  1073. if (ret) {
  1074. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1075. return ret;
  1076. }
  1077. ret = ath10k_bmi_write32(ar, hi_serial_enable, 1);
  1078. if (ret) {
  1079. ath10k_warn(ar, "could not enable UART prints (%d)\n", ret);
  1080. return ret;
  1081. }
  1082. /* Set the UART baud rate to 19200. */
  1083. ret = ath10k_bmi_write32(ar, hi_desired_baud_rate, 19200);
  1084. if (ret) {
  1085. ath10k_warn(ar, "could not set the baud rate (%d)\n", ret);
  1086. return ret;
  1087. }
  1088. ath10k_info(ar, "UART prints enabled\n");
  1089. return 0;
  1090. }
  1091. static int ath10k_init_hw_params(struct ath10k *ar)
  1092. {
  1093. const struct ath10k_hw_params *uninitialized_var(hw_params);
  1094. int i;
  1095. for (i = 0; i < ARRAY_SIZE(ath10k_hw_params_list); i++) {
  1096. hw_params = &ath10k_hw_params_list[i];
  1097. if (hw_params->id == ar->target_version &&
  1098. hw_params->dev_id == ar->dev_id)
  1099. break;
  1100. }
  1101. if (i == ARRAY_SIZE(ath10k_hw_params_list)) {
  1102. ath10k_err(ar, "Unsupported hardware version: 0x%x\n",
  1103. ar->target_version);
  1104. return -EINVAL;
  1105. }
  1106. ar->hw_params = *hw_params;
  1107. ath10k_dbg(ar, ATH10K_DBG_BOOT, "Hardware name %s version 0x%x\n",
  1108. ar->hw_params.name, ar->target_version);
  1109. return 0;
  1110. }
  1111. static void ath10k_core_restart(struct work_struct *work)
  1112. {
  1113. struct ath10k *ar = container_of(work, struct ath10k, restart_work);
  1114. set_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1115. /* Place a barrier to make sure the compiler doesn't reorder
  1116. * CRASH_FLUSH and calling other functions.
  1117. */
  1118. barrier();
  1119. ieee80211_stop_queues(ar->hw);
  1120. ath10k_drain_tx(ar);
  1121. complete_all(&ar->scan.started);
  1122. complete_all(&ar->scan.completed);
  1123. complete_all(&ar->scan.on_channel);
  1124. complete_all(&ar->offchan_tx_completed);
  1125. complete_all(&ar->install_key_done);
  1126. complete_all(&ar->vdev_setup_done);
  1127. complete_all(&ar->thermal.wmi_sync);
  1128. wake_up(&ar->htt.empty_tx_wq);
  1129. wake_up(&ar->wmi.tx_credits_wq);
  1130. wake_up(&ar->peer_mapping_wq);
  1131. mutex_lock(&ar->conf_mutex);
  1132. switch (ar->state) {
  1133. case ATH10K_STATE_ON:
  1134. ar->state = ATH10K_STATE_RESTARTING;
  1135. ath10k_hif_stop(ar);
  1136. ath10k_scan_finish(ar);
  1137. ieee80211_restart_hw(ar->hw);
  1138. break;
  1139. case ATH10K_STATE_OFF:
  1140. /* this can happen if driver is being unloaded
  1141. * or if the crash happens during FW probing */
  1142. ath10k_warn(ar, "cannot restart a device that hasn't been started\n");
  1143. break;
  1144. case ATH10K_STATE_RESTARTING:
  1145. /* hw restart might be requested from multiple places */
  1146. break;
  1147. case ATH10K_STATE_RESTARTED:
  1148. ar->state = ATH10K_STATE_WEDGED;
  1149. /* fall through */
  1150. case ATH10K_STATE_WEDGED:
  1151. ath10k_warn(ar, "device is wedged, will not restart\n");
  1152. break;
  1153. case ATH10K_STATE_UTF:
  1154. ath10k_warn(ar, "firmware restart in UTF mode not supported\n");
  1155. break;
  1156. }
  1157. mutex_unlock(&ar->conf_mutex);
  1158. }
  1159. static int ath10k_core_init_firmware_features(struct ath10k *ar)
  1160. {
  1161. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2, ar->fw_features) &&
  1162. !test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  1163. ath10k_err(ar, "feature bits corrupted: 10.2 feature requires 10.x feature to be set as well");
  1164. return -EINVAL;
  1165. }
  1166. if (ar->wmi.op_version >= ATH10K_FW_WMI_OP_VERSION_MAX) {
  1167. ath10k_err(ar, "unsupported WMI OP version (max %d): %d\n",
  1168. ATH10K_FW_WMI_OP_VERSION_MAX, ar->wmi.op_version);
  1169. return -EINVAL;
  1170. }
  1171. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_NATIVE_WIFI;
  1172. switch (ath10k_cryptmode_param) {
  1173. case ATH10K_CRYPT_MODE_HW:
  1174. clear_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1175. clear_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1176. break;
  1177. case ATH10K_CRYPT_MODE_SW:
  1178. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1179. ar->fw_features)) {
  1180. ath10k_err(ar, "cryptmode > 0 requires raw mode support from firmware");
  1181. return -EINVAL;
  1182. }
  1183. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1184. set_bit(ATH10K_FLAG_HW_CRYPTO_DISABLED, &ar->dev_flags);
  1185. break;
  1186. default:
  1187. ath10k_info(ar, "invalid cryptmode: %d\n",
  1188. ath10k_cryptmode_param);
  1189. return -EINVAL;
  1190. }
  1191. ar->htt.max_num_amsdu = ATH10K_HTT_MAX_NUM_AMSDU_DEFAULT;
  1192. ar->htt.max_num_ampdu = ATH10K_HTT_MAX_NUM_AMPDU_DEFAULT;
  1193. if (rawmode) {
  1194. if (!test_bit(ATH10K_FW_FEATURE_RAW_MODE_SUPPORT,
  1195. ar->fw_features)) {
  1196. ath10k_err(ar, "rawmode = 1 requires support from firmware");
  1197. return -EINVAL;
  1198. }
  1199. set_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags);
  1200. }
  1201. if (test_bit(ATH10K_FLAG_RAW_MODE, &ar->dev_flags)) {
  1202. ar->wmi.rx_decap_mode = ATH10K_HW_TXRX_RAW;
  1203. /* Workaround:
  1204. *
  1205. * Firmware A-MSDU aggregation breaks with RAW Tx encap mode
  1206. * and causes enormous performance issues (malformed frames,
  1207. * etc).
  1208. *
  1209. * Disabling A-MSDU makes RAW mode stable with heavy traffic
  1210. * albeit a bit slower compared to regular operation.
  1211. */
  1212. ar->htt.max_num_amsdu = 1;
  1213. }
  1214. /* Backwards compatibility for firmwares without
  1215. * ATH10K_FW_IE_WMI_OP_VERSION.
  1216. */
  1217. if (ar->wmi.op_version == ATH10K_FW_WMI_OP_VERSION_UNSET) {
  1218. if (test_bit(ATH10K_FW_FEATURE_WMI_10X, ar->fw_features)) {
  1219. if (test_bit(ATH10K_FW_FEATURE_WMI_10_2,
  1220. ar->fw_features))
  1221. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_2;
  1222. else
  1223. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_10_1;
  1224. } else {
  1225. ar->wmi.op_version = ATH10K_FW_WMI_OP_VERSION_MAIN;
  1226. }
  1227. }
  1228. switch (ar->wmi.op_version) {
  1229. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1230. ar->max_num_peers = TARGET_NUM_PEERS;
  1231. ar->max_num_stations = TARGET_NUM_STATIONS;
  1232. ar->max_num_vdevs = TARGET_NUM_VDEVS;
  1233. ar->htt.max_num_pending_tx = TARGET_NUM_MSDU_DESC;
  1234. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1235. WMI_STAT_PEER;
  1236. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1237. break;
  1238. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1239. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1240. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1241. ar->max_num_peers = TARGET_10X_NUM_PEERS;
  1242. ar->max_num_stations = TARGET_10X_NUM_STATIONS;
  1243. ar->max_num_vdevs = TARGET_10X_NUM_VDEVS;
  1244. ar->htt.max_num_pending_tx = TARGET_10X_NUM_MSDU_DESC;
  1245. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1246. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1247. break;
  1248. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1249. ar->max_num_peers = TARGET_TLV_NUM_PEERS;
  1250. ar->max_num_stations = TARGET_TLV_NUM_STATIONS;
  1251. ar->max_num_vdevs = TARGET_TLV_NUM_VDEVS;
  1252. ar->max_num_tdls_vdevs = TARGET_TLV_NUM_TDLS_VDEVS;
  1253. ar->htt.max_num_pending_tx = TARGET_TLV_NUM_MSDU_DESC;
  1254. ar->wow.max_num_patterns = TARGET_TLV_NUM_WOW_PATTERNS;
  1255. ar->fw_stats_req_mask = WMI_STAT_PDEV | WMI_STAT_VDEV |
  1256. WMI_STAT_PEER;
  1257. ar->max_spatial_stream = WMI_MAX_SPATIAL_STREAM;
  1258. break;
  1259. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1260. ar->max_num_peers = TARGET_10_4_NUM_PEERS;
  1261. ar->max_num_stations = TARGET_10_4_NUM_STATIONS;
  1262. ar->num_active_peers = TARGET_10_4_ACTIVE_PEERS;
  1263. ar->max_num_vdevs = TARGET_10_4_NUM_VDEVS;
  1264. ar->num_tids = TARGET_10_4_TGT_NUM_TIDS;
  1265. ar->htt.max_num_pending_tx = TARGET_10_4_NUM_MSDU_DESC;
  1266. ar->fw_stats_req_mask = WMI_STAT_PEER;
  1267. ar->max_spatial_stream = WMI_10_4_MAX_SPATIAL_STREAM;
  1268. break;
  1269. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1270. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1271. WARN_ON(1);
  1272. return -EINVAL;
  1273. }
  1274. /* Backwards compatibility for firmwares without
  1275. * ATH10K_FW_IE_HTT_OP_VERSION.
  1276. */
  1277. if (ar->htt.op_version == ATH10K_FW_HTT_OP_VERSION_UNSET) {
  1278. switch (ar->wmi.op_version) {
  1279. case ATH10K_FW_WMI_OP_VERSION_MAIN:
  1280. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_MAIN;
  1281. break;
  1282. case ATH10K_FW_WMI_OP_VERSION_10_1:
  1283. case ATH10K_FW_WMI_OP_VERSION_10_2:
  1284. case ATH10K_FW_WMI_OP_VERSION_10_2_4:
  1285. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_10_1;
  1286. break;
  1287. case ATH10K_FW_WMI_OP_VERSION_TLV:
  1288. ar->htt.op_version = ATH10K_FW_HTT_OP_VERSION_TLV;
  1289. break;
  1290. case ATH10K_FW_WMI_OP_VERSION_10_4:
  1291. case ATH10K_FW_WMI_OP_VERSION_UNSET:
  1292. case ATH10K_FW_WMI_OP_VERSION_MAX:
  1293. WARN_ON(1);
  1294. return -EINVAL;
  1295. }
  1296. }
  1297. return 0;
  1298. }
  1299. int ath10k_core_start(struct ath10k *ar, enum ath10k_firmware_mode mode)
  1300. {
  1301. int status;
  1302. lockdep_assert_held(&ar->conf_mutex);
  1303. clear_bit(ATH10K_FLAG_CRASH_FLUSH, &ar->dev_flags);
  1304. ath10k_bmi_start(ar);
  1305. if (ath10k_init_configure_target(ar)) {
  1306. status = -EINVAL;
  1307. goto err;
  1308. }
  1309. status = ath10k_download_cal_data(ar);
  1310. if (status)
  1311. goto err;
  1312. /* Some of of qca988x solutions are having global reset issue
  1313. * during target initialization. Bypassing PLL setting before
  1314. * downloading firmware and letting the SoC run on REF_CLK is
  1315. * fixing the problem. Corresponding firmware change is also needed
  1316. * to set the clock source once the target is initialized.
  1317. */
  1318. if (test_bit(ATH10K_FW_FEATURE_SUPPORTS_SKIP_CLOCK_INIT,
  1319. ar->fw_features)) {
  1320. status = ath10k_bmi_write32(ar, hi_skip_clock_init, 1);
  1321. if (status) {
  1322. ath10k_err(ar, "could not write to skip_clock_init: %d\n",
  1323. status);
  1324. goto err;
  1325. }
  1326. }
  1327. status = ath10k_download_fw(ar, mode);
  1328. if (status)
  1329. goto err;
  1330. status = ath10k_init_uart(ar);
  1331. if (status)
  1332. goto err;
  1333. ar->htc.htc_ops.target_send_suspend_complete =
  1334. ath10k_send_suspend_complete;
  1335. status = ath10k_htc_init(ar);
  1336. if (status) {
  1337. ath10k_err(ar, "could not init HTC (%d)\n", status);
  1338. goto err;
  1339. }
  1340. status = ath10k_bmi_done(ar);
  1341. if (status)
  1342. goto err;
  1343. status = ath10k_wmi_attach(ar);
  1344. if (status) {
  1345. ath10k_err(ar, "WMI attach failed: %d\n", status);
  1346. goto err;
  1347. }
  1348. status = ath10k_htt_init(ar);
  1349. if (status) {
  1350. ath10k_err(ar, "failed to init htt: %d\n", status);
  1351. goto err_wmi_detach;
  1352. }
  1353. status = ath10k_htt_tx_alloc(&ar->htt);
  1354. if (status) {
  1355. ath10k_err(ar, "failed to alloc htt tx: %d\n", status);
  1356. goto err_wmi_detach;
  1357. }
  1358. /* If firmware indicates Full Rx Reorder support it must be used in a
  1359. * slightly different manner. Let HTT code know.
  1360. */
  1361. ar->htt.rx_ring.in_ord_rx = !!(test_bit(WMI_SERVICE_RX_FULL_REORDER,
  1362. ar->wmi.svc_map));
  1363. status = ath10k_htt_rx_alloc(&ar->htt);
  1364. if (status) {
  1365. ath10k_err(ar, "failed to alloc htt rx: %d\n", status);
  1366. goto err_htt_tx_detach;
  1367. }
  1368. status = ath10k_hif_start(ar);
  1369. if (status) {
  1370. ath10k_err(ar, "could not start HIF: %d\n", status);
  1371. goto err_htt_rx_detach;
  1372. }
  1373. status = ath10k_htc_wait_target(&ar->htc);
  1374. if (status) {
  1375. ath10k_err(ar, "failed to connect to HTC: %d\n", status);
  1376. goto err_hif_stop;
  1377. }
  1378. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1379. status = ath10k_htt_connect(&ar->htt);
  1380. if (status) {
  1381. ath10k_err(ar, "failed to connect htt (%d)\n", status);
  1382. goto err_hif_stop;
  1383. }
  1384. }
  1385. status = ath10k_wmi_connect(ar);
  1386. if (status) {
  1387. ath10k_err(ar, "could not connect wmi: %d\n", status);
  1388. goto err_hif_stop;
  1389. }
  1390. status = ath10k_htc_start(&ar->htc);
  1391. if (status) {
  1392. ath10k_err(ar, "failed to start htc: %d\n", status);
  1393. goto err_hif_stop;
  1394. }
  1395. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1396. status = ath10k_wmi_wait_for_service_ready(ar);
  1397. if (status) {
  1398. ath10k_warn(ar, "wmi service ready event not received");
  1399. goto err_hif_stop;
  1400. }
  1401. }
  1402. ath10k_dbg(ar, ATH10K_DBG_BOOT, "firmware %s booted\n",
  1403. ar->hw->wiphy->fw_version);
  1404. status = ath10k_wmi_cmd_init(ar);
  1405. if (status) {
  1406. ath10k_err(ar, "could not send WMI init command (%d)\n",
  1407. status);
  1408. goto err_hif_stop;
  1409. }
  1410. status = ath10k_wmi_wait_for_unified_ready(ar);
  1411. if (status) {
  1412. ath10k_err(ar, "wmi unified ready event not received\n");
  1413. goto err_hif_stop;
  1414. }
  1415. status = ath10k_htt_rx_ring_refill(ar);
  1416. if (status) {
  1417. ath10k_err(ar, "failed to refill htt rx ring: %d\n", status);
  1418. goto err_hif_stop;
  1419. }
  1420. ar->free_vdev_map = (1LL << ar->max_num_vdevs) - 1;
  1421. INIT_LIST_HEAD(&ar->arvifs);
  1422. /* we don't care about HTT in UTF mode */
  1423. if (mode == ATH10K_FIRMWARE_MODE_NORMAL) {
  1424. status = ath10k_htt_setup(&ar->htt);
  1425. if (status) {
  1426. ath10k_err(ar, "failed to setup htt: %d\n", status);
  1427. goto err_hif_stop;
  1428. }
  1429. }
  1430. status = ath10k_debug_start(ar);
  1431. if (status)
  1432. goto err_hif_stop;
  1433. return 0;
  1434. err_hif_stop:
  1435. ath10k_hif_stop(ar);
  1436. err_htt_rx_detach:
  1437. ath10k_htt_rx_free(&ar->htt);
  1438. err_htt_tx_detach:
  1439. ath10k_htt_tx_free(&ar->htt);
  1440. err_wmi_detach:
  1441. ath10k_wmi_detach(ar);
  1442. err:
  1443. return status;
  1444. }
  1445. EXPORT_SYMBOL(ath10k_core_start);
  1446. int ath10k_wait_for_suspend(struct ath10k *ar, u32 suspend_opt)
  1447. {
  1448. int ret;
  1449. unsigned long time_left;
  1450. reinit_completion(&ar->target_suspend);
  1451. ret = ath10k_wmi_pdev_suspend_target(ar, suspend_opt);
  1452. if (ret) {
  1453. ath10k_warn(ar, "could not suspend target (%d)\n", ret);
  1454. return ret;
  1455. }
  1456. time_left = wait_for_completion_timeout(&ar->target_suspend, 1 * HZ);
  1457. if (!time_left) {
  1458. ath10k_warn(ar, "suspend timed out - target pause event never came\n");
  1459. return -ETIMEDOUT;
  1460. }
  1461. return 0;
  1462. }
  1463. void ath10k_core_stop(struct ath10k *ar)
  1464. {
  1465. lockdep_assert_held(&ar->conf_mutex);
  1466. ath10k_debug_stop(ar);
  1467. /* try to suspend target */
  1468. if (ar->state != ATH10K_STATE_RESTARTING &&
  1469. ar->state != ATH10K_STATE_UTF)
  1470. ath10k_wait_for_suspend(ar, WMI_PDEV_SUSPEND_AND_DISABLE_INTR);
  1471. ath10k_hif_stop(ar);
  1472. ath10k_htt_tx_free(&ar->htt);
  1473. ath10k_htt_rx_free(&ar->htt);
  1474. ath10k_wmi_detach(ar);
  1475. }
  1476. EXPORT_SYMBOL(ath10k_core_stop);
  1477. /* mac80211 manages fw/hw initialization through start/stop hooks. However in
  1478. * order to know what hw capabilities should be advertised to mac80211 it is
  1479. * necessary to load the firmware (and tear it down immediately since start
  1480. * hook will try to init it again) before registering */
  1481. static int ath10k_core_probe_fw(struct ath10k *ar)
  1482. {
  1483. struct bmi_target_info target_info;
  1484. int ret = 0;
  1485. ret = ath10k_hif_power_up(ar);
  1486. if (ret) {
  1487. ath10k_err(ar, "could not start pci hif (%d)\n", ret);
  1488. return ret;
  1489. }
  1490. memset(&target_info, 0, sizeof(target_info));
  1491. ret = ath10k_bmi_get_target_info(ar, &target_info);
  1492. if (ret) {
  1493. ath10k_err(ar, "could not get target info (%d)\n", ret);
  1494. goto err_power_down;
  1495. }
  1496. ar->target_version = target_info.version;
  1497. ar->hw->wiphy->hw_version = target_info.version;
  1498. ret = ath10k_init_hw_params(ar);
  1499. if (ret) {
  1500. ath10k_err(ar, "could not get hw params (%d)\n", ret);
  1501. goto err_power_down;
  1502. }
  1503. ret = ath10k_core_fetch_firmware_files(ar);
  1504. if (ret) {
  1505. ath10k_err(ar, "could not fetch firmware files (%d)\n", ret);
  1506. goto err_power_down;
  1507. }
  1508. ret = ath10k_core_get_board_id_from_otp(ar);
  1509. if (ret && ret != -EOPNOTSUPP) {
  1510. ath10k_err(ar, "failed to get board id from otp for qca99x0: %d\n",
  1511. ret);
  1512. return ret;
  1513. }
  1514. ret = ath10k_core_fetch_board_file(ar);
  1515. if (ret) {
  1516. ath10k_err(ar, "failed to fetch board file: %d\n", ret);
  1517. goto err_free_firmware_files;
  1518. }
  1519. ret = ath10k_core_init_firmware_features(ar);
  1520. if (ret) {
  1521. ath10k_err(ar, "fatal problem with firmware features: %d\n",
  1522. ret);
  1523. goto err_free_firmware_files;
  1524. }
  1525. ret = ath10k_swap_code_seg_init(ar);
  1526. if (ret) {
  1527. ath10k_err(ar, "failed to initialize code swap segment: %d\n",
  1528. ret);
  1529. goto err_free_firmware_files;
  1530. }
  1531. mutex_lock(&ar->conf_mutex);
  1532. ret = ath10k_core_start(ar, ATH10K_FIRMWARE_MODE_NORMAL);
  1533. if (ret) {
  1534. ath10k_err(ar, "could not init core (%d)\n", ret);
  1535. goto err_unlock;
  1536. }
  1537. ath10k_print_driver_info(ar);
  1538. ath10k_core_stop(ar);
  1539. mutex_unlock(&ar->conf_mutex);
  1540. ath10k_hif_power_down(ar);
  1541. return 0;
  1542. err_unlock:
  1543. mutex_unlock(&ar->conf_mutex);
  1544. err_free_firmware_files:
  1545. ath10k_core_free_firmware_files(ar);
  1546. err_power_down:
  1547. ath10k_hif_power_down(ar);
  1548. return ret;
  1549. }
  1550. static void ath10k_core_register_work(struct work_struct *work)
  1551. {
  1552. struct ath10k *ar = container_of(work, struct ath10k, register_work);
  1553. int status;
  1554. status = ath10k_core_probe_fw(ar);
  1555. if (status) {
  1556. ath10k_err(ar, "could not probe fw (%d)\n", status);
  1557. goto err;
  1558. }
  1559. status = ath10k_mac_register(ar);
  1560. if (status) {
  1561. ath10k_err(ar, "could not register to mac80211 (%d)\n", status);
  1562. goto err_release_fw;
  1563. }
  1564. status = ath10k_debug_register(ar);
  1565. if (status) {
  1566. ath10k_err(ar, "unable to initialize debugfs\n");
  1567. goto err_unregister_mac;
  1568. }
  1569. status = ath10k_spectral_create(ar);
  1570. if (status) {
  1571. ath10k_err(ar, "failed to initialize spectral\n");
  1572. goto err_debug_destroy;
  1573. }
  1574. status = ath10k_thermal_register(ar);
  1575. if (status) {
  1576. ath10k_err(ar, "could not register thermal device: %d\n",
  1577. status);
  1578. goto err_spectral_destroy;
  1579. }
  1580. set_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags);
  1581. return;
  1582. err_spectral_destroy:
  1583. ath10k_spectral_destroy(ar);
  1584. err_debug_destroy:
  1585. ath10k_debug_destroy(ar);
  1586. err_unregister_mac:
  1587. ath10k_mac_unregister(ar);
  1588. err_release_fw:
  1589. ath10k_core_free_firmware_files(ar);
  1590. err:
  1591. /* TODO: It's probably a good idea to release device from the driver
  1592. * but calling device_release_driver() here will cause a deadlock.
  1593. */
  1594. return;
  1595. }
  1596. int ath10k_core_register(struct ath10k *ar, u32 chip_id)
  1597. {
  1598. ar->chip_id = chip_id;
  1599. queue_work(ar->workqueue, &ar->register_work);
  1600. return 0;
  1601. }
  1602. EXPORT_SYMBOL(ath10k_core_register);
  1603. void ath10k_core_unregister(struct ath10k *ar)
  1604. {
  1605. cancel_work_sync(&ar->register_work);
  1606. if (!test_bit(ATH10K_FLAG_CORE_REGISTERED, &ar->dev_flags))
  1607. return;
  1608. ath10k_thermal_unregister(ar);
  1609. /* Stop spectral before unregistering from mac80211 to remove the
  1610. * relayfs debugfs file cleanly. Otherwise the parent debugfs tree
  1611. * would be already be free'd recursively, leading to a double free.
  1612. */
  1613. ath10k_spectral_destroy(ar);
  1614. /* We must unregister from mac80211 before we stop HTC and HIF.
  1615. * Otherwise we will fail to submit commands to FW and mac80211 will be
  1616. * unhappy about callback failures. */
  1617. ath10k_mac_unregister(ar);
  1618. ath10k_testmode_destroy(ar);
  1619. ath10k_core_free_firmware_files(ar);
  1620. ath10k_core_free_board_files(ar);
  1621. ath10k_debug_unregister(ar);
  1622. }
  1623. EXPORT_SYMBOL(ath10k_core_unregister);
  1624. struct ath10k *ath10k_core_create(size_t priv_size, struct device *dev,
  1625. enum ath10k_bus bus,
  1626. enum ath10k_hw_rev hw_rev,
  1627. const struct ath10k_hif_ops *hif_ops)
  1628. {
  1629. struct ath10k *ar;
  1630. int ret;
  1631. ar = ath10k_mac_create(priv_size);
  1632. if (!ar)
  1633. return NULL;
  1634. ar->ath_common.priv = ar;
  1635. ar->ath_common.hw = ar->hw;
  1636. ar->dev = dev;
  1637. ar->hw_rev = hw_rev;
  1638. ar->hif.ops = hif_ops;
  1639. ar->hif.bus = bus;
  1640. switch (hw_rev) {
  1641. case ATH10K_HW_QCA988X:
  1642. ar->regs = &qca988x_regs;
  1643. ar->hw_values = &qca988x_values;
  1644. break;
  1645. case ATH10K_HW_QCA6174:
  1646. case ATH10K_HW_QCA9377:
  1647. ar->regs = &qca6174_regs;
  1648. ar->hw_values = &qca6174_values;
  1649. break;
  1650. case ATH10K_HW_QCA99X0:
  1651. ar->regs = &qca99x0_regs;
  1652. ar->hw_values = &qca99x0_values;
  1653. break;
  1654. default:
  1655. ath10k_err(ar, "unsupported core hardware revision %d\n",
  1656. hw_rev);
  1657. ret = -ENOTSUPP;
  1658. goto err_free_mac;
  1659. }
  1660. init_completion(&ar->scan.started);
  1661. init_completion(&ar->scan.completed);
  1662. init_completion(&ar->scan.on_channel);
  1663. init_completion(&ar->target_suspend);
  1664. init_completion(&ar->wow.wakeup_completed);
  1665. init_completion(&ar->install_key_done);
  1666. init_completion(&ar->vdev_setup_done);
  1667. init_completion(&ar->thermal.wmi_sync);
  1668. INIT_DELAYED_WORK(&ar->scan.timeout, ath10k_scan_timeout_work);
  1669. ar->workqueue = create_singlethread_workqueue("ath10k_wq");
  1670. if (!ar->workqueue)
  1671. goto err_free_mac;
  1672. ar->workqueue_aux = create_singlethread_workqueue("ath10k_aux_wq");
  1673. if (!ar->workqueue_aux)
  1674. goto err_free_wq;
  1675. mutex_init(&ar->conf_mutex);
  1676. spin_lock_init(&ar->data_lock);
  1677. INIT_LIST_HEAD(&ar->peers);
  1678. init_waitqueue_head(&ar->peer_mapping_wq);
  1679. init_waitqueue_head(&ar->htt.empty_tx_wq);
  1680. init_waitqueue_head(&ar->wmi.tx_credits_wq);
  1681. init_completion(&ar->offchan_tx_completed);
  1682. INIT_WORK(&ar->offchan_tx_work, ath10k_offchan_tx_work);
  1683. skb_queue_head_init(&ar->offchan_tx_queue);
  1684. INIT_WORK(&ar->wmi_mgmt_tx_work, ath10k_mgmt_over_wmi_tx_work);
  1685. skb_queue_head_init(&ar->wmi_mgmt_tx_queue);
  1686. INIT_WORK(&ar->register_work, ath10k_core_register_work);
  1687. INIT_WORK(&ar->restart_work, ath10k_core_restart);
  1688. ret = ath10k_debug_create(ar);
  1689. if (ret)
  1690. goto err_free_aux_wq;
  1691. return ar;
  1692. err_free_aux_wq:
  1693. destroy_workqueue(ar->workqueue_aux);
  1694. err_free_wq:
  1695. destroy_workqueue(ar->workqueue);
  1696. err_free_mac:
  1697. ath10k_mac_destroy(ar);
  1698. return NULL;
  1699. }
  1700. EXPORT_SYMBOL(ath10k_core_create);
  1701. void ath10k_core_destroy(struct ath10k *ar)
  1702. {
  1703. flush_workqueue(ar->workqueue);
  1704. destroy_workqueue(ar->workqueue);
  1705. flush_workqueue(ar->workqueue_aux);
  1706. destroy_workqueue(ar->workqueue_aux);
  1707. ath10k_debug_destroy(ar);
  1708. ath10k_wmi_free_host_mem(ar);
  1709. ath10k_mac_destroy(ar);
  1710. }
  1711. EXPORT_SYMBOL(ath10k_core_destroy);
  1712. MODULE_AUTHOR("Qualcomm Atheros");
  1713. MODULE_DESCRIPTION("Core module for QCA988X PCIe devices.");
  1714. MODULE_LICENSE("Dual BSD/GPL");