hw.c 5.2 KB

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  1. /*
  2. * Copyright (c) 2014-2015 Qualcomm Atheros, Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include "core.h"
  18. #include "hw.h"
  19. const struct ath10k_hw_regs qca988x_regs = {
  20. .rtc_state_cold_reset_mask = 0x00000400,
  21. .rtc_soc_base_address = 0x00004000,
  22. .rtc_wmac_base_address = 0x00005000,
  23. .soc_core_base_address = 0x00009000,
  24. .ce_wrapper_base_address = 0x00057000,
  25. .ce0_base_address = 0x00057400,
  26. .ce1_base_address = 0x00057800,
  27. .ce2_base_address = 0x00057c00,
  28. .ce3_base_address = 0x00058000,
  29. .ce4_base_address = 0x00058400,
  30. .ce5_base_address = 0x00058800,
  31. .ce6_base_address = 0x00058c00,
  32. .ce7_base_address = 0x00059000,
  33. .soc_reset_control_si0_rst_mask = 0x00000001,
  34. .soc_reset_control_ce_rst_mask = 0x00040000,
  35. .soc_chip_id_address = 0x000000ec,
  36. .scratch_3_address = 0x00000030,
  37. .fw_indicator_address = 0x00009030,
  38. .pcie_local_base_address = 0x00080000,
  39. .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
  40. .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
  41. .pcie_intr_fw_mask = 0x00000400,
  42. .pcie_intr_ce_mask_all = 0x0007f800,
  43. .pcie_intr_clr_address = 0x00000014,
  44. };
  45. const struct ath10k_hw_regs qca6174_regs = {
  46. .rtc_state_cold_reset_mask = 0x00002000,
  47. .rtc_soc_base_address = 0x00000800,
  48. .rtc_wmac_base_address = 0x00001000,
  49. .soc_core_base_address = 0x0003a000,
  50. .ce_wrapper_base_address = 0x00034000,
  51. .ce0_base_address = 0x00034400,
  52. .ce1_base_address = 0x00034800,
  53. .ce2_base_address = 0x00034c00,
  54. .ce3_base_address = 0x00035000,
  55. .ce4_base_address = 0x00035400,
  56. .ce5_base_address = 0x00035800,
  57. .ce6_base_address = 0x00035c00,
  58. .ce7_base_address = 0x00036000,
  59. .soc_reset_control_si0_rst_mask = 0x00000000,
  60. .soc_reset_control_ce_rst_mask = 0x00000001,
  61. .soc_chip_id_address = 0x000000f0,
  62. .scratch_3_address = 0x00000028,
  63. .fw_indicator_address = 0x0003a028,
  64. .pcie_local_base_address = 0x00080000,
  65. .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
  66. .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
  67. .pcie_intr_fw_mask = 0x00000400,
  68. .pcie_intr_ce_mask_all = 0x0007f800,
  69. .pcie_intr_clr_address = 0x00000014,
  70. };
  71. const struct ath10k_hw_regs qca99x0_regs = {
  72. .rtc_state_cold_reset_mask = 0x00000400,
  73. .rtc_soc_base_address = 0x00080000,
  74. .rtc_wmac_base_address = 0x00000000,
  75. .soc_core_base_address = 0x00082000,
  76. .ce_wrapper_base_address = 0x0004d000,
  77. .ce0_base_address = 0x0004a000,
  78. .ce1_base_address = 0x0004a400,
  79. .ce2_base_address = 0x0004a800,
  80. .ce3_base_address = 0x0004ac00,
  81. .ce4_base_address = 0x0004b000,
  82. .ce5_base_address = 0x0004b400,
  83. .ce6_base_address = 0x0004b800,
  84. .ce7_base_address = 0x0004bc00,
  85. /* Note: qca99x0 supports upto 12 Copy Engines. Other than address of
  86. * CE0 and CE1 no other copy engine is directly referred in the code.
  87. * It is not really neccessary to assign address for newly supported
  88. * CEs in this address table.
  89. * Copy Engine Address
  90. * CE8 0x0004c000
  91. * CE9 0x0004c400
  92. * CE10 0x0004c800
  93. * CE11 0x0004cc00
  94. */
  95. .soc_reset_control_si0_rst_mask = 0x00000001,
  96. .soc_reset_control_ce_rst_mask = 0x00000100,
  97. .soc_chip_id_address = 0x000000ec,
  98. .scratch_3_address = 0x00040050,
  99. .fw_indicator_address = 0x00040050,
  100. .pcie_local_base_address = 0x00000000,
  101. .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
  102. .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
  103. .pcie_intr_fw_mask = 0x00100000,
  104. .pcie_intr_ce_mask_all = 0x000fff00,
  105. .pcie_intr_clr_address = 0x00000010,
  106. };
  107. const struct ath10k_hw_values qca988x_values = {
  108. .rtc_state_val_on = 3,
  109. .ce_count = 8,
  110. .msi_assign_ce_max = 7,
  111. .num_target_ce_config_wlan = 7,
  112. .ce_desc_meta_data_mask = 0xFFFC,
  113. .ce_desc_meta_data_lsb = 2,
  114. };
  115. const struct ath10k_hw_values qca6174_values = {
  116. .rtc_state_val_on = 3,
  117. .ce_count = 8,
  118. .msi_assign_ce_max = 7,
  119. .num_target_ce_config_wlan = 7,
  120. .ce_desc_meta_data_mask = 0xFFFC,
  121. .ce_desc_meta_data_lsb = 2,
  122. };
  123. const struct ath10k_hw_values qca99x0_values = {
  124. .rtc_state_val_on = 5,
  125. .ce_count = 12,
  126. .msi_assign_ce_max = 12,
  127. .num_target_ce_config_wlan = 10,
  128. .ce_desc_meta_data_mask = 0xFFF0,
  129. .ce_desc_meta_data_lsb = 4,
  130. };
  131. void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
  132. u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev)
  133. {
  134. u32 cc_fix = 0;
  135. survey->filled |= SURVEY_INFO_TIME |
  136. SURVEY_INFO_TIME_BUSY;
  137. if (ar->hw_params.has_shifted_cc_wraparound && cc < cc_prev) {
  138. cc_fix = 0x7fffffff;
  139. survey->filled &= ~SURVEY_INFO_TIME_BUSY;
  140. }
  141. cc -= cc_prev - cc_fix;
  142. rcc -= rcc_prev;
  143. survey->time = CCNT_TO_MSEC(ar, cc);
  144. survey->time_busy = CCNT_TO_MSEC(ar, rcc);
  145. }