ath5k.h 53 KB

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  1. /*
  2. * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifndef _ATH5K_H
  18. #define _ATH5K_H
  19. /* TODO: Clean up channel debugging (doesn't work anyway) and start
  20. * working on reg. control code using all available eeprom information
  21. * (rev. engineering needed) */
  22. #define CHAN_DEBUG 0
  23. #include <linux/io.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/types.h>
  26. #include <linux/average.h>
  27. #include <linux/leds.h>
  28. #include <net/mac80211.h>
  29. #include <net/cfg80211.h>
  30. /* RX/TX descriptor hw structs
  31. * TODO: Driver part should only see sw structs */
  32. #include "desc.h"
  33. /* EEPROM structs/offsets
  34. * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities)
  35. * and clean up common bits, then introduce set/get functions in eeprom.c */
  36. #include "eeprom.h"
  37. #include "debug.h"
  38. #include "../ath.h"
  39. #include "ani.h"
  40. /* PCI IDs */
  41. #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */
  42. #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */
  43. #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */
  44. #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */
  45. #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */
  46. #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */
  47. #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */
  48. #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */
  49. #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */
  50. #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */
  51. #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */
  52. #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */
  53. #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */
  54. #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */
  55. #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
  56. #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
  57. #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */
  58. #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */
  59. #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */
  60. #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */
  61. #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */
  62. #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */
  63. #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */
  64. #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */
  65. #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */
  66. #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */
  67. #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */
  68. #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */
  69. /****************************\
  70. GENERIC DRIVER DEFINITIONS
  71. \****************************/
  72. #define ATH5K_PRINTF(fmt, ...) \
  73. pr_warn("%s: " fmt, __func__, ##__VA_ARGS__)
  74. void __printf(3, 4)
  75. _ath5k_printk(const struct ath5k_hw *ah, const char *level,
  76. const char *fmt, ...);
  77. #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \
  78. _ath5k_printk(_sc, _level, _fmt, ##__VA_ARGS__)
  79. #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) \
  80. do { \
  81. if (net_ratelimit()) \
  82. ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \
  83. } while (0)
  84. #define ATH5K_INFO(_sc, _fmt, ...) \
  85. ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__)
  86. #define ATH5K_WARN(_sc, _fmt, ...) \
  87. ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__)
  88. #define ATH5K_ERR(_sc, _fmt, ...) \
  89. ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__)
  90. /*
  91. * AR5K REGISTER ACCESS
  92. */
  93. /* Some macros to read/write fields */
  94. /* First shift, then mask */
  95. #define AR5K_REG_SM(_val, _flags) \
  96. (((_val) << _flags##_S) & (_flags))
  97. /* First mask, then shift */
  98. #define AR5K_REG_MS(_val, _flags) \
  99. (((_val) & (_flags)) >> _flags##_S)
  100. /* Some registers can hold multiple values of interest. For this
  101. * reason when we want to write to these registers we must first
  102. * retrieve the values which we do not want to clear (lets call this
  103. * old_data) and then set the register with this and our new_value:
  104. * ( old_data | new_value) */
  105. #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
  106. ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
  107. (((_val) << _flags##_S) & (_flags)), _reg)
  108. #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
  109. ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
  110. (_mask)) | (_flags), _reg)
  111. #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
  112. ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
  113. #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
  114. ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
  115. /* Access QCU registers per queue */
  116. #define AR5K_REG_READ_Q(ah, _reg, _queue) \
  117. (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
  118. #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
  119. ath5k_hw_reg_write(ah, (1 << _queue), _reg)
  120. #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
  121. _reg |= 1 << _queue; \
  122. } while (0)
  123. #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
  124. _reg &= ~(1 << _queue); \
  125. } while (0)
  126. /* Used while writing initvals */
  127. #define AR5K_REG_WAIT(_i) do { \
  128. if (_i % 64) \
  129. udelay(1); \
  130. } while (0)
  131. /*
  132. * Some tunable values (these should be changeable by the user)
  133. * TODO: Make use of them and add more options OR use debug/configfs
  134. */
  135. #define AR5K_TUNE_DMA_BEACON_RESP 2
  136. #define AR5K_TUNE_SW_BEACON_RESP 10
  137. #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0
  138. #define AR5K_TUNE_MIN_TX_FIFO_THRES 1
  139. #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1)
  140. #define AR5K_TUNE_REGISTER_TIMEOUT 20000
  141. /* Register for RSSI threshold has a mask of 0xff, so 255 seems to
  142. * be the max value. */
  143. #define AR5K_TUNE_RSSI_THRES 129
  144. /* This must be set when setting the RSSI threshold otherwise it can
  145. * prevent a reset. If AR5K_RSSI_THR is read after writing to it
  146. * the BMISS_THRES will be seen as 0, seems hardware doesn't keep
  147. * track of it. Max value depends on hardware. For AR5210 this is just 7.
  148. * For AR5211+ this seems to be up to 255. */
  149. #define AR5K_TUNE_BMISS_THRES 7
  150. #define AR5K_TUNE_REGISTER_DWELL_TIME 20000
  151. #define AR5K_TUNE_BEACON_INTERVAL 100
  152. #define AR5K_TUNE_AIFS 2
  153. #define AR5K_TUNE_AIFS_11B 2
  154. #define AR5K_TUNE_AIFS_XR 0
  155. #define AR5K_TUNE_CWMIN 15
  156. #define AR5K_TUNE_CWMIN_11B 31
  157. #define AR5K_TUNE_CWMIN_XR 3
  158. #define AR5K_TUNE_CWMAX 1023
  159. #define AR5K_TUNE_CWMAX_11B 1023
  160. #define AR5K_TUNE_CWMAX_XR 7
  161. #define AR5K_TUNE_NOISE_FLOOR -72
  162. #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95
  163. #define AR5K_TUNE_MAX_TXPOWER 63
  164. #define AR5K_TUNE_DEFAULT_TXPOWER 25
  165. #define AR5K_TUNE_TPC_TXPOWER false
  166. #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 60000 /* 60 sec */
  167. #define ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT 10000 /* 10 sec */
  168. #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */
  169. #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */
  170. #define AR5K_INIT_CARR_SENSE_EN 1
  171. /*Swap RX/TX Descriptor for big endian archs*/
  172. #if defined(__BIG_ENDIAN)
  173. #define AR5K_INIT_CFG ( \
  174. AR5K_CFG_SWTD | AR5K_CFG_SWRD \
  175. )
  176. #else
  177. #define AR5K_INIT_CFG 0x00000000
  178. #endif
  179. /* Initial values */
  180. #define AR5K_INIT_CYCRSSI_THR1 2
  181. /* Tx retry limit defaults from standard */
  182. #define AR5K_INIT_RETRY_SHORT 7
  183. #define AR5K_INIT_RETRY_LONG 4
  184. /* Slot time */
  185. #define AR5K_INIT_SLOT_TIME_TURBO 6
  186. #define AR5K_INIT_SLOT_TIME_DEFAULT 9
  187. #define AR5K_INIT_SLOT_TIME_HALF_RATE 13
  188. #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21
  189. #define AR5K_INIT_SLOT_TIME_B 20
  190. #define AR5K_SLOT_TIME_MAX 0xffff
  191. /* SIFS */
  192. #define AR5K_INIT_SIFS_TURBO 6
  193. #define AR5K_INIT_SIFS_DEFAULT_BG 10
  194. #define AR5K_INIT_SIFS_DEFAULT_A 16
  195. #define AR5K_INIT_SIFS_HALF_RATE 32
  196. #define AR5K_INIT_SIFS_QUARTER_RATE 64
  197. /* Used to calculate tx time for non 5/10/40MHz
  198. * operation */
  199. /* It's preamble time + signal time (16 + 4) */
  200. #define AR5K_INIT_OFDM_PREAMPLE_TIME 20
  201. /* Preamble time for 40MHz (turbo) operation (min ?) */
  202. #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14
  203. #define AR5K_INIT_OFDM_SYMBOL_TIME 4
  204. #define AR5K_INIT_OFDM_PLCP_BITS 22
  205. /* Rx latency for 5 and 10MHz operation (max ?) */
  206. #define AR5K_INIT_RX_LAT_MAX 63
  207. /* Tx latencies from initvals (5212 only but no problem
  208. * because we only tweak them on 5212) */
  209. #define AR5K_INIT_TX_LAT_A 54
  210. #define AR5K_INIT_TX_LAT_BG 384
  211. /* Tx latency for 40MHz (turbo) operation (min ?) */
  212. #define AR5K_INIT_TX_LAT_MIN 32
  213. /* Default Tx/Rx latencies (same for 5211)*/
  214. #define AR5K_INIT_TX_LATENCY_5210 54
  215. #define AR5K_INIT_RX_LATENCY_5210 29
  216. /* Tx frame to Tx data start delay */
  217. #define AR5K_INIT_TXF2TXD_START_DEFAULT 14
  218. #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12
  219. #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13
  220. /* We need to increase PHY switch and agc settling time
  221. * on turbo mode */
  222. #define AR5K_SWITCH_SETTLING 5760
  223. #define AR5K_SWITCH_SETTLING_TURBO 7168
  224. #define AR5K_AGC_SETTLING 28
  225. /* 38 on 5210 but shouldn't matter */
  226. #define AR5K_AGC_SETTLING_TURBO 37
  227. /*****************************\
  228. * GENERIC CHIPSET DEFINITIONS *
  229. \*****************************/
  230. /**
  231. * enum ath5k_version - MAC Chips
  232. * @AR5K_AR5210: AR5210 (Crete)
  233. * @AR5K_AR5211: AR5211 (Oahu/Maui)
  234. * @AR5K_AR5212: AR5212 (Venice) and newer
  235. */
  236. enum ath5k_version {
  237. AR5K_AR5210 = 0,
  238. AR5K_AR5211 = 1,
  239. AR5K_AR5212 = 2,
  240. };
  241. /**
  242. * enum ath5k_radio - PHY Chips
  243. * @AR5K_RF5110: RF5110 (Fez)
  244. * @AR5K_RF5111: RF5111 (Sombrero)
  245. * @AR5K_RF5112: RF2112/5112(A) (Derby/Derby2)
  246. * @AR5K_RF2413: RF2413/2414 (Griffin/Griffin-Lite)
  247. * @AR5K_RF5413: RF5413/5414/5424 (Eagle/Condor)
  248. * @AR5K_RF2316: RF2315/2316 (Cobra SoC)
  249. * @AR5K_RF2317: RF2317 (Spider SoC)
  250. * @AR5K_RF2425: RF2425/2417 (Swan/Nalla)
  251. */
  252. enum ath5k_radio {
  253. AR5K_RF5110 = 0,
  254. AR5K_RF5111 = 1,
  255. AR5K_RF5112 = 2,
  256. AR5K_RF2413 = 3,
  257. AR5K_RF5413 = 4,
  258. AR5K_RF2316 = 5,
  259. AR5K_RF2317 = 6,
  260. AR5K_RF2425 = 7,
  261. };
  262. /*
  263. * Common silicon revision/version values
  264. */
  265. #define AR5K_SREV_UNKNOWN 0xffff
  266. #define AR5K_SREV_AR5210 0x00 /* Crete */
  267. #define AR5K_SREV_AR5311 0x10 /* Maui 1 */
  268. #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */
  269. #define AR5K_SREV_AR5311B 0x30 /* Spirit */
  270. #define AR5K_SREV_AR5211 0x40 /* Oahu */
  271. #define AR5K_SREV_AR5212 0x50 /* Venice */
  272. #define AR5K_SREV_AR5312_R2 0x52 /* AP31 */
  273. #define AR5K_SREV_AR5212_V4 0x54 /* ??? */
  274. #define AR5K_SREV_AR5213 0x55 /* ??? */
  275. #define AR5K_SREV_AR5312_R7 0x57 /* AP30 */
  276. #define AR5K_SREV_AR2313_R8 0x58 /* AP43 */
  277. #define AR5K_SREV_AR5213A 0x59 /* Hainan */
  278. #define AR5K_SREV_AR2413 0x78 /* Griffin lite */
  279. #define AR5K_SREV_AR2414 0x70 /* Griffin */
  280. #define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */
  281. #define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */
  282. #define AR5K_SREV_AR5424 0x90 /* Condor */
  283. #define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */
  284. #define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */
  285. #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */
  286. #define AR5K_SREV_AR5414 0xa0 /* Eagle */
  287. #define AR5K_SREV_AR2415 0xb0 /* Talon */
  288. #define AR5K_SREV_AR5416 0xc0 /* PCI-E */
  289. #define AR5K_SREV_AR5418 0xca /* PCI-E */
  290. #define AR5K_SREV_AR2425 0xe0 /* Swan */
  291. #define AR5K_SREV_AR2417 0xf0 /* Nala */
  292. #define AR5K_SREV_RAD_5110 0x00
  293. #define AR5K_SREV_RAD_5111 0x10
  294. #define AR5K_SREV_RAD_5111A 0x15
  295. #define AR5K_SREV_RAD_2111 0x20
  296. #define AR5K_SREV_RAD_5112 0x30
  297. #define AR5K_SREV_RAD_5112A 0x35
  298. #define AR5K_SREV_RAD_5112B 0x36
  299. #define AR5K_SREV_RAD_2112 0x40
  300. #define AR5K_SREV_RAD_2112A 0x45
  301. #define AR5K_SREV_RAD_2112B 0x46
  302. #define AR5K_SREV_RAD_2413 0x50
  303. #define AR5K_SREV_RAD_5413 0x60
  304. #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */
  305. #define AR5K_SREV_RAD_2317 0x80
  306. #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */
  307. #define AR5K_SREV_RAD_2425 0xa2
  308. #define AR5K_SREV_RAD_5133 0xc0
  309. #define AR5K_SREV_PHY_5211 0x30
  310. #define AR5K_SREV_PHY_5212 0x41
  311. #define AR5K_SREV_PHY_5212A 0x42
  312. #define AR5K_SREV_PHY_5212B 0x43
  313. #define AR5K_SREV_PHY_2413 0x45
  314. #define AR5K_SREV_PHY_5413 0x61
  315. #define AR5K_SREV_PHY_2425 0x70
  316. /* TODO add support to mac80211 for vendor-specific rates and modes */
  317. /**
  318. * DOC: Atheros XR
  319. *
  320. * Some of this information is based on Documentation from:
  321. *
  322. * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG
  323. *
  324. * Atheros' eXtended Range - range enhancing extension is a modulation scheme
  325. * that is supposed to double the link distance between an Atheros XR-enabled
  326. * client device with an Atheros XR-enabled access point. This is achieved
  327. * by increasing the receiver sensitivity up to, -105dBm, which is about 20dB
  328. * above what the 802.11 specifications demand. In addition, new (proprietary)
  329. * data rates are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
  330. *
  331. * Please note that can you either use XR or TURBO but you cannot use both,
  332. * they are exclusive.
  333. *
  334. * Also note that we do not plan to support XR mode at least for now. You can
  335. * get a mode similar to XR by using 5MHz bwmode.
  336. */
  337. /**
  338. * DOC: Atheros SuperAG
  339. *
  340. * In addition to XR we have another modulation scheme called TURBO mode
  341. * that is supposed to provide a throughput transmission speed up to 40Mbit/s
  342. * -60Mbit/s at a 108Mbit/s signaling rate achieved through the bonding of two
  343. * 54Mbit/s 802.11g channels. To use this feature both ends must support it.
  344. * There is also a distinction between "static" and "dynamic" turbo modes:
  345. *
  346. * - Static: is the dumb version: devices set to this mode stick to it until
  347. * the mode is turned off.
  348. *
  349. * - Dynamic: is the intelligent version, the network decides itself if it
  350. * is ok to use turbo. As soon as traffic is detected on adjacent channels
  351. * (which would get used in turbo mode), or when a non-turbo station joins
  352. * the network, turbo mode won't be used until the situation changes again.
  353. * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
  354. * monitors the used radio band in order to decide whether turbo mode may
  355. * be used or not.
  356. *
  357. * This article claims Super G sticks to bonding of channels 5 and 6 for
  358. * USA:
  359. *
  360. * http://www.pcworld.com/article/id,113428-page,1/article.html
  361. *
  362. * The channel bonding seems to be driver specific though.
  363. *
  364. * In addition to TURBO modes we also have the following features for even
  365. * greater speed-up:
  366. *
  367. * - Bursting: allows multiple frames to be sent at once, rather than pausing
  368. * after each frame. Bursting is a standards-compliant feature that can be
  369. * used with any Access Point.
  370. *
  371. * - Fast frames: increases the amount of information that can be sent per
  372. * frame, also resulting in a reduction of transmission overhead. It is a
  373. * proprietary feature that needs to be supported by the Access Point.
  374. *
  375. * - Compression: data frames are compressed in real time using a Lempel Ziv
  376. * algorithm. This is done transparently. Once this feature is enabled,
  377. * compression and decompression takes place inside the chipset, without
  378. * putting additional load on the host CPU.
  379. *
  380. * As with XR we also don't plan to support SuperAG features for now. You can
  381. * get a mode similar to TURBO by using 40MHz bwmode.
  382. */
  383. /**
  384. * enum ath5k_driver_mode - PHY operation mode
  385. * @AR5K_MODE_11A: 802.11a
  386. * @AR5K_MODE_11B: 802.11b
  387. * @AR5K_MODE_11G: 801.11g
  388. * @AR5K_MODE_MAX: Used for boundary checks
  389. *
  390. * Do not change the order here, we use these as
  391. * array indices and it also maps EEPROM structures.
  392. */
  393. enum ath5k_driver_mode {
  394. AR5K_MODE_11A = 0,
  395. AR5K_MODE_11B = 1,
  396. AR5K_MODE_11G = 2,
  397. AR5K_MODE_MAX = 3
  398. };
  399. /**
  400. * enum ath5k_ant_mode - Antenna operation mode
  401. * @AR5K_ANTMODE_DEFAULT: Default antenna setup
  402. * @AR5K_ANTMODE_FIXED_A: Only antenna A is present
  403. * @AR5K_ANTMODE_FIXED_B: Only antenna B is present
  404. * @AR5K_ANTMODE_SINGLE_AP: STA locked on a single ap
  405. * @AR5K_ANTMODE_SECTOR_AP: AP with tx antenna set on tx desc
  406. * @AR5K_ANTMODE_SECTOR_STA: STA with tx antenna set on tx desc
  407. * @AR5K_ANTMODE_DEBUG: Debug mode -A -> Rx, B-> Tx-
  408. * @AR5K_ANTMODE_MAX: Used for boundary checks
  409. *
  410. * For more infos on antenna control check out phy.c
  411. */
  412. enum ath5k_ant_mode {
  413. AR5K_ANTMODE_DEFAULT = 0,
  414. AR5K_ANTMODE_FIXED_A = 1,
  415. AR5K_ANTMODE_FIXED_B = 2,
  416. AR5K_ANTMODE_SINGLE_AP = 3,
  417. AR5K_ANTMODE_SECTOR_AP = 4,
  418. AR5K_ANTMODE_SECTOR_STA = 5,
  419. AR5K_ANTMODE_DEBUG = 6,
  420. AR5K_ANTMODE_MAX,
  421. };
  422. /**
  423. * enum ath5k_bw_mode - Bandwidth operation mode
  424. * @AR5K_BWMODE_DEFAULT: 20MHz, default operation
  425. * @AR5K_BWMODE_5MHZ: Quarter rate
  426. * @AR5K_BWMODE_10MHZ: Half rate
  427. * @AR5K_BWMODE_40MHZ: Turbo
  428. */
  429. enum ath5k_bw_mode {
  430. AR5K_BWMODE_DEFAULT = 0,
  431. AR5K_BWMODE_5MHZ = 1,
  432. AR5K_BWMODE_10MHZ = 2,
  433. AR5K_BWMODE_40MHZ = 3
  434. };
  435. /****************\
  436. TX DEFINITIONS
  437. \****************/
  438. /**
  439. * struct ath5k_tx_status - TX Status descriptor
  440. * @ts_seqnum: Sequence number
  441. * @ts_tstamp: Timestamp
  442. * @ts_status: Status code
  443. * @ts_final_idx: Final transmission series index
  444. * @ts_final_retry: Final retry count
  445. * @ts_rssi: RSSI for received ACK
  446. * @ts_shortretry: Short retry count
  447. * @ts_virtcol: Virtual collision count
  448. * @ts_antenna: Antenna used
  449. *
  450. * TX status descriptor gets filled by the hw
  451. * on each transmission attempt.
  452. */
  453. struct ath5k_tx_status {
  454. u16 ts_seqnum;
  455. u16 ts_tstamp;
  456. u8 ts_status;
  457. u8 ts_final_idx;
  458. u8 ts_final_retry;
  459. s8 ts_rssi;
  460. u8 ts_shortretry;
  461. u8 ts_virtcol;
  462. u8 ts_antenna;
  463. };
  464. #define AR5K_TXSTAT_ALTRATE 0x80
  465. #define AR5K_TXERR_XRETRY 0x01
  466. #define AR5K_TXERR_FILT 0x02
  467. #define AR5K_TXERR_FIFO 0x04
  468. /**
  469. * enum ath5k_tx_queue - Queue types used to classify tx queues.
  470. * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
  471. * @AR5K_TX_QUEUE_DATA: A normal data queue
  472. * @AR5K_TX_QUEUE_BEACON: The beacon queue
  473. * @AR5K_TX_QUEUE_CAB: The after-beacon queue
  474. * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
  475. */
  476. enum ath5k_tx_queue {
  477. AR5K_TX_QUEUE_INACTIVE = 0,
  478. AR5K_TX_QUEUE_DATA,
  479. AR5K_TX_QUEUE_BEACON,
  480. AR5K_TX_QUEUE_CAB,
  481. AR5K_TX_QUEUE_UAPSD,
  482. };
  483. #define AR5K_NUM_TX_QUEUES 10
  484. #define AR5K_NUM_TX_QUEUES_NOQCU 2
  485. /**
  486. * enum ath5k_tx_queue_subtype - Queue sub-types to classify normal data queues
  487. * @AR5K_WME_AC_BK: Background traffic
  488. * @AR5K_WME_AC_BE: Best-effort (normal) traffic
  489. * @AR5K_WME_AC_VI: Video traffic
  490. * @AR5K_WME_AC_VO: Voice traffic
  491. *
  492. * These are the 4 Access Categories as defined in
  493. * WME spec. 0 is the lowest priority and 4 is the
  494. * highest. Normal data that hasn't been classified
  495. * goes to the Best Effort AC.
  496. */
  497. enum ath5k_tx_queue_subtype {
  498. AR5K_WME_AC_BK = 0,
  499. AR5K_WME_AC_BE,
  500. AR5K_WME_AC_VI,
  501. AR5K_WME_AC_VO,
  502. };
  503. /**
  504. * enum ath5k_tx_queue_id - Queue ID numbers as returned by the hw functions
  505. * @AR5K_TX_QUEUE_ID_NOQCU_DATA: Data queue on AR5210 (no QCU available)
  506. * @AR5K_TX_QUEUE_ID_NOQCU_BEACON: Beacon queue on AR5210 (no QCU available)
  507. * @AR5K_TX_QUEUE_ID_DATA_MIN: Data queue min index
  508. * @AR5K_TX_QUEUE_ID_DATA_MAX: Data queue max index
  509. * @AR5K_TX_QUEUE_ID_CAB: Content after beacon queue
  510. * @AR5K_TX_QUEUE_ID_BEACON: Beacon queue
  511. * @AR5K_TX_QUEUE_ID_UAPSD: Urgent Automatic Power Save Delivery,
  512. *
  513. * Each number represents a hw queue. If hw does not support hw queues
  514. * (eg 5210) all data goes in one queue.
  515. */
  516. enum ath5k_tx_queue_id {
  517. AR5K_TX_QUEUE_ID_NOQCU_DATA = 0,
  518. AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1,
  519. AR5K_TX_QUEUE_ID_DATA_MIN = 0,
  520. AR5K_TX_QUEUE_ID_DATA_MAX = 3,
  521. AR5K_TX_QUEUE_ID_UAPSD = 7,
  522. AR5K_TX_QUEUE_ID_CAB = 8,
  523. AR5K_TX_QUEUE_ID_BEACON = 9,
  524. };
  525. /*
  526. * Flags to set hw queue's parameters...
  527. */
  528. #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */
  529. #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */
  530. #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */
  531. #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */
  532. #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */
  533. #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */
  534. #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */
  535. #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */
  536. #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */
  537. #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */
  538. #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/
  539. #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */
  540. #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */
  541. #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/
  542. /**
  543. * struct ath5k_txq - Transmit queue state
  544. * @qnum: Hardware q number
  545. * @link: Link ptr in last TX desc
  546. * @q: Transmit queue (&struct list_head)
  547. * @lock: Lock on q and link
  548. * @setup: Is the queue configured
  549. * @txq_len:Number of queued buffers
  550. * @txq_max: Max allowed num of queued buffers
  551. * @txq_poll_mark: Used to check if queue got stuck
  552. * @txq_stuck: Queue stuck counter
  553. *
  554. * One of these exists for each hardware transmit queue.
  555. * Packets sent to us from above are assigned to queues based
  556. * on their priority. Not all devices support a complete set
  557. * of hardware transmit queues. For those devices the array
  558. * sc_ac2q will map multiple priorities to fewer hardware queues
  559. * (typically all to one hardware queue).
  560. */
  561. struct ath5k_txq {
  562. unsigned int qnum;
  563. u32 *link;
  564. struct list_head q;
  565. spinlock_t lock;
  566. bool setup;
  567. int txq_len;
  568. int txq_max;
  569. bool txq_poll_mark;
  570. unsigned int txq_stuck;
  571. };
  572. /**
  573. * struct ath5k_txq_info - A struct to hold TX queue's parameters
  574. * @tqi_type: One of enum ath5k_tx_queue
  575. * @tqi_subtype: One of enum ath5k_tx_queue_subtype
  576. * @tqi_flags: TX queue flags (see above)
  577. * @tqi_aifs: Arbitrated Inter-frame Space
  578. * @tqi_cw_min: Minimum Contention Window
  579. * @tqi_cw_max: Maximum Contention Window
  580. * @tqi_cbr_period: Constant bit rate period
  581. * @tqi_ready_time: Time queue waits after an event when RDYTIME is enabled
  582. */
  583. struct ath5k_txq_info {
  584. enum ath5k_tx_queue tqi_type;
  585. enum ath5k_tx_queue_subtype tqi_subtype;
  586. u16 tqi_flags;
  587. u8 tqi_aifs;
  588. u16 tqi_cw_min;
  589. u16 tqi_cw_max;
  590. u32 tqi_cbr_period;
  591. u32 tqi_cbr_overflow_limit;
  592. u32 tqi_burst_time;
  593. u32 tqi_ready_time;
  594. };
  595. /**
  596. * enum ath5k_pkt_type - Transmit packet types
  597. * @AR5K_PKT_TYPE_NORMAL: Normal data
  598. * @AR5K_PKT_TYPE_ATIM: ATIM
  599. * @AR5K_PKT_TYPE_PSPOLL: PS-Poll
  600. * @AR5K_PKT_TYPE_BEACON: Beacon
  601. * @AR5K_PKT_TYPE_PROBE_RESP: Probe response
  602. * @AR5K_PKT_TYPE_PIFS: PIFS
  603. * Used on tx control descriptor
  604. */
  605. enum ath5k_pkt_type {
  606. AR5K_PKT_TYPE_NORMAL = 0,
  607. AR5K_PKT_TYPE_ATIM = 1,
  608. AR5K_PKT_TYPE_PSPOLL = 2,
  609. AR5K_PKT_TYPE_BEACON = 3,
  610. AR5K_PKT_TYPE_PROBE_RESP = 4,
  611. AR5K_PKT_TYPE_PIFS = 5,
  612. };
  613. /*
  614. * TX power and TPC settings
  615. */
  616. #define AR5K_TXPOWER_OFDM(_r, _v) ( \
  617. ((0 & 1) << ((_v) + 6)) | \
  618. (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
  619. )
  620. #define AR5K_TXPOWER_CCK(_r, _v) ( \
  621. (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \
  622. )
  623. /****************\
  624. RX DEFINITIONS
  625. \****************/
  626. /**
  627. * struct ath5k_rx_status - RX Status descriptor
  628. * @rs_datalen: Data length
  629. * @rs_tstamp: Timestamp
  630. * @rs_status: Status code
  631. * @rs_phyerr: PHY error mask
  632. * @rs_rssi: RSSI in 0.5dbm units
  633. * @rs_keyix: Index to the key used for decrypting
  634. * @rs_rate: Rate used to decode the frame
  635. * @rs_antenna: Antenna used to receive the frame
  636. * @rs_more: Indicates this is a frame fragment (Fast frames)
  637. */
  638. struct ath5k_rx_status {
  639. u16 rs_datalen;
  640. u16 rs_tstamp;
  641. u8 rs_status;
  642. u8 rs_phyerr;
  643. s8 rs_rssi;
  644. u8 rs_keyix;
  645. u8 rs_rate;
  646. u8 rs_antenna;
  647. u8 rs_more;
  648. };
  649. #define AR5K_RXERR_CRC 0x01
  650. #define AR5K_RXERR_PHY 0x02
  651. #define AR5K_RXERR_FIFO 0x04
  652. #define AR5K_RXERR_DECRYPT 0x08
  653. #define AR5K_RXERR_MIC 0x10
  654. #define AR5K_RXKEYIX_INVALID ((u8) -1)
  655. #define AR5K_TXKEYIX_INVALID ((u32) -1)
  656. /**************************\
  657. BEACON TIMERS DEFINITIONS
  658. \**************************/
  659. #define AR5K_BEACON_PERIOD 0x0000ffff
  660. #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/
  661. #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/
  662. /*
  663. * TSF to TU conversion:
  664. *
  665. * TSF is a 64bit value in usec (microseconds).
  666. * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
  667. * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
  668. */
  669. #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
  670. /*******************************\
  671. GAIN OPTIMIZATION DEFINITIONS
  672. \*******************************/
  673. /**
  674. * enum ath5k_rfgain - RF Gain optimization engine state
  675. * @AR5K_RFGAIN_INACTIVE: Engine disabled
  676. * @AR5K_RFGAIN_ACTIVE: Probe active
  677. * @AR5K_RFGAIN_READ_REQUESTED: Probe requested
  678. * @AR5K_RFGAIN_NEED_CHANGE: Gain_F needs change
  679. */
  680. enum ath5k_rfgain {
  681. AR5K_RFGAIN_INACTIVE = 0,
  682. AR5K_RFGAIN_ACTIVE,
  683. AR5K_RFGAIN_READ_REQUESTED,
  684. AR5K_RFGAIN_NEED_CHANGE,
  685. };
  686. /**
  687. * struct ath5k_gain - RF Gain optimization engine state data
  688. * @g_step_idx: Current step index
  689. * @g_current: Current gain
  690. * @g_target: Target gain
  691. * @g_low: Low gain boundary
  692. * @g_high: High gain boundary
  693. * @g_f_corr: Gain_F correction
  694. * @g_state: One of enum ath5k_rfgain
  695. */
  696. struct ath5k_gain {
  697. u8 g_step_idx;
  698. u8 g_current;
  699. u8 g_target;
  700. u8 g_low;
  701. u8 g_high;
  702. u8 g_f_corr;
  703. u8 g_state;
  704. };
  705. /********************\
  706. COMMON DEFINITIONS
  707. \********************/
  708. #define AR5K_SLOT_TIME_9 396
  709. #define AR5K_SLOT_TIME_20 880
  710. #define AR5K_SLOT_TIME_MAX 0xffff
  711. /**
  712. * struct ath5k_athchan_2ghz - 2GHz to 5GHZ map for RF5111
  713. * @a2_flags: Channel flags (internal)
  714. * @a2_athchan: HW channel number (internal)
  715. *
  716. * This structure is used to map 2GHz channels to
  717. * 5GHz Atheros channels on 2111 frequency converter
  718. * that comes together with RF5111
  719. * TODO: Clean up
  720. */
  721. struct ath5k_athchan_2ghz {
  722. u32 a2_flags;
  723. u16 a2_athchan;
  724. };
  725. /**
  726. * enum ath5k_dmasize - DMA size definitions (2^(n+2))
  727. * @AR5K_DMASIZE_4B: 4Bytes
  728. * @AR5K_DMASIZE_8B: 8Bytes
  729. * @AR5K_DMASIZE_16B: 16Bytes
  730. * @AR5K_DMASIZE_32B: 32Bytes
  731. * @AR5K_DMASIZE_64B: 64Bytes (Default)
  732. * @AR5K_DMASIZE_128B: 128Bytes
  733. * @AR5K_DMASIZE_256B: 256Bytes
  734. * @AR5K_DMASIZE_512B: 512Bytes
  735. *
  736. * These are used to set DMA burst size on hw
  737. *
  738. * Note: Some platforms can't handle more than 4Bytes
  739. * be careful on embedded boards.
  740. */
  741. enum ath5k_dmasize {
  742. AR5K_DMASIZE_4B = 0,
  743. AR5K_DMASIZE_8B,
  744. AR5K_DMASIZE_16B,
  745. AR5K_DMASIZE_32B,
  746. AR5K_DMASIZE_64B,
  747. AR5K_DMASIZE_128B,
  748. AR5K_DMASIZE_256B,
  749. AR5K_DMASIZE_512B
  750. };
  751. /******************\
  752. RATE DEFINITIONS
  753. \******************/
  754. /**
  755. * DOC: Rate codes
  756. *
  757. * Seems the ar5xxx hardware supports up to 32 rates, indexed by 1-32.
  758. *
  759. * The rate code is used to get the RX rate or set the TX rate on the
  760. * hardware descriptors. It is also used for internal modulation control
  761. * and settings.
  762. *
  763. * This is the hardware rate map we are aware of (html unfriendly):
  764. *
  765. * Rate code Rate (Kbps)
  766. * --------- -----------
  767. * 0x01 3000 (XR)
  768. * 0x02 1000 (XR)
  769. * 0x03 250 (XR)
  770. * 0x04 - 05 -Reserved-
  771. * 0x06 2000 (XR)
  772. * 0x07 500 (XR)
  773. * 0x08 48000 (OFDM)
  774. * 0x09 24000 (OFDM)
  775. * 0x0A 12000 (OFDM)
  776. * 0x0B 6000 (OFDM)
  777. * 0x0C 54000 (OFDM)
  778. * 0x0D 36000 (OFDM)
  779. * 0x0E 18000 (OFDM)
  780. * 0x0F 9000 (OFDM)
  781. * 0x10 - 17 -Reserved-
  782. * 0x18 11000L (CCK)
  783. * 0x19 5500L (CCK)
  784. * 0x1A 2000L (CCK)
  785. * 0x1B 1000L (CCK)
  786. * 0x1C 11000S (CCK)
  787. * 0x1D 5500S (CCK)
  788. * 0x1E 2000S (CCK)
  789. * 0x1F -Reserved-
  790. *
  791. * "S" indicates CCK rates with short preamble and "L" with long preamble.
  792. *
  793. * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
  794. * lowest 4 bits, so they are the same as above with a 0xF mask.
  795. * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
  796. * We handle this in ath5k_setup_bands().
  797. */
  798. #define AR5K_MAX_RATES 32
  799. /* B */
  800. #define ATH5K_RATE_CODE_1M 0x1B
  801. #define ATH5K_RATE_CODE_2M 0x1A
  802. #define ATH5K_RATE_CODE_5_5M 0x19
  803. #define ATH5K_RATE_CODE_11M 0x18
  804. /* A and G */
  805. #define ATH5K_RATE_CODE_6M 0x0B
  806. #define ATH5K_RATE_CODE_9M 0x0F
  807. #define ATH5K_RATE_CODE_12M 0x0A
  808. #define ATH5K_RATE_CODE_18M 0x0E
  809. #define ATH5K_RATE_CODE_24M 0x09
  810. #define ATH5K_RATE_CODE_36M 0x0D
  811. #define ATH5K_RATE_CODE_48M 0x08
  812. #define ATH5K_RATE_CODE_54M 0x0C
  813. /* Adding this flag to rate_code on B rates
  814. * enables short preamble */
  815. #define AR5K_SET_SHORT_PREAMBLE 0x04
  816. /*
  817. * Crypto definitions
  818. */
  819. #define AR5K_KEYCACHE_SIZE 8
  820. extern bool ath5k_modparam_nohwcrypt;
  821. /***********************\
  822. HW RELATED DEFINITIONS
  823. \***********************/
  824. /*
  825. * Misc definitions
  826. */
  827. #define AR5K_RSSI_EP_MULTIPLIER (1 << 7)
  828. #define AR5K_ASSERT_ENTRY(_e, _s) do { \
  829. if (_e >= _s) \
  830. return false; \
  831. } while (0)
  832. /*
  833. * Hardware interrupt abstraction
  834. */
  835. /**
  836. * enum ath5k_int - Hardware interrupt masks helpers
  837. * @AR5K_INT_RXOK: Frame successfully received
  838. * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor
  839. * @AR5K_INT_RXERR: Frame reception failed
  840. * @AR5K_INT_RXNOFRM: No frame received within a specified time period
  841. * @AR5K_INT_RXEOL: Reached "End Of List", means we need more RX descriptors
  842. * @AR5K_INT_RXORN: Indicates we got RX FIFO overrun. Note that Rx overrun is
  843. * not always fatal, on some chips we can continue operation
  844. * without resetting the card, that's why %AR5K_INT_FATAL is not
  845. * common for all chips.
  846. * @AR5K_INT_RX_ALL: Mask to identify all RX related interrupts
  847. *
  848. * @AR5K_INT_TXOK: Frame transmission success
  849. * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor
  850. * @AR5K_INT_TXERR: Frame transmission failure
  851. * @AR5K_INT_TXEOL: Received End Of List for VEOL (Virtual End Of List). The
  852. * Queue Control Unit (QCU) signals an EOL interrupt only if a
  853. * descriptor's LinkPtr is NULL. For more details, refer to:
  854. * "http://www.freepatentsonline.com/20030225739.html"
  855. * @AR5K_INT_TXNOFRM: No frame was transmitted within a specified time period
  856. * @AR5K_INT_TXURN: Indicates we got TX FIFO underrun. In such case we should
  857. * increase the TX trigger threshold.
  858. * @AR5K_INT_TX_ALL: Mask to identify all TX related interrupts
  859. *
  860. * @AR5K_INT_MIB: Indicates the either Management Information Base counters or
  861. * one of the PHY error counters reached the maximum value and
  862. * should be read and cleared.
  863. * @AR5K_INT_SWI: Software triggered interrupt.
  864. * @AR5K_INT_RXPHY: RX PHY Error
  865. * @AR5K_INT_RXKCM: RX Key cache miss
  866. * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
  867. * beacon that must be handled in software. The alternative is if
  868. * you have VEOL support, in that case you let the hardware deal
  869. * with things.
  870. * @AR5K_INT_BRSSI: Beacon received with an RSSI value below our threshold
  871. * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
  872. * beacons from the AP have associated with, we should probably
  873. * try to reassociate. When in IBSS mode this might mean we have
  874. * not received any beacons from any local stations. Note that
  875. * every station in an IBSS schedules to send beacons at the
  876. * Target Beacon Transmission Time (TBTT) with a random backoff.
  877. * @AR5K_INT_BNR: Beacon queue got triggered (DMA beacon alert) while empty.
  878. * @AR5K_INT_TIM: Beacon with local station's TIM bit set
  879. * @AR5K_INT_DTIM: Beacon with DTIM bit and zero DTIM count received
  880. * @AR5K_INT_DTIM_SYNC: DTIM sync lost
  881. * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill switches connected to
  882. * our GPIO pins.
  883. * @AR5K_INT_BCN_TIMEOUT: Beacon timeout, we waited after TBTT but got noting
  884. * @AR5K_INT_CAB_TIMEOUT: We waited for CAB traffic after the beacon but got
  885. * nothing or an incomplete CAB frame sequence.
  886. * @AR5K_INT_QCBRORN: A queue got it's CBR counter expired
  887. * @AR5K_INT_QCBRURN: A queue got triggered wile empty
  888. * @AR5K_INT_QTRIG: A queue got triggered
  889. *
  890. * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by bus/DMA
  891. * errors. Indicates we need to reset the card.
  892. * @AR5K_INT_GLOBAL: Used to clear and set the IER
  893. * @AR5K_INT_NOCARD: Signals the card has been removed
  894. * @AR5K_INT_COMMON: Common interrupts shared among MACs with the same
  895. * bit value
  896. *
  897. * These are mapped to take advantage of some common bits
  898. * between the MACs, to be able to set intr properties
  899. * easier. Some of them are not used yet inside hw.c. Most map
  900. * to the respective hw interrupt value as they are common among different
  901. * MACs.
  902. */
  903. enum ath5k_int {
  904. AR5K_INT_RXOK = 0x00000001,
  905. AR5K_INT_RXDESC = 0x00000002,
  906. AR5K_INT_RXERR = 0x00000004,
  907. AR5K_INT_RXNOFRM = 0x00000008,
  908. AR5K_INT_RXEOL = 0x00000010,
  909. AR5K_INT_RXORN = 0x00000020,
  910. AR5K_INT_TXOK = 0x00000040,
  911. AR5K_INT_TXDESC = 0x00000080,
  912. AR5K_INT_TXERR = 0x00000100,
  913. AR5K_INT_TXNOFRM = 0x00000200,
  914. AR5K_INT_TXEOL = 0x00000400,
  915. AR5K_INT_TXURN = 0x00000800,
  916. AR5K_INT_MIB = 0x00001000,
  917. AR5K_INT_SWI = 0x00002000,
  918. AR5K_INT_RXPHY = 0x00004000,
  919. AR5K_INT_RXKCM = 0x00008000,
  920. AR5K_INT_SWBA = 0x00010000,
  921. AR5K_INT_BRSSI = 0x00020000,
  922. AR5K_INT_BMISS = 0x00040000,
  923. AR5K_INT_FATAL = 0x00080000, /* Non common */
  924. AR5K_INT_BNR = 0x00100000, /* Non common */
  925. AR5K_INT_TIM = 0x00200000, /* Non common */
  926. AR5K_INT_DTIM = 0x00400000, /* Non common */
  927. AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */
  928. AR5K_INT_GPIO = 0x01000000,
  929. AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */
  930. AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */
  931. AR5K_INT_QCBRORN = 0x08000000, /* Non common */
  932. AR5K_INT_QCBRURN = 0x10000000, /* Non common */
  933. AR5K_INT_QTRIG = 0x20000000, /* Non common */
  934. AR5K_INT_GLOBAL = 0x80000000,
  935. AR5K_INT_TX_ALL = AR5K_INT_TXOK
  936. | AR5K_INT_TXDESC
  937. | AR5K_INT_TXERR
  938. | AR5K_INT_TXNOFRM
  939. | AR5K_INT_TXEOL
  940. | AR5K_INT_TXURN,
  941. AR5K_INT_RX_ALL = AR5K_INT_RXOK
  942. | AR5K_INT_RXDESC
  943. | AR5K_INT_RXERR
  944. | AR5K_INT_RXNOFRM
  945. | AR5K_INT_RXEOL
  946. | AR5K_INT_RXORN,
  947. AR5K_INT_COMMON = AR5K_INT_RXOK
  948. | AR5K_INT_RXDESC
  949. | AR5K_INT_RXERR
  950. | AR5K_INT_RXNOFRM
  951. | AR5K_INT_RXEOL
  952. | AR5K_INT_RXORN
  953. | AR5K_INT_TXOK
  954. | AR5K_INT_TXDESC
  955. | AR5K_INT_TXERR
  956. | AR5K_INT_TXNOFRM
  957. | AR5K_INT_TXEOL
  958. | AR5K_INT_TXURN
  959. | AR5K_INT_MIB
  960. | AR5K_INT_SWI
  961. | AR5K_INT_RXPHY
  962. | AR5K_INT_RXKCM
  963. | AR5K_INT_SWBA
  964. | AR5K_INT_BRSSI
  965. | AR5K_INT_BMISS
  966. | AR5K_INT_GPIO
  967. | AR5K_INT_GLOBAL,
  968. AR5K_INT_NOCARD = 0xffffffff
  969. };
  970. /**
  971. * enum ath5k_calibration_mask - Mask which calibration is active at the moment
  972. * @AR5K_CALIBRATION_FULL: Full calibration (AGC + SHORT)
  973. * @AR5K_CALIBRATION_SHORT: Short calibration (NF + I/Q)
  974. * @AR5K_CALIBRATION_NF: Noise Floor calibration
  975. * @AR5K_CALIBRATION_ANI: Adaptive Noise Immunity
  976. */
  977. enum ath5k_calibration_mask {
  978. AR5K_CALIBRATION_FULL = 0x01,
  979. AR5K_CALIBRATION_SHORT = 0x02,
  980. AR5K_CALIBRATION_NF = 0x04,
  981. AR5K_CALIBRATION_ANI = 0x08,
  982. };
  983. /**
  984. * enum ath5k_power_mode - Power management modes
  985. * @AR5K_PM_UNDEFINED: Undefined
  986. * @AR5K_PM_AUTO: Allow card to sleep if possible
  987. * @AR5K_PM_AWAKE: Force card to wake up
  988. * @AR5K_PM_FULL_SLEEP: Force card to full sleep (DANGEROUS)
  989. * @AR5K_PM_NETWORK_SLEEP: Allow to sleep for a specified duration
  990. *
  991. * Currently only PM_AWAKE is used, FULL_SLEEP and NETWORK_SLEEP/AUTO
  992. * are also known to have problems on some cards. This is not a big
  993. * problem though because we can have almost the same effect as
  994. * FULL_SLEEP by putting card on warm reset (it's almost powered down).
  995. */
  996. enum ath5k_power_mode {
  997. AR5K_PM_UNDEFINED = 0,
  998. AR5K_PM_AUTO,
  999. AR5K_PM_AWAKE,
  1000. AR5K_PM_FULL_SLEEP,
  1001. AR5K_PM_NETWORK_SLEEP,
  1002. };
  1003. /*
  1004. * These match net80211 definitions (not used in
  1005. * mac80211).
  1006. * TODO: Clean this up
  1007. */
  1008. #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/
  1009. #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/
  1010. #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/
  1011. #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/
  1012. #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/
  1013. /* GPIO-controlled software LED */
  1014. #define AR5K_SOFTLED_PIN 0
  1015. #define AR5K_SOFTLED_ON 0
  1016. #define AR5K_SOFTLED_OFF 1
  1017. /* XXX: we *may* move cap_range stuff to struct wiphy */
  1018. struct ath5k_capabilities {
  1019. /*
  1020. * Supported PHY modes
  1021. * (ie. AR5K_MODE_11A, AR5K_MODE_11B, ...)
  1022. */
  1023. DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX);
  1024. /*
  1025. * Frequency range (without regulation restrictions)
  1026. */
  1027. struct {
  1028. u16 range_2ghz_min;
  1029. u16 range_2ghz_max;
  1030. u16 range_5ghz_min;
  1031. u16 range_5ghz_max;
  1032. } cap_range;
  1033. /*
  1034. * Values stored in the EEPROM (some of them...)
  1035. */
  1036. struct ath5k_eeprom_info cap_eeprom;
  1037. /*
  1038. * Queue information
  1039. */
  1040. struct {
  1041. u8 q_tx_num;
  1042. } cap_queues;
  1043. bool cap_has_phyerr_counters;
  1044. bool cap_has_mrr_support;
  1045. bool cap_needs_2GHz_ovr;
  1046. };
  1047. /* size of noise floor history (keep it a power of two) */
  1048. #define ATH5K_NF_CAL_HIST_MAX 8
  1049. struct ath5k_nfcal_hist {
  1050. s16 index; /* current index into nfval */
  1051. s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */
  1052. };
  1053. #define ATH5K_LED_MAX_NAME_LEN 31
  1054. /*
  1055. * State for LED triggers
  1056. */
  1057. struct ath5k_led {
  1058. char name[ATH5K_LED_MAX_NAME_LEN + 1]; /* name of the LED in sysfs */
  1059. struct ath5k_hw *ah; /* driver state */
  1060. struct led_classdev led_dev; /* led classdev */
  1061. };
  1062. /* Rfkill */
  1063. struct ath5k_rfkill {
  1064. /* GPIO PIN for rfkill */
  1065. u16 gpio;
  1066. /* polarity of rfkill GPIO PIN */
  1067. bool polarity;
  1068. /* RFKILL toggle tasklet */
  1069. struct tasklet_struct toggleq;
  1070. };
  1071. /* statistics */
  1072. struct ath5k_statistics {
  1073. /* antenna use */
  1074. unsigned int antenna_rx[5]; /* frames count per antenna RX */
  1075. unsigned int antenna_tx[5]; /* frames count per antenna TX */
  1076. /* frame errors */
  1077. unsigned int rx_all_count; /* all RX frames, including errors */
  1078. unsigned int tx_all_count; /* all TX frames, including errors */
  1079. unsigned int rx_bytes_count; /* all RX bytes, including errored pkts
  1080. * and the MAC headers for each packet
  1081. */
  1082. unsigned int tx_bytes_count; /* all TX bytes, including errored pkts
  1083. * and the MAC headers and padding for
  1084. * each packet.
  1085. */
  1086. unsigned int rxerr_crc;
  1087. unsigned int rxerr_phy;
  1088. unsigned int rxerr_phy_code[32];
  1089. unsigned int rxerr_fifo;
  1090. unsigned int rxerr_decrypt;
  1091. unsigned int rxerr_mic;
  1092. unsigned int rxerr_proc;
  1093. unsigned int rxerr_jumbo;
  1094. unsigned int txerr_retry;
  1095. unsigned int txerr_fifo;
  1096. unsigned int txerr_filt;
  1097. /* MIB counters */
  1098. unsigned int ack_fail;
  1099. unsigned int rts_fail;
  1100. unsigned int rts_ok;
  1101. unsigned int fcs_error;
  1102. unsigned int beacons;
  1103. unsigned int mib_intr;
  1104. unsigned int rxorn_intr;
  1105. unsigned int rxeol_intr;
  1106. };
  1107. /*
  1108. * Misc defines
  1109. */
  1110. #define AR5K_MAX_GPIO 10
  1111. #define AR5K_MAX_RF_BANKS 8
  1112. #if CHAN_DEBUG
  1113. #define ATH_CHAN_MAX (26 + 26 + 26 + 200 + 200)
  1114. #else
  1115. #define ATH_CHAN_MAX (14 + 14 + 14 + 252 + 20)
  1116. #endif
  1117. #define ATH_RXBUF 40 /* number of RX buffers */
  1118. #define ATH_TXBUF 200 /* number of TX buffers */
  1119. #define ATH_BCBUF 4 /* number of beacon buffers */
  1120. #define ATH5K_TXQ_LEN_MAX (ATH_TXBUF / 4) /* bufs per queue */
  1121. #define ATH5K_TXQ_LEN_LOW (ATH5K_TXQ_LEN_MAX / 2) /* low mark */
  1122. DECLARE_EWMA(beacon_rssi, 1024, 8)
  1123. /* Driver state associated with an instance of a device */
  1124. struct ath5k_hw {
  1125. struct ath_common common;
  1126. struct pci_dev *pdev;
  1127. struct device *dev; /* for dma mapping */
  1128. int irq;
  1129. u16 devid;
  1130. void __iomem *iobase; /* address of the device */
  1131. struct mutex lock; /* dev-level lock */
  1132. struct ieee80211_hw *hw; /* IEEE 802.11 common */
  1133. struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
  1134. struct ieee80211_channel channels[ATH_CHAN_MAX];
  1135. struct ieee80211_rate rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
  1136. s8 rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
  1137. enum nl80211_iftype opmode;
  1138. #ifdef CONFIG_ATH5K_DEBUG
  1139. struct ath5k_dbg_info debug; /* debug info */
  1140. #endif /* CONFIG_ATH5K_DEBUG */
  1141. struct ath5k_buf *bufptr; /* allocated buffer ptr */
  1142. struct ath5k_desc *desc; /* TX/RX descriptors */
  1143. dma_addr_t desc_daddr; /* DMA (physical) address */
  1144. size_t desc_len; /* size of TX/RX descriptors */
  1145. DECLARE_BITMAP(status, 4);
  1146. #define ATH_STAT_INVALID 0 /* disable hardware accesses */
  1147. #define ATH_STAT_LEDSOFT 2 /* enable LED gpio status */
  1148. #define ATH_STAT_STARTED 3 /* opened & irqs enabled */
  1149. #define ATH_STAT_RESET 4 /* hw reset */
  1150. unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
  1151. unsigned int fif_filter_flags; /* Current FIF_* filter flags */
  1152. struct ieee80211_channel *curchan; /* current h/w channel */
  1153. u16 nvifs;
  1154. enum ath5k_int imask; /* interrupt mask copy */
  1155. spinlock_t irqlock;
  1156. bool rx_pending; /* rx tasklet pending */
  1157. bool tx_pending; /* tx tasklet pending */
  1158. u8 bssidmask[ETH_ALEN];
  1159. unsigned int led_pin, /* GPIO pin for driving LED */
  1160. led_on; /* pin setting for LED on */
  1161. struct work_struct reset_work; /* deferred chip reset */
  1162. struct work_struct calib_work; /* deferred phy calibration */
  1163. struct list_head rxbuf; /* receive buffer */
  1164. spinlock_t rxbuflock;
  1165. u32 *rxlink; /* link ptr in last RX desc */
  1166. struct tasklet_struct rxtq; /* rx intr tasklet */
  1167. struct ath5k_led rx_led; /* rx led */
  1168. struct list_head txbuf; /* transmit buffer */
  1169. spinlock_t txbuflock;
  1170. unsigned int txbuf_len; /* buf count in txbuf list */
  1171. struct ath5k_txq txqs[AR5K_NUM_TX_QUEUES]; /* tx queues */
  1172. struct tasklet_struct txtq; /* tx intr tasklet */
  1173. struct ath5k_led tx_led; /* tx led */
  1174. struct ath5k_rfkill rf_kill;
  1175. spinlock_t block; /* protects beacon */
  1176. struct tasklet_struct beacontq; /* beacon intr tasklet */
  1177. struct list_head bcbuf; /* beacon buffer */
  1178. struct ieee80211_vif *bslot[ATH_BCBUF];
  1179. u16 num_ap_vifs;
  1180. u16 num_adhoc_vifs;
  1181. u16 num_mesh_vifs;
  1182. unsigned int bhalq, /* SW q for outgoing beacons */
  1183. bmisscount, /* missed beacon transmits */
  1184. bintval, /* beacon interval in TU */
  1185. bsent;
  1186. unsigned int nexttbtt; /* next beacon time in TU */
  1187. struct ath5k_txq *cabq; /* content after beacon */
  1188. bool assoc; /* associate state */
  1189. bool enable_beacon; /* true if beacons are on */
  1190. struct ath5k_statistics stats;
  1191. struct ath5k_ani_state ani_state;
  1192. struct tasklet_struct ani_tasklet; /* ANI calibration */
  1193. struct delayed_work tx_complete_work;
  1194. struct survey_info survey; /* collected survey info */
  1195. enum ath5k_int ah_imr;
  1196. struct ieee80211_channel *ah_current_channel;
  1197. bool ah_iq_cal_needed;
  1198. bool ah_single_chip;
  1199. enum ath5k_version ah_version;
  1200. enum ath5k_radio ah_radio;
  1201. u32 ah_mac_srev;
  1202. u16 ah_mac_version;
  1203. u16 ah_phy_revision;
  1204. u16 ah_radio_5ghz_revision;
  1205. u16 ah_radio_2ghz_revision;
  1206. #define ah_modes ah_capabilities.cap_mode
  1207. #define ah_ee_version ah_capabilities.cap_eeprom.ee_version
  1208. u8 ah_retry_long;
  1209. u8 ah_retry_short;
  1210. bool ah_use_32khz_clock;
  1211. u8 ah_coverage_class;
  1212. bool ah_ack_bitrate_high;
  1213. u8 ah_bwmode;
  1214. bool ah_short_slot;
  1215. /* Antenna Control */
  1216. u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
  1217. u8 ah_ant_mode;
  1218. u8 ah_tx_ant;
  1219. u8 ah_def_ant;
  1220. struct ath5k_capabilities ah_capabilities;
  1221. struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES];
  1222. u32 ah_txq_status;
  1223. u32 ah_txq_imr_txok;
  1224. u32 ah_txq_imr_txerr;
  1225. u32 ah_txq_imr_txurn;
  1226. u32 ah_txq_imr_txdesc;
  1227. u32 ah_txq_imr_txeol;
  1228. u32 ah_txq_imr_cbrorn;
  1229. u32 ah_txq_imr_cbrurn;
  1230. u32 ah_txq_imr_qtrig;
  1231. u32 ah_txq_imr_nofrm;
  1232. u32 ah_txq_isr_txok_all;
  1233. u32 ah_txq_isr_txurn;
  1234. u32 ah_txq_isr_qcborn;
  1235. u32 ah_txq_isr_qcburn;
  1236. u32 ah_txq_isr_qtrig;
  1237. u32 *ah_rf_banks;
  1238. size_t ah_rf_banks_size;
  1239. size_t ah_rf_regs_count;
  1240. struct ath5k_gain ah_gain;
  1241. u8 ah_offset[AR5K_MAX_RF_BANKS];
  1242. struct {
  1243. /* Temporary tables used for interpolation */
  1244. u8 tmpL[AR5K_EEPROM_N_PD_GAINS]
  1245. [AR5K_EEPROM_POWER_TABLE_SIZE];
  1246. u8 tmpR[AR5K_EEPROM_N_PD_GAINS]
  1247. [AR5K_EEPROM_POWER_TABLE_SIZE];
  1248. u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
  1249. u16 txp_rates_power_table[AR5K_MAX_RATES];
  1250. u8 txp_min_idx;
  1251. bool txp_tpc;
  1252. /* Values in 0.25dB units */
  1253. s16 txp_min_pwr;
  1254. s16 txp_max_pwr;
  1255. s16 txp_cur_pwr;
  1256. /* Values in 0.5dB units */
  1257. s16 txp_offset;
  1258. s16 txp_ofdm;
  1259. s16 txp_cck_ofdm_gainf_delta;
  1260. /* Value in dB units */
  1261. s16 txp_cck_ofdm_pwr_delta;
  1262. bool txp_setup;
  1263. int txp_requested; /* Requested tx power in dBm */
  1264. } ah_txpower;
  1265. struct ath5k_nfcal_hist ah_nfcal_hist;
  1266. /* average beacon RSSI in our BSS (used by ANI) */
  1267. struct ewma_beacon_rssi ah_beacon_rssi_avg;
  1268. /* noise floor from last periodic calibration */
  1269. s32 ah_noise_floor;
  1270. /* Calibration timestamp */
  1271. unsigned long ah_cal_next_full;
  1272. unsigned long ah_cal_next_short;
  1273. unsigned long ah_cal_next_ani;
  1274. /* Calibration mask */
  1275. u8 ah_cal_mask;
  1276. /*
  1277. * Function pointers
  1278. */
  1279. int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
  1280. unsigned int, unsigned int, int, enum ath5k_pkt_type,
  1281. unsigned int, unsigned int, unsigned int, unsigned int,
  1282. unsigned int, unsigned int, unsigned int, unsigned int);
  1283. int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
  1284. struct ath5k_tx_status *);
  1285. int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
  1286. struct ath5k_rx_status *);
  1287. };
  1288. struct ath_bus_ops {
  1289. enum ath_bus_type ath_bus_type;
  1290. void (*read_cachesize)(struct ath_common *common, int *csz);
  1291. bool (*eeprom_read)(struct ath_common *common, u32 off, u16 *data);
  1292. int (*eeprom_read_mac)(struct ath5k_hw *ah, u8 *mac);
  1293. };
  1294. /*
  1295. * Prototypes
  1296. */
  1297. extern const struct ieee80211_ops ath5k_hw_ops;
  1298. /* Initialization and detach functions */
  1299. int ath5k_hw_init(struct ath5k_hw *ah);
  1300. void ath5k_hw_deinit(struct ath5k_hw *ah);
  1301. int ath5k_sysfs_register(struct ath5k_hw *ah);
  1302. void ath5k_sysfs_unregister(struct ath5k_hw *ah);
  1303. /*Chip id helper functions */
  1304. int ath5k_hw_read_srev(struct ath5k_hw *ah);
  1305. /* LED functions */
  1306. int ath5k_init_leds(struct ath5k_hw *ah);
  1307. void ath5k_led_enable(struct ath5k_hw *ah);
  1308. void ath5k_led_off(struct ath5k_hw *ah);
  1309. void ath5k_unregister_leds(struct ath5k_hw *ah);
  1310. /* Reset Functions */
  1311. int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, struct ieee80211_channel *channel);
  1312. int ath5k_hw_on_hold(struct ath5k_hw *ah);
  1313. int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
  1314. struct ieee80211_channel *channel, bool fast, bool skip_pcu);
  1315. int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
  1316. bool is_set);
  1317. /* Power management functions */
  1318. /* Clock rate related functions */
  1319. unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec);
  1320. unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock);
  1321. void ath5k_hw_set_clockrate(struct ath5k_hw *ah);
  1322. /* DMA Related Functions */
  1323. void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
  1324. u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
  1325. int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
  1326. int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
  1327. int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue);
  1328. u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
  1329. int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
  1330. u32 phys_addr);
  1331. int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
  1332. /* Interrupt handling */
  1333. bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
  1334. int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
  1335. enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
  1336. void ath5k_hw_update_mib_counters(struct ath5k_hw *ah);
  1337. /* Init/Stop functions */
  1338. void ath5k_hw_dma_init(struct ath5k_hw *ah);
  1339. int ath5k_hw_dma_stop(struct ath5k_hw *ah);
  1340. /* EEPROM access functions */
  1341. int ath5k_eeprom_init(struct ath5k_hw *ah);
  1342. void ath5k_eeprom_detach(struct ath5k_hw *ah);
  1343. int ath5k_eeprom_mode_from_channel(struct ath5k_hw *ah,
  1344. struct ieee80211_channel *channel);
  1345. /* Protocol Control Unit Functions */
  1346. /* Helpers */
  1347. int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, enum ieee80211_band band,
  1348. int len, struct ieee80211_rate *rate, bool shortpre);
  1349. unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah);
  1350. unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah);
  1351. int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode);
  1352. void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class);
  1353. /* RX filter control*/
  1354. int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
  1355. void ath5k_hw_set_bssid(struct ath5k_hw *ah);
  1356. void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
  1357. void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
  1358. u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
  1359. void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
  1360. /* Receive (DRU) start/stop functions */
  1361. void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
  1362. void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
  1363. /* Beacon control functions */
  1364. u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
  1365. void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64);
  1366. void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
  1367. void ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon,
  1368. u32 interval);
  1369. bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval);
  1370. /* Init function */
  1371. void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode);
  1372. /* Queue Control Unit, DFS Control Unit Functions */
  1373. int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
  1374. struct ath5k_txq_info *queue_info);
  1375. int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue,
  1376. const struct ath5k_txq_info *queue_info);
  1377. int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
  1378. enum ath5k_tx_queue queue_type,
  1379. struct ath5k_txq_info *queue_info);
  1380. void ath5k_hw_set_tx_retry_limits(struct ath5k_hw *ah,
  1381. unsigned int queue);
  1382. u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
  1383. void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
  1384. int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
  1385. int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time);
  1386. /* Init function */
  1387. int ath5k_hw_init_queues(struct ath5k_hw *ah);
  1388. /* Hardware Descriptor Functions */
  1389. int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
  1390. int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
  1391. u32 size, unsigned int flags);
  1392. int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
  1393. unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2,
  1394. u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3);
  1395. /* GPIO Functions */
  1396. void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
  1397. int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
  1398. int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
  1399. u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
  1400. int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
  1401. void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
  1402. u32 interrupt_level);
  1403. /* RFkill Functions */
  1404. void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
  1405. void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
  1406. /* Misc functions TODO: Cleanup */
  1407. int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
  1408. int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
  1409. int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
  1410. /* Initial register settings functions */
  1411. int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel);
  1412. /* PHY functions */
  1413. /* Misc PHY functions */
  1414. u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band);
  1415. int ath5k_hw_phy_disable(struct ath5k_hw *ah);
  1416. /* Gain_F optimization */
  1417. enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
  1418. int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
  1419. /* PHY/RF channel functions */
  1420. bool ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel);
  1421. /* PHY calibration */
  1422. void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah);
  1423. int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
  1424. struct ieee80211_channel *channel);
  1425. void ath5k_hw_update_noise_floor(struct ath5k_hw *ah);
  1426. /* Spur mitigation */
  1427. bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
  1428. struct ieee80211_channel *channel);
  1429. /* Antenna control */
  1430. void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode);
  1431. void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode);
  1432. /* TX power setup */
  1433. int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower);
  1434. /* Init function */
  1435. int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  1436. u8 mode, bool fast);
  1437. /*
  1438. * Functions used internally
  1439. */
  1440. static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah)
  1441. {
  1442. return &ah->common;
  1443. }
  1444. static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah)
  1445. {
  1446. return &(ath5k_hw_common(ah)->regulatory);
  1447. }
  1448. #ifdef CONFIG_ATH5K_AHB
  1449. #define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000)
  1450. static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg)
  1451. {
  1452. /* On AR2315 and AR2317 the PCI clock domain registers
  1453. * are outside of the WMAC register space */
  1454. if (unlikely((reg >= 0x4000) && (reg < 0x5000) &&
  1455. (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6)))
  1456. return AR5K_AR2315_PCI_BASE + reg;
  1457. return ah->iobase + reg;
  1458. }
  1459. static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
  1460. {
  1461. return ioread32(ath5k_ahb_reg(ah, reg));
  1462. }
  1463. static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
  1464. {
  1465. iowrite32(val, ath5k_ahb_reg(ah, reg));
  1466. }
  1467. #else
  1468. static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
  1469. {
  1470. return ioread32(ah->iobase + reg);
  1471. }
  1472. static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
  1473. {
  1474. iowrite32(val, ah->iobase + reg);
  1475. }
  1476. #endif
  1477. static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah)
  1478. {
  1479. return ath5k_hw_common(ah)->bus_ops->ath_bus_type;
  1480. }
  1481. static inline void ath5k_read_cachesize(struct ath_common *common, int *csz)
  1482. {
  1483. common->bus_ops->read_cachesize(common, csz);
  1484. }
  1485. static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data)
  1486. {
  1487. struct ath_common *common = ath5k_hw_common(ah);
  1488. return common->bus_ops->eeprom_read(common, off, data);
  1489. }
  1490. static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
  1491. {
  1492. u32 retval = 0, bit, i;
  1493. for (i = 0; i < bits; i++) {
  1494. bit = (val >> i) & 1;
  1495. retval = (retval << 1) | bit;
  1496. }
  1497. return retval;
  1498. }
  1499. #endif