desc.c 22 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
  5. *
  6. * Permission to use, copy, modify, and distribute this software for any
  7. * purpose with or without fee is hereby granted, provided that the above
  8. * copyright notice and this permission notice appear in all copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17. *
  18. */
  19. /******************************\
  20. Hardware Descriptor Functions
  21. \******************************/
  22. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  23. #include "ath5k.h"
  24. #include "reg.h"
  25. #include "debug.h"
  26. /**
  27. * DOC: Hardware descriptor functions
  28. *
  29. * Here we handle the processing of the low-level hw descriptors
  30. * that hw reads and writes via DMA for each TX and RX attempt (that means
  31. * we can also have descriptors for failed TX/RX tries). We have two kind of
  32. * descriptors for RX and TX, control descriptors tell the hw how to send or
  33. * receive a packet where to read/write it from/to etc and status descriptors
  34. * that contain information about how the packet was sent or received (errors
  35. * included).
  36. *
  37. * Descriptor format is not exactly the same for each MAC chip version so we
  38. * have function pointers on &struct ath5k_hw we initialize at runtime based on
  39. * the chip used.
  40. */
  41. /************************\
  42. * TX Control descriptors *
  43. \************************/
  44. /**
  45. * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor
  46. * @ah: The &struct ath5k_hw
  47. * @desc: The &struct ath5k_desc
  48. * @pkt_len: Frame length in bytes
  49. * @hdr_len: Header length in bytes (only used on AR5210)
  50. * @padsize: Any padding we've added to the frame length
  51. * @type: One of enum ath5k_pkt_type
  52. * @tx_power: Tx power in 0.5dB steps
  53. * @tx_rate0: HW idx for transmission rate
  54. * @tx_tries0: Max number of retransmissions
  55. * @key_index: Index on key table to use for encryption
  56. * @antenna_mode: Which antenna to use (0 for auto)
  57. * @flags: One of AR5K_TXDESC_* flags (desc.h)
  58. * @rtscts_rate: HW idx for RTS/CTS transmission rate
  59. * @rtscts_duration: What to put on duration field on the header of RTS/CTS
  60. *
  61. * Internal function to initialize a 2-Word TX control descriptor
  62. * found on AR5210 and AR5211 MACs chips.
  63. *
  64. * Returns 0 on success or -EINVAL on false input
  65. */
  66. static int
  67. ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah,
  68. struct ath5k_desc *desc,
  69. unsigned int pkt_len, unsigned int hdr_len,
  70. int padsize,
  71. enum ath5k_pkt_type type,
  72. unsigned int tx_power,
  73. unsigned int tx_rate0, unsigned int tx_tries0,
  74. unsigned int key_index,
  75. unsigned int antenna_mode,
  76. unsigned int flags,
  77. unsigned int rtscts_rate, unsigned int rtscts_duration)
  78. {
  79. u32 frame_type;
  80. struct ath5k_hw_2w_tx_ctl *tx_ctl;
  81. unsigned int frame_len;
  82. tx_ctl = &desc->ud.ds_tx5210.tx_ctl;
  83. /*
  84. * Validate input
  85. * - Zero retries don't make sense.
  86. * - A zero rate will put the HW into a mode where it continuously sends
  87. * noise on the channel, so it is important to avoid this.
  88. */
  89. if (unlikely(tx_tries0 == 0)) {
  90. ATH5K_ERR(ah, "zero retries\n");
  91. WARN_ON(1);
  92. return -EINVAL;
  93. }
  94. if (unlikely(tx_rate0 == 0)) {
  95. ATH5K_ERR(ah, "zero rate\n");
  96. WARN_ON(1);
  97. return -EINVAL;
  98. }
  99. /* Clear descriptor */
  100. memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc));
  101. /* Setup control descriptor */
  102. /* Verify and set frame length */
  103. /* remove padding we might have added before */
  104. frame_len = pkt_len - padsize + FCS_LEN;
  105. if (frame_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
  106. return -EINVAL;
  107. tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
  108. /* Verify and set buffer length */
  109. /* NB: beacon's BufLen must be a multiple of 4 bytes */
  110. if (type == AR5K_PKT_TYPE_BEACON)
  111. pkt_len = roundup(pkt_len, 4);
  112. if (pkt_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
  113. return -EINVAL;
  114. tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
  115. /*
  116. * Verify and set header length (only 5210)
  117. */
  118. if (ah->ah_version == AR5K_AR5210) {
  119. if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210)
  120. return -EINVAL;
  121. tx_ctl->tx_control_0 |=
  122. AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN_5210);
  123. }
  124. /*Differences between 5210-5211*/
  125. if (ah->ah_version == AR5K_AR5210) {
  126. switch (type) {
  127. case AR5K_PKT_TYPE_BEACON:
  128. case AR5K_PKT_TYPE_PROBE_RESP:
  129. frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
  130. break;
  131. case AR5K_PKT_TYPE_PIFS:
  132. frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
  133. break;
  134. default:
  135. frame_type = type;
  136. break;
  137. }
  138. tx_ctl->tx_control_0 |=
  139. AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_5210) |
  140. AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
  141. } else {
  142. tx_ctl->tx_control_0 |=
  143. AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
  144. AR5K_REG_SM(antenna_mode,
  145. AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
  146. tx_ctl->tx_control_1 |=
  147. AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_5211);
  148. }
  149. #define _TX_FLAGS(_c, _flag) \
  150. if (flags & AR5K_TXDESC_##_flag) { \
  151. tx_ctl->tx_control_##_c |= \
  152. AR5K_2W_TX_DESC_CTL##_c##_##_flag; \
  153. }
  154. #define _TX_FLAGS_5211(_c, _flag) \
  155. if (flags & AR5K_TXDESC_##_flag) { \
  156. tx_ctl->tx_control_##_c |= \
  157. AR5K_2W_TX_DESC_CTL##_c##_##_flag##_5211; \
  158. }
  159. _TX_FLAGS(0, CLRDMASK);
  160. _TX_FLAGS(0, INTREQ);
  161. _TX_FLAGS(0, RTSENA);
  162. if (ah->ah_version == AR5K_AR5211) {
  163. _TX_FLAGS_5211(0, VEOL);
  164. _TX_FLAGS_5211(1, NOACK);
  165. }
  166. #undef _TX_FLAGS
  167. #undef _TX_FLAGS_5211
  168. /*
  169. * WEP crap
  170. */
  171. if (key_index != AR5K_TXKEYIX_INVALID) {
  172. tx_ctl->tx_control_0 |=
  173. AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
  174. tx_ctl->tx_control_1 |=
  175. AR5K_REG_SM(key_index,
  176. AR5K_2W_TX_DESC_CTL1_ENC_KEY_IDX);
  177. }
  178. /*
  179. * RTS/CTS Duration [5210 ?]
  180. */
  181. if ((ah->ah_version == AR5K_AR5210) &&
  182. (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
  183. tx_ctl->tx_control_1 |= rtscts_duration &
  184. AR5K_2W_TX_DESC_CTL1_RTS_DURATION_5210;
  185. return 0;
  186. }
  187. /**
  188. * ath5k_hw_setup_4word_tx_desc() - Initialize a 4-word tx control descriptor
  189. * @ah: The &struct ath5k_hw
  190. * @desc: The &struct ath5k_desc
  191. * @pkt_len: Frame length in bytes
  192. * @hdr_len: Header length in bytes (only used on AR5210)
  193. * @padsize: Any padding we've added to the frame length
  194. * @type: One of enum ath5k_pkt_type
  195. * @tx_power: Tx power in 0.5dB steps
  196. * @tx_rate0: HW idx for transmission rate
  197. * @tx_tries0: Max number of retransmissions
  198. * @key_index: Index on key table to use for encryption
  199. * @antenna_mode: Which antenna to use (0 for auto)
  200. * @flags: One of AR5K_TXDESC_* flags (desc.h)
  201. * @rtscts_rate: HW idx for RTS/CTS transmission rate
  202. * @rtscts_duration: What to put on duration field on the header of RTS/CTS
  203. *
  204. * Internal function to initialize a 4-Word TX control descriptor
  205. * found on AR5212 and later MACs chips.
  206. *
  207. * Returns 0 on success or -EINVAL on false input
  208. */
  209. static int
  210. ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
  211. struct ath5k_desc *desc,
  212. unsigned int pkt_len, unsigned int hdr_len,
  213. int padsize,
  214. enum ath5k_pkt_type type,
  215. unsigned int tx_power,
  216. unsigned int tx_rate0, unsigned int tx_tries0,
  217. unsigned int key_index,
  218. unsigned int antenna_mode,
  219. unsigned int flags,
  220. unsigned int rtscts_rate, unsigned int rtscts_duration)
  221. {
  222. struct ath5k_hw_4w_tx_ctl *tx_ctl;
  223. unsigned int frame_len;
  224. /*
  225. * Use local variables for these to reduce load/store access on
  226. * uncached memory
  227. */
  228. u32 txctl0 = 0, txctl1 = 0, txctl2 = 0, txctl3 = 0;
  229. tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
  230. /*
  231. * Validate input
  232. * - Zero retries don't make sense.
  233. * - A zero rate will put the HW into a mode where it continuously sends
  234. * noise on the channel, so it is important to avoid this.
  235. */
  236. if (unlikely(tx_tries0 == 0)) {
  237. ATH5K_ERR(ah, "zero retries\n");
  238. WARN_ON(1);
  239. return -EINVAL;
  240. }
  241. if (unlikely(tx_rate0 == 0)) {
  242. ATH5K_ERR(ah, "zero rate\n");
  243. WARN_ON(1);
  244. return -EINVAL;
  245. }
  246. tx_power += ah->ah_txpower.txp_offset;
  247. if (tx_power > AR5K_TUNE_MAX_TXPOWER)
  248. tx_power = AR5K_TUNE_MAX_TXPOWER;
  249. /* Clear descriptor status area */
  250. memset(&desc->ud.ds_tx5212.tx_stat, 0,
  251. sizeof(desc->ud.ds_tx5212.tx_stat));
  252. /* Setup control descriptor */
  253. /* Verify and set frame length */
  254. /* remove padding we might have added before */
  255. frame_len = pkt_len - padsize + FCS_LEN;
  256. if (frame_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
  257. return -EINVAL;
  258. txctl0 = frame_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
  259. /* Verify and set buffer length */
  260. /* NB: beacon's BufLen must be a multiple of 4 bytes */
  261. if (type == AR5K_PKT_TYPE_BEACON)
  262. pkt_len = roundup(pkt_len, 4);
  263. if (pkt_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
  264. return -EINVAL;
  265. txctl1 = pkt_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
  266. txctl0 |= AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
  267. AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
  268. txctl1 |= AR5K_REG_SM(type, AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
  269. txctl2 = AR5K_REG_SM(tx_tries0, AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
  270. txctl3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
  271. #define _TX_FLAGS(_c, _flag) \
  272. if (flags & AR5K_TXDESC_##_flag) { \
  273. txctl##_c |= AR5K_4W_TX_DESC_CTL##_c##_##_flag; \
  274. }
  275. _TX_FLAGS(0, CLRDMASK);
  276. _TX_FLAGS(0, VEOL);
  277. _TX_FLAGS(0, INTREQ);
  278. _TX_FLAGS(0, RTSENA);
  279. _TX_FLAGS(0, CTSENA);
  280. _TX_FLAGS(1, NOACK);
  281. #undef _TX_FLAGS
  282. /*
  283. * WEP crap
  284. */
  285. if (key_index != AR5K_TXKEYIX_INVALID) {
  286. txctl0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
  287. txctl1 |= AR5K_REG_SM(key_index,
  288. AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_IDX);
  289. }
  290. /*
  291. * RTS/CTS
  292. */
  293. if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
  294. if ((flags & AR5K_TXDESC_RTSENA) &&
  295. (flags & AR5K_TXDESC_CTSENA))
  296. return -EINVAL;
  297. txctl2 |= rtscts_duration & AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
  298. txctl3 |= AR5K_REG_SM(rtscts_rate,
  299. AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
  300. }
  301. tx_ctl->tx_control_0 = txctl0;
  302. tx_ctl->tx_control_1 = txctl1;
  303. tx_ctl->tx_control_2 = txctl2;
  304. tx_ctl->tx_control_3 = txctl3;
  305. return 0;
  306. }
  307. /**
  308. * ath5k_hw_setup_mrr_tx_desc() - Initialize an MRR tx control descriptor
  309. * @ah: The &struct ath5k_hw
  310. * @desc: The &struct ath5k_desc
  311. * @tx_rate1: HW idx for rate used on transmission series 1
  312. * @tx_tries1: Max number of retransmissions for transmission series 1
  313. * @tx_rate2: HW idx for rate used on transmission series 2
  314. * @tx_tries2: Max number of retransmissions for transmission series 2
  315. * @tx_rate3: HW idx for rate used on transmission series 3
  316. * @tx_tries3: Max number of retransmissions for transmission series 3
  317. *
  318. * Multi rate retry (MRR) tx control descriptors are available only on AR5212
  319. * MACs, they are part of the normal 4-word tx control descriptor (see above)
  320. * but we handle them through a separate function for better abstraction.
  321. *
  322. * Returns 0 on success or -EINVAL on invalid input
  323. */
  324. int
  325. ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah,
  326. struct ath5k_desc *desc,
  327. u_int tx_rate1, u_int tx_tries1,
  328. u_int tx_rate2, u_int tx_tries2,
  329. u_int tx_rate3, u_int tx_tries3)
  330. {
  331. struct ath5k_hw_4w_tx_ctl *tx_ctl;
  332. /* no mrr support for cards older than 5212 */
  333. if (ah->ah_version < AR5K_AR5212)
  334. return 0;
  335. /*
  336. * Rates can be 0 as long as the retry count is 0 too.
  337. * A zero rate and nonzero retry count will put the HW into a mode where
  338. * it continuously sends noise on the channel, so it is important to
  339. * avoid this.
  340. */
  341. if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
  342. (tx_rate2 == 0 && tx_tries2 != 0) ||
  343. (tx_rate3 == 0 && tx_tries3 != 0))) {
  344. ATH5K_ERR(ah, "zero rate\n");
  345. WARN_ON(1);
  346. return -EINVAL;
  347. }
  348. if (ah->ah_version == AR5K_AR5212) {
  349. tx_ctl = &desc->ud.ds_tx5212.tx_ctl;
  350. #define _XTX_TRIES(_n) \
  351. if (tx_tries##_n) { \
  352. tx_ctl->tx_control_2 |= \
  353. AR5K_REG_SM(tx_tries##_n, \
  354. AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
  355. tx_ctl->tx_control_3 |= \
  356. AR5K_REG_SM(tx_rate##_n, \
  357. AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
  358. }
  359. _XTX_TRIES(1);
  360. _XTX_TRIES(2);
  361. _XTX_TRIES(3);
  362. #undef _XTX_TRIES
  363. return 1;
  364. }
  365. return 0;
  366. }
  367. /***********************\
  368. * TX Status descriptors *
  369. \***********************/
  370. /**
  371. * ath5k_hw_proc_2word_tx_status() - Process a tx status descriptor on 5210/1
  372. * @ah: The &struct ath5k_hw
  373. * @desc: The &struct ath5k_desc
  374. * @ts: The &struct ath5k_tx_status
  375. */
  376. static int
  377. ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
  378. struct ath5k_desc *desc,
  379. struct ath5k_tx_status *ts)
  380. {
  381. struct ath5k_hw_tx_status *tx_status;
  382. tx_status = &desc->ud.ds_tx5210.tx_stat;
  383. /* No frame has been send or error */
  384. if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
  385. return -EINPROGRESS;
  386. /*
  387. * Get descriptor status
  388. */
  389. ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
  390. AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
  391. ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
  392. AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
  393. ts->ts_final_retry = AR5K_REG_MS(tx_status->tx_status_0,
  394. AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
  395. /*TODO: ts->ts_virtcol + test*/
  396. ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
  397. AR5K_DESC_TX_STATUS1_SEQ_NUM);
  398. ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
  399. AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
  400. ts->ts_antenna = 1;
  401. ts->ts_status = 0;
  402. ts->ts_final_idx = 0;
  403. if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
  404. if (tx_status->tx_status_0 &
  405. AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
  406. ts->ts_status |= AR5K_TXERR_XRETRY;
  407. if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
  408. ts->ts_status |= AR5K_TXERR_FIFO;
  409. if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
  410. ts->ts_status |= AR5K_TXERR_FILT;
  411. }
  412. return 0;
  413. }
  414. /**
  415. * ath5k_hw_proc_4word_tx_status() - Process a tx status descriptor on 5212
  416. * @ah: The &struct ath5k_hw
  417. * @desc: The &struct ath5k_desc
  418. * @ts: The &struct ath5k_tx_status
  419. */
  420. static int
  421. ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
  422. struct ath5k_desc *desc,
  423. struct ath5k_tx_status *ts)
  424. {
  425. struct ath5k_hw_tx_status *tx_status;
  426. u32 txstat0, txstat1;
  427. tx_status = &desc->ud.ds_tx5212.tx_stat;
  428. txstat1 = ACCESS_ONCE(tx_status->tx_status_1);
  429. /* No frame has been send or error */
  430. if (unlikely(!(txstat1 & AR5K_DESC_TX_STATUS1_DONE)))
  431. return -EINPROGRESS;
  432. txstat0 = ACCESS_ONCE(tx_status->tx_status_0);
  433. /*
  434. * Get descriptor status
  435. */
  436. ts->ts_tstamp = AR5K_REG_MS(txstat0,
  437. AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
  438. ts->ts_shortretry = AR5K_REG_MS(txstat0,
  439. AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
  440. ts->ts_final_retry = AR5K_REG_MS(txstat0,
  441. AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
  442. ts->ts_seqnum = AR5K_REG_MS(txstat1,
  443. AR5K_DESC_TX_STATUS1_SEQ_NUM);
  444. ts->ts_rssi = AR5K_REG_MS(txstat1,
  445. AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
  446. ts->ts_antenna = (txstat1 &
  447. AR5K_DESC_TX_STATUS1_XMIT_ANTENNA_5212) ? 2 : 1;
  448. ts->ts_status = 0;
  449. ts->ts_final_idx = AR5K_REG_MS(txstat1,
  450. AR5K_DESC_TX_STATUS1_FINAL_TS_IX_5212);
  451. /* TX error */
  452. if (!(txstat0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) {
  453. if (txstat0 & AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
  454. ts->ts_status |= AR5K_TXERR_XRETRY;
  455. if (txstat0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
  456. ts->ts_status |= AR5K_TXERR_FIFO;
  457. if (txstat0 & AR5K_DESC_TX_STATUS0_FILTERED)
  458. ts->ts_status |= AR5K_TXERR_FILT;
  459. }
  460. return 0;
  461. }
  462. /****************\
  463. * RX Descriptors *
  464. \****************/
  465. /**
  466. * ath5k_hw_setup_rx_desc() - Initialize an rx control descriptor
  467. * @ah: The &struct ath5k_hw
  468. * @desc: The &struct ath5k_desc
  469. * @size: RX buffer length in bytes
  470. * @flags: One of AR5K_RXDESC_* flags
  471. */
  472. int
  473. ath5k_hw_setup_rx_desc(struct ath5k_hw *ah,
  474. struct ath5k_desc *desc,
  475. u32 size, unsigned int flags)
  476. {
  477. struct ath5k_hw_rx_ctl *rx_ctl;
  478. rx_ctl = &desc->ud.ds_rx.rx_ctl;
  479. /*
  480. * Clear the descriptor
  481. * If we don't clean the status descriptor,
  482. * while scanning we get too many results,
  483. * most of them virtual, after some secs
  484. * of scanning system hangs. M.F.
  485. */
  486. memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc));
  487. if (unlikely(size & ~AR5K_DESC_RX_CTL1_BUF_LEN))
  488. return -EINVAL;
  489. /* Setup descriptor */
  490. rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
  491. if (flags & AR5K_RXDESC_INTREQ)
  492. rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
  493. return 0;
  494. }
  495. /**
  496. * ath5k_hw_proc_5210_rx_status() - Process the rx status descriptor on 5210/1
  497. * @ah: The &struct ath5k_hw
  498. * @desc: The &struct ath5k_desc
  499. * @rs: The &struct ath5k_rx_status
  500. *
  501. * Internal function used to process an RX status descriptor
  502. * on AR5210/5211 MAC.
  503. *
  504. * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
  505. * frame yet.
  506. */
  507. static int
  508. ath5k_hw_proc_5210_rx_status(struct ath5k_hw *ah,
  509. struct ath5k_desc *desc,
  510. struct ath5k_rx_status *rs)
  511. {
  512. struct ath5k_hw_rx_status *rx_status;
  513. rx_status = &desc->ud.ds_rx.rx_stat;
  514. /* No frame received / not ready */
  515. if (unlikely(!(rx_status->rx_status_1 &
  516. AR5K_5210_RX_DESC_STATUS1_DONE)))
  517. return -EINPROGRESS;
  518. memset(rs, 0, sizeof(struct ath5k_rx_status));
  519. /*
  520. * Frame receive status
  521. */
  522. rs->rs_datalen = rx_status->rx_status_0 &
  523. AR5K_5210_RX_DESC_STATUS0_DATA_LEN;
  524. rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
  525. AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL);
  526. rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
  527. AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE);
  528. rs->rs_more = !!(rx_status->rx_status_0 &
  529. AR5K_5210_RX_DESC_STATUS0_MORE);
  530. /* TODO: this timestamp is 13 bit, later on we assume 15 bit!
  531. * also the HAL code for 5210 says the timestamp is bits [10..22] of the
  532. * TSF, and extends the timestamp here to 15 bit.
  533. * we need to check on 5210...
  534. */
  535. rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
  536. AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
  537. if (ah->ah_version == AR5K_AR5211)
  538. rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0,
  539. AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5211);
  540. else
  541. rs->rs_antenna = (rx_status->rx_status_0 &
  542. AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANT_5210)
  543. ? 2 : 1;
  544. /*
  545. * Key table status
  546. */
  547. if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID)
  548. rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
  549. AR5K_5210_RX_DESC_STATUS1_KEY_INDEX);
  550. else
  551. rs->rs_keyix = AR5K_RXKEYIX_INVALID;
  552. /*
  553. * Receive/descriptor errors
  554. */
  555. if (!(rx_status->rx_status_1 &
  556. AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
  557. if (rx_status->rx_status_1 &
  558. AR5K_5210_RX_DESC_STATUS1_CRC_ERROR)
  559. rs->rs_status |= AR5K_RXERR_CRC;
  560. /* only on 5210 */
  561. if ((ah->ah_version == AR5K_AR5210) &&
  562. (rx_status->rx_status_1 &
  563. AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN_5210))
  564. rs->rs_status |= AR5K_RXERR_FIFO;
  565. if (rx_status->rx_status_1 &
  566. AR5K_5210_RX_DESC_STATUS1_PHY_ERROR) {
  567. rs->rs_status |= AR5K_RXERR_PHY;
  568. rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1,
  569. AR5K_5210_RX_DESC_STATUS1_PHY_ERROR);
  570. }
  571. if (rx_status->rx_status_1 &
  572. AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
  573. rs->rs_status |= AR5K_RXERR_DECRYPT;
  574. }
  575. return 0;
  576. }
  577. /**
  578. * ath5k_hw_proc_5212_rx_status() - Process the rx status descriptor on 5212
  579. * @ah: The &struct ath5k_hw
  580. * @desc: The &struct ath5k_desc
  581. * @rs: The &struct ath5k_rx_status
  582. *
  583. * Internal function used to process an RX status descriptor
  584. * on AR5212 and later MAC.
  585. *
  586. * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
  587. * frame yet.
  588. */
  589. static int
  590. ath5k_hw_proc_5212_rx_status(struct ath5k_hw *ah,
  591. struct ath5k_desc *desc,
  592. struct ath5k_rx_status *rs)
  593. {
  594. struct ath5k_hw_rx_status *rx_status;
  595. u32 rxstat0, rxstat1;
  596. rx_status = &desc->ud.ds_rx.rx_stat;
  597. rxstat1 = ACCESS_ONCE(rx_status->rx_status_1);
  598. /* No frame received / not ready */
  599. if (unlikely(!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_DONE)))
  600. return -EINPROGRESS;
  601. memset(rs, 0, sizeof(struct ath5k_rx_status));
  602. rxstat0 = ACCESS_ONCE(rx_status->rx_status_0);
  603. /*
  604. * Frame receive status
  605. */
  606. rs->rs_datalen = rxstat0 & AR5K_5212_RX_DESC_STATUS0_DATA_LEN;
  607. rs->rs_rssi = AR5K_REG_MS(rxstat0,
  608. AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL);
  609. rs->rs_rate = AR5K_REG_MS(rxstat0,
  610. AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE);
  611. rs->rs_antenna = AR5K_REG_MS(rxstat0,
  612. AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA);
  613. rs->rs_more = !!(rxstat0 & AR5K_5212_RX_DESC_STATUS0_MORE);
  614. rs->rs_tstamp = AR5K_REG_MS(rxstat1,
  615. AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
  616. /*
  617. * Key table status
  618. */
  619. if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID)
  620. rs->rs_keyix = AR5K_REG_MS(rxstat1,
  621. AR5K_5212_RX_DESC_STATUS1_KEY_INDEX);
  622. else
  623. rs->rs_keyix = AR5K_RXKEYIX_INVALID;
  624. /*
  625. * Receive/descriptor errors
  626. */
  627. if (!(rxstat1 & AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK)) {
  628. if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_CRC_ERROR)
  629. rs->rs_status |= AR5K_RXERR_CRC;
  630. if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_PHY_ERROR) {
  631. rs->rs_status |= AR5K_RXERR_PHY;
  632. rs->rs_phyerr = AR5K_REG_MS(rxstat1,
  633. AR5K_5212_RX_DESC_STATUS1_PHY_ERROR_CODE);
  634. if (!ah->ah_capabilities.cap_has_phyerr_counters)
  635. ath5k_ani_phy_error_report(ah, rs->rs_phyerr);
  636. }
  637. if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
  638. rs->rs_status |= AR5K_RXERR_DECRYPT;
  639. if (rxstat1 & AR5K_5212_RX_DESC_STATUS1_MIC_ERROR)
  640. rs->rs_status |= AR5K_RXERR_MIC;
  641. }
  642. return 0;
  643. }
  644. /********\
  645. * Attach *
  646. \********/
  647. /**
  648. * ath5k_hw_init_desc_functions() - Init function pointers inside ah
  649. * @ah: The &struct ath5k_hw
  650. *
  651. * Maps the internal descriptor functions to the function pointers on ah, used
  652. * from above. This is used as an abstraction layer to handle the various chips
  653. * the same way.
  654. */
  655. int
  656. ath5k_hw_init_desc_functions(struct ath5k_hw *ah)
  657. {
  658. if (ah->ah_version == AR5K_AR5212) {
  659. ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
  660. ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
  661. ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status;
  662. } else if (ah->ah_version <= AR5K_AR5211) {
  663. ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
  664. ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
  665. ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status;
  666. } else
  667. return -ENOTSUPP;
  668. return 0;
  669. }