core.h 26 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. * Copyright (c) 2011-2012 Qualcomm Atheros, Inc.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. */
  17. #ifndef CORE_H
  18. #define CORE_H
  19. #include <linux/etherdevice.h>
  20. #include <linux/rtnetlink.h>
  21. #include <linux/firmware.h>
  22. #include <linux/sched.h>
  23. #include <linux/circ_buf.h>
  24. #include <net/cfg80211.h>
  25. #include "htc.h"
  26. #include "wmi.h"
  27. #include "bmi.h"
  28. #include "target.h"
  29. #define MAX_ATH6KL 1
  30. #define ATH6KL_MAX_RX_BUFFERS 16
  31. #define ATH6KL_BUFFER_SIZE 1664
  32. #define ATH6KL_MAX_AMSDU_RX_BUFFERS 4
  33. #define ATH6KL_AMSDU_REFILL_THRESHOLD 3
  34. #define ATH6KL_AMSDU_BUFFER_SIZE (WMI_MAX_AMSDU_RX_DATA_FRAME_LENGTH + 128)
  35. #define MAX_MSDU_SUBFRAME_PAYLOAD_LEN 1508
  36. #define MIN_MSDU_SUBFRAME_PAYLOAD_LEN 46
  37. #define USER_SAVEDKEYS_STAT_INIT 0
  38. #define USER_SAVEDKEYS_STAT_RUN 1
  39. #define ATH6KL_TX_TIMEOUT 10
  40. #define ATH6KL_MAX_ENDPOINTS 4
  41. #define MAX_NODE_NUM 15
  42. #define ATH6KL_APSD_ALL_FRAME 0xFFFF
  43. #define ATH6KL_APSD_NUM_OF_AC 0x4
  44. #define ATH6KL_APSD_FRAME_MASK 0xF
  45. /* Extra bytes for htc header alignment */
  46. #define ATH6KL_HTC_ALIGN_BYTES 3
  47. /* MAX_HI_COOKIE_NUM are reserved for high priority traffic */
  48. #define MAX_DEF_COOKIE_NUM 180
  49. #define MAX_HI_COOKIE_NUM 18 /* 10% of MAX_COOKIE_NUM */
  50. #define MAX_COOKIE_NUM (MAX_DEF_COOKIE_NUM + MAX_HI_COOKIE_NUM)
  51. #define MAX_DEFAULT_SEND_QUEUE_DEPTH (MAX_DEF_COOKIE_NUM / WMM_NUM_AC)
  52. #define DISCON_TIMER_INTVAL 10000 /* in msec */
  53. /* Channel dwell time in fg scan */
  54. #define ATH6KL_FG_SCAN_INTERVAL 50 /* in ms */
  55. /* includes also the null byte */
  56. #define ATH6KL_FIRMWARE_MAGIC "QCA-ATH6KL"
  57. enum ath6kl_fw_ie_type {
  58. ATH6KL_FW_IE_FW_VERSION = 0,
  59. ATH6KL_FW_IE_TIMESTAMP = 1,
  60. ATH6KL_FW_IE_OTP_IMAGE = 2,
  61. ATH6KL_FW_IE_FW_IMAGE = 3,
  62. ATH6KL_FW_IE_PATCH_IMAGE = 4,
  63. ATH6KL_FW_IE_RESERVED_RAM_SIZE = 5,
  64. ATH6KL_FW_IE_CAPABILITIES = 6,
  65. ATH6KL_FW_IE_PATCH_ADDR = 7,
  66. ATH6KL_FW_IE_BOARD_ADDR = 8,
  67. ATH6KL_FW_IE_VIF_MAX = 9,
  68. };
  69. enum ath6kl_fw_capability {
  70. ATH6KL_FW_CAPABILITY_HOST_P2P = 0,
  71. ATH6KL_FW_CAPABILITY_SCHED_SCAN = 1,
  72. /*
  73. * Firmware is capable of supporting P2P mgmt operations on a
  74. * station interface. After group formation, the station
  75. * interface will become a P2P client/GO interface as the case may be
  76. */
  77. ATH6KL_FW_CAPABILITY_STA_P2PDEV_DUPLEX,
  78. /*
  79. * Firmware has support to cleanup inactive stations
  80. * in AP mode.
  81. */
  82. ATH6KL_FW_CAPABILITY_INACTIVITY_TIMEOUT,
  83. /* Firmware has support to override rsn cap of rsn ie */
  84. ATH6KL_FW_CAPABILITY_RSN_CAP_OVERRIDE,
  85. /*
  86. * Multicast support in WOW and host awake mode.
  87. * Allow all multicast in host awake mode.
  88. * Apply multicast filter in WOW mode.
  89. */
  90. ATH6KL_FW_CAPABILITY_WOW_MULTICAST_FILTER,
  91. /* Firmware supports enhanced bmiss detection */
  92. ATH6KL_FW_CAPABILITY_BMISS_ENHANCE,
  93. /*
  94. * FW supports matching of ssid in schedule scan
  95. */
  96. ATH6KL_FW_CAPABILITY_SCHED_SCAN_MATCH_LIST,
  97. /* Firmware supports filtering BSS results by RSSI */
  98. ATH6KL_FW_CAPABILITY_RSSI_SCAN_THOLD,
  99. /* FW sets mac_addr[4] ^= 0x80 for newly created interfaces */
  100. ATH6KL_FW_CAPABILITY_CUSTOM_MAC_ADDR,
  101. /* Firmware supports TX error rate notification */
  102. ATH6KL_FW_CAPABILITY_TX_ERR_NOTIFY,
  103. /* supports WMI_SET_REGDOMAIN_CMDID command */
  104. ATH6KL_FW_CAPABILITY_REGDOMAIN,
  105. /* Firmware supports sched scan decoupled from host sleep */
  106. ATH6KL_FW_CAPABILITY_SCHED_SCAN_V2,
  107. /*
  108. * Firmware capability for hang detection through heart beat
  109. * challenge messages.
  110. */
  111. ATH6KL_FW_CAPABILITY_HEART_BEAT_POLL,
  112. /* WMI_SET_TX_SELECT_RATES_CMDID uses 64 bit size rate table */
  113. ATH6KL_FW_CAPABILITY_64BIT_RATES,
  114. /* WMI_AP_CONN_INACT_CMDID uses minutes as units */
  115. ATH6KL_FW_CAPABILITY_AP_INACTIVITY_MINS,
  116. /* use low priority endpoint for all data */
  117. ATH6KL_FW_CAPABILITY_MAP_LP_ENDPOINT,
  118. /* ratetable is the 2 stream version (max MCS15) */
  119. ATH6KL_FW_CAPABILITY_RATETABLE_MCS15,
  120. /* firmare doesn't support IP checksumming */
  121. ATH6KL_FW_CAPABILITY_NO_IP_CHECKSUM,
  122. /* this needs to be last */
  123. ATH6KL_FW_CAPABILITY_MAX,
  124. };
  125. #define ATH6KL_CAPABILITY_LEN (ALIGN(ATH6KL_FW_CAPABILITY_MAX, 32) / 32)
  126. struct ath6kl_fw_ie {
  127. __le32 id;
  128. __le32 len;
  129. u8 data[0];
  130. };
  131. enum ath6kl_hw_flags {
  132. ATH6KL_HW_SDIO_CRC_ERROR_WAR = BIT(3),
  133. };
  134. #define ATH6KL_FW_API2_FILE "fw-2.bin"
  135. #define ATH6KL_FW_API3_FILE "fw-3.bin"
  136. #define ATH6KL_FW_API4_FILE "fw-4.bin"
  137. #define ATH6KL_FW_API5_FILE "fw-5.bin"
  138. /* AR6003 1.0 definitions */
  139. #define AR6003_HW_1_0_VERSION 0x300002ba
  140. /* AR6003 2.0 definitions */
  141. #define AR6003_HW_2_0_VERSION 0x30000384
  142. #define AR6003_HW_2_0_PATCH_DOWNLOAD_ADDRESS 0x57e910
  143. #define AR6003_HW_2_0_FW_DIR "ath6k/AR6003/hw2.0"
  144. #define AR6003_HW_2_0_OTP_FILE "otp.bin.z77"
  145. #define AR6003_HW_2_0_FIRMWARE_FILE "athwlan.bin.z77"
  146. #define AR6003_HW_2_0_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
  147. #define AR6003_HW_2_0_PATCH_FILE "data.patch.bin"
  148. #define AR6003_HW_2_0_BOARD_DATA_FILE AR6003_HW_2_0_FW_DIR "/bdata.bin"
  149. #define AR6003_HW_2_0_DEFAULT_BOARD_DATA_FILE \
  150. AR6003_HW_2_0_FW_DIR "/bdata.SD31.bin"
  151. /* AR6003 3.0 definitions */
  152. #define AR6003_HW_2_1_1_VERSION 0x30000582
  153. #define AR6003_HW_2_1_1_FW_DIR "ath6k/AR6003/hw2.1.1"
  154. #define AR6003_HW_2_1_1_OTP_FILE "otp.bin"
  155. #define AR6003_HW_2_1_1_FIRMWARE_FILE "athwlan.bin"
  156. #define AR6003_HW_2_1_1_TCMD_FIRMWARE_FILE "athtcmd_ram.bin"
  157. #define AR6003_HW_2_1_1_UTF_FIRMWARE_FILE "utf.bin"
  158. #define AR6003_HW_2_1_1_TESTSCRIPT_FILE "nullTestFlow.bin"
  159. #define AR6003_HW_2_1_1_PATCH_FILE "data.patch.bin"
  160. #define AR6003_HW_2_1_1_BOARD_DATA_FILE AR6003_HW_2_1_1_FW_DIR "/bdata.bin"
  161. #define AR6003_HW_2_1_1_DEFAULT_BOARD_DATA_FILE \
  162. AR6003_HW_2_1_1_FW_DIR "/bdata.SD31.bin"
  163. /* AR6004 1.0 definitions */
  164. #define AR6004_HW_1_0_VERSION 0x30000623
  165. #define AR6004_HW_1_0_FW_DIR "ath6k/AR6004/hw1.0"
  166. #define AR6004_HW_1_0_FIRMWARE_FILE "fw.ram.bin"
  167. #define AR6004_HW_1_0_BOARD_DATA_FILE AR6004_HW_1_0_FW_DIR "/bdata.bin"
  168. #define AR6004_HW_1_0_DEFAULT_BOARD_DATA_FILE \
  169. AR6004_HW_1_0_FW_DIR "/bdata.DB132.bin"
  170. /* AR6004 1.1 definitions */
  171. #define AR6004_HW_1_1_VERSION 0x30000001
  172. #define AR6004_HW_1_1_FW_DIR "ath6k/AR6004/hw1.1"
  173. #define AR6004_HW_1_1_FIRMWARE_FILE "fw.ram.bin"
  174. #define AR6004_HW_1_1_BOARD_DATA_FILE AR6004_HW_1_1_FW_DIR "/bdata.bin"
  175. #define AR6004_HW_1_1_DEFAULT_BOARD_DATA_FILE \
  176. AR6004_HW_1_1_FW_DIR "/bdata.DB132.bin"
  177. /* AR6004 1.2 definitions */
  178. #define AR6004_HW_1_2_VERSION 0x300007e8
  179. #define AR6004_HW_1_2_FW_DIR "ath6k/AR6004/hw1.2"
  180. #define AR6004_HW_1_2_FIRMWARE_FILE "fw.ram.bin"
  181. #define AR6004_HW_1_2_BOARD_DATA_FILE AR6004_HW_1_2_FW_DIR "/bdata.bin"
  182. #define AR6004_HW_1_2_DEFAULT_BOARD_DATA_FILE \
  183. AR6004_HW_1_2_FW_DIR "/bdata.bin"
  184. /* AR6004 1.3 definitions */
  185. #define AR6004_HW_1_3_VERSION 0x31c8088a
  186. #define AR6004_HW_1_3_FW_DIR "ath6k/AR6004/hw1.3"
  187. #define AR6004_HW_1_3_FIRMWARE_FILE "fw.ram.bin"
  188. #define AR6004_HW_1_3_TCMD_FIRMWARE_FILE "utf.bin"
  189. #define AR6004_HW_1_3_UTF_FIRMWARE_FILE "utf.bin"
  190. #define AR6004_HW_1_3_TESTSCRIPT_FILE "nullTestFlow.bin"
  191. #define AR6004_HW_1_3_BOARD_DATA_FILE AR6004_HW_1_3_FW_DIR "/bdata.bin"
  192. #define AR6004_HW_1_3_DEFAULT_BOARD_DATA_FILE AR6004_HW_1_3_FW_DIR "/bdata.bin"
  193. /* AR6004 3.0 definitions */
  194. #define AR6004_HW_3_0_VERSION 0x31C809F8
  195. #define AR6004_HW_3_0_FW_DIR "ath6k/AR6004/hw3.0"
  196. #define AR6004_HW_3_0_FIRMWARE_FILE "fw.ram.bin"
  197. #define AR6004_HW_3_0_TCMD_FIRMWARE_FILE "utf.bin"
  198. #define AR6004_HW_3_0_UTF_FIRMWARE_FILE "utf.bin"
  199. #define AR6004_HW_3_0_TESTSCRIPT_FILE "nullTestFlow.bin"
  200. #define AR6004_HW_3_0_BOARD_DATA_FILE AR6004_HW_3_0_FW_DIR "/bdata.bin"
  201. #define AR6004_HW_3_0_DEFAULT_BOARD_DATA_FILE AR6004_HW_3_0_FW_DIR "/bdata.bin"
  202. /* Per STA data, used in AP mode */
  203. #define STA_PS_AWAKE BIT(0)
  204. #define STA_PS_SLEEP BIT(1)
  205. #define STA_PS_POLLED BIT(2)
  206. #define STA_PS_APSD_TRIGGER BIT(3)
  207. #define STA_PS_APSD_EOSP BIT(4)
  208. /* HTC TX packet tagging definitions */
  209. #define ATH6KL_CONTROL_PKT_TAG HTC_TX_PACKET_TAG_USER_DEFINED
  210. #define ATH6KL_DATA_PKT_TAG (ATH6KL_CONTROL_PKT_TAG + 1)
  211. #define AR6003_CUST_DATA_SIZE 16
  212. #define AGGR_WIN_IDX(x, y) ((x) % (y))
  213. #define AGGR_INCR_IDX(x, y) AGGR_WIN_IDX(((x) + 1), (y))
  214. #define AGGR_DCRM_IDX(x, y) AGGR_WIN_IDX(((x) - 1), (y))
  215. #define ATH6KL_MAX_SEQ_NO 0xFFF
  216. #define ATH6KL_NEXT_SEQ_NO(x) (((x) + 1) & ATH6KL_MAX_SEQ_NO)
  217. #define NUM_OF_TIDS 8
  218. #define AGGR_SZ_DEFAULT 8
  219. #define AGGR_WIN_SZ_MIN 2
  220. #define AGGR_WIN_SZ_MAX 8
  221. #define TID_WINDOW_SZ(_x) ((_x) << 1)
  222. #define AGGR_NUM_OF_FREE_NETBUFS 16
  223. #define AGGR_RX_TIMEOUT 100 /* in ms */
  224. #define WMI_TIMEOUT (2 * HZ)
  225. #define MBOX_YIELD_LIMIT 99
  226. #define ATH6KL_DEFAULT_LISTEN_INTVAL 100 /* in TUs */
  227. #define ATH6KL_DEFAULT_BMISS_TIME 1500
  228. #define ATH6KL_MAX_WOW_LISTEN_INTL 300 /* in TUs */
  229. #define ATH6KL_MAX_BMISS_TIME 5000
  230. /* configuration lags */
  231. /*
  232. * ATH6KL_CONF_IGNORE_ERP_BARKER: Ignore the barker premable in
  233. * ERP IE of beacon to determine the short premable support when
  234. * sending (Re)Assoc req.
  235. * ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN: Don't send the power
  236. * module state transition failure events which happen during
  237. * scan, to the host.
  238. */
  239. #define ATH6KL_CONF_IGNORE_ERP_BARKER BIT(0)
  240. #define ATH6KL_CONF_IGNORE_PS_FAIL_EVT_IN_SCAN BIT(1)
  241. #define ATH6KL_CONF_ENABLE_11N BIT(2)
  242. #define ATH6KL_CONF_ENABLE_TX_BURST BIT(3)
  243. #define ATH6KL_CONF_UART_DEBUG BIT(4)
  244. #define P2P_WILDCARD_SSID_LEN 7 /* DIRECT- */
  245. enum wlan_low_pwr_state {
  246. WLAN_POWER_STATE_ON,
  247. WLAN_POWER_STATE_CUT_PWR,
  248. WLAN_POWER_STATE_DEEP_SLEEP,
  249. WLAN_POWER_STATE_WOW
  250. };
  251. enum sme_state {
  252. SME_DISCONNECTED,
  253. SME_CONNECTING,
  254. SME_CONNECTED
  255. };
  256. struct skb_hold_q {
  257. struct sk_buff *skb;
  258. bool is_amsdu;
  259. u16 seq_no;
  260. };
  261. struct rxtid {
  262. bool aggr;
  263. bool timer_mon;
  264. u16 win_sz;
  265. u16 seq_next;
  266. u32 hold_q_sz;
  267. struct skb_hold_q *hold_q;
  268. struct sk_buff_head q;
  269. /*
  270. * lock mainly protects seq_next and hold_q. Movement of seq_next
  271. * needs to be protected between aggr_timeout() and
  272. * aggr_process_recv_frm(). hold_q will be holding the pending
  273. * reorder frames and it's access should also be protected.
  274. * Some of the other fields like hold_q_sz, win_sz and aggr are
  275. * initialized/reset when receiving addba/delba req, also while
  276. * deleting aggr state all the pending buffers are flushed before
  277. * resetting these fields, so there should not be any race in accessing
  278. * these fields.
  279. */
  280. spinlock_t lock;
  281. };
  282. struct rxtid_stats {
  283. u32 num_into_aggr;
  284. u32 num_dups;
  285. u32 num_oow;
  286. u32 num_mpdu;
  287. u32 num_amsdu;
  288. u32 num_delivered;
  289. u32 num_timeouts;
  290. u32 num_hole;
  291. u32 num_bar;
  292. };
  293. struct aggr_info_conn {
  294. u8 aggr_sz;
  295. u8 timer_scheduled;
  296. struct timer_list timer;
  297. struct net_device *dev;
  298. struct rxtid rx_tid[NUM_OF_TIDS];
  299. struct rxtid_stats stat[NUM_OF_TIDS];
  300. struct aggr_info *aggr_info;
  301. };
  302. struct aggr_info {
  303. struct aggr_info_conn *aggr_conn;
  304. struct sk_buff_head rx_amsdu_freeq;
  305. };
  306. struct ath6kl_wep_key {
  307. u8 key_index;
  308. u8 key_len;
  309. u8 key[64];
  310. };
  311. #define ATH6KL_KEY_SEQ_LEN 8
  312. struct ath6kl_key {
  313. u8 key[WLAN_MAX_KEY_LEN];
  314. u8 key_len;
  315. u8 seq[ATH6KL_KEY_SEQ_LEN];
  316. u8 seq_len;
  317. u32 cipher;
  318. };
  319. struct ath6kl_node_mapping {
  320. u8 mac_addr[ETH_ALEN];
  321. u8 ep_id;
  322. u8 tx_pend;
  323. };
  324. struct ath6kl_cookie {
  325. struct sk_buff *skb;
  326. u32 map_no;
  327. struct htc_packet htc_pkt;
  328. struct ath6kl_cookie *arc_list_next;
  329. };
  330. struct ath6kl_mgmt_buff {
  331. struct list_head list;
  332. u32 freq;
  333. u32 wait;
  334. u32 id;
  335. bool no_cck;
  336. size_t len;
  337. u8 buf[0];
  338. };
  339. struct ath6kl_sta {
  340. u16 sta_flags;
  341. u8 mac[ETH_ALEN];
  342. u8 aid;
  343. u8 keymgmt;
  344. u8 ucipher;
  345. u8 auth;
  346. u8 wpa_ie[ATH6KL_MAX_IE];
  347. struct sk_buff_head psq;
  348. /* protects psq, mgmt_psq, apsdq, and mgmt_psq_len fields */
  349. spinlock_t psq_lock;
  350. struct list_head mgmt_psq;
  351. size_t mgmt_psq_len;
  352. u8 apsd_info;
  353. struct sk_buff_head apsdq;
  354. struct aggr_info_conn *aggr_conn;
  355. };
  356. struct ath6kl_version {
  357. u32 target_ver;
  358. u32 wlan_ver;
  359. u32 abi_ver;
  360. };
  361. struct ath6kl_bmi {
  362. u32 cmd_credits;
  363. bool done_sent;
  364. u8 *cmd_buf;
  365. u32 max_data_size;
  366. u32 max_cmd_size;
  367. };
  368. struct target_stats {
  369. u64 tx_pkt;
  370. u64 tx_byte;
  371. u64 tx_ucast_pkt;
  372. u64 tx_ucast_byte;
  373. u64 tx_mcast_pkt;
  374. u64 tx_mcast_byte;
  375. u64 tx_bcast_pkt;
  376. u64 tx_bcast_byte;
  377. u64 tx_rts_success_cnt;
  378. u64 tx_pkt_per_ac[4];
  379. u64 tx_err;
  380. u64 tx_fail_cnt;
  381. u64 tx_retry_cnt;
  382. u64 tx_mult_retry_cnt;
  383. u64 tx_rts_fail_cnt;
  384. u64 rx_pkt;
  385. u64 rx_byte;
  386. u64 rx_ucast_pkt;
  387. u64 rx_ucast_byte;
  388. u64 rx_mcast_pkt;
  389. u64 rx_mcast_byte;
  390. u64 rx_bcast_pkt;
  391. u64 rx_bcast_byte;
  392. u64 rx_frgment_pkt;
  393. u64 rx_err;
  394. u64 rx_crc_err;
  395. u64 rx_key_cache_miss;
  396. u64 rx_decrypt_err;
  397. u64 rx_dupl_frame;
  398. u64 tkip_local_mic_fail;
  399. u64 tkip_cnter_measures_invoked;
  400. u64 tkip_replays;
  401. u64 tkip_fmt_err;
  402. u64 ccmp_fmt_err;
  403. u64 ccmp_replays;
  404. u64 pwr_save_fail_cnt;
  405. u64 cs_bmiss_cnt;
  406. u64 cs_low_rssi_cnt;
  407. u64 cs_connect_cnt;
  408. u64 cs_discon_cnt;
  409. s32 tx_ucast_rate;
  410. s32 rx_ucast_rate;
  411. u32 lq_val;
  412. u32 wow_pkt_dropped;
  413. u16 wow_evt_discarded;
  414. s16 noise_floor_calib;
  415. s16 cs_rssi;
  416. s16 cs_ave_beacon_rssi;
  417. u8 cs_ave_beacon_snr;
  418. u8 cs_last_roam_msec;
  419. u8 cs_snr;
  420. u8 wow_host_pkt_wakeups;
  421. u8 wow_host_evt_wakeups;
  422. u32 arp_received;
  423. u32 arp_matched;
  424. u32 arp_replied;
  425. };
  426. struct ath6kl_mbox_info {
  427. u32 htc_addr;
  428. u32 htc_ext_addr;
  429. u32 htc_ext_sz;
  430. u32 block_size;
  431. u32 gmbox_addr;
  432. u32 gmbox_sz;
  433. };
  434. /*
  435. * 802.11i defines an extended IV for use with non-WEP ciphers.
  436. * When the EXTIV bit is set in the key id byte an additional
  437. * 4 bytes immediately follow the IV for TKIP. For CCMP the
  438. * EXTIV bit is likewise set but the 8 bytes represent the
  439. * CCMP header rather than IV+extended-IV.
  440. */
  441. #define ATH6KL_KEYBUF_SIZE 16
  442. #define ATH6KL_MICBUF_SIZE (8+8) /* space for both tx and rx */
  443. #define ATH6KL_KEY_XMIT 0x01
  444. #define ATH6KL_KEY_RECV 0x02
  445. #define ATH6KL_KEY_DEFAULT 0x80 /* default xmit key */
  446. /* Initial group key for AP mode */
  447. struct ath6kl_req_key {
  448. bool valid;
  449. u8 key_index;
  450. int key_type;
  451. u8 key[WLAN_MAX_KEY_LEN];
  452. u8 key_len;
  453. };
  454. enum ath6kl_hif_type {
  455. ATH6KL_HIF_TYPE_SDIO,
  456. ATH6KL_HIF_TYPE_USB,
  457. };
  458. enum ath6kl_htc_type {
  459. ATH6KL_HTC_TYPE_MBOX,
  460. ATH6KL_HTC_TYPE_PIPE,
  461. };
  462. /* Max number of filters that hw supports */
  463. #define ATH6K_MAX_MC_FILTERS_PER_LIST 7
  464. struct ath6kl_mc_filter {
  465. struct list_head list;
  466. char hw_addr[ATH6KL_MCAST_FILTER_MAC_ADDR_SIZE];
  467. };
  468. struct ath6kl_htcap {
  469. bool ht_enable;
  470. u8 ampdu_factor;
  471. unsigned short cap_info;
  472. };
  473. /*
  474. * Driver's maximum limit, note that some firmwares support only one vif
  475. * and the runtime (current) limit must be checked from ar->vif_max.
  476. */
  477. #define ATH6KL_VIF_MAX 3
  478. /* vif flags info */
  479. enum ath6kl_vif_state {
  480. CONNECTED,
  481. CONNECT_PEND,
  482. WMM_ENABLED,
  483. NETQ_STOPPED,
  484. DTIM_EXPIRED,
  485. CLEAR_BSSFILTER_ON_BEACON,
  486. DTIM_PERIOD_AVAIL,
  487. WLAN_ENABLED,
  488. STATS_UPDATE_PEND,
  489. HOST_SLEEP_MODE_CMD_PROCESSED,
  490. NETDEV_MCAST_ALL_ON,
  491. NETDEV_MCAST_ALL_OFF,
  492. SCHED_SCANNING,
  493. };
  494. struct ath6kl_vif {
  495. struct list_head list;
  496. struct wireless_dev wdev;
  497. struct net_device *ndev;
  498. struct ath6kl *ar;
  499. /* Lock to protect vif specific net_stats and flags */
  500. spinlock_t if_lock;
  501. u8 fw_vif_idx;
  502. unsigned long flags;
  503. int ssid_len;
  504. u8 ssid[IEEE80211_MAX_SSID_LEN];
  505. u8 dot11_auth_mode;
  506. u8 auth_mode;
  507. u8 prwise_crypto;
  508. u8 prwise_crypto_len;
  509. u8 grp_crypto;
  510. u8 grp_crypto_len;
  511. u8 def_txkey_index;
  512. u8 next_mode;
  513. u8 nw_type;
  514. u8 bssid[ETH_ALEN];
  515. u8 req_bssid[ETH_ALEN];
  516. u16 ch_hint;
  517. u16 bss_ch;
  518. struct ath6kl_wep_key wep_key_list[WMI_MAX_KEY_INDEX + 1];
  519. struct ath6kl_key keys[WMI_MAX_KEY_INDEX + 1];
  520. struct aggr_info *aggr_cntxt;
  521. struct ath6kl_htcap htcap[IEEE80211_NUM_BANDS];
  522. struct timer_list disconnect_timer;
  523. struct timer_list sched_scan_timer;
  524. struct cfg80211_scan_request *scan_req;
  525. enum sme_state sme_state;
  526. int reconnect_flag;
  527. u32 last_roc_id;
  528. u32 last_cancel_roc_id;
  529. u32 send_action_id;
  530. bool probe_req_report;
  531. u16 assoc_bss_beacon_int;
  532. u16 listen_intvl_t;
  533. u16 bmiss_time_t;
  534. u32 txe_intvl;
  535. u16 bg_scan_period;
  536. u8 assoc_bss_dtim_period;
  537. struct net_device_stats net_stats;
  538. struct target_stats target_stats;
  539. struct wmi_connect_cmd profile;
  540. u16 rsn_capab;
  541. struct list_head mc_filter;
  542. };
  543. static inline struct ath6kl_vif *ath6kl_vif_from_wdev(struct wireless_dev *wdev)
  544. {
  545. return container_of(wdev, struct ath6kl_vif, wdev);
  546. }
  547. #define WOW_LIST_ID 0
  548. #define WOW_HOST_REQ_DELAY 500 /* ms */
  549. #define ATH6KL_SCHED_SCAN_RESULT_DELAY 5000 /* ms */
  550. /* Flag info */
  551. enum ath6kl_dev_state {
  552. WMI_ENABLED,
  553. WMI_READY,
  554. WMI_CTRL_EP_FULL,
  555. TESTMODE,
  556. DESTROY_IN_PROGRESS,
  557. SKIP_SCAN,
  558. ROAM_TBL_PEND,
  559. FIRST_BOOT,
  560. RECOVERY_CLEANUP,
  561. };
  562. enum ath6kl_state {
  563. ATH6KL_STATE_OFF,
  564. ATH6KL_STATE_ON,
  565. ATH6KL_STATE_SUSPENDING,
  566. ATH6KL_STATE_RESUMING,
  567. ATH6KL_STATE_DEEPSLEEP,
  568. ATH6KL_STATE_CUTPOWER,
  569. ATH6KL_STATE_WOW,
  570. ATH6KL_STATE_RECOVERY,
  571. };
  572. /* Fw error recovery */
  573. #define ATH6KL_HB_RESP_MISS_THRES 5
  574. enum ath6kl_fw_err {
  575. ATH6KL_FW_ASSERT,
  576. ATH6KL_FW_HB_RESP_FAILURE,
  577. ATH6KL_FW_EP_FULL,
  578. };
  579. struct ath6kl {
  580. struct device *dev;
  581. struct wiphy *wiphy;
  582. enum ath6kl_state state;
  583. unsigned int testmode;
  584. struct ath6kl_bmi bmi;
  585. const struct ath6kl_hif_ops *hif_ops;
  586. const struct ath6kl_htc_ops *htc_ops;
  587. struct wmi *wmi;
  588. int tx_pending[ENDPOINT_MAX];
  589. int total_tx_data_pend;
  590. struct htc_target *htc_target;
  591. enum ath6kl_hif_type hif_type;
  592. void *hif_priv;
  593. struct list_head vif_list;
  594. /* Lock to avoid race in vif_list entries among add/del/traverse */
  595. spinlock_t list_lock;
  596. u8 num_vif;
  597. unsigned int vif_max;
  598. u8 max_norm_iface;
  599. u8 avail_idx_map;
  600. /*
  601. * Protects at least amsdu_rx_buffer_queue, ath6kl_alloc_cookie()
  602. * calls, tx_pending and total_tx_data_pend.
  603. */
  604. spinlock_t lock;
  605. struct semaphore sem;
  606. u8 lrssi_roam_threshold;
  607. struct ath6kl_version version;
  608. u32 target_type;
  609. u8 tx_pwr;
  610. struct ath6kl_node_mapping node_map[MAX_NODE_NUM];
  611. u8 ibss_ps_enable;
  612. bool ibss_if_active;
  613. u8 node_num;
  614. u8 next_ep_id;
  615. struct ath6kl_cookie *cookie_list;
  616. u32 cookie_count;
  617. enum htc_endpoint_id ac2ep_map[WMM_NUM_AC];
  618. bool ac_stream_active[WMM_NUM_AC];
  619. u8 ac_stream_pri_map[WMM_NUM_AC];
  620. u8 hiac_stream_active_pri;
  621. u8 ep2ac_map[ENDPOINT_MAX];
  622. enum htc_endpoint_id ctrl_ep;
  623. struct ath6kl_htc_credit_info credit_state_info;
  624. u32 connect_ctrl_flags;
  625. u32 user_key_ctrl;
  626. u8 usr_bss_filter;
  627. struct ath6kl_sta sta_list[AP_MAX_NUM_STA];
  628. u8 sta_list_index;
  629. struct ath6kl_req_key ap_mode_bkey;
  630. struct sk_buff_head mcastpsq;
  631. u32 want_ch_switch;
  632. u16 last_ch;
  633. /*
  634. * FIXME: protects access to mcastpsq but is actually useless as
  635. * all skbe_queue_*() functions provide serialisation themselves
  636. */
  637. spinlock_t mcastpsq_lock;
  638. u8 intra_bss;
  639. struct wmi_ap_mode_stat ap_stats;
  640. u8 ap_country_code[3];
  641. struct list_head amsdu_rx_buffer_queue;
  642. u8 rx_meta_ver;
  643. enum wlan_low_pwr_state wlan_pwr_state;
  644. u8 mac_addr[ETH_ALEN];
  645. #define AR_MCAST_FILTER_MAC_ADDR_SIZE 4
  646. struct {
  647. void *rx_report;
  648. size_t rx_report_len;
  649. } tm;
  650. struct ath6kl_hw {
  651. u32 id;
  652. const char *name;
  653. u32 dataset_patch_addr;
  654. u32 app_load_addr;
  655. u32 app_start_override_addr;
  656. u32 board_ext_data_addr;
  657. u32 reserved_ram_size;
  658. u32 board_addr;
  659. u32 refclk_hz;
  660. u32 uarttx_pin;
  661. u32 testscript_addr;
  662. u8 tx_ant;
  663. u8 rx_ant;
  664. enum wmi_phy_cap cap;
  665. u32 flags;
  666. struct ath6kl_hw_fw {
  667. const char *dir;
  668. const char *otp;
  669. const char *fw;
  670. const char *tcmd;
  671. const char *patch;
  672. const char *utf;
  673. const char *testscript;
  674. } fw;
  675. const char *fw_board;
  676. const char *fw_default_board;
  677. } hw;
  678. u16 conf_flags;
  679. u16 suspend_mode;
  680. u16 wow_suspend_mode;
  681. wait_queue_head_t event_wq;
  682. struct ath6kl_mbox_info mbox_info;
  683. struct ath6kl_cookie cookie_mem[MAX_COOKIE_NUM];
  684. unsigned long flag;
  685. u8 *fw_board;
  686. size_t fw_board_len;
  687. u8 *fw_otp;
  688. size_t fw_otp_len;
  689. u8 *fw;
  690. size_t fw_len;
  691. u8 *fw_patch;
  692. size_t fw_patch_len;
  693. u8 *fw_testscript;
  694. size_t fw_testscript_len;
  695. unsigned int fw_api;
  696. unsigned long fw_capabilities[ATH6KL_CAPABILITY_LEN];
  697. struct workqueue_struct *ath6kl_wq;
  698. struct dentry *debugfs_phy;
  699. bool p2p;
  700. bool wiphy_registered;
  701. struct ath6kl_fw_recovery {
  702. struct work_struct recovery_work;
  703. unsigned long err_reason;
  704. unsigned long hb_poll;
  705. struct timer_list hb_timer;
  706. u32 seq_num;
  707. bool hb_pending;
  708. u8 hb_misscnt;
  709. bool enable;
  710. } fw_recovery;
  711. #ifdef CONFIG_ATH6KL_DEBUG
  712. struct {
  713. struct sk_buff_head fwlog_queue;
  714. struct completion fwlog_completion;
  715. bool fwlog_open;
  716. u32 fwlog_mask;
  717. unsigned int dbgfs_diag_reg;
  718. u32 diag_reg_addr_wr;
  719. u32 diag_reg_val_wr;
  720. struct {
  721. unsigned int invalid_rate;
  722. } war_stats;
  723. u8 *roam_tbl;
  724. unsigned int roam_tbl_len;
  725. u8 keepalive;
  726. u8 disc_timeout;
  727. } debug;
  728. #endif /* CONFIG_ATH6KL_DEBUG */
  729. };
  730. static inline struct ath6kl *ath6kl_priv(struct net_device *dev)
  731. {
  732. return ((struct ath6kl_vif *) netdev_priv(dev))->ar;
  733. }
  734. static inline u32 ath6kl_get_hi_item_addr(struct ath6kl *ar,
  735. u32 item_offset)
  736. {
  737. u32 addr = 0;
  738. if (ar->target_type == TARGET_TYPE_AR6003)
  739. addr = ATH6KL_AR6003_HI_START_ADDR + item_offset;
  740. else if (ar->target_type == TARGET_TYPE_AR6004)
  741. addr = ATH6KL_AR6004_HI_START_ADDR + item_offset;
  742. return addr;
  743. }
  744. int ath6kl_configure_target(struct ath6kl *ar);
  745. void ath6kl_detect_error(unsigned long ptr);
  746. void disconnect_timer_handler(unsigned long ptr);
  747. void init_netdev(struct net_device *dev);
  748. void ath6kl_cookie_init(struct ath6kl *ar);
  749. void ath6kl_cookie_cleanup(struct ath6kl *ar);
  750. void ath6kl_rx(struct htc_target *target, struct htc_packet *packet);
  751. void ath6kl_tx_complete(struct htc_target *context,
  752. struct list_head *packet_queue);
  753. enum htc_send_full_action ath6kl_tx_queue_full(struct htc_target *target,
  754. struct htc_packet *packet);
  755. void ath6kl_stop_txrx(struct ath6kl *ar);
  756. void ath6kl_cleanup_amsdu_rxbufs(struct ath6kl *ar);
  757. int ath6kl_diag_write32(struct ath6kl *ar, u32 address, __le32 value);
  758. int ath6kl_diag_write(struct ath6kl *ar, u32 address, void *data, u32 length);
  759. int ath6kl_diag_read32(struct ath6kl *ar, u32 address, u32 *value);
  760. int ath6kl_diag_read(struct ath6kl *ar, u32 address, void *data, u32 length);
  761. int ath6kl_read_fwlogs(struct ath6kl *ar);
  762. void ath6kl_init_profile_info(struct ath6kl_vif *vif);
  763. void ath6kl_tx_data_cleanup(struct ath6kl *ar);
  764. struct ath6kl_cookie *ath6kl_alloc_cookie(struct ath6kl *ar);
  765. void ath6kl_free_cookie(struct ath6kl *ar, struct ath6kl_cookie *cookie);
  766. int ath6kl_data_tx(struct sk_buff *skb, struct net_device *dev);
  767. struct aggr_info *aggr_init(struct ath6kl_vif *vif);
  768. void aggr_conn_init(struct ath6kl_vif *vif, struct aggr_info *aggr_info,
  769. struct aggr_info_conn *aggr_conn);
  770. void ath6kl_rx_refill(struct htc_target *target,
  771. enum htc_endpoint_id endpoint);
  772. void ath6kl_refill_amsdu_rxbufs(struct ath6kl *ar, int count);
  773. struct htc_packet *ath6kl_alloc_amsdu_rxbuf(struct htc_target *target,
  774. enum htc_endpoint_id endpoint,
  775. int len);
  776. void aggr_module_destroy(struct aggr_info *aggr_info);
  777. void aggr_reset_state(struct aggr_info_conn *aggr_conn);
  778. struct ath6kl_sta *ath6kl_find_sta(struct ath6kl_vif *vif, u8 *node_addr);
  779. struct ath6kl_sta *ath6kl_find_sta_by_aid(struct ath6kl *ar, u8 aid);
  780. void ath6kl_ready_event(void *devt, u8 *datap, u32 sw_ver, u32 abi_ver,
  781. enum wmi_phy_cap cap);
  782. int ath6kl_control_tx(void *devt, struct sk_buff *skb,
  783. enum htc_endpoint_id eid);
  784. void ath6kl_connect_event(struct ath6kl_vif *vif, u16 channel,
  785. u8 *bssid, u16 listen_int,
  786. u16 beacon_int, enum network_type net_type,
  787. u8 beacon_ie_len, u8 assoc_req_len,
  788. u8 assoc_resp_len, u8 *assoc_info);
  789. void ath6kl_connect_ap_mode_bss(struct ath6kl_vif *vif, u16 channel);
  790. void ath6kl_connect_ap_mode_sta(struct ath6kl_vif *vif, u16 aid, u8 *mac_addr,
  791. u8 keymgmt, u8 ucipher, u8 auth,
  792. u8 assoc_req_len, u8 *assoc_info, u8 apsd_info);
  793. void ath6kl_disconnect_event(struct ath6kl_vif *vif, u8 reason,
  794. u8 *bssid, u8 assoc_resp_len,
  795. u8 *assoc_info, u16 prot_reason_status);
  796. void ath6kl_tkip_micerr_event(struct ath6kl_vif *vif, u8 keyid, bool ismcast);
  797. void ath6kl_txpwr_rx_evt(void *devt, u8 tx_pwr);
  798. void ath6kl_scan_complete_evt(struct ath6kl_vif *vif, int status);
  799. void ath6kl_tgt_stats_event(struct ath6kl_vif *vif, u8 *ptr, u32 len);
  800. void ath6kl_indicate_tx_activity(void *devt, u8 traffic_class, bool active);
  801. enum htc_endpoint_id ath6kl_ac2_endpoint_id(void *devt, u8 ac);
  802. void ath6kl_pspoll_event(struct ath6kl_vif *vif, u8 aid);
  803. void ath6kl_dtimexpiry_event(struct ath6kl_vif *vif);
  804. void ath6kl_disconnect(struct ath6kl_vif *vif);
  805. void aggr_recv_delba_req_evt(struct ath6kl_vif *vif, u8 tid);
  806. void aggr_recv_addba_req_evt(struct ath6kl_vif *vif, u8 tid, u16 seq_no,
  807. u8 win_sz);
  808. void ath6kl_wakeup_event(void *dev);
  809. void ath6kl_init_control_info(struct ath6kl_vif *vif);
  810. struct ath6kl_vif *ath6kl_vif_first(struct ath6kl *ar);
  811. void ath6kl_cfg80211_vif_stop(struct ath6kl_vif *vif, bool wmi_ready);
  812. int ath6kl_init_hw_start(struct ath6kl *ar);
  813. int ath6kl_init_hw_stop(struct ath6kl *ar);
  814. int ath6kl_init_fetch_firmwares(struct ath6kl *ar);
  815. int ath6kl_init_hw_params(struct ath6kl *ar);
  816. void ath6kl_check_wow_status(struct ath6kl *ar);
  817. void ath6kl_core_tx_complete(struct ath6kl *ar, struct sk_buff *skb);
  818. void ath6kl_core_rx_complete(struct ath6kl *ar, struct sk_buff *skb, u8 pipe);
  819. struct ath6kl *ath6kl_core_create(struct device *dev);
  820. int ath6kl_core_init(struct ath6kl *ar, enum ath6kl_htc_type htc_type);
  821. void ath6kl_core_cleanup(struct ath6kl *ar);
  822. void ath6kl_core_destroy(struct ath6kl *ar);
  823. /* Fw error recovery */
  824. void ath6kl_init_hw_restart(struct ath6kl *ar);
  825. void ath6kl_recovery_err_notify(struct ath6kl *ar, enum ath6kl_fw_err reason);
  826. void ath6kl_recovery_hb_event(struct ath6kl *ar, u32 cookie);
  827. void ath6kl_recovery_init(struct ath6kl *ar);
  828. void ath6kl_recovery_cleanup(struct ath6kl *ar);
  829. void ath6kl_recovery_suspend(struct ath6kl *ar);
  830. void ath6kl_recovery_resume(struct ath6kl *ar);
  831. #endif /* CORE_H */