wmi.h 4.9 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef WMI_H
  17. #define WMI_H
  18. struct wmi_event_txrate {
  19. __be32 txrate;
  20. struct {
  21. u8 rssi_thresh;
  22. u8 per;
  23. } rc_stats;
  24. } __packed;
  25. struct wmi_cmd_hdr {
  26. __be16 command_id;
  27. __be16 seq_no;
  28. } __packed;
  29. struct wmi_fw_version {
  30. __be16 major;
  31. __be16 minor;
  32. } __packed;
  33. struct wmi_event_swba {
  34. __be64 tsf;
  35. u8 beacon_pending;
  36. } __packed;
  37. /*
  38. * 64 - HTC header - WMI header - 1 / txstatus
  39. * And some other hdr. space is also accounted for.
  40. * 12 seems to be the magic number.
  41. */
  42. #define HTC_MAX_TX_STATUS 12
  43. #define ATH9K_HTC_TXSTAT_ACK BIT(0)
  44. #define ATH9K_HTC_TXSTAT_FILT BIT(1)
  45. #define ATH9K_HTC_TXSTAT_RTC_CTS BIT(2)
  46. #define ATH9K_HTC_TXSTAT_MCS BIT(3)
  47. #define ATH9K_HTC_TXSTAT_CW40 BIT(4)
  48. #define ATH9K_HTC_TXSTAT_SGI BIT(5)
  49. /*
  50. * Legacy rates are indicated as indices.
  51. * HT rates are indicated as dot11 numbers.
  52. * This allows us to resrict the rate field
  53. * to 4 bits.
  54. */
  55. #define ATH9K_HTC_TXSTAT_RATE 0x0f
  56. #define ATH9K_HTC_TXSTAT_RATE_S 0
  57. #define ATH9K_HTC_TXSTAT_EPID 0xf0
  58. #define ATH9K_HTC_TXSTAT_EPID_S 4
  59. struct __wmi_event_txstatus {
  60. u8 cookie;
  61. u8 ts_rate; /* Also holds EP ID */
  62. u8 ts_flags;
  63. };
  64. struct wmi_event_txstatus {
  65. u8 cnt;
  66. struct __wmi_event_txstatus txstatus[HTC_MAX_TX_STATUS];
  67. } __packed;
  68. enum wmi_cmd_id {
  69. WMI_ECHO_CMDID = 0x0001,
  70. WMI_ACCESS_MEMORY_CMDID,
  71. /* Commands to Target */
  72. WMI_GET_FW_VERSION,
  73. WMI_DISABLE_INTR_CMDID,
  74. WMI_ENABLE_INTR_CMDID,
  75. WMI_ATH_INIT_CMDID,
  76. WMI_ABORT_TXQ_CMDID,
  77. WMI_STOP_TX_DMA_CMDID,
  78. WMI_ABORT_TX_DMA_CMDID,
  79. WMI_DRAIN_TXQ_CMDID,
  80. WMI_DRAIN_TXQ_ALL_CMDID,
  81. WMI_START_RECV_CMDID,
  82. WMI_STOP_RECV_CMDID,
  83. WMI_FLUSH_RECV_CMDID,
  84. WMI_SET_MODE_CMDID,
  85. WMI_NODE_CREATE_CMDID,
  86. WMI_NODE_REMOVE_CMDID,
  87. WMI_VAP_REMOVE_CMDID,
  88. WMI_VAP_CREATE_CMDID,
  89. WMI_REG_READ_CMDID,
  90. WMI_REG_WRITE_CMDID,
  91. WMI_RC_STATE_CHANGE_CMDID,
  92. WMI_RC_RATE_UPDATE_CMDID,
  93. WMI_TARGET_IC_UPDATE_CMDID,
  94. WMI_TX_AGGR_ENABLE_CMDID,
  95. WMI_TGT_DETACH_CMDID,
  96. WMI_NODE_UPDATE_CMDID,
  97. WMI_INT_STATS_CMDID,
  98. WMI_TX_STATS_CMDID,
  99. WMI_RX_STATS_CMDID,
  100. WMI_BITRATE_MASK_CMDID,
  101. WMI_REG_RMW_CMDID,
  102. };
  103. enum wmi_event_id {
  104. WMI_TGT_RDY_EVENTID = 0x1001,
  105. WMI_SWBA_EVENTID,
  106. WMI_FATAL_EVENTID,
  107. WMI_TXTO_EVENTID,
  108. WMI_BMISS_EVENTID,
  109. WMI_DELBA_EVENTID,
  110. WMI_TXSTATUS_EVENTID,
  111. };
  112. #define MAX_CMD_NUMBER 62
  113. #define MAX_RMW_CMD_NUMBER 15
  114. struct register_write {
  115. __be32 reg;
  116. __be32 val;
  117. };
  118. struct register_rmw {
  119. __be32 reg;
  120. __be32 set;
  121. __be32 clr;
  122. } __packed;
  123. struct ath9k_htc_tx_event {
  124. int count;
  125. struct __wmi_event_txstatus txs;
  126. struct list_head list;
  127. };
  128. struct wmi {
  129. struct ath9k_htc_priv *drv_priv;
  130. struct htc_target *htc;
  131. enum htc_endpoint_id ctrl_epid;
  132. struct mutex op_mutex;
  133. struct completion cmd_wait;
  134. u16 last_seq_id;
  135. struct sk_buff_head wmi_event_queue;
  136. struct tasklet_struct wmi_event_tasklet;
  137. u16 tx_seq_id;
  138. u8 *cmd_rsp_buf;
  139. u32 cmd_rsp_len;
  140. bool stopped;
  141. struct list_head pending_tx_events;
  142. spinlock_t event_lock;
  143. spinlock_t wmi_lock;
  144. /* multi write section */
  145. atomic_t mwrite_cnt;
  146. struct register_write multi_write[MAX_CMD_NUMBER];
  147. u32 multi_write_idx;
  148. struct mutex multi_write_mutex;
  149. /* multi rmw section */
  150. atomic_t m_rmw_cnt;
  151. struct register_rmw multi_rmw[MAX_RMW_CMD_NUMBER];
  152. u32 multi_rmw_idx;
  153. struct mutex multi_rmw_mutex;
  154. };
  155. struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv);
  156. void ath9k_deinit_wmi(struct ath9k_htc_priv *priv);
  157. int ath9k_wmi_connect(struct htc_target *htc, struct wmi *wmi,
  158. enum htc_endpoint_id *wmi_ctrl_epid);
  159. int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id,
  160. u8 *cmd_buf, u32 cmd_len,
  161. u8 *rsp_buf, u32 rsp_len,
  162. u32 timeout);
  163. void ath9k_wmi_event_tasklet(unsigned long data);
  164. void ath9k_fatal_work(struct work_struct *work);
  165. void ath9k_wmi_event_drain(struct ath9k_htc_priv *priv);
  166. #define WMI_CMD(_wmi_cmd) \
  167. do { \
  168. ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, NULL, 0, \
  169. (u8 *) &cmd_rsp, \
  170. sizeof(cmd_rsp), HZ*2); \
  171. } while (0)
  172. #define WMI_CMD_BUF(_wmi_cmd, _buf) \
  173. do { \
  174. ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, \
  175. (u8 *) _buf, sizeof(*_buf), \
  176. &cmd_rsp, sizeof(cmd_rsp), HZ*2); \
  177. } while (0)
  178. #endif /* WMI_H */