txrx.h 3.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167
  1. /*
  2. * Copyright (c) 2013 Eugene Krasnikov <k.eugene.e@gmail.com>
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #ifndef _TXRX_H_
  17. #define _TXRX_H_
  18. #include <linux/etherdevice.h>
  19. #include "wcn36xx.h"
  20. /* TODO describe all properties */
  21. #define WCN36XX_802_11_HEADER_LEN 24
  22. #define WCN36XX_BMU_WQ_TX 25
  23. #define WCN36XX_TID 7
  24. /* broadcast wq ID */
  25. #define WCN36XX_TX_B_WQ_ID 0xA
  26. #define WCN36XX_TX_U_WQ_ID 0x9
  27. /* bd_rate */
  28. #define WCN36XX_BD_RATE_DATA 0
  29. #define WCN36XX_BD_RATE_MGMT 2
  30. #define WCN36XX_BD_RATE_CTRL 3
  31. enum wcn36xx_txbd_ssn_type {
  32. WCN36XX_TXBD_SSN_FILL_HOST = 0,
  33. WCN36XX_TXBD_SSN_FILL_DPU_NON_QOS = 1,
  34. WCN36XX_TXBD_SSN_FILL_DPU_QOS = 2,
  35. };
  36. struct wcn36xx_pdu {
  37. u32 dpu_fb:8;
  38. u32 adu_fb:8;
  39. u32 pdu_id:16;
  40. /* 0x04*/
  41. u32 tail_pdu_idx:16;
  42. u32 head_pdu_idx:16;
  43. /* 0x08*/
  44. u32 pdu_count:7;
  45. u32 mpdu_data_off:9;
  46. u32 mpdu_header_off:8;
  47. u32 mpdu_header_len:8;
  48. /* 0x0c*/
  49. u32 reserved4:8;
  50. u32 tid:4;
  51. u32 bd_ssn:2;
  52. u32 reserved3:2;
  53. u32 mpdu_len:16;
  54. };
  55. struct wcn36xx_rx_bd {
  56. u32 bdt:2;
  57. u32 ft:1;
  58. u32 dpu_ne:1;
  59. u32 rx_key_id:3;
  60. u32 ub:1;
  61. u32 rmf:1;
  62. u32 uma_bypass:1;
  63. u32 csr11:1;
  64. u32 reserved0:1;
  65. u32 scan_learn:1;
  66. u32 rx_ch:4;
  67. u32 rtsf:1;
  68. u32 bsf:1;
  69. u32 a2hf:1;
  70. u32 st_auf:1;
  71. u32 dpu_sign:3;
  72. u32 dpu_rf:8;
  73. struct wcn36xx_pdu pdu;
  74. /* 0x14*/
  75. u32 addr3:8;
  76. u32 addr2:8;
  77. u32 addr1:8;
  78. u32 dpu_desc_idx:8;
  79. /* 0x18*/
  80. u32 rxp_flags:23;
  81. u32 rate_id:9;
  82. u32 phy_stat0;
  83. u32 phy_stat1;
  84. /* 0x24 */
  85. u32 rx_times;
  86. u32 pmi_cmd[6];
  87. /* 0x40 */
  88. u32 reserved7:4;
  89. u32 reorder_slot_id:6;
  90. u32 reorder_fwd_id:6;
  91. u32 reserved6:12;
  92. u32 reorder_code:4;
  93. /* 0x44 */
  94. u32 exp_seq_num:12;
  95. u32 cur_seq_num:12;
  96. u32 fr_type_subtype:8;
  97. /* 0x48 */
  98. u32 msdu_size:16;
  99. u32 sub_fr_id:4;
  100. u32 proc_order:4;
  101. u32 reserved9:4;
  102. u32 aef:1;
  103. u32 lsf:1;
  104. u32 esf:1;
  105. u32 asf:1;
  106. };
  107. struct wcn36xx_tx_bd {
  108. u32 bdt:2;
  109. u32 ft:1;
  110. u32 dpu_ne:1;
  111. u32 fw_tx_comp:1;
  112. u32 tx_comp:1;
  113. u32 reserved1:1;
  114. u32 ub:1;
  115. u32 rmf:1;
  116. u32 reserved0:12;
  117. u32 dpu_sign:3;
  118. u32 dpu_rf:8;
  119. struct wcn36xx_pdu pdu;
  120. /* 0x14*/
  121. u32 reserved5:7;
  122. u32 queue_id:5;
  123. u32 bd_rate:2;
  124. u32 ack_policy:2;
  125. u32 sta_index:8;
  126. u32 dpu_desc_idx:8;
  127. u32 tx_bd_sign;
  128. u32 reserved6;
  129. u32 dxe_start_time;
  130. u32 dxe_end_time;
  131. /*u32 tcp_udp_start_off:10;
  132. u32 header_cks:16;
  133. u32 reserved7:6;*/
  134. };
  135. struct wcn36xx_sta;
  136. struct wcn36xx;
  137. int wcn36xx_rx_skb(struct wcn36xx *wcn, struct sk_buff *skb);
  138. int wcn36xx_start_tx(struct wcn36xx *wcn,
  139. struct wcn36xx_sta *sta_priv,
  140. struct sk_buff *skb);
  141. #endif /* _TXRX_H_ */