wa.c 18 KB

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  1. /*
  2. Broadcom B43 wireless driver
  3. PHY workarounds.
  4. Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
  5. Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
  6. This program is free software; you can redistribute it and/or modify
  7. it under the terms of the GNU General Public License as published by
  8. the Free Software Foundation; either version 2 of the License, or
  9. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program; see the file COPYING. If not, write to
  16. the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  17. Boston, MA 02110-1301, USA.
  18. */
  19. #include "b43.h"
  20. #include "main.h"
  21. #include "tables.h"
  22. #include "phy_common.h"
  23. #include "wa.h"
  24. static void b43_wa_papd(struct b43_wldev *dev)
  25. {
  26. u16 backup;
  27. backup = b43_ofdmtab_read16(dev, B43_OFDMTAB_PWRDYN2, 0);
  28. b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, 7);
  29. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 0, 0);
  30. b43_dummy_transmission(dev, true, true);
  31. b43_ofdmtab_write16(dev, B43_OFDMTAB_PWRDYN2, 0, backup);
  32. }
  33. static void b43_wa_auxclipthr(struct b43_wldev *dev)
  34. {
  35. b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x3800);
  36. }
  37. static void b43_wa_afcdac(struct b43_wldev *dev)
  38. {
  39. b43_phy_write(dev, 0x0035, 0x03FF);
  40. b43_phy_write(dev, 0x0036, 0x0400);
  41. }
  42. static void b43_wa_txdc_offset(struct b43_wldev *dev)
  43. {
  44. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 0, 0x0051);
  45. }
  46. void b43_wa_initgains(struct b43_wldev *dev)
  47. {
  48. struct b43_phy *phy = &dev->phy;
  49. b43_phy_write(dev, B43_PHY_LNAHPFCTL, 0x1FF9);
  50. b43_phy_mask(dev, B43_PHY_LPFGAINCTL, 0xFF0F);
  51. if (phy->rev <= 2)
  52. b43_ofdmtab_write16(dev, B43_OFDMTAB_LPFGAIN, 0, 0x1FBF);
  53. b43_radio_write16(dev, 0x0002, 0x1FBF);
  54. b43_phy_write(dev, 0x0024, 0x4680);
  55. b43_phy_write(dev, 0x0020, 0x0003);
  56. b43_phy_write(dev, 0x001D, 0x0F40);
  57. b43_phy_write(dev, 0x001F, 0x1C00);
  58. if (phy->rev <= 3)
  59. b43_phy_maskset(dev, 0x002A, 0x00FF, 0x0400);
  60. else if (phy->rev == 5) {
  61. b43_phy_maskset(dev, 0x002A, 0x00FF, 0x1A00);
  62. b43_phy_write(dev, 0x00CC, 0x2121);
  63. }
  64. if (phy->rev >= 3)
  65. b43_phy_write(dev, 0x00BA, 0x3ED5);
  66. }
  67. static void b43_wa_divider(struct b43_wldev *dev)
  68. {
  69. b43_phy_mask(dev, 0x002B, ~0x0100);
  70. b43_phy_write(dev, 0x008E, 0x58C1);
  71. }
  72. static void b43_wa_gt(struct b43_wldev *dev) /* Gain table. */
  73. {
  74. if (dev->phy.rev <= 2) {
  75. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 0, 15);
  76. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 1, 31);
  77. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 2, 42);
  78. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 3, 48);
  79. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN2, 4, 58);
  80. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
  81. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
  82. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
  83. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
  84. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
  85. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
  86. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
  87. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 0, 3);
  88. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 1, 3);
  89. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN1, 2, 7);
  90. } else {
  91. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 0, 19);
  92. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 1, 19);
  93. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 2, 19);
  94. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 3, 19);
  95. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 4, 21);
  96. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 5, 21);
  97. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAIN0, 6, 25);
  98. }
  99. }
  100. static void b43_wa_rssi_lt(struct b43_wldev *dev) /* RSSI lookup table */
  101. {
  102. int i;
  103. if (0 /* FIXME: For APHY.rev=2 this might be needed */) {
  104. for (i = 0; i < 8; i++)
  105. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i + 8);
  106. for (i = 8; i < 16; i++)
  107. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i - 8);
  108. } else {
  109. for (i = 0; i < 64; i++)
  110. b43_ofdmtab_write16(dev, B43_OFDMTAB_RSSI, i, i);
  111. }
  112. }
  113. static void b43_wa_analog(struct b43_wldev *dev)
  114. {
  115. struct b43_phy *phy = &dev->phy;
  116. u16 ofdmrev;
  117. ofdmrev = b43_phy_read(dev, B43_PHY_VERSION_OFDM) & B43_PHYVER_VERSION;
  118. if (ofdmrev > 2) {
  119. if (phy->type == B43_PHYTYPE_A)
  120. b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1808);
  121. else
  122. b43_phy_write(dev, B43_PHY_PWRDOWN, 0x1000);
  123. } else {
  124. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 3, 0x1044);
  125. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 4, 0x7201);
  126. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 6, 0x0040);
  127. }
  128. }
  129. static void b43_wa_dac(struct b43_wldev *dev)
  130. {
  131. if (dev->phy.analog == 1)
  132. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
  133. (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0034) | 0x0008);
  134. else
  135. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1,
  136. (b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 1) & ~0x0078) | 0x0010);
  137. }
  138. static void b43_wa_fft(struct b43_wldev *dev) /* Fine frequency table */
  139. {
  140. int i;
  141. if (dev->phy.type == B43_PHYTYPE_A)
  142. for (i = 0; i < B43_TAB_FINEFREQA_SIZE; i++)
  143. b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqa[i]);
  144. else
  145. for (i = 0; i < B43_TAB_FINEFREQG_SIZE; i++)
  146. b43_ofdmtab_write16(dev, B43_OFDMTAB_DACRFPABB, i, b43_tab_finefreqg[i]);
  147. }
  148. static void b43_wa_nft(struct b43_wldev *dev) /* Noise figure table */
  149. {
  150. struct b43_phy *phy = &dev->phy;
  151. int i;
  152. if (phy->type == B43_PHYTYPE_A) {
  153. if (phy->rev == 2)
  154. for (i = 0; i < B43_TAB_NOISEA2_SIZE; i++)
  155. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea2[i]);
  156. else
  157. for (i = 0; i < B43_TAB_NOISEA3_SIZE; i++)
  158. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noisea3[i]);
  159. } else {
  160. if (phy->rev == 1)
  161. for (i = 0; i < B43_TAB_NOISEG1_SIZE; i++)
  162. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg1[i]);
  163. else
  164. for (i = 0; i < B43_TAB_NOISEG2_SIZE; i++)
  165. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, i, b43_tab_noiseg2[i]);
  166. }
  167. }
  168. static void b43_wa_rt(struct b43_wldev *dev) /* Rotor table */
  169. {
  170. int i;
  171. for (i = 0; i < B43_TAB_ROTOR_SIZE; i++)
  172. b43_ofdmtab_write32(dev, B43_OFDMTAB_ROTOR, i, b43_tab_rotor[i]);
  173. }
  174. static void b43_write_null_nst(struct b43_wldev *dev)
  175. {
  176. int i;
  177. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  178. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, 0);
  179. }
  180. static void b43_write_nst(struct b43_wldev *dev, const u16 *nst)
  181. {
  182. int i;
  183. for (i = 0; i < B43_TAB_NOISESCALE_SIZE; i++)
  184. b43_ofdmtab_write16(dev, B43_OFDMTAB_NOISESCALE, i, nst[i]);
  185. }
  186. static void b43_wa_nst(struct b43_wldev *dev) /* Noise scale table */
  187. {
  188. struct b43_phy *phy = &dev->phy;
  189. if (phy->type == B43_PHYTYPE_A) {
  190. if (phy->rev <= 1)
  191. b43_write_null_nst(dev);
  192. else if (phy->rev == 2)
  193. b43_write_nst(dev, b43_tab_noisescalea2);
  194. else if (phy->rev == 3)
  195. b43_write_nst(dev, b43_tab_noisescalea3);
  196. else
  197. b43_write_nst(dev, b43_tab_noisescaleg3);
  198. } else {
  199. if (phy->rev >= 6) {
  200. if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
  201. b43_write_nst(dev, b43_tab_noisescaleg3);
  202. else
  203. b43_write_nst(dev, b43_tab_noisescaleg2);
  204. } else {
  205. b43_write_nst(dev, b43_tab_noisescaleg1);
  206. }
  207. }
  208. }
  209. static void b43_wa_art(struct b43_wldev *dev) /* ADV retard table */
  210. {
  211. int i;
  212. for (i = 0; i < B43_TAB_RETARD_SIZE; i++)
  213. b43_ofdmtab_write32(dev, B43_OFDMTAB_ADVRETARD,
  214. i, b43_tab_retard[i]);
  215. }
  216. static void b43_wa_txlna_gain(struct b43_wldev *dev)
  217. {
  218. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 13, 0x0000);
  219. }
  220. static void b43_wa_crs_reset(struct b43_wldev *dev)
  221. {
  222. b43_phy_write(dev, 0x002C, 0x0064);
  223. }
  224. static void b43_wa_2060txlna_gain(struct b43_wldev *dev)
  225. {
  226. b43_hf_write(dev, b43_hf_read(dev) |
  227. B43_HF_2060W);
  228. }
  229. static void b43_wa_lms(struct b43_wldev *dev)
  230. {
  231. b43_phy_maskset(dev, 0x0055, 0xFFC0, 0x0004);
  232. }
  233. static void b43_wa_mixedsignal(struct b43_wldev *dev)
  234. {
  235. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 1, 3);
  236. }
  237. static void b43_wa_msst(struct b43_wldev *dev) /* Min sigma square table */
  238. {
  239. struct b43_phy *phy = &dev->phy;
  240. int i;
  241. const u16 *tab;
  242. if (phy->type == B43_PHYTYPE_A) {
  243. tab = b43_tab_sigmasqr1;
  244. } else if (phy->type == B43_PHYTYPE_G) {
  245. tab = b43_tab_sigmasqr2;
  246. } else {
  247. B43_WARN_ON(1);
  248. return;
  249. }
  250. for (i = 0; i < B43_TAB_SIGMASQR_SIZE; i++) {
  251. b43_ofdmtab_write16(dev, B43_OFDMTAB_MINSIGSQ,
  252. i, tab[i]);
  253. }
  254. }
  255. static void b43_wa_iqadc(struct b43_wldev *dev)
  256. {
  257. if (dev->phy.analog == 4)
  258. b43_ofdmtab_write16(dev, B43_OFDMTAB_DAC, 0,
  259. b43_ofdmtab_read16(dev, B43_OFDMTAB_DAC, 0) & ~0xF000);
  260. }
  261. static void b43_wa_crs_ed(struct b43_wldev *dev)
  262. {
  263. struct b43_phy *phy = &dev->phy;
  264. if (phy->rev == 1) {
  265. b43_phy_write(dev, B43_PHY_CRSTHRES1_R1, 0x4F19);
  266. } else if (phy->rev == 2) {
  267. b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x1861);
  268. b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0271);
  269. b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800);
  270. } else {
  271. b43_phy_write(dev, B43_PHY_CRSTHRES1, 0x0098);
  272. b43_phy_write(dev, B43_PHY_CRSTHRES2, 0x0070);
  273. b43_phy_write(dev, B43_PHY_OFDM(0xC9), 0x0080);
  274. b43_phy_set(dev, B43_PHY_ANTDWELL, 0x0800);
  275. }
  276. }
  277. static void b43_wa_crs_thr(struct b43_wldev *dev)
  278. {
  279. b43_phy_maskset(dev, B43_PHY_CRS0, ~0x03C0, 0xD000);
  280. }
  281. static void b43_wa_crs_blank(struct b43_wldev *dev)
  282. {
  283. b43_phy_write(dev, B43_PHY_OFDM(0x2C), 0x005A);
  284. }
  285. static void b43_wa_cck_shiftbits(struct b43_wldev *dev)
  286. {
  287. b43_phy_write(dev, B43_PHY_CCKSHIFTBITS, 0x0026);
  288. }
  289. static void b43_wa_wrssi_offset(struct b43_wldev *dev)
  290. {
  291. int i;
  292. if (dev->phy.rev == 1) {
  293. for (i = 0; i < 16; i++) {
  294. b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI_R1,
  295. i, 0x0020);
  296. }
  297. } else {
  298. for (i = 0; i < 32; i++) {
  299. b43_ofdmtab_write16(dev, B43_OFDMTAB_WRSSI,
  300. i, 0x0820);
  301. }
  302. }
  303. }
  304. static void b43_wa_txpuoff_rxpuon(struct b43_wldev *dev)
  305. {
  306. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 2, 15);
  307. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_0F, 3, 20);
  308. }
  309. static void b43_wa_altagc(struct b43_wldev *dev)
  310. {
  311. struct b43_phy *phy = &dev->phy;
  312. if (phy->rev == 1) {
  313. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 254);
  314. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 1, 13);
  315. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 2, 19);
  316. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 3, 25);
  317. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 0, 0x2710);
  318. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 1, 0x9B83);
  319. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 2, 0x9B83);
  320. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC2, 3, 0x0F8D);
  321. b43_phy_write(dev, B43_PHY_LMS, 4);
  322. } else {
  323. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0, 254);
  324. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 1, 13);
  325. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 2, 19);
  326. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 3, 25);
  327. }
  328. b43_phy_maskset(dev, B43_PHY_CCKSHIFTBITS_WA, 0x00FF, 0x5700);
  329. b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x007F, 0x000F);
  330. b43_phy_maskset(dev, B43_PHY_OFDM(0x1A), ~0x3F80, 0x2B80);
  331. b43_phy_maskset(dev, B43_PHY_ANTWRSETT, 0xF0FF, 0x0300);
  332. b43_radio_set(dev, 0x7A, 0x0008);
  333. b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x000F, 0x0008);
  334. b43_phy_maskset(dev, B43_PHY_P1P2GAIN, ~0x0F00, 0x0600);
  335. b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x0F00, 0x0700);
  336. b43_phy_maskset(dev, B43_PHY_N1P1GAIN, ~0x0F00, 0x0100);
  337. if (phy->rev == 1) {
  338. b43_phy_maskset(dev, B43_PHY_N1N2GAIN, ~0x000F, 0x0007);
  339. }
  340. b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x00FF, 0x001C);
  341. b43_phy_maskset(dev, B43_PHY_OFDM(0x88), ~0x3F00, 0x0200);
  342. b43_phy_maskset(dev, B43_PHY_OFDM(0x96), ~0x00FF, 0x001C);
  343. b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x00FF, 0x0020);
  344. b43_phy_maskset(dev, B43_PHY_OFDM(0x89), ~0x3F00, 0x0200);
  345. b43_phy_maskset(dev, B43_PHY_OFDM(0x82), ~0x00FF, 0x002E);
  346. b43_phy_maskset(dev, B43_PHY_OFDM(0x96), 0x00FF, 0x1A00);
  347. b43_phy_maskset(dev, B43_PHY_OFDM(0x81), ~0x00FF, 0x0028);
  348. b43_phy_maskset(dev, B43_PHY_OFDM(0x81), 0x00FF, 0x2C00);
  349. if (phy->rev == 1) {
  350. b43_phy_write(dev, B43_PHY_PEAK_COUNT, 0x092B);
  351. b43_phy_maskset(dev, B43_PHY_OFDM(0x1B), ~0x001E, 0x0002);
  352. } else {
  353. b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x001E);
  354. b43_phy_write(dev, B43_PHY_OFDM(0x1F), 0x287A);
  355. b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, ~0x000F, 0x0004);
  356. if (phy->rev >= 6) {
  357. b43_phy_write(dev, B43_PHY_OFDM(0x22), 0x287A);
  358. b43_phy_maskset(dev, B43_PHY_LPFGAINCTL, 0x0FFF, 0x3000);
  359. }
  360. }
  361. b43_phy_maskset(dev, B43_PHY_DIVSRCHIDX, 0x8080, 0x7874);
  362. b43_phy_write(dev, B43_PHY_OFDM(0x8E), 0x1C00);
  363. if (phy->rev == 1) {
  364. b43_phy_maskset(dev, B43_PHY_DIVP1P2GAIN, ~0x0F00, 0x0600);
  365. b43_phy_write(dev, B43_PHY_OFDM(0x8B), 0x005E);
  366. b43_phy_maskset(dev, B43_PHY_ANTWRSETT, ~0x00FF, 0x001E);
  367. b43_phy_write(dev, B43_PHY_OFDM(0x8D), 0x0002);
  368. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 0, 0);
  369. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 1, 7);
  370. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 2, 16);
  371. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3_R1, 3, 28);
  372. } else {
  373. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 0, 0);
  374. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 1, 7);
  375. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 2, 16);
  376. b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC3, 3, 28);
  377. }
  378. if (phy->rev >= 6) {
  379. b43_phy_mask(dev, B43_PHY_OFDM(0x26), ~0x0003);
  380. b43_phy_mask(dev, B43_PHY_OFDM(0x26), ~0x1000);
  381. }
  382. b43_phy_read(dev, B43_PHY_VERSION_OFDM); /* Dummy read */
  383. }
  384. static void b43_wa_tr_ltov(struct b43_wldev *dev) /* TR Lookup Table Original Values */
  385. {
  386. b43_gtab_write(dev, B43_GTAB_ORIGTR, 0, 0x7654);
  387. }
  388. static void b43_wa_cpll_nonpilot(struct b43_wldev *dev)
  389. {
  390. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 0, 0);
  391. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_11, 1, 0);
  392. }
  393. static void b43_wa_rssi_adc(struct b43_wldev *dev)
  394. {
  395. if (dev->phy.analog == 4)
  396. b43_phy_write(dev, 0x00DC, 0x7454);
  397. }
  398. static void b43_wa_boards_a(struct b43_wldev *dev)
  399. {
  400. if (dev->dev->board_vendor == SSB_BOARDVENDOR_BCM &&
  401. dev->dev->board_type == SSB_BOARD_BU4306 &&
  402. dev->dev->board_rev < 0x30) {
  403. b43_phy_write(dev, 0x0010, 0xE000);
  404. b43_phy_write(dev, 0x0013, 0x0140);
  405. b43_phy_write(dev, 0x0014, 0x0280);
  406. } else {
  407. if (dev->dev->board_type == SSB_BOARD_MP4318 &&
  408. dev->dev->board_rev < 0x20) {
  409. b43_phy_write(dev, 0x0013, 0x0210);
  410. b43_phy_write(dev, 0x0014, 0x0840);
  411. } else {
  412. b43_phy_write(dev, 0x0013, 0x0140);
  413. b43_phy_write(dev, 0x0014, 0x0280);
  414. }
  415. if (dev->phy.rev <= 4)
  416. b43_phy_write(dev, 0x0010, 0xE000);
  417. else
  418. b43_phy_write(dev, 0x0010, 0x2000);
  419. b43_ofdmtab_write16(dev, B43_OFDMTAB_DC, 1, 0x0039);
  420. b43_ofdmtab_write16(dev, B43_OFDMTAB_UNKNOWN_APHY, 7, 0x0040);
  421. }
  422. }
  423. static void b43_wa_boards_g(struct b43_wldev *dev)
  424. {
  425. struct ssb_sprom *sprom = dev->dev->bus_sprom;
  426. struct b43_phy *phy = &dev->phy;
  427. if (dev->dev->board_vendor != SSB_BOARDVENDOR_BCM ||
  428. dev->dev->board_type != SSB_BOARD_BU4306 ||
  429. dev->dev->board_rev != 0x17) {
  430. if (phy->rev < 2) {
  431. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 1, 0x0002);
  432. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX_R1, 2, 0x0001);
  433. } else {
  434. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 1, 0x0002);
  435. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 2, 0x0001);
  436. if ((sprom->boardflags_lo & B43_BFL_EXTLNA) &&
  437. (phy->rev >= 7)) {
  438. b43_phy_mask(dev, B43_PHY_EXTG(0x11), 0xF7FF);
  439. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0020, 0x0001);
  440. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0021, 0x0001);
  441. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0022, 0x0001);
  442. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0023, 0x0000);
  443. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0000, 0x0000);
  444. b43_ofdmtab_write16(dev, B43_OFDMTAB_GAINX, 0x0003, 0x0002);
  445. }
  446. }
  447. }
  448. if (sprom->boardflags_lo & B43_BFL_FEM) {
  449. b43_phy_write(dev, B43_PHY_GTABCTL, 0x3120);
  450. b43_phy_write(dev, B43_PHY_GTABDATA, 0xC480);
  451. }
  452. }
  453. void b43_wa_all(struct b43_wldev *dev)
  454. {
  455. struct b43_phy *phy = &dev->phy;
  456. if (phy->type == B43_PHYTYPE_A) {
  457. switch (phy->rev) {
  458. case 2:
  459. b43_wa_papd(dev);
  460. b43_wa_auxclipthr(dev);
  461. b43_wa_afcdac(dev);
  462. b43_wa_txdc_offset(dev);
  463. b43_wa_initgains(dev);
  464. b43_wa_divider(dev);
  465. b43_wa_gt(dev);
  466. b43_wa_rssi_lt(dev);
  467. b43_wa_analog(dev);
  468. b43_wa_dac(dev);
  469. b43_wa_fft(dev);
  470. b43_wa_nft(dev);
  471. b43_wa_rt(dev);
  472. b43_wa_nst(dev);
  473. b43_wa_art(dev);
  474. b43_wa_txlna_gain(dev);
  475. b43_wa_crs_reset(dev);
  476. b43_wa_2060txlna_gain(dev);
  477. b43_wa_lms(dev);
  478. break;
  479. case 3:
  480. b43_wa_papd(dev);
  481. b43_wa_mixedsignal(dev);
  482. b43_wa_rssi_lt(dev);
  483. b43_wa_txdc_offset(dev);
  484. b43_wa_initgains(dev);
  485. b43_wa_dac(dev);
  486. b43_wa_nft(dev);
  487. b43_wa_nst(dev);
  488. b43_wa_msst(dev);
  489. b43_wa_analog(dev);
  490. b43_wa_gt(dev);
  491. b43_wa_txpuoff_rxpuon(dev);
  492. b43_wa_txlna_gain(dev);
  493. break;
  494. case 5:
  495. b43_wa_iqadc(dev);
  496. case 6:
  497. b43_wa_papd(dev);
  498. b43_wa_rssi_lt(dev);
  499. b43_wa_txdc_offset(dev);
  500. b43_wa_initgains(dev);
  501. b43_wa_dac(dev);
  502. b43_wa_nft(dev);
  503. b43_wa_nst(dev);
  504. b43_wa_msst(dev);
  505. b43_wa_analog(dev);
  506. b43_wa_gt(dev);
  507. b43_wa_txpuoff_rxpuon(dev);
  508. b43_wa_txlna_gain(dev);
  509. break;
  510. case 7:
  511. b43_wa_iqadc(dev);
  512. b43_wa_papd(dev);
  513. b43_wa_rssi_lt(dev);
  514. b43_wa_txdc_offset(dev);
  515. b43_wa_initgains(dev);
  516. b43_wa_dac(dev);
  517. b43_wa_nft(dev);
  518. b43_wa_nst(dev);
  519. b43_wa_msst(dev);
  520. b43_wa_analog(dev);
  521. b43_wa_gt(dev);
  522. b43_wa_txpuoff_rxpuon(dev);
  523. b43_wa_txlna_gain(dev);
  524. b43_wa_rssi_adc(dev);
  525. default:
  526. B43_WARN_ON(1);
  527. }
  528. b43_wa_boards_a(dev);
  529. } else if (phy->type == B43_PHYTYPE_G) {
  530. switch (phy->rev) {
  531. case 1://XXX review rev1
  532. b43_wa_crs_ed(dev);
  533. b43_wa_crs_thr(dev);
  534. b43_wa_crs_blank(dev);
  535. b43_wa_cck_shiftbits(dev);
  536. b43_wa_fft(dev);
  537. b43_wa_nft(dev);
  538. b43_wa_rt(dev);
  539. b43_wa_nst(dev);
  540. b43_wa_art(dev);
  541. b43_wa_wrssi_offset(dev);
  542. b43_wa_altagc(dev);
  543. break;
  544. case 2:
  545. case 6:
  546. case 7:
  547. case 8:
  548. case 9:
  549. b43_wa_tr_ltov(dev);
  550. b43_wa_crs_ed(dev);
  551. b43_wa_rssi_lt(dev);
  552. b43_wa_nft(dev);
  553. b43_wa_nst(dev);
  554. b43_wa_msst(dev);
  555. b43_wa_wrssi_offset(dev);
  556. b43_wa_altagc(dev);
  557. b43_wa_analog(dev);
  558. b43_wa_txpuoff_rxpuon(dev);
  559. break;
  560. default:
  561. B43_WARN_ON(1);
  562. }
  563. b43_wa_boards_g(dev);
  564. } else { /* No N PHY support so far, LP PHY is in phy_lp.c */
  565. B43_WARN_ON(1);
  566. }
  567. b43_wa_cpll_nonpilot(dev);
  568. }