xmit.h 8.5 KB

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  1. #ifndef B43legacy_XMIT_H_
  2. #define B43legacy_XMIT_H_
  3. #include "main.h"
  4. #define _b43legacy_declare_plcp_hdr(size) \
  5. struct b43legacy_plcp_hdr##size { \
  6. union { \
  7. __le32 data; \
  8. __u8 raw[size]; \
  9. } __packed; \
  10. } __packed
  11. /* struct b43legacy_plcp_hdr4 */
  12. _b43legacy_declare_plcp_hdr(4);
  13. /* struct b43legacy_plcp_hdr6 */
  14. _b43legacy_declare_plcp_hdr(6);
  15. #undef _b43legacy_declare_plcp_hdr
  16. /* TX header for v3 firmware */
  17. struct b43legacy_txhdr_fw3 {
  18. __le32 mac_ctl; /* MAC TX control */
  19. __le16 mac_frame_ctl; /* Copy of the FrameControl */
  20. __le16 tx_fes_time_norm; /* TX FES Time Normal */
  21. __le16 phy_ctl; /* PHY TX control */
  22. __u8 iv[16]; /* Encryption IV */
  23. __u8 tx_receiver[6]; /* TX Frame Receiver address */
  24. __le16 tx_fes_time_fb; /* TX FES Time Fallback */
  25. struct b43legacy_plcp_hdr4 rts_plcp_fb; /* RTS fallback PLCP */
  26. __le16 rts_dur_fb; /* RTS fallback duration */
  27. struct b43legacy_plcp_hdr4 plcp_fb; /* Fallback PLCP */
  28. __le16 dur_fb; /* Fallback duration */
  29. PAD_BYTES(2);
  30. __le16 cookie;
  31. __le16 unknown_scb_stuff;
  32. struct b43legacy_plcp_hdr6 rts_plcp; /* RTS PLCP */
  33. __u8 rts_frame[18]; /* The RTS frame (if used) */
  34. struct b43legacy_plcp_hdr6 plcp;
  35. } __packed;
  36. /* MAC TX control */
  37. #define B43legacy_TX4_MAC_KEYIDX 0x0FF00000 /* Security key index */
  38. #define B43legacy_TX4_MAC_KEYIDX_SHIFT 20
  39. #define B43legacy_TX4_MAC_KEYALG 0x00070000 /* Security key algorithm */
  40. #define B43legacy_TX4_MAC_KEYALG_SHIFT 16
  41. #define B43legacy_TX4_MAC_LIFETIME 0x00001000
  42. #define B43legacy_TX4_MAC_FRAMEBURST 0x00000800
  43. #define B43legacy_TX4_MAC_SENDCTS 0x00000400
  44. #define B43legacy_TX4_MAC_AMPDU 0x00000300
  45. #define B43legacy_TX4_MAC_AMPDU_SHIFT 8
  46. #define B43legacy_TX4_MAC_CTSFALLBACKOFDM 0x00000200
  47. #define B43legacy_TX4_MAC_FALLBACKOFDM 0x00000100
  48. #define B43legacy_TX4_MAC_5GHZ 0x00000080
  49. #define B43legacy_TX4_MAC_IGNPMQ 0x00000020
  50. #define B43legacy_TX4_MAC_HWSEQ 0x00000010 /* Use Hardware Seq No */
  51. #define B43legacy_TX4_MAC_STMSDU 0x00000008 /* Start MSDU */
  52. #define B43legacy_TX4_MAC_SENDRTS 0x00000004
  53. #define B43legacy_TX4_MAC_LONGFRAME 0x00000002
  54. #define B43legacy_TX4_MAC_ACK 0x00000001
  55. /* Extra Frame Types */
  56. #define B43legacy_TX4_EFT_FBOFDM 0x0001 /* Data frame fb rate type */
  57. #define B43legacy_TX4_EFT_RTSOFDM 0x0004 /* RTS/CTS rate type */
  58. #define B43legacy_TX4_EFT_RTSFBOFDM 0x0010 /* RTS/CTS fallback rate type */
  59. /* PHY TX control word */
  60. #define B43legacy_TX4_PHY_ENC 0x0003 /* Data frame encoding */
  61. #define B43legacy_TX4_PHY_ENC_CCK 0x0000 /* CCK */
  62. #define B43legacy_TX4_PHY_ENC_OFDM 0x0001 /* Data frame rate type */
  63. #define B43legacy_TX4_PHY_SHORTPRMBL 0x0010 /* Use short preamble */
  64. #define B43legacy_TX4_PHY_ANT 0x03C0 /* Antenna selection */
  65. #define B43legacy_TX4_PHY_ANT0 0x0000 /* Use antenna 0 */
  66. #define B43legacy_TX4_PHY_ANT1 0x0100 /* Use antenna 1 */
  67. #define B43legacy_TX4_PHY_ANTLAST 0x0300 /* Use last used antenna */
  68. int b43legacy_generate_txhdr(struct b43legacy_wldev *dev,
  69. u8 *txhdr,
  70. const unsigned char *fragment_data,
  71. unsigned int fragment_len,
  72. struct ieee80211_tx_info *info,
  73. u16 cookie);
  74. /* Transmit Status */
  75. struct b43legacy_txstatus {
  76. u16 cookie; /* The cookie from the txhdr */
  77. u16 seq; /* Sequence number */
  78. u8 phy_stat; /* PHY TX status */
  79. u8 frame_count; /* Frame transmit count */
  80. u8 rts_count; /* RTS transmit count */
  81. u8 supp_reason; /* Suppression reason */
  82. /* flags */
  83. u8 pm_indicated;/* PM mode indicated to AP */
  84. u8 intermediate;/* Intermediate status notification */
  85. u8 for_ampdu; /* Status is for an AMPDU (afterburner) */
  86. u8 acked; /* Wireless ACK received */
  87. };
  88. /* txstatus supp_reason values */
  89. enum {
  90. B43legacy_TXST_SUPP_NONE, /* Not suppressed */
  91. B43legacy_TXST_SUPP_PMQ, /* Suppressed due to PMQ entry */
  92. B43legacy_TXST_SUPP_FLUSH, /* Suppressed due to flush request */
  93. B43legacy_TXST_SUPP_PREV, /* Previous fragment failed */
  94. B43legacy_TXST_SUPP_CHAN, /* Channel mismatch */
  95. B43legacy_TXST_SUPP_LIFE, /* Lifetime expired */
  96. B43legacy_TXST_SUPP_UNDER, /* Buffer underflow */
  97. B43legacy_TXST_SUPP_ABNACK, /* Afterburner NACK */
  98. };
  99. /* Transmit Status as received through DMA/PIO on old chips */
  100. struct b43legacy_hwtxstatus {
  101. PAD_BYTES(4);
  102. __le16 cookie;
  103. u8 flags;
  104. u8 count;
  105. PAD_BYTES(2);
  106. __le16 seq;
  107. u8 phy_stat;
  108. PAD_BYTES(1);
  109. } __packed;
  110. /* Receive header for v3 firmware. */
  111. struct b43legacy_rxhdr_fw3 {
  112. __le16 frame_len; /* Frame length */
  113. PAD_BYTES(2);
  114. __le16 phy_status0; /* PHY RX Status 0 */
  115. __u8 jssi; /* PHY RX Status 1: JSSI */
  116. __u8 sig_qual; /* PHY RX Status 1: Signal Quality */
  117. PAD_BYTES(2); /* PHY RX Status 2 */
  118. __le16 phy_status3; /* PHY RX Status 3 */
  119. __le16 mac_status; /* MAC RX status */
  120. __le16 mac_time;
  121. __le16 channel;
  122. } __packed;
  123. /* PHY RX Status 0 */
  124. #define B43legacy_RX_PHYST0_GAINCTL 0x4000 /* Gain Control */
  125. #define B43legacy_RX_PHYST0_PLCPHCF 0x0200
  126. #define B43legacy_RX_PHYST0_PLCPFV 0x0100
  127. #define B43legacy_RX_PHYST0_SHORTPRMBL 0x0080 /* Recvd with Short Preamble */
  128. #define B43legacy_RX_PHYST0_LCRS 0x0040
  129. #define B43legacy_RX_PHYST0_ANT 0x0020 /* Antenna */
  130. #define B43legacy_RX_PHYST0_UNSRATE 0x0010
  131. #define B43legacy_RX_PHYST0_CLIP 0x000C
  132. #define B43legacy_RX_PHYST0_CLIP_SHIFT 2
  133. #define B43legacy_RX_PHYST0_FTYPE 0x0003 /* Frame type */
  134. #define B43legacy_RX_PHYST0_CCK 0x0000 /* Frame type: CCK */
  135. #define B43legacy_RX_PHYST0_OFDM 0x0001 /* Frame type: OFDM */
  136. #define B43legacy_RX_PHYST0_PRE_N 0x0002 /* Pre-standard N-PHY frame */
  137. #define B43legacy_RX_PHYST0_STD_N 0x0003 /* Standard N-PHY frame */
  138. /* PHY RX Status 2 */
  139. #define B43legacy_RX_PHYST2_LNAG 0xC000 /* LNA Gain */
  140. #define B43legacy_RX_PHYST2_LNAG_SHIFT 14
  141. #define B43legacy_RX_PHYST2_PNAG 0x3C00 /* PNA Gain */
  142. #define B43legacy_RX_PHYST2_PNAG_SHIFT 10
  143. #define B43legacy_RX_PHYST2_FOFF 0x03FF /* F offset */
  144. /* PHY RX Status 3 */
  145. #define B43legacy_RX_PHYST3_DIGG 0x1800 /* DIG Gain */
  146. #define B43legacy_RX_PHYST3_DIGG_SHIFT 11
  147. #define B43legacy_RX_PHYST3_TRSTATE 0x0400 /* TR state */
  148. /* MAC RX Status */
  149. #define B43legacy_RX_MAC_BEACONSENT 0x00008000 /* Beacon send flag */
  150. #define B43legacy_RX_MAC_KEYIDX 0x000007E0 /* Key index */
  151. #define B43legacy_RX_MAC_KEYIDX_SHIFT 5
  152. #define B43legacy_RX_MAC_DECERR 0x00000010 /* Decrypt error */
  153. #define B43legacy_RX_MAC_DEC 0x00000008 /* Decryption attempted */
  154. #define B43legacy_RX_MAC_PADDING 0x00000004 /* Pad bytes present */
  155. #define B43legacy_RX_MAC_RESP 0x00000002 /* Response frame xmitted */
  156. #define B43legacy_RX_MAC_FCSERR 0x00000001 /* FCS error */
  157. /* RX channel */
  158. #define B43legacy_RX_CHAN_GAIN 0xFC00 /* Gain */
  159. #define B43legacy_RX_CHAN_GAIN_SHIFT 10
  160. #define B43legacy_RX_CHAN_ID 0x03FC /* Channel ID */
  161. #define B43legacy_RX_CHAN_ID_SHIFT 2
  162. #define B43legacy_RX_CHAN_PHYTYPE 0x0003 /* PHY type */
  163. u8 b43legacy_plcp_get_ratecode_cck(const u8 bitrate);
  164. u8 b43legacy_plcp_get_ratecode_ofdm(const u8 bitrate);
  165. void b43legacy_generate_plcp_hdr(struct b43legacy_plcp_hdr4 *plcp,
  166. const u16 octets, const u8 bitrate);
  167. void b43legacy_rx(struct b43legacy_wldev *dev,
  168. struct sk_buff *skb,
  169. const void *_rxhdr);
  170. void b43legacy_handle_txstatus(struct b43legacy_wldev *dev,
  171. const struct b43legacy_txstatus *status);
  172. void b43legacy_handle_hwtxstatus(struct b43legacy_wldev *dev,
  173. const struct b43legacy_hwtxstatus *hw);
  174. void b43legacy_tx_suspend(struct b43legacy_wldev *dev);
  175. void b43legacy_tx_resume(struct b43legacy_wldev *dev);
  176. #define B43legacy_NR_QOSPARMS 22
  177. enum {
  178. B43legacy_QOSPARM_TXOP = 0,
  179. B43legacy_QOSPARM_CWMIN,
  180. B43legacy_QOSPARM_CWMAX,
  181. B43legacy_QOSPARM_CWCUR,
  182. B43legacy_QOSPARM_AIFS,
  183. B43legacy_QOSPARM_BSLOTS,
  184. B43legacy_QOSPARM_REGGAP,
  185. B43legacy_QOSPARM_STATUS,
  186. };
  187. void b43legacy_qos_init(struct b43legacy_wldev *dev);
  188. /* Helper functions for converting the key-table index from "firmware-format"
  189. * to "raw-format" and back. The firmware API changed for this at some revision.
  190. * We need to account for that here. */
  191. static inline
  192. int b43legacy_new_kidx_api(struct b43legacy_wldev *dev)
  193. {
  194. /* FIXME: Not sure the change was at rev 351 */
  195. return (dev->fw.rev >= 351);
  196. }
  197. static inline
  198. u8 b43legacy_kidx_to_fw(struct b43legacy_wldev *dev, u8 raw_kidx)
  199. {
  200. u8 firmware_kidx;
  201. if (b43legacy_new_kidx_api(dev))
  202. firmware_kidx = raw_kidx;
  203. else {
  204. if (raw_kidx >= 4) /* Is per STA key? */
  205. firmware_kidx = raw_kidx - 4;
  206. else
  207. firmware_kidx = raw_kidx; /* TX default key */
  208. }
  209. return firmware_kidx;
  210. }
  211. static inline
  212. u8 b43legacy_kidx_to_raw(struct b43legacy_wldev *dev, u8 firmware_kidx)
  213. {
  214. u8 raw_kidx;
  215. if (b43legacy_new_kidx_api(dev))
  216. raw_kidx = firmware_kidx;
  217. else
  218. /* RX default keys or per STA keys */
  219. raw_kidx = firmware_kidx + 4;
  220. return raw_kidx;
  221. }
  222. #endif /* B43legacy_XMIT_H_ */