fw.c 32 KB

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  1. /******************************************************************************
  2. *
  3. * This file is provided under a dual BSD/GPLv2 license. When using or
  4. * redistributing this file, you may do so under either license.
  5. *
  6. * GPL LICENSE SUMMARY
  7. *
  8. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  9. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of version 2 of the GNU General Public License as
  13. * published by the Free Software Foundation.
  14. *
  15. * This program is distributed in the hope that it will be useful, but
  16. * WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  23. * USA
  24. *
  25. * The full GNU General Public License is included in this distribution
  26. * in the file called COPYING.
  27. *
  28. * Contact Information:
  29. * Intel Linux Wireless <ilw@linux.intel.com>
  30. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  31. *
  32. * BSD LICENSE
  33. *
  34. * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
  35. * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  36. * All rights reserved.
  37. *
  38. * Redistribution and use in source and binary forms, with or without
  39. * modification, are permitted provided that the following conditions
  40. * are met:
  41. *
  42. * * Redistributions of source code must retain the above copyright
  43. * notice, this list of conditions and the following disclaimer.
  44. * * Redistributions in binary form must reproduce the above copyright
  45. * notice, this list of conditions and the following disclaimer in
  46. * the documentation and/or other materials provided with the
  47. * distribution.
  48. * * Neither the name Intel Corporation nor the names of its
  49. * contributors may be used to endorse or promote products derived
  50. * from this software without specific prior written permission.
  51. *
  52. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  53. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  54. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  55. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  56. * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  57. * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  58. * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  59. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  60. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  61. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  62. * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  63. *
  64. *****************************************************************************/
  65. #include <net/mac80211.h>
  66. #include "iwl-trans.h"
  67. #include "iwl-op-mode.h"
  68. #include "iwl-fw.h"
  69. #include "iwl-debug.h"
  70. #include "iwl-csr.h" /* for iwl_mvm_rx_card_state_notif */
  71. #include "iwl-io.h" /* for iwl_mvm_rx_card_state_notif */
  72. #include "iwl-prph.h"
  73. #include "iwl-eeprom-parse.h"
  74. #include "mvm.h"
  75. #include "iwl-phy-db.h"
  76. #define MVM_UCODE_ALIVE_TIMEOUT HZ
  77. #define MVM_UCODE_CALIB_TIMEOUT (2*HZ)
  78. #define UCODE_VALID_OK cpu_to_le32(0x1)
  79. struct iwl_mvm_alive_data {
  80. bool valid;
  81. u32 scd_base_addr;
  82. };
  83. static inline const struct fw_img *
  84. iwl_get_ucode_image(struct iwl_mvm *mvm, enum iwl_ucode_type ucode_type)
  85. {
  86. if (ucode_type >= IWL_UCODE_TYPE_MAX)
  87. return NULL;
  88. return &mvm->fw->img[ucode_type];
  89. }
  90. static int iwl_send_tx_ant_cfg(struct iwl_mvm *mvm, u8 valid_tx_ant)
  91. {
  92. struct iwl_tx_ant_cfg_cmd tx_ant_cmd = {
  93. .valid = cpu_to_le32(valid_tx_ant),
  94. };
  95. IWL_DEBUG_FW(mvm, "select valid tx ant: %u\n", valid_tx_ant);
  96. return iwl_mvm_send_cmd_pdu(mvm, TX_ANT_CONFIGURATION_CMD, 0,
  97. sizeof(tx_ant_cmd), &tx_ant_cmd);
  98. }
  99. void iwl_free_fw_paging(struct iwl_mvm *mvm)
  100. {
  101. int i;
  102. if (!mvm->fw_paging_db[0].fw_paging_block)
  103. return;
  104. for (i = 0; i < NUM_OF_FW_PAGING_BLOCKS; i++) {
  105. if (!mvm->fw_paging_db[i].fw_paging_block) {
  106. IWL_DEBUG_FW(mvm,
  107. "Paging: block %d already freed, continue to next page\n",
  108. i);
  109. continue;
  110. }
  111. __free_pages(mvm->fw_paging_db[i].fw_paging_block,
  112. get_order(mvm->fw_paging_db[i].fw_paging_size));
  113. }
  114. kfree(mvm->trans->paging_download_buf);
  115. mvm->trans->paging_download_buf = NULL;
  116. memset(mvm->fw_paging_db, 0, sizeof(mvm->fw_paging_db));
  117. }
  118. static int iwl_fill_paging_mem(struct iwl_mvm *mvm, const struct fw_img *image)
  119. {
  120. int sec_idx, idx;
  121. u32 offset = 0;
  122. /*
  123. * find where is the paging image start point:
  124. * if CPU2 exist and it's in paging format, then the image looks like:
  125. * CPU1 sections (2 or more)
  126. * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between CPU1 to CPU2
  127. * CPU2 sections (not paged)
  128. * PAGING_SEPARATOR_SECTION delimiter - separate between CPU2
  129. * non paged to CPU2 paging sec
  130. * CPU2 paging CSS
  131. * CPU2 paging image (including instruction and data)
  132. */
  133. for (sec_idx = 0; sec_idx < IWL_UCODE_SECTION_MAX; sec_idx++) {
  134. if (image->sec[sec_idx].offset == PAGING_SEPARATOR_SECTION) {
  135. sec_idx++;
  136. break;
  137. }
  138. }
  139. if (sec_idx >= IWL_UCODE_SECTION_MAX) {
  140. IWL_ERR(mvm, "driver didn't find paging image\n");
  141. iwl_free_fw_paging(mvm);
  142. return -EINVAL;
  143. }
  144. /* copy the CSS block to the dram */
  145. IWL_DEBUG_FW(mvm, "Paging: load paging CSS to FW, sec = %d\n",
  146. sec_idx);
  147. memcpy(page_address(mvm->fw_paging_db[0].fw_paging_block),
  148. image->sec[sec_idx].data,
  149. mvm->fw_paging_db[0].fw_paging_size);
  150. IWL_DEBUG_FW(mvm,
  151. "Paging: copied %d CSS bytes to first block\n",
  152. mvm->fw_paging_db[0].fw_paging_size);
  153. sec_idx++;
  154. /*
  155. * copy the paging blocks to the dram
  156. * loop index start from 1 since that CSS block already copied to dram
  157. * and CSS index is 0.
  158. * loop stop at num_of_paging_blk since that last block is not full.
  159. */
  160. for (idx = 1; idx < mvm->num_of_paging_blk; idx++) {
  161. memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
  162. image->sec[sec_idx].data + offset,
  163. mvm->fw_paging_db[idx].fw_paging_size);
  164. IWL_DEBUG_FW(mvm,
  165. "Paging: copied %d paging bytes to block %d\n",
  166. mvm->fw_paging_db[idx].fw_paging_size,
  167. idx);
  168. offset += mvm->fw_paging_db[idx].fw_paging_size;
  169. }
  170. /* copy the last paging block */
  171. if (mvm->num_of_pages_in_last_blk > 0) {
  172. memcpy(page_address(mvm->fw_paging_db[idx].fw_paging_block),
  173. image->sec[sec_idx].data + offset,
  174. FW_PAGING_SIZE * mvm->num_of_pages_in_last_blk);
  175. IWL_DEBUG_FW(mvm,
  176. "Paging: copied %d pages in the last block %d\n",
  177. mvm->num_of_pages_in_last_blk, idx);
  178. }
  179. return 0;
  180. }
  181. static int iwl_alloc_fw_paging_mem(struct iwl_mvm *mvm,
  182. const struct fw_img *image)
  183. {
  184. struct page *block;
  185. dma_addr_t phys = 0;
  186. int blk_idx = 0;
  187. int order, num_of_pages;
  188. int dma_enabled;
  189. if (mvm->fw_paging_db[0].fw_paging_block)
  190. return 0;
  191. dma_enabled = is_device_dma_capable(mvm->trans->dev);
  192. /* ensure BLOCK_2_EXP_SIZE is power of 2 of PAGING_BLOCK_SIZE */
  193. BUILD_BUG_ON(BIT(BLOCK_2_EXP_SIZE) != PAGING_BLOCK_SIZE);
  194. num_of_pages = image->paging_mem_size / FW_PAGING_SIZE;
  195. mvm->num_of_paging_blk = ((num_of_pages - 1) /
  196. NUM_OF_PAGE_PER_GROUP) + 1;
  197. mvm->num_of_pages_in_last_blk =
  198. num_of_pages -
  199. NUM_OF_PAGE_PER_GROUP * (mvm->num_of_paging_blk - 1);
  200. IWL_DEBUG_FW(mvm,
  201. "Paging: allocating mem for %d paging blocks, each block holds 8 pages, last block holds %d pages\n",
  202. mvm->num_of_paging_blk,
  203. mvm->num_of_pages_in_last_blk);
  204. /* allocate block of 4Kbytes for paging CSS */
  205. order = get_order(FW_PAGING_SIZE);
  206. block = alloc_pages(GFP_KERNEL, order);
  207. if (!block) {
  208. /* free all the previous pages since we failed */
  209. iwl_free_fw_paging(mvm);
  210. return -ENOMEM;
  211. }
  212. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  213. mvm->fw_paging_db[blk_idx].fw_paging_size = FW_PAGING_SIZE;
  214. if (dma_enabled) {
  215. phys = dma_map_page(mvm->trans->dev, block, 0,
  216. PAGE_SIZE << order, DMA_BIDIRECTIONAL);
  217. if (dma_mapping_error(mvm->trans->dev, phys)) {
  218. /*
  219. * free the previous pages and the current one since
  220. * we failed to map_page.
  221. */
  222. iwl_free_fw_paging(mvm);
  223. return -ENOMEM;
  224. }
  225. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  226. } else {
  227. mvm->fw_paging_db[blk_idx].fw_paging_phys = PAGING_ADDR_SIG |
  228. blk_idx << BLOCK_2_EXP_SIZE;
  229. }
  230. IWL_DEBUG_FW(mvm,
  231. "Paging: allocated 4K(CSS) bytes (order %d) for firmware paging.\n",
  232. order);
  233. /*
  234. * allocate blocks in dram.
  235. * since that CSS allocated in fw_paging_db[0] loop start from index 1
  236. */
  237. for (blk_idx = 1; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  238. /* allocate block of PAGING_BLOCK_SIZE (32K) */
  239. order = get_order(PAGING_BLOCK_SIZE);
  240. block = alloc_pages(GFP_KERNEL, order);
  241. if (!block) {
  242. /* free all the previous pages since we failed */
  243. iwl_free_fw_paging(mvm);
  244. return -ENOMEM;
  245. }
  246. mvm->fw_paging_db[blk_idx].fw_paging_block = block;
  247. mvm->fw_paging_db[blk_idx].fw_paging_size = PAGING_BLOCK_SIZE;
  248. if (dma_enabled) {
  249. phys = dma_map_page(mvm->trans->dev, block, 0,
  250. PAGE_SIZE << order,
  251. DMA_BIDIRECTIONAL);
  252. if (dma_mapping_error(mvm->trans->dev, phys)) {
  253. /*
  254. * free the previous pages and the current one
  255. * since we failed to map_page.
  256. */
  257. iwl_free_fw_paging(mvm);
  258. return -ENOMEM;
  259. }
  260. mvm->fw_paging_db[blk_idx].fw_paging_phys = phys;
  261. } else {
  262. mvm->fw_paging_db[blk_idx].fw_paging_phys =
  263. PAGING_ADDR_SIG |
  264. blk_idx << BLOCK_2_EXP_SIZE;
  265. }
  266. IWL_DEBUG_FW(mvm,
  267. "Paging: allocated 32K bytes (order %d) for firmware paging.\n",
  268. order);
  269. }
  270. return 0;
  271. }
  272. static int iwl_save_fw_paging(struct iwl_mvm *mvm,
  273. const struct fw_img *fw)
  274. {
  275. int ret;
  276. ret = iwl_alloc_fw_paging_mem(mvm, fw);
  277. if (ret)
  278. return ret;
  279. return iwl_fill_paging_mem(mvm, fw);
  280. }
  281. /* send paging cmd to FW in case CPU2 has paging image */
  282. static int iwl_send_paging_cmd(struct iwl_mvm *mvm, const struct fw_img *fw)
  283. {
  284. int blk_idx;
  285. __le32 dev_phy_addr;
  286. struct iwl_fw_paging_cmd fw_paging_cmd = {
  287. .flags =
  288. cpu_to_le32(PAGING_CMD_IS_SECURED |
  289. PAGING_CMD_IS_ENABLED |
  290. (mvm->num_of_pages_in_last_blk <<
  291. PAGING_CMD_NUM_OF_PAGES_IN_LAST_GRP_POS)),
  292. .block_size = cpu_to_le32(BLOCK_2_EXP_SIZE),
  293. .block_num = cpu_to_le32(mvm->num_of_paging_blk),
  294. };
  295. /* loop for for all paging blocks + CSS block */
  296. for (blk_idx = 0; blk_idx < mvm->num_of_paging_blk + 1; blk_idx++) {
  297. dev_phy_addr =
  298. cpu_to_le32(mvm->fw_paging_db[blk_idx].fw_paging_phys >>
  299. PAGE_2_EXP_SIZE);
  300. fw_paging_cmd.device_phy_addr[blk_idx] = dev_phy_addr;
  301. }
  302. return iwl_mvm_send_cmd_pdu(mvm, iwl_cmd_id(FW_PAGING_BLOCK_CMD,
  303. IWL_ALWAYS_LONG_GROUP, 0),
  304. 0, sizeof(fw_paging_cmd), &fw_paging_cmd);
  305. }
  306. /*
  307. * Send paging item cmd to FW in case CPU2 has paging image
  308. */
  309. static int iwl_trans_get_paging_item(struct iwl_mvm *mvm)
  310. {
  311. int ret;
  312. struct iwl_fw_get_item_cmd fw_get_item_cmd = {
  313. .item_id = cpu_to_le32(IWL_FW_ITEM_ID_PAGING),
  314. };
  315. struct iwl_fw_get_item_resp *item_resp;
  316. struct iwl_host_cmd cmd = {
  317. .id = iwl_cmd_id(FW_GET_ITEM_CMD, IWL_ALWAYS_LONG_GROUP, 0),
  318. .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
  319. .data = { &fw_get_item_cmd, },
  320. };
  321. cmd.len[0] = sizeof(struct iwl_fw_get_item_cmd);
  322. ret = iwl_mvm_send_cmd(mvm, &cmd);
  323. if (ret) {
  324. IWL_ERR(mvm,
  325. "Paging: Failed to send FW_GET_ITEM_CMD cmd (err = %d)\n",
  326. ret);
  327. return ret;
  328. }
  329. item_resp = (void *)((struct iwl_rx_packet *)cmd.resp_pkt)->data;
  330. if (item_resp->item_id != cpu_to_le32(IWL_FW_ITEM_ID_PAGING)) {
  331. IWL_ERR(mvm,
  332. "Paging: got wrong item in FW_GET_ITEM_CMD resp (item_id = %u)\n",
  333. le32_to_cpu(item_resp->item_id));
  334. ret = -EIO;
  335. goto exit;
  336. }
  337. mvm->trans->paging_download_buf = kzalloc(MAX_PAGING_IMAGE_SIZE,
  338. GFP_KERNEL);
  339. if (!mvm->trans->paging_download_buf) {
  340. ret = -ENOMEM;
  341. goto exit;
  342. }
  343. mvm->trans->paging_req_addr = le32_to_cpu(item_resp->item_val);
  344. mvm->trans->paging_db = mvm->fw_paging_db;
  345. IWL_DEBUG_FW(mvm,
  346. "Paging: got paging request address (paging_req_addr 0x%08x)\n",
  347. mvm->trans->paging_req_addr);
  348. exit:
  349. iwl_free_resp(&cmd);
  350. return ret;
  351. }
  352. static bool iwl_alive_fn(struct iwl_notif_wait_data *notif_wait,
  353. struct iwl_rx_packet *pkt, void *data)
  354. {
  355. struct iwl_mvm *mvm =
  356. container_of(notif_wait, struct iwl_mvm, notif_wait);
  357. struct iwl_mvm_alive_data *alive_data = data;
  358. struct mvm_alive_resp_ver1 *palive1;
  359. struct mvm_alive_resp_ver2 *palive2;
  360. struct mvm_alive_resp *palive;
  361. if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive1)) {
  362. palive1 = (void *)pkt->data;
  363. mvm->support_umac_log = false;
  364. mvm->error_event_table =
  365. le32_to_cpu(palive1->error_event_table_ptr);
  366. mvm->log_event_table =
  367. le32_to_cpu(palive1->log_event_table_ptr);
  368. alive_data->scd_base_addr = le32_to_cpu(palive1->scd_base_ptr);
  369. alive_data->valid = le16_to_cpu(palive1->status) ==
  370. IWL_ALIVE_STATUS_OK;
  371. IWL_DEBUG_FW(mvm,
  372. "Alive VER1 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  373. le16_to_cpu(palive1->status), palive1->ver_type,
  374. palive1->ver_subtype, palive1->flags);
  375. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive2)) {
  376. palive2 = (void *)pkt->data;
  377. mvm->error_event_table =
  378. le32_to_cpu(palive2->error_event_table_ptr);
  379. mvm->log_event_table =
  380. le32_to_cpu(palive2->log_event_table_ptr);
  381. alive_data->scd_base_addr = le32_to_cpu(palive2->scd_base_ptr);
  382. mvm->umac_error_event_table =
  383. le32_to_cpu(palive2->error_info_addr);
  384. mvm->sf_space.addr = le32_to_cpu(palive2->st_fwrd_addr);
  385. mvm->sf_space.size = le32_to_cpu(palive2->st_fwrd_size);
  386. alive_data->valid = le16_to_cpu(palive2->status) ==
  387. IWL_ALIVE_STATUS_OK;
  388. if (mvm->umac_error_event_table)
  389. mvm->support_umac_log = true;
  390. IWL_DEBUG_FW(mvm,
  391. "Alive VER2 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  392. le16_to_cpu(palive2->status), palive2->ver_type,
  393. palive2->ver_subtype, palive2->flags);
  394. IWL_DEBUG_FW(mvm,
  395. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  396. palive2->umac_major, palive2->umac_minor);
  397. } else if (iwl_rx_packet_payload_len(pkt) == sizeof(*palive)) {
  398. palive = (void *)pkt->data;
  399. mvm->error_event_table =
  400. le32_to_cpu(palive->error_event_table_ptr);
  401. mvm->log_event_table =
  402. le32_to_cpu(palive->log_event_table_ptr);
  403. alive_data->scd_base_addr = le32_to_cpu(palive->scd_base_ptr);
  404. mvm->umac_error_event_table =
  405. le32_to_cpu(palive->error_info_addr);
  406. mvm->sf_space.addr = le32_to_cpu(palive->st_fwrd_addr);
  407. mvm->sf_space.size = le32_to_cpu(palive->st_fwrd_size);
  408. alive_data->valid = le16_to_cpu(palive->status) ==
  409. IWL_ALIVE_STATUS_OK;
  410. if (mvm->umac_error_event_table)
  411. mvm->support_umac_log = true;
  412. IWL_DEBUG_FW(mvm,
  413. "Alive VER3 ucode status 0x%04x revision 0x%01X 0x%01X flags 0x%01X\n",
  414. le16_to_cpu(palive->status), palive->ver_type,
  415. palive->ver_subtype, palive->flags);
  416. IWL_DEBUG_FW(mvm,
  417. "UMAC version: Major - 0x%x, Minor - 0x%x\n",
  418. le32_to_cpu(palive->umac_major),
  419. le32_to_cpu(palive->umac_minor));
  420. }
  421. return true;
  422. }
  423. static bool iwl_wait_phy_db_entry(struct iwl_notif_wait_data *notif_wait,
  424. struct iwl_rx_packet *pkt, void *data)
  425. {
  426. struct iwl_phy_db *phy_db = data;
  427. if (pkt->hdr.cmd != CALIB_RES_NOTIF_PHY_DB) {
  428. WARN_ON(pkt->hdr.cmd != INIT_COMPLETE_NOTIF);
  429. return true;
  430. }
  431. WARN_ON(iwl_phy_db_set_section(phy_db, pkt, GFP_ATOMIC));
  432. return false;
  433. }
  434. static int iwl_mvm_load_ucode_wait_alive(struct iwl_mvm *mvm,
  435. enum iwl_ucode_type ucode_type)
  436. {
  437. struct iwl_notification_wait alive_wait;
  438. struct iwl_mvm_alive_data alive_data;
  439. const struct fw_img *fw;
  440. int ret, i;
  441. enum iwl_ucode_type old_type = mvm->cur_ucode;
  442. static const u16 alive_cmd[] = { MVM_ALIVE };
  443. struct iwl_sf_region st_fwrd_space;
  444. if (ucode_type == IWL_UCODE_REGULAR &&
  445. iwl_fw_dbg_conf_usniffer(mvm->fw, FW_DBG_START_FROM_ALIVE))
  446. fw = iwl_get_ucode_image(mvm, IWL_UCODE_REGULAR_USNIFFER);
  447. else
  448. fw = iwl_get_ucode_image(mvm, ucode_type);
  449. if (WARN_ON(!fw))
  450. return -EINVAL;
  451. mvm->cur_ucode = ucode_type;
  452. mvm->ucode_loaded = false;
  453. iwl_init_notification_wait(&mvm->notif_wait, &alive_wait,
  454. alive_cmd, ARRAY_SIZE(alive_cmd),
  455. iwl_alive_fn, &alive_data);
  456. ret = iwl_trans_start_fw(mvm->trans, fw, ucode_type == IWL_UCODE_INIT);
  457. if (ret) {
  458. mvm->cur_ucode = old_type;
  459. iwl_remove_notification(&mvm->notif_wait, &alive_wait);
  460. return ret;
  461. }
  462. /*
  463. * Some things may run in the background now, but we
  464. * just wait for the ALIVE notification here.
  465. */
  466. ret = iwl_wait_notification(&mvm->notif_wait, &alive_wait,
  467. MVM_UCODE_ALIVE_TIMEOUT);
  468. if (ret) {
  469. if (mvm->trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
  470. IWL_ERR(mvm,
  471. "SecBoot CPU1 Status: 0x%x, CPU2 Status: 0x%x\n",
  472. iwl_read_prph(mvm->trans, SB_CPU_1_STATUS),
  473. iwl_read_prph(mvm->trans, SB_CPU_2_STATUS));
  474. mvm->cur_ucode = old_type;
  475. return ret;
  476. }
  477. if (!alive_data.valid) {
  478. IWL_ERR(mvm, "Loaded ucode is not valid!\n");
  479. mvm->cur_ucode = old_type;
  480. return -EIO;
  481. }
  482. /*
  483. * update the sdio allocation according to the pointer we get in the
  484. * alive notification.
  485. */
  486. st_fwrd_space.addr = mvm->sf_space.addr;
  487. st_fwrd_space.size = mvm->sf_space.size;
  488. ret = iwl_trans_update_sf(mvm->trans, &st_fwrd_space);
  489. if (ret) {
  490. IWL_ERR(mvm, "Failed to update SF size. ret %d\n", ret);
  491. return ret;
  492. }
  493. iwl_trans_fw_alive(mvm->trans, alive_data.scd_base_addr);
  494. /*
  495. * configure and operate fw paging mechanism.
  496. * driver configures the paging flow only once, CPU2 paging image
  497. * included in the IWL_UCODE_INIT image.
  498. */
  499. if (fw->paging_mem_size) {
  500. /*
  501. * When dma is not enabled, the driver needs to copy / write
  502. * the downloaded / uploaded page to / from the smem.
  503. * This gets the location of the place were the pages are
  504. * stored.
  505. */
  506. if (!is_device_dma_capable(mvm->trans->dev)) {
  507. ret = iwl_trans_get_paging_item(mvm);
  508. if (ret) {
  509. IWL_ERR(mvm, "failed to get FW paging item\n");
  510. return ret;
  511. }
  512. }
  513. ret = iwl_save_fw_paging(mvm, fw);
  514. if (ret) {
  515. IWL_ERR(mvm, "failed to save the FW paging image\n");
  516. return ret;
  517. }
  518. ret = iwl_send_paging_cmd(mvm, fw);
  519. if (ret) {
  520. IWL_ERR(mvm, "failed to send the paging cmd\n");
  521. iwl_free_fw_paging(mvm);
  522. return ret;
  523. }
  524. }
  525. /*
  526. * Note: all the queues are enabled as part of the interface
  527. * initialization, but in firmware restart scenarios they
  528. * could be stopped, so wake them up. In firmware restart,
  529. * mac80211 will have the queues stopped as well until the
  530. * reconfiguration completes. During normal startup, they
  531. * will be empty.
  532. */
  533. memset(&mvm->queue_info, 0, sizeof(mvm->queue_info));
  534. mvm->queue_info[IWL_MVM_CMD_QUEUE].hw_queue_refcount = 1;
  535. for (i = 0; i < IEEE80211_MAX_QUEUES; i++)
  536. atomic_set(&mvm->mac80211_queue_stop_count[i], 0);
  537. mvm->ucode_loaded = true;
  538. return 0;
  539. }
  540. static int iwl_send_phy_cfg_cmd(struct iwl_mvm *mvm)
  541. {
  542. struct iwl_phy_cfg_cmd phy_cfg_cmd;
  543. enum iwl_ucode_type ucode_type = mvm->cur_ucode;
  544. /* Set parameters */
  545. phy_cfg_cmd.phy_cfg = cpu_to_le32(iwl_mvm_get_phy_config(mvm));
  546. phy_cfg_cmd.calib_control.event_trigger =
  547. mvm->fw->default_calib[ucode_type].event_trigger;
  548. phy_cfg_cmd.calib_control.flow_trigger =
  549. mvm->fw->default_calib[ucode_type].flow_trigger;
  550. IWL_DEBUG_INFO(mvm, "Sending Phy CFG command: 0x%x\n",
  551. phy_cfg_cmd.phy_cfg);
  552. return iwl_mvm_send_cmd_pdu(mvm, PHY_CONFIGURATION_CMD, 0,
  553. sizeof(phy_cfg_cmd), &phy_cfg_cmd);
  554. }
  555. int iwl_run_init_mvm_ucode(struct iwl_mvm *mvm, bool read_nvm)
  556. {
  557. struct iwl_notification_wait calib_wait;
  558. static const u16 init_complete[] = {
  559. INIT_COMPLETE_NOTIF,
  560. CALIB_RES_NOTIF_PHY_DB
  561. };
  562. int ret;
  563. lockdep_assert_held(&mvm->mutex);
  564. if (WARN_ON_ONCE(mvm->calibrating))
  565. return 0;
  566. iwl_init_notification_wait(&mvm->notif_wait,
  567. &calib_wait,
  568. init_complete,
  569. ARRAY_SIZE(init_complete),
  570. iwl_wait_phy_db_entry,
  571. mvm->phy_db);
  572. /* Will also start the device */
  573. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_INIT);
  574. if (ret) {
  575. IWL_ERR(mvm, "Failed to start INIT ucode: %d\n", ret);
  576. goto error;
  577. }
  578. ret = iwl_send_bt_init_conf(mvm);
  579. if (ret)
  580. goto error;
  581. /* Read the NVM only at driver load time, no need to do this twice */
  582. if (read_nvm) {
  583. /* Read nvm */
  584. ret = iwl_nvm_init(mvm, true);
  585. if (ret) {
  586. IWL_ERR(mvm, "Failed to read NVM: %d\n", ret);
  587. goto error;
  588. }
  589. }
  590. /* In case we read the NVM from external file, load it to the NIC */
  591. if (mvm->nvm_file_name)
  592. iwl_mvm_load_nvm_to_nic(mvm);
  593. ret = iwl_nvm_check_version(mvm->nvm_data, mvm->trans);
  594. WARN_ON(ret);
  595. /*
  596. * abort after reading the nvm in case RF Kill is on, we will complete
  597. * the init seq later when RF kill will switch to off
  598. */
  599. if (iwl_mvm_is_radio_hw_killed(mvm)) {
  600. IWL_DEBUG_RF_KILL(mvm,
  601. "jump over all phy activities due to RF kill\n");
  602. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  603. ret = 1;
  604. goto out;
  605. }
  606. mvm->calibrating = true;
  607. /* Send TX valid antennas before triggering calibrations */
  608. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  609. if (ret)
  610. goto error;
  611. /*
  612. * Send phy configurations command to init uCode
  613. * to start the 16.0 uCode init image internal calibrations.
  614. */
  615. ret = iwl_send_phy_cfg_cmd(mvm);
  616. if (ret) {
  617. IWL_ERR(mvm, "Failed to run INIT calibrations: %d\n",
  618. ret);
  619. goto error;
  620. }
  621. /*
  622. * Some things may run in the background now, but we
  623. * just wait for the calibration complete notification.
  624. */
  625. ret = iwl_wait_notification(&mvm->notif_wait, &calib_wait,
  626. MVM_UCODE_CALIB_TIMEOUT);
  627. if (ret && iwl_mvm_is_radio_hw_killed(mvm)) {
  628. IWL_DEBUG_RF_KILL(mvm, "RFKILL while calibrating.\n");
  629. ret = 1;
  630. }
  631. goto out;
  632. error:
  633. iwl_remove_notification(&mvm->notif_wait, &calib_wait);
  634. out:
  635. mvm->calibrating = false;
  636. if (iwlmvm_mod_params.init_dbg && !mvm->nvm_data) {
  637. /* we want to debug INIT and we have no NVM - fake */
  638. mvm->nvm_data = kzalloc(sizeof(struct iwl_nvm_data) +
  639. sizeof(struct ieee80211_channel) +
  640. sizeof(struct ieee80211_rate),
  641. GFP_KERNEL);
  642. if (!mvm->nvm_data)
  643. return -ENOMEM;
  644. mvm->nvm_data->bands[0].channels = mvm->nvm_data->channels;
  645. mvm->nvm_data->bands[0].n_channels = 1;
  646. mvm->nvm_data->bands[0].n_bitrates = 1;
  647. mvm->nvm_data->bands[0].bitrates =
  648. (void *)mvm->nvm_data->channels + 1;
  649. mvm->nvm_data->bands[0].bitrates->hw_value = 10;
  650. }
  651. return ret;
  652. }
  653. static void iwl_mvm_get_shared_mem_conf(struct iwl_mvm *mvm)
  654. {
  655. struct iwl_host_cmd cmd = {
  656. .id = SHARED_MEM_CFG,
  657. .flags = CMD_WANT_SKB,
  658. .data = { NULL, },
  659. .len = { 0, },
  660. };
  661. struct iwl_rx_packet *pkt;
  662. struct iwl_shared_mem_cfg *mem_cfg;
  663. u32 i;
  664. lockdep_assert_held(&mvm->mutex);
  665. if (WARN_ON(iwl_mvm_send_cmd(mvm, &cmd)))
  666. return;
  667. pkt = cmd.resp_pkt;
  668. mem_cfg = (void *)pkt->data;
  669. mvm->shared_mem_cfg.shared_mem_addr =
  670. le32_to_cpu(mem_cfg->shared_mem_addr);
  671. mvm->shared_mem_cfg.shared_mem_size =
  672. le32_to_cpu(mem_cfg->shared_mem_size);
  673. mvm->shared_mem_cfg.sample_buff_addr =
  674. le32_to_cpu(mem_cfg->sample_buff_addr);
  675. mvm->shared_mem_cfg.sample_buff_size =
  676. le32_to_cpu(mem_cfg->sample_buff_size);
  677. mvm->shared_mem_cfg.txfifo_addr = le32_to_cpu(mem_cfg->txfifo_addr);
  678. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.txfifo_size); i++)
  679. mvm->shared_mem_cfg.txfifo_size[i] =
  680. le32_to_cpu(mem_cfg->txfifo_size[i]);
  681. for (i = 0; i < ARRAY_SIZE(mvm->shared_mem_cfg.rxfifo_size); i++)
  682. mvm->shared_mem_cfg.rxfifo_size[i] =
  683. le32_to_cpu(mem_cfg->rxfifo_size[i]);
  684. mvm->shared_mem_cfg.page_buff_addr =
  685. le32_to_cpu(mem_cfg->page_buff_addr);
  686. mvm->shared_mem_cfg.page_buff_size =
  687. le32_to_cpu(mem_cfg->page_buff_size);
  688. IWL_DEBUG_INFO(mvm, "SHARED MEM CFG: got memory offsets/sizes\n");
  689. iwl_free_resp(&cmd);
  690. }
  691. int iwl_mvm_fw_dbg_collect_desc(struct iwl_mvm *mvm,
  692. struct iwl_mvm_dump_desc *desc,
  693. struct iwl_fw_dbg_trigger_tlv *trigger)
  694. {
  695. unsigned int delay = 0;
  696. if (trigger)
  697. delay = msecs_to_jiffies(le32_to_cpu(trigger->stop_delay));
  698. if (test_and_set_bit(IWL_MVM_STATUS_DUMPING_FW_LOG, &mvm->status))
  699. return -EBUSY;
  700. if (WARN_ON(mvm->fw_dump_desc))
  701. iwl_mvm_free_fw_dump_desc(mvm);
  702. IWL_WARN(mvm, "Collecting data: trigger %d fired.\n",
  703. le32_to_cpu(desc->trig_desc.type));
  704. mvm->fw_dump_desc = desc;
  705. mvm->fw_dump_trig = trigger;
  706. queue_delayed_work(system_wq, &mvm->fw_dump_wk, delay);
  707. return 0;
  708. }
  709. int iwl_mvm_fw_dbg_collect(struct iwl_mvm *mvm, enum iwl_fw_dbg_trigger trig,
  710. const char *str, size_t len,
  711. struct iwl_fw_dbg_trigger_tlv *trigger)
  712. {
  713. struct iwl_mvm_dump_desc *desc;
  714. desc = kzalloc(sizeof(*desc) + len, GFP_ATOMIC);
  715. if (!desc)
  716. return -ENOMEM;
  717. desc->len = len;
  718. desc->trig_desc.type = cpu_to_le32(trig);
  719. memcpy(desc->trig_desc.data, str, len);
  720. return iwl_mvm_fw_dbg_collect_desc(mvm, desc, trigger);
  721. }
  722. int iwl_mvm_fw_dbg_collect_trig(struct iwl_mvm *mvm,
  723. struct iwl_fw_dbg_trigger_tlv *trigger,
  724. const char *fmt, ...)
  725. {
  726. u16 occurrences = le16_to_cpu(trigger->occurrences);
  727. int ret, len = 0;
  728. char buf[64];
  729. if (!occurrences)
  730. return 0;
  731. if (fmt) {
  732. va_list ap;
  733. buf[sizeof(buf) - 1] = '\0';
  734. va_start(ap, fmt);
  735. vsnprintf(buf, sizeof(buf), fmt, ap);
  736. va_end(ap);
  737. /* check for truncation */
  738. if (WARN_ON_ONCE(buf[sizeof(buf) - 1]))
  739. buf[sizeof(buf) - 1] = '\0';
  740. len = strlen(buf) + 1;
  741. }
  742. ret = iwl_mvm_fw_dbg_collect(mvm, le32_to_cpu(trigger->id), buf, len,
  743. trigger);
  744. if (ret)
  745. return ret;
  746. trigger->occurrences = cpu_to_le16(occurrences - 1);
  747. return 0;
  748. }
  749. static inline void iwl_mvm_restart_early_start(struct iwl_mvm *mvm)
  750. {
  751. if (mvm->cfg->device_family == IWL_DEVICE_FAMILY_7000)
  752. iwl_clear_bits_prph(mvm->trans, MON_BUFF_SAMPLE_CTL, 0x100);
  753. else
  754. iwl_write_prph(mvm->trans, DBGC_IN_SAMPLE, 1);
  755. }
  756. int iwl_mvm_start_fw_dbg_conf(struct iwl_mvm *mvm, u8 conf_id)
  757. {
  758. u8 *ptr;
  759. int ret;
  760. int i;
  761. if (WARN_ONCE(conf_id >= ARRAY_SIZE(mvm->fw->dbg_conf_tlv),
  762. "Invalid configuration %d\n", conf_id))
  763. return -EINVAL;
  764. /* EARLY START - firmware's configuration is hard coded */
  765. if ((!mvm->fw->dbg_conf_tlv[conf_id] ||
  766. !mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds) &&
  767. conf_id == FW_DBG_START_FROM_ALIVE) {
  768. iwl_mvm_restart_early_start(mvm);
  769. return 0;
  770. }
  771. if (!mvm->fw->dbg_conf_tlv[conf_id])
  772. return -EINVAL;
  773. if (mvm->fw_dbg_conf != FW_DBG_INVALID)
  774. IWL_WARN(mvm, "FW already configured (%d) - re-configuring\n",
  775. mvm->fw_dbg_conf);
  776. /* Send all HCMDs for configuring the FW debug */
  777. ptr = (void *)&mvm->fw->dbg_conf_tlv[conf_id]->hcmd;
  778. for (i = 0; i < mvm->fw->dbg_conf_tlv[conf_id]->num_of_hcmds; i++) {
  779. struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr;
  780. ret = iwl_mvm_send_cmd_pdu(mvm, cmd->id, 0,
  781. le16_to_cpu(cmd->len), cmd->data);
  782. if (ret)
  783. return ret;
  784. ptr += sizeof(*cmd);
  785. ptr += le16_to_cpu(cmd->len);
  786. }
  787. mvm->fw_dbg_conf = conf_id;
  788. return 0;
  789. }
  790. static int iwl_mvm_config_ltr(struct iwl_mvm *mvm)
  791. {
  792. struct iwl_ltr_config_cmd cmd = {
  793. .flags = cpu_to_le32(LTR_CFG_FLAG_FEATURE_ENABLE),
  794. };
  795. if (!mvm->trans->ltr_enabled)
  796. return 0;
  797. return iwl_mvm_send_cmd_pdu(mvm, LTR_CONFIG, 0,
  798. sizeof(cmd), &cmd);
  799. }
  800. int iwl_mvm_up(struct iwl_mvm *mvm)
  801. {
  802. int ret, i;
  803. struct ieee80211_channel *chan;
  804. struct cfg80211_chan_def chandef;
  805. lockdep_assert_held(&mvm->mutex);
  806. ret = iwl_trans_start_hw(mvm->trans);
  807. if (ret)
  808. return ret;
  809. /*
  810. * If we haven't completed the run of the init ucode during
  811. * module loading, load init ucode now
  812. * (for example, if we were in RFKILL)
  813. */
  814. ret = iwl_run_init_mvm_ucode(mvm, false);
  815. if (ret && !iwlmvm_mod_params.init_dbg) {
  816. IWL_ERR(mvm, "Failed to run INIT ucode: %d\n", ret);
  817. /* this can't happen */
  818. if (WARN_ON(ret > 0))
  819. ret = -ERFKILL;
  820. goto error;
  821. }
  822. if (!iwlmvm_mod_params.init_dbg) {
  823. /*
  824. * Stop and start the transport without entering low power
  825. * mode. This will save the state of other components on the
  826. * device that are triggered by the INIT firwmare (MFUART).
  827. */
  828. _iwl_trans_stop_device(mvm->trans, false);
  829. ret = _iwl_trans_start_hw(mvm->trans, false);
  830. if (ret)
  831. goto error;
  832. }
  833. if (iwlmvm_mod_params.init_dbg)
  834. return 0;
  835. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_REGULAR);
  836. if (ret) {
  837. IWL_ERR(mvm, "Failed to start RT ucode: %d\n", ret);
  838. goto error;
  839. }
  840. iwl_mvm_get_shared_mem_conf(mvm);
  841. ret = iwl_mvm_sf_update(mvm, NULL, false);
  842. if (ret)
  843. IWL_ERR(mvm, "Failed to initialize Smart Fifo\n");
  844. mvm->fw_dbg_conf = FW_DBG_INVALID;
  845. /* if we have a destination, assume EARLY START */
  846. if (mvm->fw->dbg_dest_tlv)
  847. mvm->fw_dbg_conf = FW_DBG_START_FROM_ALIVE;
  848. iwl_mvm_start_fw_dbg_conf(mvm, FW_DBG_START_FROM_ALIVE);
  849. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  850. if (ret)
  851. goto error;
  852. ret = iwl_send_bt_init_conf(mvm);
  853. if (ret)
  854. goto error;
  855. /* Send phy db control command and then phy db calibration*/
  856. ret = iwl_send_phy_db_data(mvm->phy_db);
  857. if (ret)
  858. goto error;
  859. ret = iwl_send_phy_cfg_cmd(mvm);
  860. if (ret)
  861. goto error;
  862. /* init the fw <-> mac80211 STA mapping */
  863. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  864. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  865. mvm->tdls_cs.peer.sta_id = IWL_MVM_STATION_COUNT;
  866. /* reset quota debouncing buffer - 0xff will yield invalid data */
  867. memset(&mvm->last_quota_cmd, 0xff, sizeof(mvm->last_quota_cmd));
  868. /* Add auxiliary station for scanning */
  869. ret = iwl_mvm_add_aux_sta(mvm);
  870. if (ret)
  871. goto error;
  872. /* Add all the PHY contexts */
  873. chan = &mvm->hw->wiphy->bands[IEEE80211_BAND_2GHZ]->channels[0];
  874. cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_NO_HT);
  875. for (i = 0; i < NUM_PHY_CTX; i++) {
  876. /*
  877. * The channel used here isn't relevant as it's
  878. * going to be overwritten in the other flows.
  879. * For now use the first channel we have.
  880. */
  881. ret = iwl_mvm_phy_ctxt_add(mvm, &mvm->phy_ctxts[i],
  882. &chandef, 1, 1);
  883. if (ret)
  884. goto error;
  885. }
  886. /* Initialize tx backoffs to the minimal possible */
  887. iwl_mvm_tt_tx_backoff(mvm, 0);
  888. WARN_ON(iwl_mvm_config_ltr(mvm));
  889. ret = iwl_mvm_power_update_device(mvm);
  890. if (ret)
  891. goto error;
  892. /*
  893. * RTNL is not taken during Ct-kill, but we don't need to scan/Tx
  894. * anyway, so don't init MCC.
  895. */
  896. if (!test_bit(IWL_MVM_STATUS_HW_CTKILL, &mvm->status)) {
  897. ret = iwl_mvm_init_mcc(mvm);
  898. if (ret)
  899. goto error;
  900. }
  901. if (fw_has_capa(&mvm->fw->ucode_capa, IWL_UCODE_TLV_CAPA_UMAC_SCAN)) {
  902. ret = iwl_mvm_config_scan(mvm);
  903. if (ret)
  904. goto error;
  905. }
  906. if (iwl_mvm_is_csum_supported(mvm) &&
  907. mvm->cfg->features & NETIF_F_RXCSUM)
  908. iwl_trans_write_prph(mvm->trans, RX_EN_CSUM, 0x3);
  909. /* allow FW/transport low power modes if not during restart */
  910. if (!test_bit(IWL_MVM_STATUS_IN_HW_RESTART, &mvm->status))
  911. iwl_mvm_unref(mvm, IWL_MVM_REF_UCODE_DOWN);
  912. IWL_DEBUG_INFO(mvm, "RT uCode started.\n");
  913. return 0;
  914. error:
  915. iwl_trans_stop_device(mvm->trans);
  916. return ret;
  917. }
  918. int iwl_mvm_load_d3_fw(struct iwl_mvm *mvm)
  919. {
  920. int ret, i;
  921. lockdep_assert_held(&mvm->mutex);
  922. ret = iwl_trans_start_hw(mvm->trans);
  923. if (ret)
  924. return ret;
  925. ret = iwl_mvm_load_ucode_wait_alive(mvm, IWL_UCODE_WOWLAN);
  926. if (ret) {
  927. IWL_ERR(mvm, "Failed to start WoWLAN firmware: %d\n", ret);
  928. goto error;
  929. }
  930. ret = iwl_send_tx_ant_cfg(mvm, iwl_mvm_get_valid_tx_ant(mvm));
  931. if (ret)
  932. goto error;
  933. /* Send phy db control command and then phy db calibration*/
  934. ret = iwl_send_phy_db_data(mvm->phy_db);
  935. if (ret)
  936. goto error;
  937. ret = iwl_send_phy_cfg_cmd(mvm);
  938. if (ret)
  939. goto error;
  940. /* init the fw <-> mac80211 STA mapping */
  941. for (i = 0; i < IWL_MVM_STATION_COUNT; i++)
  942. RCU_INIT_POINTER(mvm->fw_id_to_mac_id[i], NULL);
  943. /* Add auxiliary station for scanning */
  944. ret = iwl_mvm_add_aux_sta(mvm);
  945. if (ret)
  946. goto error;
  947. return 0;
  948. error:
  949. iwl_trans_stop_device(mvm->trans);
  950. return ret;
  951. }
  952. void iwl_mvm_rx_card_state_notif(struct iwl_mvm *mvm,
  953. struct iwl_rx_cmd_buffer *rxb)
  954. {
  955. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  956. struct iwl_card_state_notif *card_state_notif = (void *)pkt->data;
  957. u32 flags = le32_to_cpu(card_state_notif->flags);
  958. IWL_DEBUG_RF_KILL(mvm, "Card state received: HW:%s SW:%s CT:%s\n",
  959. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  960. (flags & SW_CARD_DISABLED) ? "Kill" : "On",
  961. (flags & CT_KILL_CARD_DISABLED) ?
  962. "Reached" : "Not reached");
  963. }
  964. void iwl_mvm_rx_mfuart_notif(struct iwl_mvm *mvm,
  965. struct iwl_rx_cmd_buffer *rxb)
  966. {
  967. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  968. struct iwl_mfuart_load_notif *mfuart_notif = (void *)pkt->data;
  969. IWL_DEBUG_INFO(mvm,
  970. "MFUART: installed ver: 0x%08x, external ver: 0x%08x, status: 0x%08x, duration: 0x%08x\n",
  971. le32_to_cpu(mfuart_notif->installed_ver),
  972. le32_to_cpu(mfuart_notif->external_ver),
  973. le32_to_cpu(mfuart_notif->status),
  974. le32_to_cpu(mfuart_notif->duration));
  975. }