p54pci.c 17 KB

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  1. /*
  2. * Linux device driver for PCI based Prism54
  3. *
  4. * Copyright (c) 2006, Michael Wu <flamingice@sourmilk.net>
  5. * Copyright (c) 2008, Christian Lamparter <chunkeey@web.de>
  6. *
  7. * Based on the islsm (softmac prism54) driver, which is:
  8. * Copyright 2004-2006 Jean-Baptiste Note <jean-baptiste.note@m4x.org>, et al.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/pci.h>
  15. #include <linux/slab.h>
  16. #include <linux/firmware.h>
  17. #include <linux/etherdevice.h>
  18. #include <linux/delay.h>
  19. #include <linux/completion.h>
  20. #include <linux/module.h>
  21. #include <net/mac80211.h>
  22. #include "p54.h"
  23. #include "lmac.h"
  24. #include "p54pci.h"
  25. MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
  26. MODULE_DESCRIPTION("Prism54 PCI wireless driver");
  27. MODULE_LICENSE("GPL");
  28. MODULE_ALIAS("prism54pci");
  29. MODULE_FIRMWARE("isl3886pci");
  30. static const struct pci_device_id p54p_table[] = {
  31. /* Intersil PRISM Duette/Prism GT Wireless LAN adapter */
  32. { PCI_DEVICE(0x1260, 0x3890) },
  33. /* 3COM 3CRWE154G72 Wireless LAN adapter */
  34. { PCI_DEVICE(0x10b7, 0x6001) },
  35. /* Intersil PRISM Indigo Wireless LAN adapter */
  36. { PCI_DEVICE(0x1260, 0x3877) },
  37. /* Intersil PRISM Javelin/Xbow Wireless LAN adapter */
  38. { PCI_DEVICE(0x1260, 0x3886) },
  39. /* Intersil PRISM Xbow Wireless LAN adapter (Symbol AP-300) */
  40. { PCI_DEVICE(0x1260, 0xffff) },
  41. { },
  42. };
  43. MODULE_DEVICE_TABLE(pci, p54p_table);
  44. static int p54p_upload_firmware(struct ieee80211_hw *dev)
  45. {
  46. struct p54p_priv *priv = dev->priv;
  47. __le32 reg;
  48. int err;
  49. __le32 *data;
  50. u32 remains, left, device_addr;
  51. P54P_WRITE(int_enable, cpu_to_le32(0));
  52. P54P_READ(int_enable);
  53. udelay(10);
  54. reg = P54P_READ(ctrl_stat);
  55. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  56. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
  57. P54P_WRITE(ctrl_stat, reg);
  58. P54P_READ(ctrl_stat);
  59. udelay(10);
  60. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  61. P54P_WRITE(ctrl_stat, reg);
  62. wmb();
  63. udelay(10);
  64. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  65. P54P_WRITE(ctrl_stat, reg);
  66. wmb();
  67. /* wait for the firmware to reset properly */
  68. mdelay(10);
  69. err = p54_parse_firmware(dev, priv->firmware);
  70. if (err)
  71. return err;
  72. if (priv->common.fw_interface != FW_LM86) {
  73. dev_err(&priv->pdev->dev, "wrong firmware, "
  74. "please get a LM86(PCI) firmware a try again.\n");
  75. return -EINVAL;
  76. }
  77. data = (__le32 *) priv->firmware->data;
  78. remains = priv->firmware->size;
  79. device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
  80. while (remains) {
  81. u32 i = 0;
  82. left = min((u32)0x1000, remains);
  83. P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
  84. P54P_READ(int_enable);
  85. device_addr += 0x1000;
  86. while (i < left) {
  87. P54P_WRITE(direct_mem_win[i], *data++);
  88. i += sizeof(u32);
  89. }
  90. remains -= left;
  91. P54P_READ(int_enable);
  92. }
  93. reg = P54P_READ(ctrl_stat);
  94. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
  95. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  96. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
  97. P54P_WRITE(ctrl_stat, reg);
  98. P54P_READ(ctrl_stat);
  99. udelay(10);
  100. reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
  101. P54P_WRITE(ctrl_stat, reg);
  102. wmb();
  103. udelay(10);
  104. reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
  105. P54P_WRITE(ctrl_stat, reg);
  106. wmb();
  107. udelay(10);
  108. /* wait for the firmware to boot properly */
  109. mdelay(100);
  110. return 0;
  111. }
  112. static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
  113. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  114. struct sk_buff **rx_buf, u32 index)
  115. {
  116. struct p54p_priv *priv = dev->priv;
  117. struct p54p_ring_control *ring_control = priv->ring_control;
  118. u32 limit, idx, i;
  119. idx = le32_to_cpu(ring_control->host_idx[ring_index]);
  120. limit = idx;
  121. limit -= index;
  122. limit = ring_limit - limit;
  123. i = idx % ring_limit;
  124. while (limit-- > 1) {
  125. struct p54p_desc *desc = &ring[i];
  126. if (!desc->host_addr) {
  127. struct sk_buff *skb;
  128. dma_addr_t mapping;
  129. skb = dev_alloc_skb(priv->common.rx_mtu + 32);
  130. if (!skb)
  131. break;
  132. mapping = pci_map_single(priv->pdev,
  133. skb_tail_pointer(skb),
  134. priv->common.rx_mtu + 32,
  135. PCI_DMA_FROMDEVICE);
  136. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  137. dev_kfree_skb_any(skb);
  138. dev_err(&priv->pdev->dev,
  139. "RX DMA Mapping error\n");
  140. break;
  141. }
  142. desc->host_addr = cpu_to_le32(mapping);
  143. desc->device_addr = 0; // FIXME: necessary?
  144. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  145. desc->flags = 0;
  146. rx_buf[i] = skb;
  147. }
  148. i++;
  149. idx++;
  150. i %= ring_limit;
  151. }
  152. wmb();
  153. ring_control->host_idx[ring_index] = cpu_to_le32(idx);
  154. }
  155. static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
  156. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  157. struct sk_buff **rx_buf)
  158. {
  159. struct p54p_priv *priv = dev->priv;
  160. struct p54p_ring_control *ring_control = priv->ring_control;
  161. struct p54p_desc *desc;
  162. u32 idx, i;
  163. i = (*index) % ring_limit;
  164. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  165. idx %= ring_limit;
  166. while (i != idx) {
  167. u16 len;
  168. struct sk_buff *skb;
  169. dma_addr_t dma_addr;
  170. desc = &ring[i];
  171. len = le16_to_cpu(desc->len);
  172. skb = rx_buf[i];
  173. if (!skb) {
  174. i++;
  175. i %= ring_limit;
  176. continue;
  177. }
  178. if (unlikely(len > priv->common.rx_mtu)) {
  179. if (net_ratelimit())
  180. dev_err(&priv->pdev->dev, "rx'd frame size "
  181. "exceeds length threshold.\n");
  182. len = priv->common.rx_mtu;
  183. }
  184. dma_addr = le32_to_cpu(desc->host_addr);
  185. pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
  186. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  187. skb_put(skb, len);
  188. if (p54_rx(dev, skb)) {
  189. pci_unmap_single(priv->pdev, dma_addr,
  190. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  191. rx_buf[i] = NULL;
  192. desc->host_addr = cpu_to_le32(0);
  193. } else {
  194. skb_trim(skb, 0);
  195. pci_dma_sync_single_for_device(priv->pdev, dma_addr,
  196. priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
  197. desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
  198. }
  199. i++;
  200. i %= ring_limit;
  201. }
  202. p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
  203. }
  204. static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
  205. int ring_index, struct p54p_desc *ring, u32 ring_limit,
  206. struct sk_buff **tx_buf)
  207. {
  208. struct p54p_priv *priv = dev->priv;
  209. struct p54p_ring_control *ring_control = priv->ring_control;
  210. struct p54p_desc *desc;
  211. struct sk_buff *skb;
  212. u32 idx, i;
  213. i = (*index) % ring_limit;
  214. (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
  215. idx %= ring_limit;
  216. while (i != idx) {
  217. desc = &ring[i];
  218. skb = tx_buf[i];
  219. tx_buf[i] = NULL;
  220. pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
  221. le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
  222. desc->host_addr = 0;
  223. desc->device_addr = 0;
  224. desc->len = 0;
  225. desc->flags = 0;
  226. if (skb && FREE_AFTER_TX(skb))
  227. p54_free_skb(dev, skb);
  228. i++;
  229. i %= ring_limit;
  230. }
  231. }
  232. static void p54p_tasklet(unsigned long dev_id)
  233. {
  234. struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
  235. struct p54p_priv *priv = dev->priv;
  236. struct p54p_ring_control *ring_control = priv->ring_control;
  237. p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
  238. ARRAY_SIZE(ring_control->tx_mgmt),
  239. priv->tx_buf_mgmt);
  240. p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
  241. ARRAY_SIZE(ring_control->tx_data),
  242. priv->tx_buf_data);
  243. p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
  244. ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
  245. p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
  246. ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
  247. wmb();
  248. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  249. }
  250. static irqreturn_t p54p_interrupt(int irq, void *dev_id)
  251. {
  252. struct ieee80211_hw *dev = dev_id;
  253. struct p54p_priv *priv = dev->priv;
  254. __le32 reg;
  255. reg = P54P_READ(int_ident);
  256. if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
  257. goto out;
  258. }
  259. P54P_WRITE(int_ack, reg);
  260. reg &= P54P_READ(int_enable);
  261. if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
  262. tasklet_schedule(&priv->tasklet);
  263. else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
  264. complete(&priv->boot_comp);
  265. out:
  266. return reg ? IRQ_HANDLED : IRQ_NONE;
  267. }
  268. static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  269. {
  270. unsigned long flags;
  271. struct p54p_priv *priv = dev->priv;
  272. struct p54p_ring_control *ring_control = priv->ring_control;
  273. struct p54p_desc *desc;
  274. dma_addr_t mapping;
  275. u32 idx, i;
  276. spin_lock_irqsave(&priv->lock, flags);
  277. idx = le32_to_cpu(ring_control->host_idx[1]);
  278. i = idx % ARRAY_SIZE(ring_control->tx_data);
  279. mapping = pci_map_single(priv->pdev, skb->data, skb->len,
  280. PCI_DMA_TODEVICE);
  281. if (pci_dma_mapping_error(priv->pdev, mapping)) {
  282. spin_unlock_irqrestore(&priv->lock, flags);
  283. p54_free_skb(dev, skb);
  284. dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
  285. return ;
  286. }
  287. priv->tx_buf_data[i] = skb;
  288. desc = &ring_control->tx_data[i];
  289. desc->host_addr = cpu_to_le32(mapping);
  290. desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
  291. desc->len = cpu_to_le16(skb->len);
  292. desc->flags = 0;
  293. wmb();
  294. ring_control->host_idx[1] = cpu_to_le32(idx + 1);
  295. spin_unlock_irqrestore(&priv->lock, flags);
  296. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  297. P54P_READ(dev_int);
  298. }
  299. static void p54p_stop(struct ieee80211_hw *dev)
  300. {
  301. struct p54p_priv *priv = dev->priv;
  302. struct p54p_ring_control *ring_control = priv->ring_control;
  303. unsigned int i;
  304. struct p54p_desc *desc;
  305. P54P_WRITE(int_enable, cpu_to_le32(0));
  306. P54P_READ(int_enable);
  307. udelay(10);
  308. free_irq(priv->pdev->irq, dev);
  309. tasklet_kill(&priv->tasklet);
  310. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  311. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
  312. desc = &ring_control->rx_data[i];
  313. if (desc->host_addr)
  314. pci_unmap_single(priv->pdev,
  315. le32_to_cpu(desc->host_addr),
  316. priv->common.rx_mtu + 32,
  317. PCI_DMA_FROMDEVICE);
  318. kfree_skb(priv->rx_buf_data[i]);
  319. priv->rx_buf_data[i] = NULL;
  320. }
  321. for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
  322. desc = &ring_control->rx_mgmt[i];
  323. if (desc->host_addr)
  324. pci_unmap_single(priv->pdev,
  325. le32_to_cpu(desc->host_addr),
  326. priv->common.rx_mtu + 32,
  327. PCI_DMA_FROMDEVICE);
  328. kfree_skb(priv->rx_buf_mgmt[i]);
  329. priv->rx_buf_mgmt[i] = NULL;
  330. }
  331. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
  332. desc = &ring_control->tx_data[i];
  333. if (desc->host_addr)
  334. pci_unmap_single(priv->pdev,
  335. le32_to_cpu(desc->host_addr),
  336. le16_to_cpu(desc->len),
  337. PCI_DMA_TODEVICE);
  338. p54_free_skb(dev, priv->tx_buf_data[i]);
  339. priv->tx_buf_data[i] = NULL;
  340. }
  341. for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
  342. desc = &ring_control->tx_mgmt[i];
  343. if (desc->host_addr)
  344. pci_unmap_single(priv->pdev,
  345. le32_to_cpu(desc->host_addr),
  346. le16_to_cpu(desc->len),
  347. PCI_DMA_TODEVICE);
  348. p54_free_skb(dev, priv->tx_buf_mgmt[i]);
  349. priv->tx_buf_mgmt[i] = NULL;
  350. }
  351. memset(ring_control, 0, sizeof(*ring_control));
  352. }
  353. static int p54p_open(struct ieee80211_hw *dev)
  354. {
  355. struct p54p_priv *priv = dev->priv;
  356. int err;
  357. long timeout;
  358. init_completion(&priv->boot_comp);
  359. err = request_irq(priv->pdev->irq, p54p_interrupt,
  360. IRQF_SHARED, "p54pci", dev);
  361. if (err) {
  362. dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
  363. return err;
  364. }
  365. memset(priv->ring_control, 0, sizeof(*priv->ring_control));
  366. err = p54p_upload_firmware(dev);
  367. if (err) {
  368. free_irq(priv->pdev->irq, dev);
  369. return err;
  370. }
  371. priv->rx_idx_data = priv->tx_idx_data = 0;
  372. priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
  373. p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
  374. ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
  375. p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
  376. ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
  377. P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
  378. P54P_READ(ring_control_base);
  379. wmb();
  380. udelay(10);
  381. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
  382. P54P_READ(int_enable);
  383. wmb();
  384. udelay(10);
  385. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
  386. P54P_READ(dev_int);
  387. timeout = wait_for_completion_interruptible_timeout(
  388. &priv->boot_comp, HZ);
  389. if (timeout <= 0) {
  390. wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
  391. p54p_stop(dev);
  392. return timeout ? -ERESTARTSYS : -ETIMEDOUT;
  393. }
  394. P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
  395. P54P_READ(int_enable);
  396. wmb();
  397. udelay(10);
  398. P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
  399. P54P_READ(dev_int);
  400. wmb();
  401. udelay(10);
  402. return 0;
  403. }
  404. static void p54p_firmware_step2(const struct firmware *fw,
  405. void *context)
  406. {
  407. struct p54p_priv *priv = context;
  408. struct ieee80211_hw *dev = priv->common.hw;
  409. struct pci_dev *pdev = priv->pdev;
  410. int err;
  411. if (!fw) {
  412. dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
  413. err = -ENOENT;
  414. goto out;
  415. }
  416. priv->firmware = fw;
  417. err = p54p_open(dev);
  418. if (err)
  419. goto out;
  420. err = p54_read_eeprom(dev);
  421. p54p_stop(dev);
  422. if (err)
  423. goto out;
  424. err = p54_register_common(dev, &pdev->dev);
  425. if (err)
  426. goto out;
  427. out:
  428. complete(&priv->fw_loaded);
  429. if (err) {
  430. struct device *parent = pdev->dev.parent;
  431. if (parent)
  432. device_lock(parent);
  433. /*
  434. * This will indirectly result in a call to p54p_remove.
  435. * Hence, we don't need to bother with freeing any
  436. * allocated ressources at all.
  437. */
  438. device_release_driver(&pdev->dev);
  439. if (parent)
  440. device_unlock(parent);
  441. }
  442. pci_dev_put(pdev);
  443. }
  444. static int p54p_probe(struct pci_dev *pdev,
  445. const struct pci_device_id *id)
  446. {
  447. struct p54p_priv *priv;
  448. struct ieee80211_hw *dev;
  449. unsigned long mem_addr, mem_len;
  450. int err;
  451. pci_dev_get(pdev);
  452. err = pci_enable_device(pdev);
  453. if (err) {
  454. dev_err(&pdev->dev, "Cannot enable new PCI device\n");
  455. return err;
  456. }
  457. mem_addr = pci_resource_start(pdev, 0);
  458. mem_len = pci_resource_len(pdev, 0);
  459. if (mem_len < sizeof(struct p54p_csr)) {
  460. dev_err(&pdev->dev, "Too short PCI resources\n");
  461. err = -ENODEV;
  462. goto err_disable_dev;
  463. }
  464. err = pci_request_regions(pdev, "p54pci");
  465. if (err) {
  466. dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
  467. goto err_disable_dev;
  468. }
  469. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  470. if (!err)
  471. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  472. if (err) {
  473. dev_err(&pdev->dev, "No suitable DMA available\n");
  474. goto err_free_reg;
  475. }
  476. pci_set_master(pdev);
  477. pci_try_set_mwi(pdev);
  478. pci_write_config_byte(pdev, 0x40, 0);
  479. pci_write_config_byte(pdev, 0x41, 0);
  480. dev = p54_init_common(sizeof(*priv));
  481. if (!dev) {
  482. dev_err(&pdev->dev, "ieee80211 alloc failed\n");
  483. err = -ENOMEM;
  484. goto err_free_reg;
  485. }
  486. priv = dev->priv;
  487. priv->pdev = pdev;
  488. init_completion(&priv->fw_loaded);
  489. SET_IEEE80211_DEV(dev, &pdev->dev);
  490. pci_set_drvdata(pdev, dev);
  491. priv->map = ioremap(mem_addr, mem_len);
  492. if (!priv->map) {
  493. dev_err(&pdev->dev, "Cannot map device memory\n");
  494. err = -ENOMEM;
  495. goto err_free_dev;
  496. }
  497. priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
  498. &priv->ring_control_dma);
  499. if (!priv->ring_control) {
  500. dev_err(&pdev->dev, "Cannot allocate rings\n");
  501. err = -ENOMEM;
  502. goto err_iounmap;
  503. }
  504. priv->common.open = p54p_open;
  505. priv->common.stop = p54p_stop;
  506. priv->common.tx = p54p_tx;
  507. spin_lock_init(&priv->lock);
  508. tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
  509. err = request_firmware_nowait(THIS_MODULE, 1, "isl3886pci",
  510. &priv->pdev->dev, GFP_KERNEL,
  511. priv, p54p_firmware_step2);
  512. if (!err)
  513. return 0;
  514. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  515. priv->ring_control, priv->ring_control_dma);
  516. err_iounmap:
  517. iounmap(priv->map);
  518. err_free_dev:
  519. p54_free_common(dev);
  520. err_free_reg:
  521. pci_release_regions(pdev);
  522. err_disable_dev:
  523. pci_disable_device(pdev);
  524. pci_dev_put(pdev);
  525. return err;
  526. }
  527. static void p54p_remove(struct pci_dev *pdev)
  528. {
  529. struct ieee80211_hw *dev = pci_get_drvdata(pdev);
  530. struct p54p_priv *priv;
  531. if (!dev)
  532. return;
  533. priv = dev->priv;
  534. wait_for_completion(&priv->fw_loaded);
  535. p54_unregister_common(dev);
  536. release_firmware(priv->firmware);
  537. pci_free_consistent(pdev, sizeof(*priv->ring_control),
  538. priv->ring_control, priv->ring_control_dma);
  539. iounmap(priv->map);
  540. pci_release_regions(pdev);
  541. pci_disable_device(pdev);
  542. p54_free_common(dev);
  543. }
  544. #ifdef CONFIG_PM_SLEEP
  545. static int p54p_suspend(struct device *device)
  546. {
  547. struct pci_dev *pdev = to_pci_dev(device);
  548. pci_save_state(pdev);
  549. pci_set_power_state(pdev, PCI_D3hot);
  550. pci_disable_device(pdev);
  551. return 0;
  552. }
  553. static int p54p_resume(struct device *device)
  554. {
  555. struct pci_dev *pdev = to_pci_dev(device);
  556. int err;
  557. err = pci_reenable_device(pdev);
  558. if (err)
  559. return err;
  560. return pci_set_power_state(pdev, PCI_D0);
  561. }
  562. static SIMPLE_DEV_PM_OPS(p54pci_pm_ops, p54p_suspend, p54p_resume);
  563. #define P54P_PM_OPS (&p54pci_pm_ops)
  564. #else
  565. #define P54P_PM_OPS (NULL)
  566. #endif /* CONFIG_PM_SLEEP */
  567. static struct pci_driver p54p_driver = {
  568. .name = "p54pci",
  569. .id_table = p54p_table,
  570. .probe = p54p_probe,
  571. .remove = p54p_remove,
  572. .driver.pm = P54P_PM_OPS,
  573. };
  574. module_pci_driver(p54p_driver);