p54spi.c 17 KB

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  1. /*
  2. * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de>
  3. * Copyright 2008 Johannes Berg <johannes@sipsolutions.net>
  4. *
  5. * This driver is a port from stlc45xx:
  6. * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies).
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. */
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/firmware.h>
  26. #include <linux/delay.h>
  27. #include <linux/irq.h>
  28. #include <linux/spi/spi.h>
  29. #include <linux/etherdevice.h>
  30. #include <linux/gpio.h>
  31. #include <linux/slab.h>
  32. #include "p54spi.h"
  33. #include "p54.h"
  34. #include "lmac.h"
  35. #ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
  36. #include "p54spi_eeprom.h"
  37. #endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
  38. MODULE_FIRMWARE("3826.arm");
  39. /* gpios should be handled in board files and provided via platform data,
  40. * but because it's currently impossible for p54spi to have a header file
  41. * in include/linux, let's use module paramaters for now
  42. */
  43. static int p54spi_gpio_power = 97;
  44. module_param(p54spi_gpio_power, int, 0444);
  45. MODULE_PARM_DESC(p54spi_gpio_power, "gpio number for power line");
  46. static int p54spi_gpio_irq = 87;
  47. module_param(p54spi_gpio_irq, int, 0444);
  48. MODULE_PARM_DESC(p54spi_gpio_irq, "gpio number for irq line");
  49. static void p54spi_spi_read(struct p54s_priv *priv, u8 address,
  50. void *buf, size_t len)
  51. {
  52. struct spi_transfer t[2];
  53. struct spi_message m;
  54. __le16 addr;
  55. /* We first push the address */
  56. addr = cpu_to_le16(address << 8 | SPI_ADRS_READ_BIT_15);
  57. spi_message_init(&m);
  58. memset(t, 0, sizeof(t));
  59. t[0].tx_buf = &addr;
  60. t[0].len = sizeof(addr);
  61. spi_message_add_tail(&t[0], &m);
  62. t[1].rx_buf = buf;
  63. t[1].len = len;
  64. spi_message_add_tail(&t[1], &m);
  65. spi_sync(priv->spi, &m);
  66. }
  67. static void p54spi_spi_write(struct p54s_priv *priv, u8 address,
  68. const void *buf, size_t len)
  69. {
  70. struct spi_transfer t[3];
  71. struct spi_message m;
  72. __le16 addr;
  73. /* We first push the address */
  74. addr = cpu_to_le16(address << 8);
  75. spi_message_init(&m);
  76. memset(t, 0, sizeof(t));
  77. t[0].tx_buf = &addr;
  78. t[0].len = sizeof(addr);
  79. spi_message_add_tail(&t[0], &m);
  80. t[1].tx_buf = buf;
  81. t[1].len = len & ~1;
  82. spi_message_add_tail(&t[1], &m);
  83. if (len % 2) {
  84. __le16 last_word;
  85. last_word = cpu_to_le16(((u8 *)buf)[len - 1]);
  86. t[2].tx_buf = &last_word;
  87. t[2].len = sizeof(last_word);
  88. spi_message_add_tail(&t[2], &m);
  89. }
  90. spi_sync(priv->spi, &m);
  91. }
  92. static u32 p54spi_read32(struct p54s_priv *priv, u8 addr)
  93. {
  94. __le32 val;
  95. p54spi_spi_read(priv, addr, &val, sizeof(val));
  96. return le32_to_cpu(val);
  97. }
  98. static inline void p54spi_write16(struct p54s_priv *priv, u8 addr, __le16 val)
  99. {
  100. p54spi_spi_write(priv, addr, &val, sizeof(val));
  101. }
  102. static inline void p54spi_write32(struct p54s_priv *priv, u8 addr, __le32 val)
  103. {
  104. p54spi_spi_write(priv, addr, &val, sizeof(val));
  105. }
  106. static int p54spi_wait_bit(struct p54s_priv *priv, u16 reg, u32 bits)
  107. {
  108. int i;
  109. for (i = 0; i < 2000; i++) {
  110. u32 buffer = p54spi_read32(priv, reg);
  111. if ((buffer & bits) == bits)
  112. return 1;
  113. }
  114. return 0;
  115. }
  116. static int p54spi_spi_write_dma(struct p54s_priv *priv, __le32 base,
  117. const void *buf, size_t len)
  118. {
  119. if (!p54spi_wait_bit(priv, SPI_ADRS_DMA_WRITE_CTRL, HOST_ALLOWED)) {
  120. dev_err(&priv->spi->dev, "spi_write_dma not allowed "
  121. "to DMA write.\n");
  122. return -EAGAIN;
  123. }
  124. p54spi_write16(priv, SPI_ADRS_DMA_WRITE_CTRL,
  125. cpu_to_le16(SPI_DMA_WRITE_CTRL_ENABLE));
  126. p54spi_write16(priv, SPI_ADRS_DMA_WRITE_LEN, cpu_to_le16(len));
  127. p54spi_write32(priv, SPI_ADRS_DMA_WRITE_BASE, base);
  128. p54spi_spi_write(priv, SPI_ADRS_DMA_DATA, buf, len);
  129. return 0;
  130. }
  131. static int p54spi_request_firmware(struct ieee80211_hw *dev)
  132. {
  133. struct p54s_priv *priv = dev->priv;
  134. int ret;
  135. /* FIXME: should driver use it's own struct device? */
  136. ret = request_firmware(&priv->firmware, "3826.arm", &priv->spi->dev);
  137. if (ret < 0) {
  138. dev_err(&priv->spi->dev, "request_firmware() failed: %d", ret);
  139. return ret;
  140. }
  141. ret = p54_parse_firmware(dev, priv->firmware);
  142. if (ret) {
  143. release_firmware(priv->firmware);
  144. return ret;
  145. }
  146. return 0;
  147. }
  148. static int p54spi_request_eeprom(struct ieee80211_hw *dev)
  149. {
  150. struct p54s_priv *priv = dev->priv;
  151. const struct firmware *eeprom;
  152. int ret;
  153. /* allow users to customize their eeprom.
  154. */
  155. ret = request_firmware_direct(&eeprom, "3826.eeprom", &priv->spi->dev);
  156. if (ret < 0) {
  157. #ifdef CONFIG_P54_SPI_DEFAULT_EEPROM
  158. dev_info(&priv->spi->dev, "loading default eeprom...\n");
  159. ret = p54_parse_eeprom(dev, (void *) p54spi_eeprom,
  160. sizeof(p54spi_eeprom));
  161. #else
  162. dev_err(&priv->spi->dev, "Failed to request user eeprom\n");
  163. #endif /* CONFIG_P54_SPI_DEFAULT_EEPROM */
  164. } else {
  165. dev_info(&priv->spi->dev, "loading user eeprom...\n");
  166. ret = p54_parse_eeprom(dev, (void *) eeprom->data,
  167. (int)eeprom->size);
  168. release_firmware(eeprom);
  169. }
  170. return ret;
  171. }
  172. static int p54spi_upload_firmware(struct ieee80211_hw *dev)
  173. {
  174. struct p54s_priv *priv = dev->priv;
  175. unsigned long fw_len, _fw_len;
  176. unsigned int offset = 0;
  177. int err = 0;
  178. u8 *fw;
  179. fw_len = priv->firmware->size;
  180. fw = kmemdup(priv->firmware->data, fw_len, GFP_KERNEL);
  181. if (!fw)
  182. return -ENOMEM;
  183. /* stop the device */
  184. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  185. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
  186. SPI_CTRL_STAT_START_HALTED));
  187. msleep(TARGET_BOOT_SLEEP);
  188. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  189. SPI_CTRL_STAT_HOST_OVERRIDE |
  190. SPI_CTRL_STAT_START_HALTED));
  191. msleep(TARGET_BOOT_SLEEP);
  192. while (fw_len > 0) {
  193. _fw_len = min_t(long, fw_len, SPI_MAX_PACKET_SIZE);
  194. err = p54spi_spi_write_dma(priv, cpu_to_le32(
  195. ISL38XX_DEV_FIRMWARE_ADDR + offset),
  196. (fw + offset), _fw_len);
  197. if (err < 0)
  198. goto out;
  199. fw_len -= _fw_len;
  200. offset += _fw_len;
  201. }
  202. BUG_ON(fw_len != 0);
  203. /* enable host interrupts */
  204. p54spi_write32(priv, SPI_ADRS_HOST_INT_EN,
  205. cpu_to_le32(SPI_HOST_INTS_DEFAULT));
  206. /* boot the device */
  207. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  208. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_HOST_RESET |
  209. SPI_CTRL_STAT_RAM_BOOT));
  210. msleep(TARGET_BOOT_SLEEP);
  211. p54spi_write16(priv, SPI_ADRS_DEV_CTRL_STAT, cpu_to_le16(
  212. SPI_CTRL_STAT_HOST_OVERRIDE | SPI_CTRL_STAT_RAM_BOOT));
  213. msleep(TARGET_BOOT_SLEEP);
  214. out:
  215. kfree(fw);
  216. return err;
  217. }
  218. static void p54spi_power_off(struct p54s_priv *priv)
  219. {
  220. disable_irq(gpio_to_irq(p54spi_gpio_irq));
  221. gpio_set_value(p54spi_gpio_power, 0);
  222. }
  223. static void p54spi_power_on(struct p54s_priv *priv)
  224. {
  225. gpio_set_value(p54spi_gpio_power, 1);
  226. enable_irq(gpio_to_irq(p54spi_gpio_irq));
  227. /* need to wait a while before device can be accessed, the length
  228. * is just a guess
  229. */
  230. msleep(10);
  231. }
  232. static inline void p54spi_int_ack(struct p54s_priv *priv, u32 val)
  233. {
  234. p54spi_write32(priv, SPI_ADRS_HOST_INT_ACK, cpu_to_le32(val));
  235. }
  236. static int p54spi_wakeup(struct p54s_priv *priv)
  237. {
  238. /* wake the chip */
  239. p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
  240. cpu_to_le32(SPI_TARGET_INT_WAKEUP));
  241. /* And wait for the READY interrupt */
  242. if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
  243. SPI_HOST_INT_READY)) {
  244. dev_err(&priv->spi->dev, "INT_READY timeout\n");
  245. return -EBUSY;
  246. }
  247. p54spi_int_ack(priv, SPI_HOST_INT_READY);
  248. return 0;
  249. }
  250. static inline void p54spi_sleep(struct p54s_priv *priv)
  251. {
  252. p54spi_write32(priv, SPI_ADRS_ARM_INTERRUPTS,
  253. cpu_to_le32(SPI_TARGET_INT_SLEEP));
  254. }
  255. static void p54spi_int_ready(struct p54s_priv *priv)
  256. {
  257. p54spi_write32(priv, SPI_ADRS_HOST_INT_EN, cpu_to_le32(
  258. SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE));
  259. switch (priv->fw_state) {
  260. case FW_STATE_BOOTING:
  261. priv->fw_state = FW_STATE_READY;
  262. complete(&priv->fw_comp);
  263. break;
  264. case FW_STATE_RESETTING:
  265. priv->fw_state = FW_STATE_READY;
  266. /* TODO: reinitialize state */
  267. break;
  268. default:
  269. break;
  270. }
  271. }
  272. static int p54spi_rx(struct p54s_priv *priv)
  273. {
  274. struct sk_buff *skb;
  275. u16 len;
  276. u16 rx_head[2];
  277. #define READAHEAD_SZ (sizeof(rx_head)-sizeof(u16))
  278. if (p54spi_wakeup(priv) < 0)
  279. return -EBUSY;
  280. /* Read data size and first data word in one SPI transaction
  281. * This is workaround for firmware/DMA bug,
  282. * when first data word gets lost under high load.
  283. */
  284. p54spi_spi_read(priv, SPI_ADRS_DMA_DATA, rx_head, sizeof(rx_head));
  285. len = rx_head[0];
  286. if (len == 0) {
  287. p54spi_sleep(priv);
  288. dev_err(&priv->spi->dev, "rx request of zero bytes\n");
  289. return 0;
  290. }
  291. /* Firmware may insert up to 4 padding bytes after the lmac header,
  292. * but it does not amend the size of SPI data transfer.
  293. * Such packets has correct data size in header, thus referencing
  294. * past the end of allocated skb. Reserve extra 4 bytes for this case
  295. */
  296. skb = dev_alloc_skb(len + 4);
  297. if (!skb) {
  298. p54spi_sleep(priv);
  299. dev_err(&priv->spi->dev, "could not alloc skb");
  300. return -ENOMEM;
  301. }
  302. if (len <= READAHEAD_SZ) {
  303. memcpy(skb_put(skb, len), rx_head + 1, len);
  304. } else {
  305. memcpy(skb_put(skb, READAHEAD_SZ), rx_head + 1, READAHEAD_SZ);
  306. p54spi_spi_read(priv, SPI_ADRS_DMA_DATA,
  307. skb_put(skb, len - READAHEAD_SZ),
  308. len - READAHEAD_SZ);
  309. }
  310. p54spi_sleep(priv);
  311. /* Put additional bytes to compensate for the possible
  312. * alignment-caused truncation
  313. */
  314. skb_put(skb, 4);
  315. if (p54_rx(priv->hw, skb) == 0)
  316. dev_kfree_skb(skb);
  317. return 0;
  318. }
  319. static irqreturn_t p54spi_interrupt(int irq, void *config)
  320. {
  321. struct spi_device *spi = config;
  322. struct p54s_priv *priv = spi_get_drvdata(spi);
  323. ieee80211_queue_work(priv->hw, &priv->work);
  324. return IRQ_HANDLED;
  325. }
  326. static int p54spi_tx_frame(struct p54s_priv *priv, struct sk_buff *skb)
  327. {
  328. struct p54_hdr *hdr = (struct p54_hdr *) skb->data;
  329. int ret = 0;
  330. if (p54spi_wakeup(priv) < 0)
  331. return -EBUSY;
  332. ret = p54spi_spi_write_dma(priv, hdr->req_id, skb->data, skb->len);
  333. if (ret < 0)
  334. goto out;
  335. if (!p54spi_wait_bit(priv, SPI_ADRS_HOST_INTERRUPTS,
  336. SPI_HOST_INT_WR_READY)) {
  337. dev_err(&priv->spi->dev, "WR_READY timeout\n");
  338. ret = -EAGAIN;
  339. goto out;
  340. }
  341. p54spi_int_ack(priv, SPI_HOST_INT_WR_READY);
  342. if (FREE_AFTER_TX(skb))
  343. p54_free_skb(priv->hw, skb);
  344. out:
  345. p54spi_sleep(priv);
  346. return ret;
  347. }
  348. static int p54spi_wq_tx(struct p54s_priv *priv)
  349. {
  350. struct p54s_tx_info *entry;
  351. struct sk_buff *skb;
  352. struct ieee80211_tx_info *info;
  353. struct p54_tx_info *minfo;
  354. struct p54s_tx_info *dinfo;
  355. unsigned long flags;
  356. int ret = 0;
  357. spin_lock_irqsave(&priv->tx_lock, flags);
  358. while (!list_empty(&priv->tx_pending)) {
  359. entry = list_entry(priv->tx_pending.next,
  360. struct p54s_tx_info, tx_list);
  361. list_del_init(&entry->tx_list);
  362. spin_unlock_irqrestore(&priv->tx_lock, flags);
  363. dinfo = container_of((void *) entry, struct p54s_tx_info,
  364. tx_list);
  365. minfo = container_of((void *) dinfo, struct p54_tx_info,
  366. data);
  367. info = container_of((void *) minfo, struct ieee80211_tx_info,
  368. rate_driver_data);
  369. skb = container_of((void *) info, struct sk_buff, cb);
  370. ret = p54spi_tx_frame(priv, skb);
  371. if (ret < 0) {
  372. p54_free_skb(priv->hw, skb);
  373. return ret;
  374. }
  375. spin_lock_irqsave(&priv->tx_lock, flags);
  376. }
  377. spin_unlock_irqrestore(&priv->tx_lock, flags);
  378. return ret;
  379. }
  380. static void p54spi_op_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
  381. {
  382. struct p54s_priv *priv = dev->priv;
  383. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  384. struct p54_tx_info *mi = (struct p54_tx_info *) info->rate_driver_data;
  385. struct p54s_tx_info *di = (struct p54s_tx_info *) mi->data;
  386. unsigned long flags;
  387. BUILD_BUG_ON(sizeof(*di) > sizeof((mi->data)));
  388. spin_lock_irqsave(&priv->tx_lock, flags);
  389. list_add_tail(&di->tx_list, &priv->tx_pending);
  390. spin_unlock_irqrestore(&priv->tx_lock, flags);
  391. ieee80211_queue_work(priv->hw, &priv->work);
  392. }
  393. static void p54spi_work(struct work_struct *work)
  394. {
  395. struct p54s_priv *priv = container_of(work, struct p54s_priv, work);
  396. u32 ints;
  397. int ret;
  398. mutex_lock(&priv->mutex);
  399. if (priv->fw_state == FW_STATE_OFF)
  400. goto out;
  401. ints = p54spi_read32(priv, SPI_ADRS_HOST_INTERRUPTS);
  402. if (ints & SPI_HOST_INT_READY) {
  403. p54spi_int_ready(priv);
  404. p54spi_int_ack(priv, SPI_HOST_INT_READY);
  405. }
  406. if (priv->fw_state != FW_STATE_READY)
  407. goto out;
  408. if (ints & SPI_HOST_INT_UPDATE) {
  409. p54spi_int_ack(priv, SPI_HOST_INT_UPDATE);
  410. ret = p54spi_rx(priv);
  411. if (ret < 0)
  412. goto out;
  413. }
  414. if (ints & SPI_HOST_INT_SW_UPDATE) {
  415. p54spi_int_ack(priv, SPI_HOST_INT_SW_UPDATE);
  416. ret = p54spi_rx(priv);
  417. if (ret < 0)
  418. goto out;
  419. }
  420. ret = p54spi_wq_tx(priv);
  421. out:
  422. mutex_unlock(&priv->mutex);
  423. }
  424. static int p54spi_op_start(struct ieee80211_hw *dev)
  425. {
  426. struct p54s_priv *priv = dev->priv;
  427. unsigned long timeout;
  428. int ret = 0;
  429. if (mutex_lock_interruptible(&priv->mutex)) {
  430. ret = -EINTR;
  431. goto out;
  432. }
  433. priv->fw_state = FW_STATE_BOOTING;
  434. p54spi_power_on(priv);
  435. ret = p54spi_upload_firmware(dev);
  436. if (ret < 0) {
  437. p54spi_power_off(priv);
  438. goto out_unlock;
  439. }
  440. mutex_unlock(&priv->mutex);
  441. timeout = msecs_to_jiffies(2000);
  442. timeout = wait_for_completion_interruptible_timeout(&priv->fw_comp,
  443. timeout);
  444. if (!timeout) {
  445. dev_err(&priv->spi->dev, "firmware boot failed");
  446. p54spi_power_off(priv);
  447. ret = -1;
  448. goto out;
  449. }
  450. if (mutex_lock_interruptible(&priv->mutex)) {
  451. ret = -EINTR;
  452. p54spi_power_off(priv);
  453. goto out;
  454. }
  455. WARN_ON(priv->fw_state != FW_STATE_READY);
  456. out_unlock:
  457. mutex_unlock(&priv->mutex);
  458. out:
  459. return ret;
  460. }
  461. static void p54spi_op_stop(struct ieee80211_hw *dev)
  462. {
  463. struct p54s_priv *priv = dev->priv;
  464. unsigned long flags;
  465. mutex_lock(&priv->mutex);
  466. WARN_ON(priv->fw_state != FW_STATE_READY);
  467. p54spi_power_off(priv);
  468. spin_lock_irqsave(&priv->tx_lock, flags);
  469. INIT_LIST_HEAD(&priv->tx_pending);
  470. spin_unlock_irqrestore(&priv->tx_lock, flags);
  471. priv->fw_state = FW_STATE_OFF;
  472. mutex_unlock(&priv->mutex);
  473. cancel_work_sync(&priv->work);
  474. }
  475. static int p54spi_probe(struct spi_device *spi)
  476. {
  477. struct p54s_priv *priv = NULL;
  478. struct ieee80211_hw *hw;
  479. int ret = -EINVAL;
  480. hw = p54_init_common(sizeof(*priv));
  481. if (!hw) {
  482. dev_err(&spi->dev, "could not alloc ieee80211_hw");
  483. return -ENOMEM;
  484. }
  485. priv = hw->priv;
  486. priv->hw = hw;
  487. spi_set_drvdata(spi, priv);
  488. priv->spi = spi;
  489. spi->bits_per_word = 16;
  490. spi->max_speed_hz = 24000000;
  491. ret = spi_setup(spi);
  492. if (ret < 0) {
  493. dev_err(&priv->spi->dev, "spi_setup failed");
  494. goto err_free;
  495. }
  496. ret = gpio_request(p54spi_gpio_power, "p54spi power");
  497. if (ret < 0) {
  498. dev_err(&priv->spi->dev, "power GPIO request failed: %d", ret);
  499. goto err_free;
  500. }
  501. ret = gpio_request(p54spi_gpio_irq, "p54spi irq");
  502. if (ret < 0) {
  503. dev_err(&priv->spi->dev, "irq GPIO request failed: %d", ret);
  504. goto err_free_gpio_power;
  505. }
  506. gpio_direction_output(p54spi_gpio_power, 0);
  507. gpio_direction_input(p54spi_gpio_irq);
  508. ret = request_irq(gpio_to_irq(p54spi_gpio_irq),
  509. p54spi_interrupt, 0, "p54spi",
  510. priv->spi);
  511. if (ret < 0) {
  512. dev_err(&priv->spi->dev, "request_irq() failed");
  513. goto err_free_gpio_irq;
  514. }
  515. irq_set_irq_type(gpio_to_irq(p54spi_gpio_irq), IRQ_TYPE_EDGE_RISING);
  516. disable_irq(gpio_to_irq(p54spi_gpio_irq));
  517. INIT_WORK(&priv->work, p54spi_work);
  518. init_completion(&priv->fw_comp);
  519. INIT_LIST_HEAD(&priv->tx_pending);
  520. mutex_init(&priv->mutex);
  521. spin_lock_init(&priv->tx_lock);
  522. SET_IEEE80211_DEV(hw, &spi->dev);
  523. priv->common.open = p54spi_op_start;
  524. priv->common.stop = p54spi_op_stop;
  525. priv->common.tx = p54spi_op_tx;
  526. ret = p54spi_request_firmware(hw);
  527. if (ret < 0)
  528. goto err_free_common;
  529. ret = p54spi_request_eeprom(hw);
  530. if (ret)
  531. goto err_free_common;
  532. ret = p54_register_common(hw, &priv->spi->dev);
  533. if (ret)
  534. goto err_free_common;
  535. return 0;
  536. err_free_common:
  537. free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
  538. err_free_gpio_irq:
  539. gpio_free(p54spi_gpio_irq);
  540. err_free_gpio_power:
  541. gpio_free(p54spi_gpio_power);
  542. err_free:
  543. p54_free_common(priv->hw);
  544. return ret;
  545. }
  546. static int p54spi_remove(struct spi_device *spi)
  547. {
  548. struct p54s_priv *priv = spi_get_drvdata(spi);
  549. p54_unregister_common(priv->hw);
  550. free_irq(gpio_to_irq(p54spi_gpio_irq), spi);
  551. gpio_free(p54spi_gpio_power);
  552. gpio_free(p54spi_gpio_irq);
  553. release_firmware(priv->firmware);
  554. mutex_destroy(&priv->mutex);
  555. p54_free_common(priv->hw);
  556. return 0;
  557. }
  558. static struct spi_driver p54spi_driver = {
  559. .driver = {
  560. .name = "p54spi",
  561. },
  562. .probe = p54spi_probe,
  563. .remove = p54spi_remove,
  564. };
  565. module_spi_driver(p54spi_driver);
  566. MODULE_LICENSE("GPL");
  567. MODULE_AUTHOR("Christian Lamparter <chunkeey@web.de>");
  568. MODULE_ALIAS("spi:cx3110x");
  569. MODULE_ALIAS("spi:p54spi");
  570. MODULE_ALIAS("spi:stlc45xx");