phy.h 4.7 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153
  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2014 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #ifndef __RTL92E_PHY_H__
  26. #define __RTL92E_PHY_H__
  27. /* MAX_TX_COUNT must always set to 4, otherwise read efuse table sequence
  28. * will be wrong.
  29. */
  30. #define MAX_TX_COUNT 4
  31. #define TX_1S 0
  32. #define TX_2S 1
  33. #define TX_3S 2
  34. #define TX_4S 3
  35. #define MAX_POWER_INDEX 0x3f
  36. #define MAX_PRECMD_CNT 16
  37. #define MAX_RFDEPENDCMD_CNT 16
  38. #define MAX_POSTCMD_CNT 16
  39. #define MAX_DOZE_WAITING_TIMES_9x 64
  40. #define RT_CANNOT_IO(hw) false
  41. #define HIGHPOWER_RADIOA_ARRAYLEN 22
  42. #define IQK_ADDA_REG_NUM 16
  43. #define IQK_MAC_REG_NUM 4
  44. #define IQK_BB_REG_NUM 9
  45. #define MAX_TOLERANCE 5
  46. #define IQK_DELAY_TIME 10
  47. #define index_mapping_NUM 15
  48. #define APK_BB_REG_NUM 5
  49. #define APK_AFE_REG_NUM 16
  50. #define APK_CURVE_REG_NUM 4
  51. #define PATH_NUM 2
  52. #define LOOP_LIMIT 5
  53. #define MAX_STALL_TIME 50
  54. #define ANTENNADIVERSITYVALUE 0x80
  55. #define MAX_TXPWR_IDX_NMODE_92S 63
  56. #define RESET_CNT_LIMIT 3
  57. #define RF6052_MAX_PATH 2
  58. #define CT_OFFSET_MAC_ADDR 0X16
  59. #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
  60. #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
  61. #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
  62. #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
  63. #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
  64. #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
  65. #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
  66. #define CT_OFFSET_CHANNEL_PLAH 0x75
  67. #define CT_OFFSET_THERMAL_METER 0x78
  68. #define CT_OFFSET_RF_OPTION 0x79
  69. #define CT_OFFSET_VERSION 0x7E
  70. #define CT_OFFSET_CUSTOMER_ID 0x7F
  71. #define RTL92C_MAX_PATH_NUM 2
  72. enum swchnlcmd_id {
  73. CMDID_END,
  74. CMDID_SET_TXPOWEROWER_LEVEL,
  75. CMDID_BBREGWRITE10,
  76. CMDID_WRITEPORT_ULONG,
  77. CMDID_WRITEPORT_USHORT,
  78. CMDID_WRITEPORT_UCHAR,
  79. CMDID_RF_WRITEREG,
  80. };
  81. struct swchnlcmd {
  82. enum swchnlcmd_id cmdid;
  83. u32 para1;
  84. u32 para2;
  85. u32 msdelay;
  86. };
  87. enum baseband_config_type {
  88. BASEBAND_CONFIG_PHY_REG = 0,
  89. BASEBAND_CONFIG_AGC_TAB = 1,
  90. };
  91. enum ant_div_type {
  92. NO_ANTDIV = 0xFF,
  93. CG_TRX_HW_ANTDIV = 0x01,
  94. CGCS_RX_HW_ANTDIV = 0x02,
  95. FIXED_HW_ANTDIV = 0x03,
  96. CG_TRX_SMART_ANTDIV = 0x04,
  97. CGCS_RX_SW_ANTDIV = 0x05,
  98. };
  99. u32 rtl92ee_phy_query_bb_reg(struct ieee80211_hw *hw,
  100. u32 regaddr, u32 bitmask);
  101. void rtl92ee_phy_set_bb_reg(struct ieee80211_hw *hw,
  102. u32 regaddr, u32 bitmask, u32 data);
  103. u32 rtl92ee_phy_query_rf_reg(struct ieee80211_hw *hw,
  104. enum radio_path rfpath, u32 regaddr,
  105. u32 bitmask);
  106. void rtl92ee_phy_set_rf_reg(struct ieee80211_hw *hw,
  107. enum radio_path rfpath, u32 regaddr,
  108. u32 bitmask, u32 data);
  109. bool rtl92ee_phy_mac_config(struct ieee80211_hw *hw);
  110. bool rtl92ee_phy_bb_config(struct ieee80211_hw *hw);
  111. bool rtl92ee_phy_rf_config(struct ieee80211_hw *hw);
  112. void rtl92ee_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
  113. void rtl92ee_phy_get_txpower_level(struct ieee80211_hw *hw,
  114. long *powerlevel);
  115. void rtl92ee_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
  116. void rtl92ee_phy_scan_operation_backup(struct ieee80211_hw *hw,
  117. u8 operation);
  118. void rtl92ee_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
  119. void rtl92ee_phy_set_bw_mode(struct ieee80211_hw *hw,
  120. enum nl80211_channel_type ch_type);
  121. void rtl92ee_phy_sw_chnl_callback(struct ieee80211_hw *hw);
  122. u8 rtl92ee_phy_sw_chnl(struct ieee80211_hw *hw);
  123. void rtl92ee_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
  124. void rtl92ee_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
  125. void rtl92ee_phy_lc_calibrate(struct ieee80211_hw *hw);
  126. void rtl92ee_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
  127. bool rtl92ee_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
  128. enum radio_path rfpath);
  129. bool rtl92ee_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
  130. bool rtl92ee_phy_set_rf_power_state(struct ieee80211_hw *hw,
  131. enum rf_pwrstate rfpwr_state);
  132. #endif