trx.c 30 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2014 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * The full GNU General Public License is included in this distribution in the
  15. * file called LICENSE.
  16. *
  17. * Contact Information:
  18. * wlanfae <wlanfae@realtek.com>
  19. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20. * Hsinchu 300, Taiwan.
  21. *
  22. * Larry Finger <Larry.Finger@lwfinger.net>
  23. *
  24. *****************************************************************************/
  25. #include "../wifi.h"
  26. #include "../pci.h"
  27. #include "../base.h"
  28. #include "../stats.h"
  29. #include "reg.h"
  30. #include "def.h"
  31. #include "phy.h"
  32. #include "trx.h"
  33. #include "led.h"
  34. #include "dm.h"
  35. #include "fw.h"
  36. static u8 _rtl92ee_map_hwqueue_to_fwqueue(struct sk_buff *skb, u8 hw_queue)
  37. {
  38. __le16 fc = rtl_get_fc(skb);
  39. if (unlikely(ieee80211_is_beacon(fc)))
  40. return QSLT_BEACON;
  41. if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
  42. return QSLT_MGNT;
  43. return skb->priority;
  44. }
  45. static void _rtl92ee_query_rxphystatus(struct ieee80211_hw *hw,
  46. struct rtl_stats *pstatus, u8 *pdesc,
  47. struct rx_fwinfo *p_drvinfo,
  48. bool bpacket_match_bssid,
  49. bool bpacket_toself,
  50. bool packet_beacon)
  51. {
  52. struct rtl_priv *rtlpriv = rtl_priv(hw);
  53. struct phy_status_rpt *p_phystrpt = (struct phy_status_rpt *)p_drvinfo;
  54. char rx_pwr_all = 0, rx_pwr[4];
  55. u8 rf_rx_num = 0, evm, pwdb_all;
  56. u8 i, max_spatial_stream;
  57. u32 rssi, total_rssi = 0;
  58. bool is_cck = pstatus->is_cck;
  59. u8 lan_idx, vga_idx;
  60. /* Record it for next packet processing */
  61. pstatus->packet_matchbssid = bpacket_match_bssid;
  62. pstatus->packet_toself = bpacket_toself;
  63. pstatus->packet_beacon = packet_beacon;
  64. pstatus->rx_mimo_signalquality[0] = -1;
  65. pstatus->rx_mimo_signalquality[1] = -1;
  66. if (is_cck) {
  67. u8 cck_highpwr;
  68. u8 cck_agc_rpt;
  69. /* CCK Driver info Structure is not the same as OFDM packet. */
  70. cck_agc_rpt = p_phystrpt->cck_agc_rpt_ofdm_cfosho_a;
  71. /* (1)Hardware does not provide RSSI for CCK
  72. * (2)PWDB, Average PWDB cacluated by
  73. * hardware (for rate adaptive)
  74. */
  75. cck_highpwr = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2,
  76. BIT(9));
  77. lan_idx = ((cck_agc_rpt & 0xE0) >> 5);
  78. vga_idx = (cck_agc_rpt & 0x1f);
  79. switch (lan_idx) {
  80. case 7: /*VGA_idx = 27~2*/
  81. if (vga_idx <= 27)
  82. rx_pwr_all = -100 + 2 * (27 - vga_idx);
  83. else
  84. rx_pwr_all = -100;
  85. break;
  86. case 6: /*VGA_idx = 2~0*/
  87. rx_pwr_all = -48 + 2 * (2 - vga_idx);
  88. break;
  89. case 5: /*VGA_idx = 7~5*/
  90. rx_pwr_all = -42 + 2 * (7 - vga_idx);
  91. break;
  92. case 4: /*VGA_idx = 7~4*/
  93. rx_pwr_all = -36 + 2 * (7 - vga_idx);
  94. break;
  95. case 3: /*VGA_idx = 7~0*/
  96. rx_pwr_all = -24 + 2 * (7 - vga_idx);
  97. break;
  98. case 2: /*VGA_idx = 5~0*/
  99. if (cck_highpwr)
  100. rx_pwr_all = -12 + 2 * (5 - vga_idx);
  101. else
  102. rx_pwr_all = -6 + 2 * (5 - vga_idx);
  103. break;
  104. case 1:
  105. rx_pwr_all = 8 - 2 * vga_idx;
  106. break;
  107. case 0:
  108. rx_pwr_all = 14 - 2 * vga_idx;
  109. break;
  110. default:
  111. break;
  112. }
  113. rx_pwr_all += 16;
  114. pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
  115. if (!cck_highpwr) {
  116. if (pwdb_all >= 80)
  117. pwdb_all = ((pwdb_all - 80) << 1) +
  118. ((pwdb_all - 80) >> 1) + 80;
  119. else if ((pwdb_all <= 78) && (pwdb_all >= 20))
  120. pwdb_all += 3;
  121. if (pwdb_all > 100)
  122. pwdb_all = 100;
  123. }
  124. pstatus->rx_pwdb_all = pwdb_all;
  125. pstatus->bt_rx_rssi_percentage = pwdb_all;
  126. pstatus->recvsignalpower = rx_pwr_all;
  127. /* (3) Get Signal Quality (EVM) */
  128. if (bpacket_match_bssid) {
  129. u8 sq, sq_rpt;
  130. if (pstatus->rx_pwdb_all > 40) {
  131. sq = 100;
  132. } else {
  133. sq_rpt = p_phystrpt->cck_sig_qual_ofdm_pwdb_all;
  134. if (sq_rpt > 64)
  135. sq = 0;
  136. else if (sq_rpt < 20)
  137. sq = 100;
  138. else
  139. sq = ((64 - sq_rpt) * 100) / 44;
  140. }
  141. pstatus->signalquality = sq;
  142. pstatus->rx_mimo_signalquality[0] = sq;
  143. pstatus->rx_mimo_signalquality[1] = -1;
  144. }
  145. } else {
  146. /* (1)Get RSSI for HT rate */
  147. for (i = RF90_PATH_A; i < RF6052_MAX_PATH; i++) {
  148. /* we will judge RF RX path now. */
  149. if (rtlpriv->dm.rfpath_rxenable[i])
  150. rf_rx_num++;
  151. rx_pwr[i] = ((p_phystrpt->path_agc[i].gain & 0x3f) * 2)
  152. - 110;
  153. pstatus->rx_pwr[i] = rx_pwr[i];
  154. /* Translate DBM to percentage. */
  155. rssi = rtl_query_rxpwrpercentage(rx_pwr[i]);
  156. total_rssi += rssi;
  157. pstatus->rx_mimo_signalstrength[i] = (u8)rssi;
  158. }
  159. /* (2)PWDB, Average PWDB cacluated by
  160. * hardware (for rate adaptive)
  161. */
  162. rx_pwr_all = ((p_phystrpt->cck_sig_qual_ofdm_pwdb_all >> 1)
  163. & 0x7f) - 110;
  164. pwdb_all = rtl_query_rxpwrpercentage(rx_pwr_all);
  165. pstatus->rx_pwdb_all = pwdb_all;
  166. pstatus->bt_rx_rssi_percentage = pwdb_all;
  167. pstatus->rxpower = rx_pwr_all;
  168. pstatus->recvsignalpower = rx_pwr_all;
  169. /* (3)EVM of HT rate */
  170. if (pstatus->rate >= DESC_RATEMCS8 &&
  171. pstatus->rate <= DESC_RATEMCS15)
  172. max_spatial_stream = 2;
  173. else
  174. max_spatial_stream = 1;
  175. for (i = 0; i < max_spatial_stream; i++) {
  176. evm = rtl_evm_db_to_percentage(
  177. p_phystrpt->stream_rxevm[i]);
  178. if (bpacket_match_bssid) {
  179. /* Fill value in RFD, Get the first
  180. * spatial stream only
  181. */
  182. if (i == 0)
  183. pstatus->signalquality = (u8)(evm &
  184. 0xff);
  185. pstatus->rx_mimo_signalquality[i] = (u8)(evm &
  186. 0xff);
  187. }
  188. }
  189. if (bpacket_match_bssid) {
  190. for (i = RF90_PATH_A; i <= RF90_PATH_B; i++)
  191. rtl_priv(hw)->dm.cfo_tail[i] =
  192. (int)p_phystrpt->path_cfotail[i];
  193. if (rtl_priv(hw)->dm.packet_count == 0xffffffff)
  194. rtl_priv(hw)->dm.packet_count = 0;
  195. else
  196. rtl_priv(hw)->dm.packet_count++;
  197. }
  198. }
  199. /* UI BSS List signal strength(in percentage),
  200. * make it good looking, from 0~100.
  201. */
  202. if (is_cck)
  203. pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
  204. pwdb_all));
  205. else if (rf_rx_num != 0)
  206. pstatus->signalstrength = (u8)(rtl_signal_scale_mapping(hw,
  207. total_rssi /= rf_rx_num));
  208. }
  209. static void _rtl92ee_translate_rx_signal_stuff(struct ieee80211_hw *hw,
  210. struct sk_buff *skb,
  211. struct rtl_stats *pstatus,
  212. u8 *pdesc,
  213. struct rx_fwinfo *p_drvinfo)
  214. {
  215. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  216. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  217. struct ieee80211_hdr *hdr;
  218. u8 *tmp_buf;
  219. u8 *praddr;
  220. u8 *psaddr;
  221. __le16 fc;
  222. bool packet_matchbssid, packet_toself, packet_beacon;
  223. tmp_buf = skb->data + pstatus->rx_drvinfo_size +
  224. pstatus->rx_bufshift + 24;
  225. hdr = (struct ieee80211_hdr *)tmp_buf;
  226. fc = hdr->frame_control;
  227. praddr = hdr->addr1;
  228. psaddr = ieee80211_get_SA(hdr);
  229. ether_addr_copy(pstatus->psaddr, psaddr);
  230. packet_matchbssid = (!ieee80211_is_ctl(fc) &&
  231. (ether_addr_equal(mac->bssid,
  232. ieee80211_has_tods(fc) ?
  233. hdr->addr1 :
  234. ieee80211_has_fromds(fc) ?
  235. hdr->addr2 : hdr->addr3)) &&
  236. (!pstatus->hwerror) && (!pstatus->crc) &&
  237. (!pstatus->icv));
  238. packet_toself = packet_matchbssid &&
  239. (ether_addr_equal(praddr, rtlefuse->dev_addr));
  240. if (ieee80211_is_beacon(fc))
  241. packet_beacon = true;
  242. else
  243. packet_beacon = false;
  244. if (packet_beacon && packet_matchbssid)
  245. rtl_priv(hw)->dm.dbginfo.num_qry_beacon_pkt++;
  246. if (packet_matchbssid && ieee80211_is_data_qos(hdr->frame_control) &&
  247. !is_multicast_ether_addr(ieee80211_get_DA(hdr))) {
  248. struct ieee80211_qos_hdr *hdr_qos =
  249. (struct ieee80211_qos_hdr *)tmp_buf;
  250. u16 tid = le16_to_cpu(hdr_qos->qos_ctrl) & 0xf;
  251. if (tid != 0 && tid != 3)
  252. rtl_priv(hw)->dm.dbginfo.num_non_be_pkt++;
  253. }
  254. _rtl92ee_query_rxphystatus(hw, pstatus, pdesc, p_drvinfo,
  255. packet_matchbssid, packet_toself,
  256. packet_beacon);
  257. rtl_process_phyinfo(hw, tmp_buf, pstatus);
  258. }
  259. static void _rtl92ee_insert_emcontent(struct rtl_tcb_desc *ptcb_desc,
  260. u8 *virtualaddress)
  261. {
  262. u32 dwtmp = 0;
  263. memset(virtualaddress, 0, 8);
  264. SET_EARLYMODE_PKTNUM(virtualaddress, ptcb_desc->empkt_num);
  265. if (ptcb_desc->empkt_num == 1) {
  266. dwtmp = ptcb_desc->empkt_len[0];
  267. } else {
  268. dwtmp = ptcb_desc->empkt_len[0];
  269. dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
  270. dwtmp += ptcb_desc->empkt_len[1];
  271. }
  272. SET_EARLYMODE_LEN0(virtualaddress, dwtmp);
  273. if (ptcb_desc->empkt_num <= 3) {
  274. dwtmp = ptcb_desc->empkt_len[2];
  275. } else {
  276. dwtmp = ptcb_desc->empkt_len[2];
  277. dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
  278. dwtmp += ptcb_desc->empkt_len[3];
  279. }
  280. SET_EARLYMODE_LEN1(virtualaddress, dwtmp);
  281. if (ptcb_desc->empkt_num <= 5) {
  282. dwtmp = ptcb_desc->empkt_len[4];
  283. } else {
  284. dwtmp = ptcb_desc->empkt_len[4];
  285. dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
  286. dwtmp += ptcb_desc->empkt_len[5];
  287. }
  288. SET_EARLYMODE_LEN2_1(virtualaddress, dwtmp & 0xF);
  289. SET_EARLYMODE_LEN2_2(virtualaddress, dwtmp >> 4);
  290. if (ptcb_desc->empkt_num <= 7) {
  291. dwtmp = ptcb_desc->empkt_len[6];
  292. } else {
  293. dwtmp = ptcb_desc->empkt_len[6];
  294. dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
  295. dwtmp += ptcb_desc->empkt_len[7];
  296. }
  297. SET_EARLYMODE_LEN3(virtualaddress, dwtmp);
  298. if (ptcb_desc->empkt_num <= 9) {
  299. dwtmp = ptcb_desc->empkt_len[8];
  300. } else {
  301. dwtmp = ptcb_desc->empkt_len[8];
  302. dwtmp += ((dwtmp % 4) ? (4 - dwtmp % 4) : 0) + 4;
  303. dwtmp += ptcb_desc->empkt_len[9];
  304. }
  305. SET_EARLYMODE_LEN4(virtualaddress, dwtmp);
  306. }
  307. bool rtl92ee_rx_query_desc(struct ieee80211_hw *hw,
  308. struct rtl_stats *status,
  309. struct ieee80211_rx_status *rx_status,
  310. u8 *pdesc, struct sk_buff *skb)
  311. {
  312. struct rtl_priv *rtlpriv = rtl_priv(hw);
  313. struct rx_fwinfo *p_drvinfo;
  314. struct ieee80211_hdr *hdr;
  315. u32 phystatus = GET_RX_DESC_PHYST(pdesc);
  316. if (GET_RX_STATUS_DESC_RPT_SEL(pdesc) == 0)
  317. status->packet_report_type = NORMAL_RX;
  318. else
  319. status->packet_report_type = C2H_PACKET;
  320. status->length = (u16)GET_RX_DESC_PKT_LEN(pdesc);
  321. status->rx_drvinfo_size = (u8)GET_RX_DESC_DRV_INFO_SIZE(pdesc) *
  322. RX_DRV_INFO_SIZE_UNIT;
  323. status->rx_bufshift = (u8)(GET_RX_DESC_SHIFT(pdesc) & 0x03);
  324. status->icv = (u16)GET_RX_DESC_ICV(pdesc);
  325. status->crc = (u16)GET_RX_DESC_CRC32(pdesc);
  326. status->hwerror = (status->crc | status->icv);
  327. status->decrypted = !GET_RX_DESC_SWDEC(pdesc);
  328. status->rate = (u8)GET_RX_DESC_RXMCS(pdesc);
  329. status->isampdu = (bool)(GET_RX_DESC_PAGGR(pdesc) == 1);
  330. status->timestamp_low = GET_RX_DESC_TSFL(pdesc);
  331. status->is_cck = RTL92EE_RX_HAL_IS_CCK_RATE(status->rate);
  332. status->macid = GET_RX_DESC_MACID(pdesc);
  333. if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
  334. status->wake_match = BIT(2);
  335. else if (GET_RX_STATUS_DESC_MAGIC_MATCH(pdesc))
  336. status->wake_match = BIT(1);
  337. else if (GET_RX_STATUS_DESC_UNICAST_MATCH(pdesc))
  338. status->wake_match = BIT(0);
  339. else
  340. status->wake_match = 0;
  341. if (status->wake_match)
  342. RT_TRACE(rtlpriv, COMP_RXDESC, DBG_LOUD,
  343. "GGGGGGGGGGGGGet Wakeup Packet!! WakeMatch=%d\n",
  344. status->wake_match);
  345. rx_status->freq = hw->conf.chandef.chan->center_freq;
  346. rx_status->band = hw->conf.chandef.chan->band;
  347. hdr = (struct ieee80211_hdr *)(skb->data + status->rx_drvinfo_size +
  348. status->rx_bufshift + 24);
  349. if (status->crc)
  350. rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
  351. if (status->rx_is40Mhzpacket)
  352. rx_status->flag |= RX_FLAG_40MHZ;
  353. if (status->is_ht)
  354. rx_status->flag |= RX_FLAG_HT;
  355. rx_status->flag |= RX_FLAG_MACTIME_START;
  356. /* hw will set status->decrypted true, if it finds the
  357. * frame is open data frame or mgmt frame.
  358. * So hw will not decryption robust managment frame
  359. * for IEEE80211w but still set status->decrypted
  360. * true, so here we should set it back to undecrypted
  361. * for IEEE80211w frame, and mac80211 sw will help
  362. * to decrypt it
  363. */
  364. if (status->decrypted) {
  365. if ((!_ieee80211_is_robust_mgmt_frame(hdr)) &&
  366. (ieee80211_has_protected(hdr->frame_control)))
  367. rx_status->flag |= RX_FLAG_DECRYPTED;
  368. else
  369. rx_status->flag &= ~RX_FLAG_DECRYPTED;
  370. }
  371. /* rate_idx: index of data rate into band's
  372. * supported rates or MCS index if HT rates
  373. * are use (RX_FLAG_HT)
  374. * Notice: this is diff with windows define
  375. */
  376. rx_status->rate_idx = rtlwifi_rate_mapping(hw, status->is_ht,
  377. false, status->rate);
  378. rx_status->mactime = status->timestamp_low;
  379. if (phystatus) {
  380. p_drvinfo = (struct rx_fwinfo *)(skb->data +
  381. status->rx_bufshift + 24);
  382. _rtl92ee_translate_rx_signal_stuff(hw, skb, status, pdesc,
  383. p_drvinfo);
  384. }
  385. rx_status->signal = status->recvsignalpower + 10;
  386. if (status->packet_report_type == TX_REPORT2) {
  387. status->macid_valid_entry[0] =
  388. GET_RX_RPT2_DESC_MACID_VALID_1(pdesc);
  389. status->macid_valid_entry[1] =
  390. GET_RX_RPT2_DESC_MACID_VALID_2(pdesc);
  391. }
  392. return true;
  393. }
  394. /*in Windows, this == Rx_92EE_Interrupt*/
  395. void rtl92ee_rx_check_dma_ok(struct ieee80211_hw *hw, u8 *header_desc,
  396. u8 queue_index)
  397. {
  398. u8 first_seg = 0;
  399. u8 last_seg = 0;
  400. u16 total_len = 0;
  401. u16 read_cnt = 0;
  402. if (header_desc == NULL)
  403. return;
  404. total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
  405. first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
  406. last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
  407. while (total_len == 0 && first_seg == 0 && last_seg == 0) {
  408. read_cnt++;
  409. total_len = (u16)GET_RX_BUFFER_DESC_TOTAL_LENGTH(header_desc);
  410. first_seg = (u8)GET_RX_BUFFER_DESC_FS(header_desc);
  411. last_seg = (u8)GET_RX_BUFFER_DESC_LS(header_desc);
  412. if (read_cnt > 20)
  413. break;
  414. }
  415. }
  416. u16 rtl92ee_rx_desc_buff_remained_cnt(struct ieee80211_hw *hw, u8 queue_index)
  417. {
  418. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  419. struct rtl_priv *rtlpriv = rtl_priv(hw);
  420. u16 read_point = 0, write_point = 0, remind_cnt = 0;
  421. u32 tmp_4byte = 0;
  422. static u16 last_read_point;
  423. static bool start_rx;
  424. tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
  425. read_point = (u16)((tmp_4byte>>16) & 0x7ff);
  426. write_point = (u16)(tmp_4byte & 0x7ff);
  427. if (write_point != rtlpci->rx_ring[queue_index].next_rx_rp) {
  428. RT_TRACE(rtlpriv, COMP_RXDESC, DBG_DMESG,
  429. "!!!write point is 0x%x, reg 0x3B4 value is 0x%x\n",
  430. write_point, tmp_4byte);
  431. tmp_4byte = rtl_read_dword(rtlpriv, REG_RXQ_TXBD_IDX);
  432. read_point = (u16)((tmp_4byte>>16) & 0x7ff);
  433. write_point = (u16)(tmp_4byte & 0x7ff);
  434. }
  435. if (read_point > 0)
  436. start_rx = true;
  437. if (!start_rx)
  438. return 0;
  439. remind_cnt = calc_fifo_space(read_point, write_point);
  440. if (remind_cnt == 0)
  441. return 0;
  442. rtlpci->rx_ring[queue_index].next_rx_rp = write_point;
  443. last_read_point = read_point;
  444. return remind_cnt;
  445. }
  446. static u16 get_desc_addr_fr_q_idx(u16 queue_index)
  447. {
  448. u16 desc_address = REG_BEQ_TXBD_IDX;
  449. switch (queue_index) {
  450. case BK_QUEUE:
  451. desc_address = REG_BKQ_TXBD_IDX;
  452. break;
  453. case BE_QUEUE:
  454. desc_address = REG_BEQ_TXBD_IDX;
  455. break;
  456. case VI_QUEUE:
  457. desc_address = REG_VIQ_TXBD_IDX;
  458. break;
  459. case VO_QUEUE:
  460. desc_address = REG_VOQ_TXBD_IDX;
  461. break;
  462. case BEACON_QUEUE:
  463. desc_address = REG_BEQ_TXBD_IDX;
  464. break;
  465. case TXCMD_QUEUE:
  466. desc_address = REG_BEQ_TXBD_IDX;
  467. break;
  468. case MGNT_QUEUE:
  469. desc_address = REG_MGQ_TXBD_IDX;
  470. break;
  471. case HIGH_QUEUE:
  472. desc_address = REG_HI0Q_TXBD_IDX;
  473. break;
  474. case HCCA_QUEUE:
  475. desc_address = REG_BEQ_TXBD_IDX;
  476. break;
  477. default:
  478. break;
  479. }
  480. return desc_address;
  481. }
  482. u16 rtl92ee_get_available_desc(struct ieee80211_hw *hw, u8 q_idx)
  483. {
  484. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  485. struct rtl_priv *rtlpriv = rtl_priv(hw);
  486. u16 point_diff = 0;
  487. u16 current_tx_read_point = 0, current_tx_write_point = 0;
  488. u32 tmp_4byte;
  489. tmp_4byte = rtl_read_dword(rtlpriv,
  490. get_desc_addr_fr_q_idx(q_idx));
  491. current_tx_read_point = (u16)((tmp_4byte >> 16) & 0x0fff);
  492. current_tx_write_point = (u16)((tmp_4byte) & 0x0fff);
  493. point_diff = calc_fifo_space(current_tx_read_point,
  494. current_tx_write_point);
  495. rtlpci->tx_ring[q_idx].avl_desc = point_diff;
  496. return point_diff;
  497. }
  498. void rtl92ee_pre_fill_tx_bd_desc(struct ieee80211_hw *hw,
  499. u8 *tx_bd_desc, u8 *desc, u8 queue_index,
  500. struct sk_buff *skb, dma_addr_t addr)
  501. {
  502. struct rtl_priv *rtlpriv = rtl_priv(hw);
  503. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  504. u32 pkt_len = skb->len;
  505. u16 desc_size = 40; /*tx desc size*/
  506. u32 psblen = 0;
  507. u16 tx_page_size = 0;
  508. u32 total_packet_size = 0;
  509. u16 current_bd_desc;
  510. u8 i = 0;
  511. u16 real_desc_size = 0x28;
  512. u16 append_early_mode_size = 0;
  513. #if (RTL8192EE_SEG_NUM == 0)
  514. u8 segmentnum = 2;
  515. #elif (RTL8192EE_SEG_NUM == 1)
  516. u8 segmentnum = 4;
  517. #elif (RTL8192EE_SEG_NUM == 2)
  518. u8 segmentnum = 8;
  519. #endif
  520. tx_page_size = 2;
  521. current_bd_desc = rtlpci->tx_ring[queue_index].cur_tx_wp;
  522. total_packet_size = desc_size+pkt_len;
  523. if (rtlpriv->rtlhal.earlymode_enable) {
  524. if (queue_index < BEACON_QUEUE) {
  525. append_early_mode_size = 8;
  526. total_packet_size += append_early_mode_size;
  527. }
  528. }
  529. if (tx_page_size > 0) {
  530. psblen = (pkt_len + real_desc_size + append_early_mode_size) /
  531. (tx_page_size * 128);
  532. if (psblen * (tx_page_size * 128) < total_packet_size)
  533. psblen += 1;
  534. }
  535. /* Reset */
  536. SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, 0);
  537. SET_TX_BUFF_DESC_PSB(tx_bd_desc, 0);
  538. SET_TX_BUFF_DESC_OWN(tx_bd_desc, 0);
  539. for (i = 1; i < segmentnum; i++) {
  540. SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, i, 0);
  541. SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, i, 0);
  542. SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, i, 0);
  543. #if (DMA_IS_64BIT == 1)
  544. SET_TXBUFFER_DESC_ADD_HIGT_WITH_OFFSET(tx_bd_desc, i, 0);
  545. #endif
  546. }
  547. SET_TX_BUFF_DESC_LEN_1(tx_bd_desc, 0);
  548. SET_TX_BUFF_DESC_AMSDU_1(tx_bd_desc, 0);
  549. SET_TX_BUFF_DESC_LEN_2(tx_bd_desc, 0);
  550. SET_TX_BUFF_DESC_AMSDU_2(tx_bd_desc, 0);
  551. SET_TX_BUFF_DESC_LEN_3(tx_bd_desc, 0);
  552. SET_TX_BUFF_DESC_AMSDU_3(tx_bd_desc, 0);
  553. /* Clear all status */
  554. CLEAR_PCI_TX_DESC_CONTENT(desc, TX_DESC_SIZE);
  555. if (rtlpriv->rtlhal.earlymode_enable) {
  556. if (queue_index < BEACON_QUEUE) {
  557. /* This if needs braces */
  558. SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size + 8);
  559. } else {
  560. SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
  561. }
  562. } else {
  563. SET_TX_BUFF_DESC_LEN_0(tx_bd_desc, desc_size);
  564. }
  565. SET_TX_BUFF_DESC_PSB(tx_bd_desc, psblen);
  566. SET_TX_BUFF_DESC_ADDR_LOW_0(tx_bd_desc,
  567. rtlpci->tx_ring[queue_index].dma +
  568. (current_bd_desc * TX_DESC_SIZE));
  569. SET_TXBUFFER_DESC_LEN_WITH_OFFSET(tx_bd_desc, 1, pkt_len);
  570. /* don't using extendsion mode. */
  571. SET_TXBUFFER_DESC_AMSDU_WITH_OFFSET(tx_bd_desc, 1, 0);
  572. SET_TXBUFFER_DESC_ADD_LOW_WITH_OFFSET(tx_bd_desc, 1, addr);
  573. SET_TX_DESC_PKT_SIZE(desc, (u16)(pkt_len));
  574. SET_TX_DESC_TX_BUFFER_SIZE(desc, (u16)(pkt_len));
  575. }
  576. void rtl92ee_tx_fill_desc(struct ieee80211_hw *hw,
  577. struct ieee80211_hdr *hdr, u8 *pdesc_tx,
  578. u8 *pbd_desc_tx,
  579. struct ieee80211_tx_info *info,
  580. struct ieee80211_sta *sta,
  581. struct sk_buff *skb,
  582. u8 hw_queue, struct rtl_tcb_desc *ptcb_desc)
  583. {
  584. struct rtl_priv *rtlpriv = rtl_priv(hw);
  585. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  586. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  587. struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
  588. u8 *pdesc = (u8 *)pdesc_tx;
  589. u16 seq_number;
  590. __le16 fc = hdr->frame_control;
  591. unsigned int buf_len = 0;
  592. u8 fw_qsel = _rtl92ee_map_hwqueue_to_fwqueue(skb, hw_queue);
  593. bool firstseg = ((hdr->seq_ctrl &
  594. cpu_to_le16(IEEE80211_SCTL_FRAG)) == 0);
  595. bool lastseg = ((hdr->frame_control &
  596. cpu_to_le16(IEEE80211_FCTL_MOREFRAGS)) == 0);
  597. dma_addr_t mapping;
  598. u8 bw_40 = 0;
  599. u8 short_gi = 0;
  600. if (mac->opmode == NL80211_IFTYPE_STATION) {
  601. bw_40 = mac->bw_40;
  602. } else if (mac->opmode == NL80211_IFTYPE_AP ||
  603. mac->opmode == NL80211_IFTYPE_ADHOC) {
  604. if (sta)
  605. bw_40 = sta->ht_cap.cap &
  606. IEEE80211_HT_CAP_SUP_WIDTH_20_40;
  607. }
  608. seq_number = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
  609. rtl_get_tcb_desc(hw, info, sta, skb, ptcb_desc);
  610. /* reserve 8 byte for AMPDU early mode */
  611. if (rtlhal->earlymode_enable) {
  612. skb_push(skb, EM_HDR_LEN);
  613. memset(skb->data, 0, EM_HDR_LEN);
  614. }
  615. buf_len = skb->len;
  616. mapping = pci_map_single(rtlpci->pdev, skb->data, skb->len,
  617. PCI_DMA_TODEVICE);
  618. if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
  619. RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
  620. "DMA mapping error");
  621. return;
  622. }
  623. if (pbd_desc_tx != NULL)
  624. rtl92ee_pre_fill_tx_bd_desc(hw, pbd_desc_tx, pdesc, hw_queue,
  625. skb, mapping);
  626. if (ieee80211_is_nullfunc(fc) || ieee80211_is_ctl(fc)) {
  627. firstseg = true;
  628. lastseg = true;
  629. }
  630. if (firstseg) {
  631. if (rtlhal->earlymode_enable) {
  632. SET_TX_DESC_PKT_OFFSET(pdesc, 1);
  633. SET_TX_DESC_OFFSET(pdesc,
  634. USB_HWDESC_HEADER_LEN + EM_HDR_LEN);
  635. if (ptcb_desc->empkt_num) {
  636. RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
  637. "Insert 8 byte.pTcb->EMPktNum:%d\n",
  638. ptcb_desc->empkt_num);
  639. _rtl92ee_insert_emcontent(ptcb_desc,
  640. (u8 *)(skb->data));
  641. }
  642. } else {
  643. SET_TX_DESC_OFFSET(pdesc, USB_HWDESC_HEADER_LEN);
  644. }
  645. SET_TX_DESC_TX_RATE(pdesc, ptcb_desc->hw_rate);
  646. if (ieee80211_is_mgmt(fc)) {
  647. ptcb_desc->use_driver_rate = true;
  648. } else {
  649. if (rtlpriv->ra.is_special_data) {
  650. ptcb_desc->use_driver_rate = true;
  651. SET_TX_DESC_TX_RATE(pdesc, DESC_RATE11M);
  652. } else {
  653. ptcb_desc->use_driver_rate = false;
  654. }
  655. }
  656. if (ptcb_desc->hw_rate > DESC_RATEMCS0)
  657. short_gi = (ptcb_desc->use_shortgi) ? 1 : 0;
  658. else
  659. short_gi = (ptcb_desc->use_shortpreamble) ? 1 : 0;
  660. if (info->flags & IEEE80211_TX_CTL_AMPDU) {
  661. SET_TX_DESC_AGG_ENABLE(pdesc, 1);
  662. SET_TX_DESC_MAX_AGG_NUM(pdesc, 0x14);
  663. }
  664. SET_TX_DESC_SEQ(pdesc, seq_number);
  665. SET_TX_DESC_RTS_ENABLE(pdesc,
  666. ((ptcb_desc->rts_enable &&
  667. !ptcb_desc->cts_enable) ? 1 : 0));
  668. SET_TX_DESC_HW_RTS_ENABLE(pdesc, 0);
  669. SET_TX_DESC_CTS2SELF(pdesc,
  670. ((ptcb_desc->cts_enable) ? 1 : 0));
  671. SET_TX_DESC_RTS_RATE(pdesc, ptcb_desc->rts_rate);
  672. SET_TX_DESC_RTS_SC(pdesc, ptcb_desc->rts_sc);
  673. SET_TX_DESC_RTS_SHORT(pdesc,
  674. ((ptcb_desc->rts_rate <= DESC_RATE54M) ?
  675. (ptcb_desc->rts_use_shortpreamble ? 1 : 0) :
  676. (ptcb_desc->rts_use_shortgi ? 1 : 0)));
  677. if (ptcb_desc->tx_enable_sw_calc_duration)
  678. SET_TX_DESC_NAV_USE_HDR(pdesc, 1);
  679. if (bw_40) {
  680. if (ptcb_desc->packet_bw == HT_CHANNEL_WIDTH_20_40) {
  681. SET_TX_DESC_DATA_BW(pdesc, 1);
  682. SET_TX_DESC_TX_SUB_CARRIER(pdesc, 3);
  683. } else {
  684. SET_TX_DESC_DATA_BW(pdesc, 0);
  685. SET_TX_DESC_TX_SUB_CARRIER(pdesc,
  686. mac->cur_40_prime_sc);
  687. }
  688. } else {
  689. SET_TX_DESC_DATA_BW(pdesc, 0);
  690. SET_TX_DESC_TX_SUB_CARRIER(pdesc, 0);
  691. }
  692. SET_TX_DESC_LINIP(pdesc, 0);
  693. if (sta) {
  694. u8 ampdu_density = sta->ht_cap.ampdu_density;
  695. SET_TX_DESC_AMPDU_DENSITY(pdesc, ampdu_density);
  696. }
  697. if (info->control.hw_key) {
  698. struct ieee80211_key_conf *key = info->control.hw_key;
  699. switch (key->cipher) {
  700. case WLAN_CIPHER_SUITE_WEP40:
  701. case WLAN_CIPHER_SUITE_WEP104:
  702. case WLAN_CIPHER_SUITE_TKIP:
  703. SET_TX_DESC_SEC_TYPE(pdesc, 0x1);
  704. break;
  705. case WLAN_CIPHER_SUITE_CCMP:
  706. SET_TX_DESC_SEC_TYPE(pdesc, 0x3);
  707. break;
  708. default:
  709. SET_TX_DESC_SEC_TYPE(pdesc, 0x0);
  710. break;
  711. }
  712. }
  713. SET_TX_DESC_QUEUE_SEL(pdesc, fw_qsel);
  714. SET_TX_DESC_DATA_RATE_FB_LIMIT(pdesc, 0x1F);
  715. SET_TX_DESC_RTS_RATE_FB_LIMIT(pdesc, 0xF);
  716. SET_TX_DESC_DISABLE_FB(pdesc,
  717. ptcb_desc->disable_ratefallback ? 1 : 0);
  718. SET_TX_DESC_USE_RATE(pdesc, ptcb_desc->use_driver_rate ? 1 : 0);
  719. /*SET_TX_DESC_PWR_STATUS(pdesc, pwr_status);*/
  720. /* Set TxRate and RTSRate in TxDesc */
  721. /* This prevent Tx initial rate of new-coming packets */
  722. /* from being overwritten by retried packet rate.*/
  723. if (!ptcb_desc->use_driver_rate) {
  724. /*SET_TX_DESC_RTS_RATE(pdesc, 0x08); */
  725. /* SET_TX_DESC_TX_RATE(pdesc, 0x0b); */
  726. }
  727. if (ieee80211_is_data_qos(fc)) {
  728. if (mac->rdg_en) {
  729. RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
  730. "Enable RDG function.\n");
  731. SET_TX_DESC_RDG_ENABLE(pdesc, 1);
  732. SET_TX_DESC_HTC(pdesc, 1);
  733. }
  734. }
  735. }
  736. SET_TX_DESC_FIRST_SEG(pdesc, (firstseg ? 1 : 0));
  737. SET_TX_DESC_LAST_SEG(pdesc, (lastseg ? 1 : 0));
  738. SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
  739. if (rtlpriv->dm.useramask) {
  740. SET_TX_DESC_RATE_ID(pdesc, ptcb_desc->ratr_index);
  741. SET_TX_DESC_MACID(pdesc, ptcb_desc->mac_id);
  742. } else {
  743. SET_TX_DESC_RATE_ID(pdesc, 0xC + ptcb_desc->ratr_index);
  744. SET_TX_DESC_MACID(pdesc, ptcb_desc->ratr_index);
  745. }
  746. SET_TX_DESC_MORE_FRAG(pdesc, (lastseg ? 0 : 1));
  747. if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
  748. is_broadcast_ether_addr(ieee80211_get_DA(hdr))) {
  749. SET_TX_DESC_BMC(pdesc, 1);
  750. }
  751. RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE, "\n");
  752. }
  753. void rtl92ee_tx_fill_cmddesc(struct ieee80211_hw *hw,
  754. u8 *pdesc, bool firstseg,
  755. bool lastseg, struct sk_buff *skb)
  756. {
  757. struct rtl_priv *rtlpriv = rtl_priv(hw);
  758. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  759. u8 fw_queue = QSLT_BEACON;
  760. dma_addr_t mapping = pci_map_single(rtlpci->pdev,
  761. skb->data, skb->len,
  762. PCI_DMA_TODEVICE);
  763. u8 txdesc_len = 40;
  764. if (pci_dma_mapping_error(rtlpci->pdev, mapping)) {
  765. RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
  766. "DMA mapping error");
  767. return;
  768. }
  769. CLEAR_PCI_TX_DESC_CONTENT(pdesc, txdesc_len);
  770. if (firstseg)
  771. SET_TX_DESC_OFFSET(pdesc, txdesc_len);
  772. SET_TX_DESC_TX_RATE(pdesc, DESC_RATE1M);
  773. SET_TX_DESC_SEQ(pdesc, 0);
  774. SET_TX_DESC_LINIP(pdesc, 0);
  775. SET_TX_DESC_QUEUE_SEL(pdesc, fw_queue);
  776. SET_TX_DESC_FIRST_SEG(pdesc, 1);
  777. SET_TX_DESC_LAST_SEG(pdesc, 1);
  778. SET_TX_DESC_TX_BUFFER_SIZE(pdesc, (u16)(skb->len));
  779. SET_TX_DESC_TX_BUFFER_ADDRESS(pdesc, mapping);
  780. SET_TX_DESC_RATE_ID(pdesc, 7);
  781. SET_TX_DESC_MACID(pdesc, 0);
  782. SET_TX_DESC_OWN(pdesc, 1);
  783. SET_TX_DESC_PKT_SIZE((u8 *)pdesc, (u16)(skb->len));
  784. SET_TX_DESC_FIRST_SEG(pdesc, 1);
  785. SET_TX_DESC_LAST_SEG(pdesc, 1);
  786. SET_TX_DESC_OFFSET(pdesc, 40);
  787. SET_TX_DESC_USE_RATE(pdesc, 1);
  788. RT_PRINT_DATA(rtlpriv, COMP_CMD, DBG_LOUD,
  789. "H2C Tx Cmd Content\n", pdesc, txdesc_len);
  790. }
  791. void rtl92ee_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx,
  792. u8 desc_name, u8 *val)
  793. {
  794. struct rtl_priv *rtlpriv = rtl_priv(hw);
  795. u16 cur_tx_rp = 0;
  796. u16 cur_tx_wp = 0;
  797. static u16 last_txw_point;
  798. static bool over_run;
  799. u32 tmp = 0;
  800. u8 q_idx = *val;
  801. if (istx) {
  802. switch (desc_name) {
  803. case HW_DESC_TX_NEXTDESC_ADDR:
  804. SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val);
  805. break;
  806. case HW_DESC_OWN:{
  807. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  808. struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[q_idx];
  809. u16 max_tx_desc = ring->entries;
  810. if (q_idx == BEACON_QUEUE) {
  811. ring->cur_tx_wp = 0;
  812. ring->cur_tx_rp = 0;
  813. SET_TX_BUFF_DESC_OWN(pdesc, 1);
  814. return;
  815. }
  816. ring->cur_tx_wp = ((ring->cur_tx_wp + 1) % max_tx_desc);
  817. if (over_run) {
  818. ring->cur_tx_wp = 0;
  819. over_run = false;
  820. }
  821. if (ring->avl_desc > 1) {
  822. ring->avl_desc--;
  823. rtl_write_word(rtlpriv,
  824. get_desc_addr_fr_q_idx(q_idx),
  825. ring->cur_tx_wp);
  826. if (q_idx == 1)
  827. last_txw_point = cur_tx_wp;
  828. }
  829. if (ring->avl_desc < (max_tx_desc - 15)) {
  830. u16 point_diff = 0;
  831. tmp =
  832. rtl_read_dword(rtlpriv,
  833. get_desc_addr_fr_q_idx(q_idx));
  834. cur_tx_rp = (u16)((tmp >> 16) & 0x0fff);
  835. cur_tx_wp = (u16)(tmp & 0x0fff);
  836. ring->cur_tx_wp = cur_tx_wp;
  837. ring->cur_tx_rp = cur_tx_rp;
  838. point_diff = ((cur_tx_rp > cur_tx_wp) ?
  839. (cur_tx_rp - cur_tx_wp) :
  840. (TX_DESC_NUM_92E - 1 -
  841. cur_tx_wp + cur_tx_rp));
  842. ring->avl_desc = point_diff;
  843. }
  844. }
  845. break;
  846. }
  847. } else {
  848. switch (desc_name) {
  849. case HW_DESC_RX_PREPARE:
  850. SET_RX_BUFFER_DESC_LS(pdesc, 0);
  851. SET_RX_BUFFER_DESC_FS(pdesc, 0);
  852. SET_RX_BUFFER_DESC_TOTAL_LENGTH(pdesc, 0);
  853. SET_RX_BUFFER_DESC_DATA_LENGTH(pdesc,
  854. MAX_RECEIVE_BUFFER_SIZE +
  855. RX_DESC_SIZE);
  856. SET_RX_BUFFER_PHYSICAL_LOW(pdesc, *(u32 *)val);
  857. break;
  858. case HW_DESC_RXERO:
  859. SET_RX_DESC_EOR(pdesc, 1);
  860. break;
  861. default:
  862. RT_ASSERT(false,
  863. "ERR rxdesc :%d not process\n", desc_name);
  864. break;
  865. }
  866. }
  867. }
  868. u32 rtl92ee_get_desc(u8 *pdesc, bool istx, u8 desc_name)
  869. {
  870. u32 ret = 0;
  871. if (istx) {
  872. switch (desc_name) {
  873. case HW_DESC_OWN:
  874. ret = GET_TX_DESC_OWN(pdesc);
  875. break;
  876. case HW_DESC_TXBUFF_ADDR:
  877. ret = GET_TXBUFFER_DESC_ADDR_LOW(pdesc, 1);
  878. break;
  879. default:
  880. RT_ASSERT(false,
  881. "ERR txdesc :%d not process\n", desc_name);
  882. break;
  883. }
  884. } else {
  885. switch (desc_name) {
  886. case HW_DESC_OWN:
  887. ret = GET_RX_DESC_OWN(pdesc);
  888. break;
  889. case HW_DESC_RXPKT_LEN:
  890. ret = GET_RX_DESC_PKT_LEN(pdesc);
  891. break;
  892. case HW_DESC_RXBUFF_ADDR:
  893. ret = GET_RX_DESC_BUFF_ADDR(pdesc);
  894. break;
  895. default:
  896. RT_ASSERT(false,
  897. "ERR rxdesc :%d not process\n", desc_name);
  898. break;
  899. }
  900. }
  901. return ret;
  902. }
  903. bool rtl92ee_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue, u16 index)
  904. {
  905. struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  906. struct rtl_priv *rtlpriv = rtl_priv(hw);
  907. u16 read_point, write_point, available_desc_num;
  908. bool ret = false;
  909. static u8 stop_report_cnt;
  910. struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
  911. {
  912. u16 point_diff = 0;
  913. u16 cur_tx_rp, cur_tx_wp;
  914. u32 tmpu32 = 0;
  915. tmpu32 =
  916. rtl_read_dword(rtlpriv,
  917. get_desc_addr_fr_q_idx(hw_queue));
  918. cur_tx_rp = (u16)((tmpu32 >> 16) & 0x0fff);
  919. cur_tx_wp = (u16)(tmpu32 & 0x0fff);
  920. ring->cur_tx_wp = cur_tx_wp;
  921. ring->cur_tx_rp = cur_tx_rp;
  922. point_diff = ((cur_tx_rp > cur_tx_wp) ?
  923. (cur_tx_rp - cur_tx_wp) :
  924. (TX_DESC_NUM_92E - cur_tx_wp + cur_tx_rp));
  925. ring->avl_desc = point_diff;
  926. }
  927. read_point = ring->cur_tx_rp;
  928. write_point = ring->cur_tx_wp;
  929. available_desc_num = ring->avl_desc;
  930. if (write_point > read_point) {
  931. if (index < write_point && index >= read_point)
  932. ret = false;
  933. else
  934. ret = true;
  935. } else if (write_point < read_point) {
  936. if (index > write_point && index < read_point)
  937. ret = true;
  938. else
  939. ret = false;
  940. } else {
  941. if (index != read_point)
  942. ret = true;
  943. }
  944. if (hw_queue == BEACON_QUEUE)
  945. ret = true;
  946. if (rtlpriv->rtlhal.driver_is_goingto_unload ||
  947. rtlpriv->psc.rfoff_reason > RF_CHANGE_BY_PS)
  948. ret = true;
  949. if (hw_queue < BEACON_QUEUE) {
  950. if (!ret)
  951. stop_report_cnt++;
  952. else
  953. stop_report_cnt = 0;
  954. }
  955. return ret;
  956. }
  957. void rtl92ee_tx_polling(struct ieee80211_hw *hw, u8 hw_queue)
  958. {
  959. }
  960. u32 rtl92ee_rx_command_packet(struct ieee80211_hw *hw,
  961. struct rtl_stats status,
  962. struct sk_buff *skb)
  963. {
  964. u32 result = 0;
  965. struct rtl_priv *rtlpriv = rtl_priv(hw);
  966. switch (status.packet_report_type) {
  967. case NORMAL_RX:
  968. result = 0;
  969. break;
  970. case C2H_PACKET:
  971. rtl92ee_c2h_packet_handler(hw, skb->data, (u8)skb->len);
  972. result = 1;
  973. break;
  974. default:
  975. RT_TRACE(rtlpriv, COMP_RECV, DBG_TRACE,
  976. "Unknown packet type %d\n", status.packet_report_type);
  977. break;
  978. }
  979. return result;
  980. }