parport_serial.c 20 KB

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  1. /*
  2. * Support for common PCI multi-I/O cards (which is most of them)
  3. *
  4. * Copyright (C) 2001 Tim Waugh <twaugh@redhat.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. *
  11. *
  12. * Multi-function PCI cards are supposed to present separate logical
  13. * devices on the bus. A common thing to do seems to be to just use
  14. * one logical device with lots of base address registers for both
  15. * parallel ports and serial ports. This driver is for dealing with
  16. * that.
  17. *
  18. */
  19. #include <linux/types.h>
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/slab.h>
  23. #include <linux/pci.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/parport.h>
  26. #include <linux/parport_pc.h>
  27. #include <linux/8250_pci.h>
  28. enum parport_pc_pci_cards {
  29. titan_110l = 0,
  30. titan_210l,
  31. netmos_9xx5_combo,
  32. netmos_9855,
  33. netmos_9855_2p,
  34. netmos_9900,
  35. netmos_9900_2p,
  36. netmos_99xx_1p,
  37. avlab_1s1p,
  38. avlab_1s2p,
  39. avlab_2s1p,
  40. siig_1s1p_10x,
  41. siig_2s1p_10x,
  42. siig_2p1s_20x,
  43. siig_1s1p_20x,
  44. siig_2s1p_20x,
  45. timedia_4078a,
  46. timedia_4079h,
  47. timedia_4085h,
  48. timedia_4088a,
  49. timedia_4089a,
  50. timedia_4095a,
  51. timedia_4096a,
  52. timedia_4078u,
  53. timedia_4079a,
  54. timedia_4085u,
  55. timedia_4079r,
  56. timedia_4079s,
  57. timedia_4079d,
  58. timedia_4079e,
  59. timedia_4079f,
  60. timedia_9079a,
  61. timedia_9079b,
  62. timedia_9079c,
  63. wch_ch353_1s1p,
  64. wch_ch353_2s1p,
  65. wch_ch382_2s1p,
  66. sunix_2s1p,
  67. };
  68. /* each element directly indexed from enum list, above */
  69. struct parport_pc_pci {
  70. int numports;
  71. struct { /* BAR (base address registers) numbers in the config
  72. space header */
  73. int lo;
  74. int hi; /* -1 if not there, >6 for offset-method (max
  75. BAR is 6) */
  76. } addr[4];
  77. /* If set, this is called immediately after pci_enable_device.
  78. * If it returns non-zero, no probing will take place and the
  79. * ports will not be used. */
  80. int (*preinit_hook) (struct pci_dev *pdev, struct parport_pc_pci *card,
  81. int autoirq, int autodma);
  82. /* If set, this is called after probing for ports. If 'failed'
  83. * is non-zero we couldn't use any of the ports. */
  84. void (*postinit_hook) (struct pci_dev *pdev,
  85. struct parport_pc_pci *card, int failed);
  86. };
  87. static int netmos_parallel_init(struct pci_dev *dev, struct parport_pc_pci *par,
  88. int autoirq, int autodma)
  89. {
  90. /* the rule described below doesn't hold for this device */
  91. if (dev->device == PCI_DEVICE_ID_NETMOS_9835 &&
  92. dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
  93. dev->subsystem_device == 0x0299)
  94. return -ENODEV;
  95. if (dev->device == PCI_DEVICE_ID_NETMOS_9912) {
  96. par->numports = 1;
  97. } else {
  98. /*
  99. * Netmos uses the subdevice ID to indicate the number of parallel
  100. * and serial ports. The form is 0x00PS, where <P> is the number of
  101. * parallel ports and <S> is the number of serial ports.
  102. */
  103. par->numports = (dev->subsystem_device & 0xf0) >> 4;
  104. if (par->numports > ARRAY_SIZE(par->addr))
  105. par->numports = ARRAY_SIZE(par->addr);
  106. }
  107. return 0;
  108. }
  109. static struct parport_pc_pci cards[] = {
  110. /* titan_110l */ { 1, { { 3, -1 }, } },
  111. /* titan_210l */ { 1, { { 3, -1 }, } },
  112. /* netmos_9xx5_combo */ { 1, { { 2, -1 }, }, netmos_parallel_init },
  113. /* netmos_9855 */ { 1, { { 0, -1 }, }, netmos_parallel_init },
  114. /* netmos_9855_2p */ { 2, { { 0, -1 }, { 2, -1 }, } },
  115. /* netmos_9900 */ {1, { { 3, 4 }, }, netmos_parallel_init },
  116. /* netmos_9900_2p */ {2, { { 0, 1 }, { 3, 4 }, } },
  117. /* netmos_99xx_1p */ {1, { { 0, 1 }, } },
  118. /* avlab_1s1p */ { 1, { { 1, 2}, } },
  119. /* avlab_1s2p */ { 2, { { 1, 2}, { 3, 4 },} },
  120. /* avlab_2s1p */ { 1, { { 2, 3}, } },
  121. /* siig_1s1p_10x */ { 1, { { 3, 4 }, } },
  122. /* siig_2s1p_10x */ { 1, { { 4, 5 }, } },
  123. /* siig_2p1s_20x */ { 2, { { 1, 2 }, { 3, 4 }, } },
  124. /* siig_1s1p_20x */ { 1, { { 1, 2 }, } },
  125. /* siig_2s1p_20x */ { 1, { { 2, 3 }, } },
  126. /* timedia_4078a */ { 1, { { 2, -1 }, } },
  127. /* timedia_4079h */ { 1, { { 2, 3 }, } },
  128. /* timedia_4085h */ { 2, { { 2, -1 }, { 4, -1 }, } },
  129. /* timedia_4088a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  130. /* timedia_4089a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  131. /* timedia_4095a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  132. /* timedia_4096a */ { 2, { { 2, 3 }, { 4, 5 }, } },
  133. /* timedia_4078u */ { 1, { { 2, -1 }, } },
  134. /* timedia_4079a */ { 1, { { 2, 3 }, } },
  135. /* timedia_4085u */ { 2, { { 2, -1 }, { 4, -1 }, } },
  136. /* timedia_4079r */ { 1, { { 2, 3 }, } },
  137. /* timedia_4079s */ { 1, { { 2, 3 }, } },
  138. /* timedia_4079d */ { 1, { { 2, 3 }, } },
  139. /* timedia_4079e */ { 1, { { 2, 3 }, } },
  140. /* timedia_4079f */ { 1, { { 2, 3 }, } },
  141. /* timedia_9079a */ { 1, { { 2, 3 }, } },
  142. /* timedia_9079b */ { 1, { { 2, 3 }, } },
  143. /* timedia_9079c */ { 1, { { 2, 3 }, } },
  144. /* wch_ch353_1s1p*/ { 1, { { 1, -1}, } },
  145. /* wch_ch353_2s1p*/ { 1, { { 2, -1}, } },
  146. /* wch_ch382_2s1p*/ { 1, { { 2, -1}, } },
  147. /* sunix_2s1p */ { 1, { { 3, -1 }, } },
  148. };
  149. #define PCI_VENDOR_ID_SUNIX 0x1fd4
  150. #define PCI_DEVICE_ID_SUNIX_1999 0x1999
  151. static struct pci_device_id parport_serial_pci_tbl[] = {
  152. /* PCI cards */
  153. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_110L,
  154. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_110l },
  155. { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_210L,
  156. PCI_ANY_ID, PCI_ANY_ID, 0, 0, titan_210l },
  157. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9735,
  158. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  159. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9745,
  160. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  161. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
  162. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  163. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9845,
  164. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9xx5_combo },
  165. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  166. 0x1000, 0x0020, 0, 0, netmos_9855_2p },
  167. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  168. 0x1000, 0x0022, 0, 0, netmos_9855_2p },
  169. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9855,
  170. PCI_ANY_ID, PCI_ANY_ID, 0, 0, netmos_9855 },
  171. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  172. 0xA000, 0x3011, 0, 0, netmos_9900 },
  173. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  174. 0xA000, 0x3012, 0, 0, netmos_9900 },
  175. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  176. 0xA000, 0x3020, 0, 0, netmos_9900_2p },
  177. { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
  178. 0xA000, 0x2000, 0, 0, netmos_99xx_1p },
  179. /* PCI_VENDOR_ID_AVLAB/Intek21 has another bunch of cards ...*/
  180. { PCI_VENDOR_ID_AFAVLAB, 0x2110,
  181. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  182. { PCI_VENDOR_ID_AFAVLAB, 0x2111,
  183. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  184. { PCI_VENDOR_ID_AFAVLAB, 0x2112,
  185. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s1p },
  186. { PCI_VENDOR_ID_AFAVLAB, 0x2140,
  187. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  188. { PCI_VENDOR_ID_AFAVLAB, 0x2141,
  189. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  190. { PCI_VENDOR_ID_AFAVLAB, 0x2142,
  191. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_1s2p },
  192. { PCI_VENDOR_ID_AFAVLAB, 0x2160,
  193. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  194. { PCI_VENDOR_ID_AFAVLAB, 0x2161,
  195. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  196. { PCI_VENDOR_ID_AFAVLAB, 0x2162,
  197. PCI_ANY_ID, PCI_ANY_ID, 0, 0, avlab_2s1p },
  198. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_550,
  199. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  200. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_650,
  201. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  202. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_10x_850,
  203. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_10x },
  204. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_550,
  205. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  206. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_650,
  207. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  208. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_10x_850,
  209. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_10x },
  210. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_550,
  211. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  212. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_650,
  213. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  214. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2P1S_20x_850,
  215. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2p1s_20x },
  216. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_550,
  217. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  218. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_650,
  219. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  220. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S1P_20x_850,
  221. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_1s1p_20x },
  222. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_550,
  223. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  224. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_650,
  225. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  226. { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S1P_20x_850,
  227. PCI_ANY_ID, PCI_ANY_ID, 0, 0, siig_2s1p_20x },
  228. /* PCI_VENDOR_ID_TIMEDIA/SUNIX has many differing cards ...*/
  229. { 0x1409, 0x7168, 0x1409, 0x4078, 0, 0, timedia_4078a },
  230. { 0x1409, 0x7168, 0x1409, 0x4079, 0, 0, timedia_4079h },
  231. { 0x1409, 0x7168, 0x1409, 0x4085, 0, 0, timedia_4085h },
  232. { 0x1409, 0x7168, 0x1409, 0x4088, 0, 0, timedia_4088a },
  233. { 0x1409, 0x7168, 0x1409, 0x4089, 0, 0, timedia_4089a },
  234. { 0x1409, 0x7168, 0x1409, 0x4095, 0, 0, timedia_4095a },
  235. { 0x1409, 0x7168, 0x1409, 0x4096, 0, 0, timedia_4096a },
  236. { 0x1409, 0x7168, 0x1409, 0x5078, 0, 0, timedia_4078u },
  237. { 0x1409, 0x7168, 0x1409, 0x5079, 0, 0, timedia_4079a },
  238. { 0x1409, 0x7168, 0x1409, 0x5085, 0, 0, timedia_4085u },
  239. { 0x1409, 0x7168, 0x1409, 0x6079, 0, 0, timedia_4079r },
  240. { 0x1409, 0x7168, 0x1409, 0x7079, 0, 0, timedia_4079s },
  241. { 0x1409, 0x7168, 0x1409, 0x8079, 0, 0, timedia_4079d },
  242. { 0x1409, 0x7168, 0x1409, 0x9079, 0, 0, timedia_4079e },
  243. { 0x1409, 0x7168, 0x1409, 0xa079, 0, 0, timedia_4079f },
  244. { 0x1409, 0x7168, 0x1409, 0xb079, 0, 0, timedia_9079a },
  245. { 0x1409, 0x7168, 0x1409, 0xc079, 0, 0, timedia_9079b },
  246. { 0x1409, 0x7168, 0x1409, 0xd079, 0, 0, timedia_9079c },
  247. /* WCH CARDS */
  248. { 0x4348, 0x5053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, wch_ch353_1s1p},
  249. { 0x4348, 0x7053, 0x4348, 0x3253, 0, 0, wch_ch353_2s1p},
  250. { 0x1c00, 0x3250, 0x1c00, 0x3250, 0, 0, wch_ch382_2s1p},
  251. /*
  252. * More SUNIX variations. At least one of these has part number
  253. * '5079A but subdevice 0x102. That board reports 0x0708 as
  254. * its PCI Class.
  255. */
  256. { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999, PCI_VENDOR_ID_SUNIX,
  257. 0x0102, 0, 0, sunix_2s1p },
  258. { 0, } /* terminate list */
  259. };
  260. MODULE_DEVICE_TABLE(pci,parport_serial_pci_tbl);
  261. /*
  262. * This table describes the serial "geometry" of these boards. Any
  263. * quirks for these can be found in drivers/serial/8250_pci.c
  264. *
  265. * Cards not tested are marked n/t
  266. * If you have one of these cards and it works for you, please tell me..
  267. */
  268. static struct pciserial_board pci_parport_serial_boards[] = {
  269. [titan_110l] = {
  270. .flags = FL_BASE1 | FL_BASE_BARS,
  271. .num_ports = 1,
  272. .base_baud = 921600,
  273. .uart_offset = 8,
  274. },
  275. [titan_210l] = {
  276. .flags = FL_BASE1 | FL_BASE_BARS,
  277. .num_ports = 2,
  278. .base_baud = 921600,
  279. .uart_offset = 8,
  280. },
  281. [netmos_9xx5_combo] = {
  282. .flags = FL_BASE0 | FL_BASE_BARS,
  283. .num_ports = 1,
  284. .base_baud = 115200,
  285. .uart_offset = 8,
  286. },
  287. [netmos_9855] = {
  288. .flags = FL_BASE2 | FL_BASE_BARS,
  289. .num_ports = 1,
  290. .base_baud = 115200,
  291. .uart_offset = 8,
  292. },
  293. [netmos_9855_2p] = {
  294. .flags = FL_BASE4 | FL_BASE_BARS,
  295. .num_ports = 1,
  296. .base_baud = 115200,
  297. .uart_offset = 8,
  298. },
  299. [netmos_9900] = { /* n/t */
  300. .flags = FL_BASE0 | FL_BASE_BARS,
  301. .num_ports = 1,
  302. .base_baud = 115200,
  303. .uart_offset = 8,
  304. },
  305. [netmos_9900_2p] = { /* parallel only */ /* n/t */
  306. .flags = FL_BASE0,
  307. .num_ports = 0,
  308. .base_baud = 115200,
  309. .uart_offset = 8,
  310. },
  311. [netmos_99xx_1p] = { /* parallel only */ /* n/t */
  312. .flags = FL_BASE0,
  313. .num_ports = 0,
  314. .base_baud = 115200,
  315. .uart_offset = 8,
  316. },
  317. [avlab_1s1p] = { /* n/t */
  318. .flags = FL_BASE0 | FL_BASE_BARS,
  319. .num_ports = 1,
  320. .base_baud = 115200,
  321. .uart_offset = 8,
  322. },
  323. [avlab_1s2p] = { /* n/t */
  324. .flags = FL_BASE0 | FL_BASE_BARS,
  325. .num_ports = 1,
  326. .base_baud = 115200,
  327. .uart_offset = 8,
  328. },
  329. [avlab_2s1p] = { /* n/t */
  330. .flags = FL_BASE0 | FL_BASE_BARS,
  331. .num_ports = 2,
  332. .base_baud = 115200,
  333. .uart_offset = 8,
  334. },
  335. [siig_1s1p_10x] = {
  336. .flags = FL_BASE2,
  337. .num_ports = 1,
  338. .base_baud = 460800,
  339. .uart_offset = 8,
  340. },
  341. [siig_2s1p_10x] = {
  342. .flags = FL_BASE2,
  343. .num_ports = 1,
  344. .base_baud = 921600,
  345. .uart_offset = 8,
  346. },
  347. [siig_2p1s_20x] = {
  348. .flags = FL_BASE0,
  349. .num_ports = 1,
  350. .base_baud = 921600,
  351. .uart_offset = 8,
  352. },
  353. [siig_1s1p_20x] = {
  354. .flags = FL_BASE0,
  355. .num_ports = 1,
  356. .base_baud = 921600,
  357. .uart_offset = 8,
  358. },
  359. [siig_2s1p_20x] = {
  360. .flags = FL_BASE0,
  361. .num_ports = 1,
  362. .base_baud = 921600,
  363. .uart_offset = 8,
  364. },
  365. [timedia_4078a] = {
  366. .flags = FL_BASE0|FL_BASE_BARS,
  367. .num_ports = 1,
  368. .base_baud = 921600,
  369. .uart_offset = 8,
  370. },
  371. [timedia_4079h] = {
  372. .flags = FL_BASE0|FL_BASE_BARS,
  373. .num_ports = 1,
  374. .base_baud = 921600,
  375. .uart_offset = 8,
  376. },
  377. [timedia_4085h] = {
  378. .flags = FL_BASE0|FL_BASE_BARS,
  379. .num_ports = 1,
  380. .base_baud = 921600,
  381. .uart_offset = 8,
  382. },
  383. [timedia_4088a] = {
  384. .flags = FL_BASE0|FL_BASE_BARS,
  385. .num_ports = 1,
  386. .base_baud = 921600,
  387. .uart_offset = 8,
  388. },
  389. [timedia_4089a] = {
  390. .flags = FL_BASE0|FL_BASE_BARS,
  391. .num_ports = 1,
  392. .base_baud = 921600,
  393. .uart_offset = 8,
  394. },
  395. [timedia_4095a] = {
  396. .flags = FL_BASE0|FL_BASE_BARS,
  397. .num_ports = 1,
  398. .base_baud = 921600,
  399. .uart_offset = 8,
  400. },
  401. [timedia_4096a] = {
  402. .flags = FL_BASE0|FL_BASE_BARS,
  403. .num_ports = 1,
  404. .base_baud = 921600,
  405. .uart_offset = 8,
  406. },
  407. [timedia_4078u] = {
  408. .flags = FL_BASE0|FL_BASE_BARS,
  409. .num_ports = 1,
  410. .base_baud = 921600,
  411. .uart_offset = 8,
  412. },
  413. [timedia_4079a] = {
  414. .flags = FL_BASE0|FL_BASE_BARS,
  415. .num_ports = 1,
  416. .base_baud = 921600,
  417. .uart_offset = 8,
  418. },
  419. [timedia_4085u] = {
  420. .flags = FL_BASE0|FL_BASE_BARS,
  421. .num_ports = 1,
  422. .base_baud = 921600,
  423. .uart_offset = 8,
  424. },
  425. [timedia_4079r] = {
  426. .flags = FL_BASE0|FL_BASE_BARS,
  427. .num_ports = 1,
  428. .base_baud = 921600,
  429. .uart_offset = 8,
  430. },
  431. [timedia_4079s] = {
  432. .flags = FL_BASE0|FL_BASE_BARS,
  433. .num_ports = 1,
  434. .base_baud = 921600,
  435. .uart_offset = 8,
  436. },
  437. [timedia_4079d] = {
  438. .flags = FL_BASE0|FL_BASE_BARS,
  439. .num_ports = 1,
  440. .base_baud = 921600,
  441. .uart_offset = 8,
  442. },
  443. [timedia_4079e] = {
  444. .flags = FL_BASE0|FL_BASE_BARS,
  445. .num_ports = 1,
  446. .base_baud = 921600,
  447. .uart_offset = 8,
  448. },
  449. [timedia_4079f] = {
  450. .flags = FL_BASE0|FL_BASE_BARS,
  451. .num_ports = 1,
  452. .base_baud = 921600,
  453. .uart_offset = 8,
  454. },
  455. [timedia_9079a] = {
  456. .flags = FL_BASE0|FL_BASE_BARS,
  457. .num_ports = 1,
  458. .base_baud = 921600,
  459. .uart_offset = 8,
  460. },
  461. [timedia_9079b] = {
  462. .flags = FL_BASE0|FL_BASE_BARS,
  463. .num_ports = 1,
  464. .base_baud = 921600,
  465. .uart_offset = 8,
  466. },
  467. [timedia_9079c] = {
  468. .flags = FL_BASE0|FL_BASE_BARS,
  469. .num_ports = 1,
  470. .base_baud = 921600,
  471. .uart_offset = 8,
  472. },
  473. [wch_ch353_1s1p] = {
  474. .flags = FL_BASE0|FL_BASE_BARS,
  475. .num_ports = 1,
  476. .base_baud = 115200,
  477. .uart_offset = 8,
  478. },
  479. [wch_ch353_2s1p] = {
  480. .flags = FL_BASE0|FL_BASE_BARS,
  481. .num_ports = 2,
  482. .base_baud = 115200,
  483. .uart_offset = 8,
  484. },
  485. [wch_ch382_2s1p] = {
  486. .flags = FL_BASE0,
  487. .num_ports = 2,
  488. .base_baud = 115200,
  489. .uart_offset = 8,
  490. .first_offset = 0xC0,
  491. },
  492. [sunix_2s1p] = {
  493. .flags = FL_BASE0|FL_BASE_BARS,
  494. .num_ports = 2,
  495. .base_baud = 921600,
  496. .uart_offset = 8,
  497. },
  498. };
  499. struct parport_serial_private {
  500. struct serial_private *serial;
  501. int num_par;
  502. struct parport *port[PARPORT_MAX];
  503. struct parport_pc_pci par;
  504. };
  505. /* Register the serial port(s) of a PCI card. */
  506. static int serial_register(struct pci_dev *dev, const struct pci_device_id *id)
  507. {
  508. struct parport_serial_private *priv = pci_get_drvdata (dev);
  509. struct pciserial_board *board;
  510. struct serial_private *serial;
  511. board = &pci_parport_serial_boards[id->driver_data];
  512. if (board->num_ports == 0)
  513. return 0;
  514. serial = pciserial_init_ports(dev, board);
  515. if (IS_ERR(serial))
  516. return PTR_ERR(serial);
  517. priv->serial = serial;
  518. return 0;
  519. }
  520. /* Register the parallel port(s) of a PCI card. */
  521. static int parport_register(struct pci_dev *dev, const struct pci_device_id *id)
  522. {
  523. struct parport_pc_pci *card;
  524. struct parport_serial_private *priv = pci_get_drvdata (dev);
  525. int n, success = 0;
  526. priv->par = cards[id->driver_data];
  527. card = &priv->par;
  528. if (card->preinit_hook &&
  529. card->preinit_hook (dev, card, PARPORT_IRQ_NONE, PARPORT_DMA_NONE))
  530. return -ENODEV;
  531. for (n = 0; n < card->numports; n++) {
  532. struct parport *port;
  533. int lo = card->addr[n].lo;
  534. int hi = card->addr[n].hi;
  535. unsigned long io_lo, io_hi;
  536. int irq;
  537. if (priv->num_par == ARRAY_SIZE (priv->port)) {
  538. printk (KERN_WARNING
  539. "parport_serial: %s: only %zu parallel ports "
  540. "supported (%d reported)\n", pci_name (dev),
  541. ARRAY_SIZE(priv->port), card->numports);
  542. break;
  543. }
  544. io_lo = pci_resource_start (dev, lo);
  545. io_hi = 0;
  546. if ((hi >= 0) && (hi <= 6))
  547. io_hi = pci_resource_start (dev, hi);
  548. else if (hi > 6)
  549. io_lo += hi; /* Reinterpret the meaning of
  550. "hi" as an offset (see SYBA
  551. def.) */
  552. /* TODO: test if sharing interrupts works */
  553. irq = dev->irq;
  554. if (irq == IRQ_NONE) {
  555. dev_dbg(&dev->dev,
  556. "PCI parallel port detected: I/O at %#lx(%#lx)\n",
  557. io_lo, io_hi);
  558. irq = PARPORT_IRQ_NONE;
  559. } else {
  560. dev_dbg(&dev->dev,
  561. "PCI parallel port detected: I/O at %#lx(%#lx), IRQ %d\n",
  562. io_lo, io_hi, irq);
  563. }
  564. port = parport_pc_probe_port (io_lo, io_hi, irq,
  565. PARPORT_DMA_NONE, &dev->dev, IRQF_SHARED);
  566. if (port) {
  567. priv->port[priv->num_par++] = port;
  568. success = 1;
  569. }
  570. }
  571. if (card->postinit_hook)
  572. card->postinit_hook (dev, card, !success);
  573. return 0;
  574. }
  575. static int parport_serial_pci_probe(struct pci_dev *dev,
  576. const struct pci_device_id *id)
  577. {
  578. struct parport_serial_private *priv;
  579. int err;
  580. priv = kzalloc (sizeof *priv, GFP_KERNEL);
  581. if (!priv)
  582. return -ENOMEM;
  583. pci_set_drvdata (dev, priv);
  584. err = pci_enable_device (dev);
  585. if (err) {
  586. kfree (priv);
  587. return err;
  588. }
  589. if (parport_register (dev, id)) {
  590. kfree (priv);
  591. return -ENODEV;
  592. }
  593. if (serial_register (dev, id)) {
  594. int i;
  595. for (i = 0; i < priv->num_par; i++)
  596. parport_pc_unregister_port (priv->port[i]);
  597. kfree (priv);
  598. return -ENODEV;
  599. }
  600. return 0;
  601. }
  602. static void parport_serial_pci_remove(struct pci_dev *dev)
  603. {
  604. struct parport_serial_private *priv = pci_get_drvdata (dev);
  605. int i;
  606. // Serial ports
  607. if (priv->serial)
  608. pciserial_remove_ports(priv->serial);
  609. // Parallel ports
  610. for (i = 0; i < priv->num_par; i++)
  611. parport_pc_unregister_port (priv->port[i]);
  612. kfree (priv);
  613. return;
  614. }
  615. #ifdef CONFIG_PM
  616. static int parport_serial_pci_suspend(struct pci_dev *dev, pm_message_t state)
  617. {
  618. struct parport_serial_private *priv = pci_get_drvdata(dev);
  619. if (priv->serial)
  620. pciserial_suspend_ports(priv->serial);
  621. /* FIXME: What about parport? */
  622. pci_save_state(dev);
  623. pci_set_power_state(dev, pci_choose_state(dev, state));
  624. return 0;
  625. }
  626. static int parport_serial_pci_resume(struct pci_dev *dev)
  627. {
  628. struct parport_serial_private *priv = pci_get_drvdata(dev);
  629. int err;
  630. pci_set_power_state(dev, PCI_D0);
  631. pci_restore_state(dev);
  632. /*
  633. * The device may have been disabled. Re-enable it.
  634. */
  635. err = pci_enable_device(dev);
  636. if (err) {
  637. printk(KERN_ERR "parport_serial: %s: error enabling "
  638. "device for resume (%d)\n", pci_name(dev), err);
  639. return err;
  640. }
  641. if (priv->serial)
  642. pciserial_resume_ports(priv->serial);
  643. /* FIXME: What about parport? */
  644. return 0;
  645. }
  646. #endif
  647. static struct pci_driver parport_serial_pci_driver = {
  648. .name = "parport_serial",
  649. .id_table = parport_serial_pci_tbl,
  650. .probe = parport_serial_pci_probe,
  651. .remove = parport_serial_pci_remove,
  652. #ifdef CONFIG_PM
  653. .suspend = parport_serial_pci_suspend,
  654. .resume = parport_serial_pci_resume,
  655. #endif
  656. };
  657. static int __init parport_serial_init (void)
  658. {
  659. return pci_register_driver (&parport_serial_pci_driver);
  660. }
  661. static void __exit parport_serial_exit (void)
  662. {
  663. pci_unregister_driver (&parport_serial_pci_driver);
  664. return;
  665. }
  666. MODULE_AUTHOR("Tim Waugh <twaugh@redhat.com>");
  667. MODULE_DESCRIPTION("Driver for common parallel+serial multi-I/O PCI cards");
  668. MODULE_LICENSE("GPL");
  669. module_init(parport_serial_init);
  670. module_exit(parport_serial_exit);