phy-s5pv210-usb2.c 4.4 KB

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  1. /*
  2. * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support
  3. *
  4. * Copyright (C) 2013 Samsung Electronics Co., Ltd.
  5. * Authors: Kamil Debski <k.debski@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/io.h>
  13. #include <linux/phy/phy.h>
  14. #include "phy-samsung-usb2.h"
  15. /* Exynos USB PHY registers */
  16. /* PHY power control */
  17. #define S5PV210_UPHYPWR 0x0
  18. #define S5PV210_UPHYPWR_PHY0_SUSPEND BIT(0)
  19. #define S5PV210_UPHYPWR_PHY0_PWR BIT(3)
  20. #define S5PV210_UPHYPWR_PHY0_OTG_PWR BIT(4)
  21. #define S5PV210_UPHYPWR_PHY0 ( \
  22. S5PV210_UPHYPWR_PHY0_SUSPEND | \
  23. S5PV210_UPHYPWR_PHY0_PWR | \
  24. S5PV210_UPHYPWR_PHY0_OTG_PWR)
  25. #define S5PV210_UPHYPWR_PHY1_SUSPEND BIT(6)
  26. #define S5PV210_UPHYPWR_PHY1_PWR BIT(7)
  27. #define S5PV210_UPHYPWR_PHY1 ( \
  28. S5PV210_UPHYPWR_PHY1_SUSPEND | \
  29. S5PV210_UPHYPWR_PHY1_PWR)
  30. /* PHY clock control */
  31. #define S5PV210_UPHYCLK 0x4
  32. #define S5PV210_UPHYCLK_PHYFSEL_MASK (0x3 << 0)
  33. #define S5PV210_UPHYCLK_PHYFSEL_48MHZ (0x0 << 0)
  34. #define S5PV210_UPHYCLK_PHYFSEL_24MHZ (0x3 << 0)
  35. #define S5PV210_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
  36. #define S5PV210_UPHYCLK_PHY0_ID_PULLUP BIT(2)
  37. #define S5PV210_UPHYCLK_PHY0_COMMON_ON BIT(4)
  38. #define S5PV210_UPHYCLK_PHY1_COMMON_ON BIT(7)
  39. /* PHY reset control */
  40. #define S5PV210_UPHYRST 0x8
  41. #define S5PV210_URSTCON_PHY0 BIT(0)
  42. #define S5PV210_URSTCON_OTG_HLINK BIT(1)
  43. #define S5PV210_URSTCON_OTG_PHYLINK BIT(2)
  44. #define S5PV210_URSTCON_PHY1_ALL BIT(3)
  45. #define S5PV210_URSTCON_HOST_LINK_ALL BIT(4)
  46. /* Isolation, configured in the power management unit */
  47. #define S5PV210_USB_ISOL_OFFSET 0x680c
  48. #define S5PV210_USB_ISOL_DEVICE BIT(0)
  49. #define S5PV210_USB_ISOL_HOST BIT(1)
  50. enum s5pv210_phy_id {
  51. S5PV210_DEVICE,
  52. S5PV210_HOST,
  53. S5PV210_NUM_PHYS,
  54. };
  55. /*
  56. * s5pv210_rate_to_clk() converts the supplied clock rate to the value that
  57. * can be written to the phy register.
  58. */
  59. static int s5pv210_rate_to_clk(unsigned long rate, u32 *reg)
  60. {
  61. switch (rate) {
  62. case 12 * MHZ:
  63. *reg = S5PV210_UPHYCLK_PHYFSEL_12MHZ;
  64. break;
  65. case 24 * MHZ:
  66. *reg = S5PV210_UPHYCLK_PHYFSEL_24MHZ;
  67. break;
  68. case 48 * MHZ:
  69. *reg = S5PV210_UPHYCLK_PHYFSEL_48MHZ;
  70. break;
  71. default:
  72. return -EINVAL;
  73. }
  74. return 0;
  75. }
  76. static void s5pv210_isol(struct samsung_usb2_phy_instance *inst, bool on)
  77. {
  78. struct samsung_usb2_phy_driver *drv = inst->drv;
  79. u32 mask;
  80. switch (inst->cfg->id) {
  81. case S5PV210_DEVICE:
  82. mask = S5PV210_USB_ISOL_DEVICE;
  83. break;
  84. case S5PV210_HOST:
  85. mask = S5PV210_USB_ISOL_HOST;
  86. break;
  87. default:
  88. return;
  89. };
  90. regmap_update_bits(drv->reg_pmu, S5PV210_USB_ISOL_OFFSET,
  91. mask, on ? 0 : mask);
  92. }
  93. static void s5pv210_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
  94. {
  95. struct samsung_usb2_phy_driver *drv = inst->drv;
  96. u32 rstbits = 0;
  97. u32 phypwr = 0;
  98. u32 rst;
  99. u32 pwr;
  100. switch (inst->cfg->id) {
  101. case S5PV210_DEVICE:
  102. phypwr = S5PV210_UPHYPWR_PHY0;
  103. rstbits = S5PV210_URSTCON_PHY0;
  104. break;
  105. case S5PV210_HOST:
  106. phypwr = S5PV210_UPHYPWR_PHY1;
  107. rstbits = S5PV210_URSTCON_PHY1_ALL |
  108. S5PV210_URSTCON_HOST_LINK_ALL;
  109. break;
  110. };
  111. if (on) {
  112. writel(drv->ref_reg_val, drv->reg_phy + S5PV210_UPHYCLK);
  113. pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
  114. pwr &= ~phypwr;
  115. writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
  116. rst = readl(drv->reg_phy + S5PV210_UPHYRST);
  117. rst |= rstbits;
  118. writel(rst, drv->reg_phy + S5PV210_UPHYRST);
  119. udelay(10);
  120. rst &= ~rstbits;
  121. writel(rst, drv->reg_phy + S5PV210_UPHYRST);
  122. } else {
  123. pwr = readl(drv->reg_phy + S5PV210_UPHYPWR);
  124. pwr |= phypwr;
  125. writel(pwr, drv->reg_phy + S5PV210_UPHYPWR);
  126. }
  127. }
  128. static int s5pv210_power_on(struct samsung_usb2_phy_instance *inst)
  129. {
  130. s5pv210_isol(inst, 0);
  131. s5pv210_phy_pwr(inst, 1);
  132. return 0;
  133. }
  134. static int s5pv210_power_off(struct samsung_usb2_phy_instance *inst)
  135. {
  136. s5pv210_phy_pwr(inst, 0);
  137. s5pv210_isol(inst, 1);
  138. return 0;
  139. }
  140. static const struct samsung_usb2_common_phy s5pv210_phys[S5PV210_NUM_PHYS] = {
  141. [S5PV210_DEVICE] = {
  142. .label = "device",
  143. .id = S5PV210_DEVICE,
  144. .power_on = s5pv210_power_on,
  145. .power_off = s5pv210_power_off,
  146. },
  147. [S5PV210_HOST] = {
  148. .label = "host",
  149. .id = S5PV210_HOST,
  150. .power_on = s5pv210_power_on,
  151. .power_off = s5pv210_power_off,
  152. },
  153. };
  154. const struct samsung_usb2_phy_config s5pv210_usb2_phy_config = {
  155. .num_phys = ARRAY_SIZE(s5pv210_phys),
  156. .phys = s5pv210_phys,
  157. .rate_to_clk = s5pv210_rate_to_clk,
  158. };