pinctrl-palmas.c 33 KB

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  1. /*
  2. * pinctrl-palmas.c -- TI PALMAS series pin control driver.
  3. *
  4. * Copyright (c) 2013, NVIDIA Corporation.
  5. *
  6. * Author: Laxman Dewangan <ldewangan@nvidia.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
  13. * whether express or implied; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
  20. * 02111-1307, USA
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/module.h>
  24. #include <linux/mfd/palmas.h>
  25. #include <linux/of.h>
  26. #include <linux/of_device.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/pinctrl/machine.h>
  29. #include <linux/pinctrl/pinctrl.h>
  30. #include <linux/pinctrl/pinconf-generic.h>
  31. #include <linux/pinctrl/pinconf.h>
  32. #include <linux/pinctrl/pinmux.h>
  33. #include <linux/pm.h>
  34. #include <linux/slab.h>
  35. #include "core.h"
  36. #include "pinconf.h"
  37. #include "pinctrl-utils.h"
  38. #define PALMAS_PIN_GPIO0_ID 0
  39. #define PALMAS_PIN_GPIO1_VBUS_LED1_PWM1 1
  40. #define PALMAS_PIN_GPIO2_REGEN_LED2_PWM2 2
  41. #define PALMAS_PIN_GPIO3_CHRG_DET 3
  42. #define PALMAS_PIN_GPIO4_SYSEN1 4
  43. #define PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL 5
  44. #define PALMAS_PIN_GPIO6_SYSEN2 6
  45. #define PALMAS_PIN_GPIO7_MSECURE_PWRHOLD 7
  46. #define PALMAS_PIN_GPIO8_SIM1RSTI 8
  47. #define PALMAS_PIN_GPIO9_LOW_VBAT 9
  48. #define PALMAS_PIN_GPIO10_WIRELESS_CHRG1 10
  49. #define PALMAS_PIN_GPIO11_RCM 11
  50. #define PALMAS_PIN_GPIO12_SIM2RSTO 12
  51. #define PALMAS_PIN_GPIO13 13
  52. #define PALMAS_PIN_GPIO14 14
  53. #define PALMAS_PIN_GPIO15_SIM2RSTI 15
  54. #define PALMAS_PIN_VAC 16
  55. #define PALMAS_PIN_POWERGOOD_USB_PSEL 17
  56. #define PALMAS_PIN_NRESWARM 18
  57. #define PALMAS_PIN_PWRDOWN 19
  58. #define PALMAS_PIN_GPADC_START 20
  59. #define PALMAS_PIN_RESET_IN 21
  60. #define PALMAS_PIN_NSLEEP 22
  61. #define PALMAS_PIN_ENABLE1 23
  62. #define PALMAS_PIN_ENABLE2 24
  63. #define PALMAS_PIN_INT 25
  64. #define PALMAS_PIN_NUM (PALMAS_PIN_INT + 1)
  65. struct palmas_pin_function {
  66. const char *name;
  67. const char * const *groups;
  68. unsigned ngroups;
  69. };
  70. struct palmas_pctrl_chip_info {
  71. struct device *dev;
  72. struct pinctrl_dev *pctl;
  73. struct palmas *palmas;
  74. int pins_current_opt[PALMAS_PIN_NUM];
  75. const struct palmas_pin_function *functions;
  76. unsigned num_functions;
  77. const struct palmas_pingroup *pin_groups;
  78. int num_pin_groups;
  79. const struct pinctrl_pin_desc *pins;
  80. unsigned num_pins;
  81. };
  82. static const struct pinctrl_pin_desc palmas_pins_desc[] = {
  83. PINCTRL_PIN(PALMAS_PIN_GPIO0_ID, "gpio0"),
  84. PINCTRL_PIN(PALMAS_PIN_GPIO1_VBUS_LED1_PWM1, "gpio1"),
  85. PINCTRL_PIN(PALMAS_PIN_GPIO2_REGEN_LED2_PWM2, "gpio2"),
  86. PINCTRL_PIN(PALMAS_PIN_GPIO3_CHRG_DET, "gpio3"),
  87. PINCTRL_PIN(PALMAS_PIN_GPIO4_SYSEN1, "gpio4"),
  88. PINCTRL_PIN(PALMAS_PIN_GPIO5_CLK32KGAUDIO_USB_PSEL, "gpio5"),
  89. PINCTRL_PIN(PALMAS_PIN_GPIO6_SYSEN2, "gpio6"),
  90. PINCTRL_PIN(PALMAS_PIN_GPIO7_MSECURE_PWRHOLD, "gpio7"),
  91. PINCTRL_PIN(PALMAS_PIN_GPIO8_SIM1RSTI, "gpio8"),
  92. PINCTRL_PIN(PALMAS_PIN_GPIO9_LOW_VBAT, "gpio9"),
  93. PINCTRL_PIN(PALMAS_PIN_GPIO10_WIRELESS_CHRG1, "gpio10"),
  94. PINCTRL_PIN(PALMAS_PIN_GPIO11_RCM, "gpio11"),
  95. PINCTRL_PIN(PALMAS_PIN_GPIO12_SIM2RSTO, "gpio12"),
  96. PINCTRL_PIN(PALMAS_PIN_GPIO13, "gpio13"),
  97. PINCTRL_PIN(PALMAS_PIN_GPIO14, "gpio14"),
  98. PINCTRL_PIN(PALMAS_PIN_GPIO15_SIM2RSTI, "gpio15"),
  99. PINCTRL_PIN(PALMAS_PIN_VAC, "vac"),
  100. PINCTRL_PIN(PALMAS_PIN_POWERGOOD_USB_PSEL, "powergood"),
  101. PINCTRL_PIN(PALMAS_PIN_NRESWARM, "nreswarm"),
  102. PINCTRL_PIN(PALMAS_PIN_PWRDOWN, "pwrdown"),
  103. PINCTRL_PIN(PALMAS_PIN_GPADC_START, "gpadc_start"),
  104. PINCTRL_PIN(PALMAS_PIN_RESET_IN, "reset_in"),
  105. PINCTRL_PIN(PALMAS_PIN_NSLEEP, "nsleep"),
  106. PINCTRL_PIN(PALMAS_PIN_ENABLE1, "enable1"),
  107. PINCTRL_PIN(PALMAS_PIN_ENABLE2, "enable2"),
  108. PINCTRL_PIN(PALMAS_PIN_INT, "int"),
  109. };
  110. static const char * const opt0_groups[] = {
  111. "gpio0",
  112. "gpio1",
  113. "gpio2",
  114. "gpio3",
  115. "gpio4",
  116. "gpio5",
  117. "gpio6",
  118. "gpio7",
  119. "gpio8",
  120. "gpio9",
  121. "gpio10",
  122. "gpio11",
  123. "gpio12",
  124. "gpio13",
  125. "gpio14",
  126. "gpio15",
  127. "vac",
  128. "powergood",
  129. "nreswarm",
  130. "pwrdown",
  131. "gpadc_start",
  132. "reset_in",
  133. "nsleep",
  134. "enable1",
  135. "enable2",
  136. "int",
  137. };
  138. static const char * const opt1_groups[] = {
  139. "gpio0",
  140. "gpio1",
  141. "gpio2",
  142. "gpio3",
  143. "gpio4",
  144. "gpio5",
  145. "gpio6",
  146. "gpio7",
  147. "gpio8",
  148. "gpio9",
  149. "gpio10",
  150. "gpio11",
  151. "gpio12",
  152. "gpio15",
  153. "vac",
  154. "powergood",
  155. };
  156. static const char * const opt2_groups[] = {
  157. "gpio1",
  158. "gpio2",
  159. "gpio5",
  160. "gpio7",
  161. };
  162. static const char * const opt3_groups[] = {
  163. "gpio1",
  164. "gpio2",
  165. };
  166. static const char * const gpio_groups[] = {
  167. "gpio0",
  168. "gpio1",
  169. "gpio2",
  170. "gpio3",
  171. "gpio4",
  172. "gpio5",
  173. "gpio6",
  174. "gpio7",
  175. "gpio8",
  176. "gpio9",
  177. "gpio10",
  178. "gpio11",
  179. "gpio12",
  180. "gpio13",
  181. "gpio14",
  182. "gpio15",
  183. };
  184. static const char * const led_groups[] = {
  185. "gpio1",
  186. "gpio2",
  187. };
  188. static const char * const pwm_groups[] = {
  189. "gpio1",
  190. "gpio2",
  191. };
  192. static const char * const regen_groups[] = {
  193. "gpio2",
  194. };
  195. static const char * const sysen_groups[] = {
  196. "gpio4",
  197. "gpio6",
  198. };
  199. static const char * const clk32kgaudio_groups[] = {
  200. "gpio5",
  201. };
  202. static const char * const id_groups[] = {
  203. "gpio0",
  204. };
  205. static const char * const vbus_det_groups[] = {
  206. "gpio1",
  207. };
  208. static const char * const chrg_det_groups[] = {
  209. "gpio3",
  210. };
  211. static const char * const vac_groups[] = {
  212. "vac",
  213. };
  214. static const char * const vacok_groups[] = {
  215. "vac",
  216. };
  217. static const char * const powergood_groups[] = {
  218. "powergood",
  219. };
  220. static const char * const usb_psel_groups[] = {
  221. "gpio5",
  222. "powergood",
  223. };
  224. static const char * const msecure_groups[] = {
  225. "gpio7",
  226. };
  227. static const char * const pwrhold_groups[] = {
  228. "gpio7",
  229. };
  230. static const char * const int_groups[] = {
  231. "int",
  232. };
  233. static const char * const nreswarm_groups[] = {
  234. "nreswarm",
  235. };
  236. static const char * const simrsto_groups[] = {
  237. "gpio12",
  238. };
  239. static const char * const simrsti_groups[] = {
  240. "gpio8",
  241. "gpio15",
  242. };
  243. static const char * const low_vbat_groups[] = {
  244. "gpio9",
  245. };
  246. static const char * const wireless_chrg1_groups[] = {
  247. "gpio10",
  248. };
  249. static const char * const rcm_groups[] = {
  250. "gpio11",
  251. };
  252. static const char * const pwrdown_groups[] = {
  253. "pwrdown",
  254. };
  255. static const char * const gpadc_start_groups[] = {
  256. "gpadc_start",
  257. };
  258. static const char * const reset_in_groups[] = {
  259. "reset_in",
  260. };
  261. static const char * const nsleep_groups[] = {
  262. "nsleep",
  263. };
  264. static const char * const enable_groups[] = {
  265. "enable1",
  266. "enable2",
  267. };
  268. #define FUNCTION_GROUPS \
  269. FUNCTION_GROUP(opt0, OPTION0), \
  270. FUNCTION_GROUP(opt1, OPTION1), \
  271. FUNCTION_GROUP(opt2, OPTION2), \
  272. FUNCTION_GROUP(opt3, OPTION3), \
  273. FUNCTION_GROUP(gpio, GPIO), \
  274. FUNCTION_GROUP(led, LED), \
  275. FUNCTION_GROUP(pwm, PWM), \
  276. FUNCTION_GROUP(regen, REGEN), \
  277. FUNCTION_GROUP(sysen, SYSEN), \
  278. FUNCTION_GROUP(clk32kgaudio, CLK32KGAUDIO), \
  279. FUNCTION_GROUP(id, ID), \
  280. FUNCTION_GROUP(vbus_det, VBUS_DET), \
  281. FUNCTION_GROUP(chrg_det, CHRG_DET), \
  282. FUNCTION_GROUP(vac, VAC), \
  283. FUNCTION_GROUP(vacok, VACOK), \
  284. FUNCTION_GROUP(powergood, POWERGOOD), \
  285. FUNCTION_GROUP(usb_psel, USB_PSEL), \
  286. FUNCTION_GROUP(msecure, MSECURE), \
  287. FUNCTION_GROUP(pwrhold, PWRHOLD), \
  288. FUNCTION_GROUP(int, INT), \
  289. FUNCTION_GROUP(nreswarm, NRESWARM), \
  290. FUNCTION_GROUP(simrsto, SIMRSTO), \
  291. FUNCTION_GROUP(simrsti, SIMRSTI), \
  292. FUNCTION_GROUP(low_vbat, LOW_VBAT), \
  293. FUNCTION_GROUP(wireless_chrg1, WIRELESS_CHRG1), \
  294. FUNCTION_GROUP(rcm, RCM), \
  295. FUNCTION_GROUP(pwrdown, PWRDOWN), \
  296. FUNCTION_GROUP(gpadc_start, GPADC_START), \
  297. FUNCTION_GROUP(reset_in, RESET_IN), \
  298. FUNCTION_GROUP(nsleep, NSLEEP), \
  299. FUNCTION_GROUP(enable, ENABLE)
  300. static const struct palmas_pin_function palmas_pin_function[] = {
  301. #undef FUNCTION_GROUP
  302. #define FUNCTION_GROUP(fname, mux) \
  303. { \
  304. .name = #fname, \
  305. .groups = fname##_groups, \
  306. .ngroups = ARRAY_SIZE(fname##_groups), \
  307. }
  308. FUNCTION_GROUPS,
  309. };
  310. enum palmas_pinmux {
  311. #undef FUNCTION_GROUP
  312. #define FUNCTION_GROUP(fname, mux) PALMAS_PINMUX_##mux
  313. FUNCTION_GROUPS,
  314. PALMAS_PINMUX_NA = 0xFFFF,
  315. };
  316. struct palmas_pins_pullup_dn_info {
  317. int pullup_dn_reg_base;
  318. int pullup_dn_reg_add;
  319. int pullup_dn_mask;
  320. int normal_val;
  321. int pull_up_val;
  322. int pull_dn_val;
  323. };
  324. struct palmas_pins_od_info {
  325. int od_reg_base;
  326. int od_reg_add;
  327. int od_mask;
  328. int od_enable;
  329. int od_disable;
  330. };
  331. struct palmas_pin_info {
  332. enum palmas_pinmux mux_opt;
  333. const struct palmas_pins_pullup_dn_info *pud_info;
  334. const struct palmas_pins_od_info *od_info;
  335. };
  336. struct palmas_pingroup {
  337. const char *name;
  338. const unsigned pins[1];
  339. unsigned npins;
  340. unsigned mux_reg_base;
  341. unsigned mux_reg_add;
  342. unsigned mux_reg_mask;
  343. unsigned mux_bit_shift;
  344. const struct palmas_pin_info *opt[4];
  345. };
  346. #define PULL_UP_DN(_name, _rbase, _add, _mask, _nv, _uv, _dv) \
  347. static const struct palmas_pins_pullup_dn_info pud_##_name##_info = { \
  348. .pullup_dn_reg_base = PALMAS_##_rbase##_BASE, \
  349. .pullup_dn_reg_add = _add, \
  350. .pullup_dn_mask = _mask, \
  351. .normal_val = _nv, \
  352. .pull_up_val = _uv, \
  353. .pull_dn_val = _dv, \
  354. }
  355. PULL_UP_DN(nreswarm, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x2, 0x0, 0x2, -1);
  356. PULL_UP_DN(pwrdown, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x4, 0x0, -1, 0x4);
  357. PULL_UP_DN(gpadc_start, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x30, 0x0, 0x20, 0x10);
  358. PULL_UP_DN(reset_in, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL1, 0x40, 0x0, -1, 0x40);
  359. PULL_UP_DN(nsleep, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x3, 0x0, 0x2, 0x1);
  360. PULL_UP_DN(enable1, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0xC, 0x0, 0x8, 0x4);
  361. PULL_UP_DN(enable2, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL2, 0x30, 0x0, 0x20, 0x10);
  362. PULL_UP_DN(vacok, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x40, 0x0, -1, 0x40);
  363. PULL_UP_DN(chrg_det, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x10, 0x0, -1, 0x10);
  364. PULL_UP_DN(pwrhold, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x4, 0x0, -1, 0x4);
  365. PULL_UP_DN(msecure, PU_PD_OD, PALMAS_PU_PD_INPUT_CTRL3, 0x1, 0x0, -1, 0x1);
  366. PULL_UP_DN(id, USB_OTG, PALMAS_USB_ID_CTRL_SET, 0x40, 0x0, 0x40, -1);
  367. PULL_UP_DN(gpio0, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x04, 0, -1, 1);
  368. PULL_UP_DN(gpio1, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x0C, 0, 0x8, 0x4);
  369. PULL_UP_DN(gpio2, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x30, 0x0, 0x20, 0x10);
  370. PULL_UP_DN(gpio3, GPIO, PALMAS_PU_PD_GPIO_CTRL1, 0x40, 0x0, -1, 0x40);
  371. PULL_UP_DN(gpio4, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x03, 0x0, 0x2, 0x1);
  372. PULL_UP_DN(gpio5, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x0c, 0x0, 0x8, 0x4);
  373. PULL_UP_DN(gpio6, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x30, 0x0, 0x20, 0x10);
  374. PULL_UP_DN(gpio7, GPIO, PALMAS_PU_PD_GPIO_CTRL2, 0x40, 0x0, -1, 0x40);
  375. PULL_UP_DN(gpio9, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x0C, 0x0, 0x8, 0x4);
  376. PULL_UP_DN(gpio10, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0x30, 0x0, 0x20, 0x10);
  377. PULL_UP_DN(gpio11, GPIO, PALMAS_PU_PD_GPIO_CTRL3, 0xC0, 0x0, 0x80, 0x40);
  378. PULL_UP_DN(gpio13, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x04, 0x0, -1, 0x04);
  379. PULL_UP_DN(gpio14, GPIO, PALMAS_PU_PD_GPIO_CTRL4, 0x30, 0x0, 0x20, 0x10);
  380. #define OD_INFO(_name, _rbase, _add, _mask, _ev, _dv) \
  381. static const struct palmas_pins_od_info od_##_name##_info = { \
  382. .od_reg_base = PALMAS_##_rbase##_BASE, \
  383. .od_reg_add = _add, \
  384. .od_mask = _mask, \
  385. .od_enable = _ev, \
  386. .od_disable = _dv, \
  387. }
  388. OD_INFO(gpio1, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x1, 0x1, 0x0);
  389. OD_INFO(gpio2, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x2, 0x2, 0x0);
  390. OD_INFO(gpio5, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL, 0x20, 0x20, 0x0);
  391. OD_INFO(gpio10, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x04, 0x04, 0x0);
  392. OD_INFO(gpio13, GPIO, PALMAS_OD_OUTPUT_GPIO_CTRL2, 0x20, 0x20, 0x0);
  393. OD_INFO(int, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x8, 0x8, 0x0);
  394. OD_INFO(pwm1, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x20, 0x20, 0x0);
  395. OD_INFO(pwm2, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x80, 0x80, 0x0);
  396. OD_INFO(vbus_det, PU_PD_OD, PALMAS_OD_OUTPUT_CTRL, 0x40, 0x40, 0x0);
  397. #define PIN_INFO(_name, _id, _pud_info, _od_info) \
  398. static const struct palmas_pin_info pin_##_name##_info = { \
  399. .mux_opt = PALMAS_PINMUX_##_id, \
  400. .pud_info = _pud_info, \
  401. .od_info = _od_info \
  402. }
  403. PIN_INFO(gpio0, GPIO, &pud_gpio0_info, NULL);
  404. PIN_INFO(gpio1, GPIO, &pud_gpio1_info, &od_gpio1_info);
  405. PIN_INFO(gpio2, GPIO, &pud_gpio2_info, &od_gpio2_info);
  406. PIN_INFO(gpio3, GPIO, &pud_gpio3_info, NULL);
  407. PIN_INFO(gpio4, GPIO, &pud_gpio4_info, NULL);
  408. PIN_INFO(gpio5, GPIO, &pud_gpio5_info, &od_gpio5_info);
  409. PIN_INFO(gpio6, GPIO, &pud_gpio6_info, NULL);
  410. PIN_INFO(gpio7, GPIO, &pud_gpio7_info, NULL);
  411. PIN_INFO(gpio8, GPIO, NULL, NULL);
  412. PIN_INFO(gpio9, GPIO, &pud_gpio9_info, NULL);
  413. PIN_INFO(gpio10, GPIO, &pud_gpio10_info, &od_gpio10_info);
  414. PIN_INFO(gpio11, GPIO, &pud_gpio11_info, NULL);
  415. PIN_INFO(gpio12, GPIO, NULL, NULL);
  416. PIN_INFO(gpio13, GPIO, &pud_gpio13_info, &od_gpio13_info);
  417. PIN_INFO(gpio14, GPIO, &pud_gpio14_info, NULL);
  418. PIN_INFO(gpio15, GPIO, NULL, NULL);
  419. PIN_INFO(id, ID, &pud_id_info, NULL);
  420. PIN_INFO(led1, LED, NULL, NULL);
  421. PIN_INFO(led2, LED, NULL, NULL);
  422. PIN_INFO(regen, REGEN, NULL, NULL);
  423. PIN_INFO(sysen1, SYSEN, NULL, NULL);
  424. PIN_INFO(sysen2, SYSEN, NULL, NULL);
  425. PIN_INFO(int, INT, NULL, &od_int_info);
  426. PIN_INFO(pwm1, PWM, NULL, &od_pwm1_info);
  427. PIN_INFO(pwm2, PWM, NULL, &od_pwm2_info);
  428. PIN_INFO(vacok, VACOK, &pud_vacok_info, NULL);
  429. PIN_INFO(chrg_det, CHRG_DET, &pud_chrg_det_info, NULL);
  430. PIN_INFO(pwrhold, PWRHOLD, &pud_pwrhold_info, NULL);
  431. PIN_INFO(msecure, MSECURE, &pud_msecure_info, NULL);
  432. PIN_INFO(nreswarm, NA, &pud_nreswarm_info, NULL);
  433. PIN_INFO(pwrdown, NA, &pud_pwrdown_info, NULL);
  434. PIN_INFO(gpadc_start, NA, &pud_gpadc_start_info, NULL);
  435. PIN_INFO(reset_in, NA, &pud_reset_in_info, NULL);
  436. PIN_INFO(nsleep, NA, &pud_nsleep_info, NULL);
  437. PIN_INFO(enable1, NA, &pud_enable1_info, NULL);
  438. PIN_INFO(enable2, NA, &pud_enable2_info, NULL);
  439. PIN_INFO(clk32kgaudio, CLK32KGAUDIO, NULL, NULL);
  440. PIN_INFO(usb_psel, USB_PSEL, NULL, NULL);
  441. PIN_INFO(vac, VAC, NULL, NULL);
  442. PIN_INFO(powergood, POWERGOOD, NULL, NULL);
  443. PIN_INFO(vbus_det, VBUS_DET, NULL, &od_vbus_det_info);
  444. PIN_INFO(sim1rsti, SIMRSTI, NULL, NULL);
  445. PIN_INFO(low_vbat, LOW_VBAT, NULL, NULL);
  446. PIN_INFO(rcm, RCM, NULL, NULL);
  447. PIN_INFO(sim2rsto, SIMRSTO, NULL, NULL);
  448. PIN_INFO(sim2rsti, SIMRSTI, NULL, NULL);
  449. PIN_INFO(wireless_chrg1, WIRELESS_CHRG1, NULL, NULL);
  450. #define PALMAS_PRIMARY_SECONDARY_NONE 0
  451. #define PALMAS_NONE_BASE 0
  452. #define PALMAS_PRIMARY_SECONDARY_INPUT3 PALMAS_PU_PD_INPUT_CTRL3
  453. #define PALMAS_PINGROUP(pg_name, pin_id, base, reg, _mask, _bshift, o0, o1, o2, o3) \
  454. { \
  455. .name = #pg_name, \
  456. .pins = {PALMAS_PIN_##pin_id}, \
  457. .npins = 1, \
  458. .mux_reg_base = PALMAS_##base##_BASE, \
  459. .mux_reg_add = PALMAS_PRIMARY_SECONDARY_##reg, \
  460. .mux_reg_mask = _mask, \
  461. .mux_bit_shift = _bshift, \
  462. .opt = { \
  463. o0, \
  464. o1, \
  465. o2, \
  466. o3, \
  467. }, \
  468. }
  469. static const struct palmas_pingroup tps65913_pingroups[] = {
  470. PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
  471. PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
  472. PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
  473. PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
  474. PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
  475. PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
  476. PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
  477. PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
  478. PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
  479. PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
  480. PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
  481. PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
  482. PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
  483. PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
  484. PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
  485. PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
  486. PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
  487. PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
  488. };
  489. static const struct palmas_pingroup tps80036_pingroups[] = {
  490. PALMAS_PINGROUP(gpio0, GPIO0_ID, PU_PD_OD, PAD1, 0x4, 0x2, &pin_gpio0_info, &pin_id_info, NULL, NULL),
  491. PALMAS_PINGROUP(gpio1, GPIO1_VBUS_LED1_PWM1, PU_PD_OD, PAD1, 0x18, 0x3, &pin_gpio1_info, &pin_vbus_det_info, &pin_led1_info, &pin_pwm1_info),
  492. PALMAS_PINGROUP(gpio2, GPIO2_REGEN_LED2_PWM2, PU_PD_OD, PAD1, 0x60, 0x5, &pin_gpio2_info, &pin_regen_info, &pin_led2_info, &pin_pwm2_info),
  493. PALMAS_PINGROUP(gpio3, GPIO3_CHRG_DET, PU_PD_OD, PAD1, 0x80, 0x7, &pin_gpio3_info, &pin_chrg_det_info, NULL, NULL),
  494. PALMAS_PINGROUP(gpio4, GPIO4_SYSEN1, PU_PD_OD, PAD1, 0x01, 0x0, &pin_gpio4_info, &pin_sysen1_info, NULL, NULL),
  495. PALMAS_PINGROUP(gpio5, GPIO5_CLK32KGAUDIO_USB_PSEL, PU_PD_OD, PAD2, 0x6, 0x1, &pin_gpio5_info, &pin_clk32kgaudio_info, &pin_usb_psel_info, NULL),
  496. PALMAS_PINGROUP(gpio6, GPIO6_SYSEN2, PU_PD_OD, PAD2, 0x08, 0x3, &pin_gpio6_info, &pin_sysen2_info, NULL, NULL),
  497. PALMAS_PINGROUP(gpio7, GPIO7_MSECURE_PWRHOLD, PU_PD_OD, PAD2, 0x30, 0x4, &pin_gpio7_info, &pin_msecure_info, &pin_pwrhold_info, NULL),
  498. PALMAS_PINGROUP(gpio8, GPIO8_SIM1RSTI, PU_PD_OD, PAD4, 0x01, 0x0, &pin_gpio8_info, &pin_sim1rsti_info, NULL, NULL),
  499. PALMAS_PINGROUP(gpio9, GPIO9_LOW_VBAT, PU_PD_OD, PAD4, 0x02, 0x1, &pin_gpio9_info, &pin_low_vbat_info, NULL, NULL),
  500. PALMAS_PINGROUP(gpio10, GPIO10_WIRELESS_CHRG1, PU_PD_OD, PAD4, 0x04, 0x2, &pin_gpio10_info, &pin_wireless_chrg1_info, NULL, NULL),
  501. PALMAS_PINGROUP(gpio11, GPIO11_RCM, PU_PD_OD, PAD4, 0x08, 0x3, &pin_gpio11_info, &pin_rcm_info, NULL, NULL),
  502. PALMAS_PINGROUP(gpio12, GPIO12_SIM2RSTO, PU_PD_OD, PAD4, 0x10, 0x4, &pin_gpio12_info, &pin_sim2rsto_info, NULL, NULL),
  503. PALMAS_PINGROUP(gpio13, GPIO13, NONE, NONE, 0x00, 0x0, &pin_gpio13_info, NULL, NULL, NULL),
  504. PALMAS_PINGROUP(gpio14, GPIO14, NONE, NONE, 0x00, 0x0, &pin_gpio14_info, NULL, NULL, NULL),
  505. PALMAS_PINGROUP(gpio15, GPIO15_SIM2RSTI, PU_PD_OD, PAD4, 0x80, 0x7, &pin_gpio15_info, &pin_sim2rsti_info, NULL, NULL),
  506. PALMAS_PINGROUP(vac, VAC, PU_PD_OD, PAD1, 0x02, 0x1, &pin_vac_info, &pin_vacok_info, NULL, NULL),
  507. PALMAS_PINGROUP(powergood, POWERGOOD_USB_PSEL, PU_PD_OD, PAD1, 0x01, 0x0, &pin_powergood_info, &pin_usb_psel_info, NULL, NULL),
  508. PALMAS_PINGROUP(nreswarm, NRESWARM, NONE, NONE, 0x0, 0x0, &pin_nreswarm_info, NULL, NULL, NULL),
  509. PALMAS_PINGROUP(pwrdown, PWRDOWN, NONE, NONE, 0x0, 0x0, &pin_pwrdown_info, NULL, NULL, NULL),
  510. PALMAS_PINGROUP(gpadc_start, GPADC_START, NONE, NONE, 0x0, 0x0, &pin_gpadc_start_info, NULL, NULL, NULL),
  511. PALMAS_PINGROUP(reset_in, RESET_IN, NONE, NONE, 0x0, 0x0, &pin_reset_in_info, NULL, NULL, NULL),
  512. PALMAS_PINGROUP(nsleep, NSLEEP, NONE, NONE, 0x0, 0x0, &pin_nsleep_info, NULL, NULL, NULL),
  513. PALMAS_PINGROUP(enable1, ENABLE1, NONE, NONE, 0x0, 0x0, &pin_enable1_info, NULL, NULL, NULL),
  514. PALMAS_PINGROUP(enable2, ENABLE2, NONE, NONE, 0x0, 0x0, &pin_enable2_info, NULL, NULL, NULL),
  515. PALMAS_PINGROUP(int, INT, NONE, NONE, 0x0, 0x0, &pin_int_info, NULL, NULL, NULL),
  516. };
  517. static int palmas_pinctrl_get_pin_mux(struct palmas_pctrl_chip_info *pci)
  518. {
  519. const struct palmas_pingroup *g;
  520. unsigned int val;
  521. int ret;
  522. int i;
  523. for (i = 0; i < pci->num_pin_groups; ++i) {
  524. g = &pci->pin_groups[i];
  525. if (g->mux_reg_base == PALMAS_NONE_BASE) {
  526. pci->pins_current_opt[i] = 0;
  527. continue;
  528. }
  529. ret = palmas_read(pci->palmas, g->mux_reg_base,
  530. g->mux_reg_add, &val);
  531. if (ret < 0) {
  532. dev_err(pci->dev, "mux_reg 0x%02x read failed: %d\n",
  533. g->mux_reg_add, ret);
  534. return ret;
  535. }
  536. val &= g->mux_reg_mask;
  537. pci->pins_current_opt[i] = val >> g->mux_bit_shift;
  538. }
  539. return 0;
  540. }
  541. static int palmas_pinctrl_set_dvfs1(struct palmas_pctrl_chip_info *pci,
  542. bool enable)
  543. {
  544. int ret;
  545. int val;
  546. val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 : 0;
  547. ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
  548. PALMAS_PRIMARY_SECONDARY_PAD3,
  549. PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1, val);
  550. if (ret < 0)
  551. dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
  552. return ret;
  553. }
  554. static int palmas_pinctrl_set_dvfs2(struct palmas_pctrl_chip_info *pci,
  555. bool enable)
  556. {
  557. int ret;
  558. int val;
  559. val = enable ? PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 : 0;
  560. ret = palmas_update_bits(pci->palmas, PALMAS_PU_PD_OD_BASE,
  561. PALMAS_PRIMARY_SECONDARY_PAD3,
  562. PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2, val);
  563. if (ret < 0)
  564. dev_err(pci->dev, "SECONDARY_PAD3 update failed %d\n", ret);
  565. return ret;
  566. }
  567. static int palmas_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
  568. {
  569. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  570. return pci->num_pin_groups;
  571. }
  572. static const char *palmas_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
  573. unsigned group)
  574. {
  575. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  576. return pci->pin_groups[group].name;
  577. }
  578. static int palmas_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
  579. unsigned group, const unsigned **pins, unsigned *num_pins)
  580. {
  581. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  582. *pins = pci->pin_groups[group].pins;
  583. *num_pins = pci->pin_groups[group].npins;
  584. return 0;
  585. }
  586. static const struct pinctrl_ops palmas_pinctrl_ops = {
  587. .get_groups_count = palmas_pinctrl_get_groups_count,
  588. .get_group_name = palmas_pinctrl_get_group_name,
  589. .get_group_pins = palmas_pinctrl_get_group_pins,
  590. .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
  591. .dt_free_map = pinctrl_utils_dt_free_map,
  592. };
  593. static int palmas_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
  594. {
  595. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  596. return pci->num_functions;
  597. }
  598. static const char *palmas_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
  599. unsigned function)
  600. {
  601. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  602. return pci->functions[function].name;
  603. }
  604. static int palmas_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
  605. unsigned function, const char * const **groups,
  606. unsigned * const num_groups)
  607. {
  608. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  609. *groups = pci->functions[function].groups;
  610. *num_groups = pci->functions[function].ngroups;
  611. return 0;
  612. }
  613. static int palmas_pinctrl_set_mux(struct pinctrl_dev *pctldev,
  614. unsigned function,
  615. unsigned group)
  616. {
  617. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  618. const struct palmas_pingroup *g;
  619. int i;
  620. int ret;
  621. g = &pci->pin_groups[group];
  622. /* If direct option is provided here */
  623. if (function <= PALMAS_PINMUX_OPTION3) {
  624. if (!g->opt[function]) {
  625. dev_err(pci->dev, "Pin %s does not support option %d\n",
  626. g->name, function);
  627. return -EINVAL;
  628. }
  629. i = function;
  630. } else {
  631. for (i = 0; i < ARRAY_SIZE(g->opt); i++) {
  632. if (!g->opt[i])
  633. continue;
  634. if (g->opt[i]->mux_opt == function)
  635. break;
  636. }
  637. if (WARN_ON(i == ARRAY_SIZE(g->opt))) {
  638. dev_err(pci->dev, "Pin %s does not support option %d\n",
  639. g->name, function);
  640. return -EINVAL;
  641. }
  642. }
  643. if (g->mux_reg_base == PALMAS_NONE_BASE) {
  644. if (WARN_ON(i != 0))
  645. return -EINVAL;
  646. return 0;
  647. }
  648. dev_dbg(pci->dev, "%s(): Base0x%02x:0x%02x:0x%02x:0x%02x\n",
  649. __func__, g->mux_reg_base, g->mux_reg_add,
  650. g->mux_reg_mask, i << g->mux_bit_shift);
  651. ret = palmas_update_bits(pci->palmas, g->mux_reg_base, g->mux_reg_add,
  652. g->mux_reg_mask, i << g->mux_bit_shift);
  653. if (ret < 0) {
  654. dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
  655. g->mux_reg_add, ret);
  656. return ret;
  657. }
  658. pci->pins_current_opt[group] = i;
  659. return 0;
  660. }
  661. static const struct pinmux_ops palmas_pinmux_ops = {
  662. .get_functions_count = palmas_pinctrl_get_funcs_count,
  663. .get_function_name = palmas_pinctrl_get_func_name,
  664. .get_function_groups = palmas_pinctrl_get_func_groups,
  665. .set_mux = palmas_pinctrl_set_mux,
  666. };
  667. static int palmas_pinconf_get(struct pinctrl_dev *pctldev,
  668. unsigned pin, unsigned long *config)
  669. {
  670. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  671. enum pin_config_param param = pinconf_to_config_param(*config);
  672. const struct palmas_pingroup *g;
  673. const struct palmas_pin_info *opt;
  674. unsigned int val;
  675. int ret;
  676. int base, add;
  677. int rval;
  678. int arg;
  679. int group_nr;
  680. for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
  681. if (pci->pin_groups[group_nr].pins[0] == pin)
  682. break;
  683. }
  684. if (group_nr == pci->num_pin_groups) {
  685. dev_err(pci->dev,
  686. "Pinconf is not supported for pin-id %d\n", pin);
  687. return -ENOTSUPP;
  688. }
  689. g = &pci->pin_groups[group_nr];
  690. opt = g->opt[pci->pins_current_opt[group_nr]];
  691. if (!opt) {
  692. dev_err(pci->dev,
  693. "Pinconf is not supported for pin %s\n", g->name);
  694. return -ENOTSUPP;
  695. }
  696. switch (param) {
  697. case PIN_CONFIG_BIAS_DISABLE:
  698. case PIN_CONFIG_BIAS_PULL_UP:
  699. case PIN_CONFIG_BIAS_PULL_DOWN:
  700. if (!opt->pud_info) {
  701. dev_err(pci->dev,
  702. "PULL control not supported for pin %s\n",
  703. g->name);
  704. return -ENOTSUPP;
  705. }
  706. base = opt->pud_info->pullup_dn_reg_base;
  707. add = opt->pud_info->pullup_dn_reg_add;
  708. ret = palmas_read(pci->palmas, base, add, &val);
  709. if (ret < 0) {
  710. dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
  711. add, ret);
  712. return ret;
  713. }
  714. rval = val & opt->pud_info->pullup_dn_mask;
  715. arg = 0;
  716. if ((opt->pud_info->normal_val >= 0) &&
  717. (opt->pud_info->normal_val == rval) &&
  718. (param == PIN_CONFIG_BIAS_DISABLE))
  719. arg = 1;
  720. else if ((opt->pud_info->pull_up_val >= 0) &&
  721. (opt->pud_info->pull_up_val == rval) &&
  722. (param == PIN_CONFIG_BIAS_PULL_UP))
  723. arg = 1;
  724. else if ((opt->pud_info->pull_dn_val >= 0) &&
  725. (opt->pud_info->pull_dn_val == rval) &&
  726. (param == PIN_CONFIG_BIAS_PULL_DOWN))
  727. arg = 1;
  728. break;
  729. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  730. if (!opt->od_info) {
  731. dev_err(pci->dev,
  732. "OD control not supported for pin %s\n",
  733. g->name);
  734. return -ENOTSUPP;
  735. }
  736. base = opt->od_info->od_reg_base;
  737. add = opt->od_info->od_reg_add;
  738. ret = palmas_read(pci->palmas, base, add, &val);
  739. if (ret < 0) {
  740. dev_err(pci->dev, "Reg 0x%02x read failed: %d\n",
  741. add, ret);
  742. return ret;
  743. }
  744. rval = val & opt->od_info->od_mask;
  745. arg = -1;
  746. if ((opt->od_info->od_disable >= 0) &&
  747. (opt->od_info->od_disable == rval))
  748. arg = 0;
  749. else if ((opt->od_info->od_enable >= 0) &&
  750. (opt->od_info->od_enable == rval))
  751. arg = 1;
  752. if (arg < 0) {
  753. dev_err(pci->dev,
  754. "OD control not supported for pin %s\n",
  755. g->name);
  756. return -ENOTSUPP;
  757. }
  758. break;
  759. default:
  760. dev_err(pci->dev, "Properties not supported\n");
  761. return -ENOTSUPP;
  762. }
  763. *config = pinconf_to_config_packed(param, (u16)arg);
  764. return 0;
  765. }
  766. static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
  767. unsigned pin, unsigned long *configs,
  768. unsigned num_configs)
  769. {
  770. struct palmas_pctrl_chip_info *pci = pinctrl_dev_get_drvdata(pctldev);
  771. enum pin_config_param param;
  772. u16 param_val;
  773. const struct palmas_pingroup *g;
  774. const struct palmas_pin_info *opt;
  775. int ret;
  776. int base, add, mask;
  777. int rval;
  778. int group_nr;
  779. int i;
  780. for (group_nr = 0; group_nr < pci->num_pin_groups; ++group_nr) {
  781. if (pci->pin_groups[group_nr].pins[0] == pin)
  782. break;
  783. }
  784. if (group_nr == pci->num_pin_groups) {
  785. dev_err(pci->dev,
  786. "Pinconf is not supported for pin-id %d\n", pin);
  787. return -ENOTSUPP;
  788. }
  789. g = &pci->pin_groups[group_nr];
  790. opt = g->opt[pci->pins_current_opt[group_nr]];
  791. if (!opt) {
  792. dev_err(pci->dev,
  793. "Pinconf is not supported for pin %s\n", g->name);
  794. return -ENOTSUPP;
  795. }
  796. for (i = 0; i < num_configs; i++) {
  797. param = pinconf_to_config_param(configs[i]);
  798. param_val = pinconf_to_config_argument(configs[i]);
  799. switch (param) {
  800. case PIN_CONFIG_BIAS_DISABLE:
  801. case PIN_CONFIG_BIAS_PULL_UP:
  802. case PIN_CONFIG_BIAS_PULL_DOWN:
  803. if (!opt->pud_info) {
  804. dev_err(pci->dev,
  805. "PULL control not supported for pin %s\n",
  806. g->name);
  807. return -ENOTSUPP;
  808. }
  809. base = opt->pud_info->pullup_dn_reg_base;
  810. add = opt->pud_info->pullup_dn_reg_add;
  811. mask = opt->pud_info->pullup_dn_mask;
  812. if (param == PIN_CONFIG_BIAS_DISABLE)
  813. rval = opt->pud_info->normal_val;
  814. else if (param == PIN_CONFIG_BIAS_PULL_UP)
  815. rval = opt->pud_info->pull_up_val;
  816. else
  817. rval = opt->pud_info->pull_dn_val;
  818. if (rval < 0) {
  819. dev_err(pci->dev,
  820. "PULL control not supported for pin %s\n",
  821. g->name);
  822. return -ENOTSUPP;
  823. }
  824. break;
  825. case PIN_CONFIG_DRIVE_OPEN_DRAIN:
  826. if (!opt->od_info) {
  827. dev_err(pci->dev,
  828. "OD control not supported for pin %s\n",
  829. g->name);
  830. return -ENOTSUPP;
  831. }
  832. base = opt->od_info->od_reg_base;
  833. add = opt->od_info->od_reg_add;
  834. mask = opt->od_info->od_mask;
  835. if (param_val == 0)
  836. rval = opt->od_info->od_disable;
  837. else
  838. rval = opt->od_info->od_enable;
  839. if (rval < 0) {
  840. dev_err(pci->dev,
  841. "OD control not supported for pin %s\n",
  842. g->name);
  843. return -ENOTSUPP;
  844. }
  845. break;
  846. default:
  847. dev_err(pci->dev, "Properties not supported\n");
  848. return -ENOTSUPP;
  849. }
  850. dev_dbg(pci->dev, "%s(): Add0x%02x:0x%02x:0x%02x:0x%02x\n",
  851. __func__, base, add, mask, rval);
  852. ret = palmas_update_bits(pci->palmas, base, add, mask, rval);
  853. if (ret < 0) {
  854. dev_err(pci->dev, "Reg 0x%02x update failed: %d\n",
  855. add, ret);
  856. return ret;
  857. }
  858. } /* for each config */
  859. return 0;
  860. }
  861. static const struct pinconf_ops palmas_pinconf_ops = {
  862. .pin_config_get = palmas_pinconf_get,
  863. .pin_config_set = palmas_pinconf_set,
  864. };
  865. static struct pinctrl_desc palmas_pinctrl_desc = {
  866. .pctlops = &palmas_pinctrl_ops,
  867. .pmxops = &palmas_pinmux_ops,
  868. .confops = &palmas_pinconf_ops,
  869. .owner = THIS_MODULE,
  870. };
  871. struct palmas_pinctrl_data {
  872. const struct palmas_pingroup *pin_groups;
  873. int num_pin_groups;
  874. };
  875. static struct palmas_pinctrl_data tps65913_pinctrl_data = {
  876. .pin_groups = tps65913_pingroups,
  877. .num_pin_groups = ARRAY_SIZE(tps65913_pingroups),
  878. };
  879. static struct palmas_pinctrl_data tps80036_pinctrl_data = {
  880. .pin_groups = tps80036_pingroups,
  881. .num_pin_groups = ARRAY_SIZE(tps80036_pingroups),
  882. };
  883. static const struct of_device_id palmas_pinctrl_of_match[] = {
  884. { .compatible = "ti,palmas-pinctrl", .data = &tps65913_pinctrl_data},
  885. { .compatible = "ti,tps65913-pinctrl", .data = &tps65913_pinctrl_data},
  886. { .compatible = "ti,tps80036-pinctrl", .data = &tps80036_pinctrl_data},
  887. { },
  888. };
  889. MODULE_DEVICE_TABLE(of, palmas_pinctrl_of_match);
  890. static int palmas_pinctrl_probe(struct platform_device *pdev)
  891. {
  892. struct palmas_pctrl_chip_info *pci;
  893. const struct palmas_pinctrl_data *pinctrl_data = &tps65913_pinctrl_data;
  894. int ret;
  895. bool enable_dvfs1 = false;
  896. bool enable_dvfs2 = false;
  897. if (pdev->dev.of_node) {
  898. const struct of_device_id *match;
  899. match = of_match_device(palmas_pinctrl_of_match, &pdev->dev);
  900. pinctrl_data = match->data;
  901. enable_dvfs1 = of_property_read_bool(pdev->dev.of_node,
  902. "ti,palmas-enable-dvfs1");
  903. enable_dvfs2 = of_property_read_bool(pdev->dev.of_node,
  904. "ti,palmas-enable-dvfs2");
  905. }
  906. pci = devm_kzalloc(&pdev->dev, sizeof(*pci), GFP_KERNEL);
  907. if (!pci) {
  908. dev_err(&pdev->dev, "Malloc for pci failed\n");
  909. return -ENOMEM;
  910. }
  911. pci->dev = &pdev->dev;
  912. pci->palmas = dev_get_drvdata(pdev->dev.parent);
  913. pci->pins = palmas_pins_desc;
  914. pci->num_pins = ARRAY_SIZE(palmas_pins_desc);
  915. pci->functions = palmas_pin_function;
  916. pci->num_functions = ARRAY_SIZE(palmas_pin_function);
  917. pci->pin_groups = pinctrl_data->pin_groups;
  918. pci->num_pin_groups = pinctrl_data->num_pin_groups;
  919. platform_set_drvdata(pdev, pci);
  920. palmas_pinctrl_set_dvfs1(pci, enable_dvfs1);
  921. palmas_pinctrl_set_dvfs2(pci, enable_dvfs2);
  922. ret = palmas_pinctrl_get_pin_mux(pci);
  923. if (ret < 0) {
  924. dev_err(&pdev->dev,
  925. "Reading pinctrol option register failed: %d\n", ret);
  926. return ret;
  927. }
  928. palmas_pinctrl_desc.name = dev_name(&pdev->dev);
  929. palmas_pinctrl_desc.pins = palmas_pins_desc;
  930. palmas_pinctrl_desc.npins = ARRAY_SIZE(palmas_pins_desc);
  931. pci->pctl = pinctrl_register(&palmas_pinctrl_desc, &pdev->dev, pci);
  932. if (IS_ERR(pci->pctl)) {
  933. dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
  934. return PTR_ERR(pci->pctl);
  935. }
  936. return 0;
  937. }
  938. static int palmas_pinctrl_remove(struct platform_device *pdev)
  939. {
  940. struct palmas_pctrl_chip_info *pci = platform_get_drvdata(pdev);
  941. pinctrl_unregister(pci->pctl);
  942. return 0;
  943. }
  944. static struct platform_driver palmas_pinctrl_driver = {
  945. .driver = {
  946. .name = "palmas-pinctrl",
  947. .of_match_table = palmas_pinctrl_of_match,
  948. },
  949. .probe = palmas_pinctrl_probe,
  950. .remove = palmas_pinctrl_remove,
  951. };
  952. module_platform_driver(palmas_pinctrl_driver);
  953. MODULE_DESCRIPTION("Palmas pin control driver");
  954. MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
  955. MODULE_ALIAS("platform:palmas-pinctrl");
  956. MODULE_LICENSE("GPL v2");