pinctrl-spmi-mpp.c 24 KB

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  1. /*
  2. * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 and
  6. * only version 2 as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/gpio.h>
  14. #include <linux/module.h>
  15. #include <linux/of.h>
  16. #include <linux/pinctrl/pinconf-generic.h>
  17. #include <linux/pinctrl/pinconf.h>
  18. #include <linux/pinctrl/pinmux.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #include <linux/slab.h>
  22. #include <linux/types.h>
  23. #include <dt-bindings/pinctrl/qcom,pmic-mpp.h>
  24. #include "../core.h"
  25. #include "../pinctrl-utils.h"
  26. #define PMIC_MPP_ADDRESS_RANGE 0x100
  27. /*
  28. * Pull Up Values - it indicates whether a pull-up should be
  29. * applied for bidirectional mode only. The hardware ignores the
  30. * configuration when operating in other modes.
  31. */
  32. #define PMIC_MPP_PULL_UP_0P6KOHM 0
  33. #define PMIC_MPP_PULL_UP_10KOHM 1
  34. #define PMIC_MPP_PULL_UP_30KOHM 2
  35. #define PMIC_MPP_PULL_UP_OPEN 3
  36. /* type registers base address bases */
  37. #define PMIC_MPP_REG_TYPE 0x4
  38. #define PMIC_MPP_REG_SUBTYPE 0x5
  39. /* mpp peripheral type and subtype values */
  40. #define PMIC_MPP_TYPE 0x11
  41. #define PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT 0x3
  42. #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT 0x4
  43. #define PMIC_MPP_SUBTYPE_4CH_NO_SINK 0x5
  44. #define PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK 0x6
  45. #define PMIC_MPP_SUBTYPE_4CH_FULL_FUNC 0x7
  46. #define PMIC_MPP_SUBTYPE_8CH_FULL_FUNC 0xf
  47. #define PMIC_MPP_REG_RT_STS 0x10
  48. #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1
  49. /* control register base address bases */
  50. #define PMIC_MPP_REG_MODE_CTL 0x40
  51. #define PMIC_MPP_REG_DIG_VIN_CTL 0x41
  52. #define PMIC_MPP_REG_DIG_PULL_CTL 0x42
  53. #define PMIC_MPP_REG_DIG_IN_CTL 0x43
  54. #define PMIC_MPP_REG_EN_CTL 0x46
  55. #define PMIC_MPP_REG_AOUT_CTL 0x48
  56. #define PMIC_MPP_REG_AIN_CTL 0x4a
  57. #define PMIC_MPP_REG_SINK_CTL 0x4c
  58. /* PMIC_MPP_REG_MODE_CTL */
  59. #define PMIC_MPP_REG_MODE_VALUE_MASK 0x1
  60. #define PMIC_MPP_REG_MODE_FUNCTION_SHIFT 1
  61. #define PMIC_MPP_REG_MODE_FUNCTION_MASK 0x7
  62. #define PMIC_MPP_REG_MODE_DIR_SHIFT 4
  63. #define PMIC_MPP_REG_MODE_DIR_MASK 0x7
  64. /* PMIC_MPP_REG_DIG_VIN_CTL */
  65. #define PMIC_MPP_REG_VIN_SHIFT 0
  66. #define PMIC_MPP_REG_VIN_MASK 0x7
  67. /* PMIC_MPP_REG_DIG_PULL_CTL */
  68. #define PMIC_MPP_REG_PULL_SHIFT 0
  69. #define PMIC_MPP_REG_PULL_MASK 0x7
  70. /* PMIC_MPP_REG_EN_CTL */
  71. #define PMIC_MPP_REG_MASTER_EN_SHIFT 7
  72. /* PMIC_MPP_REG_AIN_CTL */
  73. #define PMIC_MPP_REG_AIN_ROUTE_SHIFT 0
  74. #define PMIC_MPP_REG_AIN_ROUTE_MASK 0x7
  75. #define PMIC_MPP_MODE_DIGITAL_INPUT 0
  76. #define PMIC_MPP_MODE_DIGITAL_OUTPUT 1
  77. #define PMIC_MPP_MODE_DIGITAL_BIDIR 2
  78. #define PMIC_MPP_MODE_ANALOG_BIDIR 3
  79. #define PMIC_MPP_MODE_ANALOG_INPUT 4
  80. #define PMIC_MPP_MODE_ANALOG_OUTPUT 5
  81. #define PMIC_MPP_MODE_CURRENT_SINK 6
  82. #define PMIC_MPP_SELECTOR_NORMAL 0
  83. #define PMIC_MPP_SELECTOR_PAIRED 1
  84. #define PMIC_MPP_SELECTOR_DTEST_FIRST 4
  85. #define PMIC_MPP_PHYSICAL_OFFSET 1
  86. /* Qualcomm specific pin configurations */
  87. #define PMIC_MPP_CONF_AMUX_ROUTE (PIN_CONFIG_END + 1)
  88. #define PMIC_MPP_CONF_ANALOG_LEVEL (PIN_CONFIG_END + 2)
  89. #define PMIC_MPP_CONF_DTEST_SELECTOR (PIN_CONFIG_END + 3)
  90. #define PMIC_MPP_CONF_PAIRED (PIN_CONFIG_END + 4)
  91. /**
  92. * struct pmic_mpp_pad - keep current MPP settings
  93. * @base: Address base in SPMI device.
  94. * @irq: IRQ number which this MPP generate.
  95. * @is_enabled: Set to false when MPP should be put in high Z state.
  96. * @out_value: Cached pin output value.
  97. * @output_enabled: Set to true if MPP output logic is enabled.
  98. * @input_enabled: Set to true if MPP input buffer logic is enabled.
  99. * @paired: Pin operates in paired mode
  100. * @num_sources: Number of power-sources supported by this MPP.
  101. * @power_source: Current power-source used.
  102. * @amux_input: Set the source for analog input.
  103. * @aout_level: Analog output level
  104. * @pullup: Pullup resistor value. Valid in Bidirectional mode only.
  105. * @function: See pmic_mpp_functions[].
  106. * @drive_strength: Amount of current in sink mode
  107. * @dtest: DTEST route selector
  108. */
  109. struct pmic_mpp_pad {
  110. u16 base;
  111. int irq;
  112. bool is_enabled;
  113. bool out_value;
  114. bool output_enabled;
  115. bool input_enabled;
  116. bool paired;
  117. unsigned int num_sources;
  118. unsigned int power_source;
  119. unsigned int amux_input;
  120. unsigned int aout_level;
  121. unsigned int pullup;
  122. unsigned int function;
  123. unsigned int drive_strength;
  124. unsigned int dtest;
  125. };
  126. struct pmic_mpp_state {
  127. struct device *dev;
  128. struct regmap *map;
  129. struct pinctrl_dev *ctrl;
  130. struct gpio_chip chip;
  131. };
  132. static const struct pinconf_generic_params pmic_mpp_bindings[] = {
  133. {"qcom,amux-route", PMIC_MPP_CONF_AMUX_ROUTE, 0},
  134. {"qcom,analog-level", PMIC_MPP_CONF_ANALOG_LEVEL, 0},
  135. {"qcom,dtest", PMIC_MPP_CONF_DTEST_SELECTOR, 0},
  136. {"qcom,paired", PMIC_MPP_CONF_PAIRED, 0},
  137. };
  138. #ifdef CONFIG_DEBUG_FS
  139. static const struct pin_config_item pmic_conf_items[] = {
  140. PCONFDUMP(PMIC_MPP_CONF_AMUX_ROUTE, "analog mux", NULL, true),
  141. PCONFDUMP(PMIC_MPP_CONF_ANALOG_LEVEL, "analog level", NULL, true),
  142. PCONFDUMP(PMIC_MPP_CONF_DTEST_SELECTOR, "dtest", NULL, true),
  143. PCONFDUMP(PMIC_MPP_CONF_PAIRED, "paired", NULL, false),
  144. };
  145. #endif
  146. static const char *const pmic_mpp_groups[] = {
  147. "mpp1", "mpp2", "mpp3", "mpp4", "mpp5", "mpp6", "mpp7", "mpp8",
  148. };
  149. #define PMIC_MPP_DIGITAL 0
  150. #define PMIC_MPP_ANALOG 1
  151. #define PMIC_MPP_SINK 2
  152. static const char *const pmic_mpp_functions[] = {
  153. "digital", "analog", "sink"
  154. };
  155. static inline struct pmic_mpp_state *to_mpp_state(struct gpio_chip *chip)
  156. {
  157. return container_of(chip, struct pmic_mpp_state, chip);
  158. };
  159. static int pmic_mpp_read(struct pmic_mpp_state *state,
  160. struct pmic_mpp_pad *pad, unsigned int addr)
  161. {
  162. unsigned int val;
  163. int ret;
  164. ret = regmap_read(state->map, pad->base + addr, &val);
  165. if (ret < 0)
  166. dev_err(state->dev, "read 0x%x failed\n", addr);
  167. else
  168. ret = val;
  169. return ret;
  170. }
  171. static int pmic_mpp_write(struct pmic_mpp_state *state,
  172. struct pmic_mpp_pad *pad, unsigned int addr,
  173. unsigned int val)
  174. {
  175. int ret;
  176. ret = regmap_write(state->map, pad->base + addr, val);
  177. if (ret < 0)
  178. dev_err(state->dev, "write 0x%x failed\n", addr);
  179. return ret;
  180. }
  181. static int pmic_mpp_get_groups_count(struct pinctrl_dev *pctldev)
  182. {
  183. /* Every PIN is a group */
  184. return pctldev->desc->npins;
  185. }
  186. static const char *pmic_mpp_get_group_name(struct pinctrl_dev *pctldev,
  187. unsigned pin)
  188. {
  189. return pctldev->desc->pins[pin].name;
  190. }
  191. static int pmic_mpp_get_group_pins(struct pinctrl_dev *pctldev,
  192. unsigned pin,
  193. const unsigned **pins, unsigned *num_pins)
  194. {
  195. *pins = &pctldev->desc->pins[pin].number;
  196. *num_pins = 1;
  197. return 0;
  198. }
  199. static const struct pinctrl_ops pmic_mpp_pinctrl_ops = {
  200. .get_groups_count = pmic_mpp_get_groups_count,
  201. .get_group_name = pmic_mpp_get_group_name,
  202. .get_group_pins = pmic_mpp_get_group_pins,
  203. .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
  204. .dt_free_map = pinctrl_utils_dt_free_map,
  205. };
  206. static int pmic_mpp_get_functions_count(struct pinctrl_dev *pctldev)
  207. {
  208. return ARRAY_SIZE(pmic_mpp_functions);
  209. }
  210. static const char *pmic_mpp_get_function_name(struct pinctrl_dev *pctldev,
  211. unsigned function)
  212. {
  213. return pmic_mpp_functions[function];
  214. }
  215. static int pmic_mpp_get_function_groups(struct pinctrl_dev *pctldev,
  216. unsigned function,
  217. const char *const **groups,
  218. unsigned *const num_qgroups)
  219. {
  220. *groups = pmic_mpp_groups;
  221. *num_qgroups = pctldev->desc->npins;
  222. return 0;
  223. }
  224. static int pmic_mpp_write_mode_ctl(struct pmic_mpp_state *state,
  225. struct pmic_mpp_pad *pad)
  226. {
  227. unsigned int mode;
  228. unsigned int sel;
  229. unsigned int val;
  230. unsigned int en;
  231. switch (pad->function) {
  232. case PMIC_MPP_ANALOG:
  233. if (pad->input_enabled && pad->output_enabled)
  234. mode = PMIC_MPP_MODE_ANALOG_BIDIR;
  235. else if (pad->input_enabled)
  236. mode = PMIC_MPP_MODE_ANALOG_INPUT;
  237. else
  238. mode = PMIC_MPP_MODE_ANALOG_OUTPUT;
  239. break;
  240. case PMIC_MPP_DIGITAL:
  241. if (pad->input_enabled && pad->output_enabled)
  242. mode = PMIC_MPP_MODE_DIGITAL_BIDIR;
  243. else if (pad->input_enabled)
  244. mode = PMIC_MPP_MODE_DIGITAL_INPUT;
  245. else
  246. mode = PMIC_MPP_MODE_DIGITAL_OUTPUT;
  247. break;
  248. case PMIC_MPP_SINK:
  249. default:
  250. mode = PMIC_MPP_MODE_CURRENT_SINK;
  251. break;
  252. }
  253. if (pad->dtest)
  254. sel = PMIC_MPP_SELECTOR_DTEST_FIRST + pad->dtest - 1;
  255. else if (pad->paired)
  256. sel = PMIC_MPP_SELECTOR_PAIRED;
  257. else
  258. sel = PMIC_MPP_SELECTOR_NORMAL;
  259. en = !!pad->out_value;
  260. val = mode << PMIC_MPP_REG_MODE_DIR_SHIFT |
  261. sel << PMIC_MPP_REG_MODE_FUNCTION_SHIFT |
  262. en;
  263. return pmic_mpp_write(state, pad, PMIC_MPP_REG_MODE_CTL, val);
  264. }
  265. static int pmic_mpp_set_mux(struct pinctrl_dev *pctldev, unsigned function,
  266. unsigned pin)
  267. {
  268. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  269. struct pmic_mpp_pad *pad;
  270. unsigned int val;
  271. int ret;
  272. pad = pctldev->desc->pins[pin].drv_data;
  273. pad->function = function;
  274. ret = pmic_mpp_write_mode_ctl(state, pad);
  275. if (ret < 0)
  276. return ret;
  277. val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
  278. return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
  279. }
  280. static const struct pinmux_ops pmic_mpp_pinmux_ops = {
  281. .get_functions_count = pmic_mpp_get_functions_count,
  282. .get_function_name = pmic_mpp_get_function_name,
  283. .get_function_groups = pmic_mpp_get_function_groups,
  284. .set_mux = pmic_mpp_set_mux,
  285. };
  286. static int pmic_mpp_config_get(struct pinctrl_dev *pctldev,
  287. unsigned int pin, unsigned long *config)
  288. {
  289. unsigned param = pinconf_to_config_param(*config);
  290. struct pmic_mpp_pad *pad;
  291. unsigned arg = 0;
  292. pad = pctldev->desc->pins[pin].drv_data;
  293. switch (param) {
  294. case PIN_CONFIG_BIAS_DISABLE:
  295. if (pad->pullup != PMIC_MPP_PULL_UP_OPEN)
  296. return -EINVAL;
  297. arg = 1;
  298. break;
  299. case PIN_CONFIG_BIAS_PULL_UP:
  300. switch (pad->pullup) {
  301. case PMIC_MPP_PULL_UP_0P6KOHM:
  302. arg = 600;
  303. break;
  304. case PMIC_MPP_PULL_UP_10KOHM:
  305. arg = 10000;
  306. break;
  307. case PMIC_MPP_PULL_UP_30KOHM:
  308. arg = 30000;
  309. break;
  310. default:
  311. return -EINVAL;
  312. }
  313. break;
  314. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  315. if (pad->is_enabled)
  316. return -EINVAL;
  317. arg = 1;
  318. break;
  319. case PIN_CONFIG_POWER_SOURCE:
  320. arg = pad->power_source;
  321. break;
  322. case PIN_CONFIG_INPUT_ENABLE:
  323. if (!pad->input_enabled)
  324. return -EINVAL;
  325. arg = 1;
  326. break;
  327. case PIN_CONFIG_OUTPUT:
  328. arg = pad->out_value;
  329. break;
  330. case PMIC_MPP_CONF_DTEST_SELECTOR:
  331. arg = pad->dtest;
  332. break;
  333. case PMIC_MPP_CONF_AMUX_ROUTE:
  334. arg = pad->amux_input;
  335. break;
  336. case PMIC_MPP_CONF_PAIRED:
  337. if (!pad->paired)
  338. return -EINVAL;
  339. arg = 1;
  340. break;
  341. case PIN_CONFIG_DRIVE_STRENGTH:
  342. arg = pad->drive_strength;
  343. break;
  344. case PMIC_MPP_CONF_ANALOG_LEVEL:
  345. arg = pad->aout_level;
  346. break;
  347. default:
  348. return -EINVAL;
  349. }
  350. /* Convert register value to pinconf value */
  351. *config = pinconf_to_config_packed(param, arg);
  352. return 0;
  353. }
  354. static int pmic_mpp_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
  355. unsigned long *configs, unsigned nconfs)
  356. {
  357. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  358. struct pmic_mpp_pad *pad;
  359. unsigned param, arg;
  360. unsigned int val;
  361. int i, ret;
  362. pad = pctldev->desc->pins[pin].drv_data;
  363. /* Make it possible to enable the pin, by not setting high impedance */
  364. pad->is_enabled = true;
  365. for (i = 0; i < nconfs; i++) {
  366. param = pinconf_to_config_param(configs[i]);
  367. arg = pinconf_to_config_argument(configs[i]);
  368. switch (param) {
  369. case PIN_CONFIG_BIAS_DISABLE:
  370. pad->pullup = PMIC_MPP_PULL_UP_OPEN;
  371. break;
  372. case PIN_CONFIG_BIAS_PULL_UP:
  373. switch (arg) {
  374. case 600:
  375. pad->pullup = PMIC_MPP_PULL_UP_0P6KOHM;
  376. break;
  377. case 10000:
  378. pad->pullup = PMIC_MPP_PULL_UP_10KOHM;
  379. break;
  380. case 30000:
  381. pad->pullup = PMIC_MPP_PULL_UP_30KOHM;
  382. break;
  383. default:
  384. return -EINVAL;
  385. }
  386. break;
  387. case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
  388. pad->is_enabled = false;
  389. break;
  390. case PIN_CONFIG_POWER_SOURCE:
  391. if (arg >= pad->num_sources)
  392. return -EINVAL;
  393. pad->power_source = arg;
  394. break;
  395. case PIN_CONFIG_INPUT_ENABLE:
  396. pad->input_enabled = arg ? true : false;
  397. break;
  398. case PIN_CONFIG_OUTPUT:
  399. pad->output_enabled = true;
  400. pad->out_value = arg;
  401. break;
  402. case PMIC_MPP_CONF_DTEST_SELECTOR:
  403. pad->dtest = arg;
  404. break;
  405. case PIN_CONFIG_DRIVE_STRENGTH:
  406. pad->drive_strength = arg;
  407. break;
  408. case PMIC_MPP_CONF_AMUX_ROUTE:
  409. if (arg >= PMIC_MPP_AMUX_ROUTE_ABUS4)
  410. return -EINVAL;
  411. pad->amux_input = arg;
  412. break;
  413. case PMIC_MPP_CONF_ANALOG_LEVEL:
  414. pad->aout_level = arg;
  415. break;
  416. case PMIC_MPP_CONF_PAIRED:
  417. pad->paired = !!arg;
  418. break;
  419. default:
  420. return -EINVAL;
  421. }
  422. }
  423. val = pad->power_source << PMIC_MPP_REG_VIN_SHIFT;
  424. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_VIN_CTL, val);
  425. if (ret < 0)
  426. return ret;
  427. val = pad->pullup << PMIC_MPP_REG_PULL_SHIFT;
  428. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_DIG_PULL_CTL, val);
  429. if (ret < 0)
  430. return ret;
  431. val = pad->amux_input & PMIC_MPP_REG_AIN_ROUTE_MASK;
  432. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AIN_CTL, val);
  433. if (ret < 0)
  434. return ret;
  435. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_AOUT_CTL, pad->aout_level);
  436. if (ret < 0)
  437. return ret;
  438. ret = pmic_mpp_write_mode_ctl(state, pad);
  439. if (ret < 0)
  440. return ret;
  441. ret = pmic_mpp_write(state, pad, PMIC_MPP_REG_SINK_CTL, pad->drive_strength);
  442. if (ret < 0)
  443. return ret;
  444. val = pad->is_enabled << PMIC_MPP_REG_MASTER_EN_SHIFT;
  445. return pmic_mpp_write(state, pad, PMIC_MPP_REG_EN_CTL, val);
  446. }
  447. static void pmic_mpp_config_dbg_show(struct pinctrl_dev *pctldev,
  448. struct seq_file *s, unsigned pin)
  449. {
  450. struct pmic_mpp_state *state = pinctrl_dev_get_drvdata(pctldev);
  451. struct pmic_mpp_pad *pad;
  452. int ret;
  453. static const char *const biases[] = {
  454. "0.6kOhm", "10kOhm", "30kOhm", "Disabled"
  455. };
  456. pad = pctldev->desc->pins[pin].drv_data;
  457. seq_printf(s, " mpp%-2d:", pin + PMIC_MPP_PHYSICAL_OFFSET);
  458. if (!pad->is_enabled) {
  459. seq_puts(s, " ---");
  460. } else {
  461. if (pad->input_enabled) {
  462. ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
  463. if (ret < 0)
  464. return;
  465. ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
  466. pad->out_value = ret;
  467. }
  468. seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in");
  469. seq_printf(s, " %-7s", pmic_mpp_functions[pad->function]);
  470. seq_printf(s, " vin-%d", pad->power_source);
  471. seq_printf(s, " %d", pad->aout_level);
  472. seq_printf(s, " %-8s", biases[pad->pullup]);
  473. seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
  474. if (pad->dtest)
  475. seq_printf(s, " dtest%d", pad->dtest);
  476. if (pad->paired)
  477. seq_puts(s, " paired");
  478. }
  479. }
  480. static const struct pinconf_ops pmic_mpp_pinconf_ops = {
  481. .is_generic = true,
  482. .pin_config_group_get = pmic_mpp_config_get,
  483. .pin_config_group_set = pmic_mpp_config_set,
  484. .pin_config_group_dbg_show = pmic_mpp_config_dbg_show,
  485. };
  486. static int pmic_mpp_direction_input(struct gpio_chip *chip, unsigned pin)
  487. {
  488. struct pmic_mpp_state *state = to_mpp_state(chip);
  489. unsigned long config;
  490. config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
  491. return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  492. }
  493. static int pmic_mpp_direction_output(struct gpio_chip *chip,
  494. unsigned pin, int val)
  495. {
  496. struct pmic_mpp_state *state = to_mpp_state(chip);
  497. unsigned long config;
  498. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
  499. return pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  500. }
  501. static int pmic_mpp_get(struct gpio_chip *chip, unsigned pin)
  502. {
  503. struct pmic_mpp_state *state = to_mpp_state(chip);
  504. struct pmic_mpp_pad *pad;
  505. int ret;
  506. pad = state->ctrl->desc->pins[pin].drv_data;
  507. if (pad->input_enabled) {
  508. ret = pmic_mpp_read(state, pad, PMIC_MPP_REG_RT_STS);
  509. if (ret < 0)
  510. return ret;
  511. pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
  512. }
  513. return pad->out_value;
  514. }
  515. static void pmic_mpp_set(struct gpio_chip *chip, unsigned pin, int value)
  516. {
  517. struct pmic_mpp_state *state = to_mpp_state(chip);
  518. unsigned long config;
  519. config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
  520. pmic_mpp_config_set(state->ctrl, pin, &config, 1);
  521. }
  522. static int pmic_mpp_of_xlate(struct gpio_chip *chip,
  523. const struct of_phandle_args *gpio_desc,
  524. u32 *flags)
  525. {
  526. if (chip->of_gpio_n_cells < 2)
  527. return -EINVAL;
  528. if (flags)
  529. *flags = gpio_desc->args[1];
  530. return gpio_desc->args[0] - PMIC_MPP_PHYSICAL_OFFSET;
  531. }
  532. static int pmic_mpp_to_irq(struct gpio_chip *chip, unsigned pin)
  533. {
  534. struct pmic_mpp_state *state = to_mpp_state(chip);
  535. struct pmic_mpp_pad *pad;
  536. pad = state->ctrl->desc->pins[pin].drv_data;
  537. return pad->irq;
  538. }
  539. static void pmic_mpp_dbg_show(struct seq_file *s, struct gpio_chip *chip)
  540. {
  541. struct pmic_mpp_state *state = to_mpp_state(chip);
  542. unsigned i;
  543. for (i = 0; i < chip->ngpio; i++) {
  544. pmic_mpp_config_dbg_show(state->ctrl, s, i);
  545. seq_puts(s, "\n");
  546. }
  547. }
  548. static const struct gpio_chip pmic_mpp_gpio_template = {
  549. .direction_input = pmic_mpp_direction_input,
  550. .direction_output = pmic_mpp_direction_output,
  551. .get = pmic_mpp_get,
  552. .set = pmic_mpp_set,
  553. .request = gpiochip_generic_request,
  554. .free = gpiochip_generic_free,
  555. .of_xlate = pmic_mpp_of_xlate,
  556. .to_irq = pmic_mpp_to_irq,
  557. .dbg_show = pmic_mpp_dbg_show,
  558. };
  559. static int pmic_mpp_populate(struct pmic_mpp_state *state,
  560. struct pmic_mpp_pad *pad)
  561. {
  562. int type, subtype, val, dir;
  563. unsigned int sel;
  564. type = pmic_mpp_read(state, pad, PMIC_MPP_REG_TYPE);
  565. if (type < 0)
  566. return type;
  567. if (type != PMIC_MPP_TYPE) {
  568. dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
  569. type, pad->base);
  570. return -ENODEV;
  571. }
  572. subtype = pmic_mpp_read(state, pad, PMIC_MPP_REG_SUBTYPE);
  573. if (subtype < 0)
  574. return subtype;
  575. switch (subtype) {
  576. case PMIC_MPP_SUBTYPE_4CH_NO_ANA_OUT:
  577. case PMIC_MPP_SUBTYPE_ULT_4CH_NO_ANA_OUT:
  578. case PMIC_MPP_SUBTYPE_4CH_NO_SINK:
  579. case PMIC_MPP_SUBTYPE_ULT_4CH_NO_SINK:
  580. case PMIC_MPP_SUBTYPE_4CH_FULL_FUNC:
  581. pad->num_sources = 4;
  582. break;
  583. case PMIC_MPP_SUBTYPE_8CH_FULL_FUNC:
  584. pad->num_sources = 8;
  585. break;
  586. default:
  587. dev_err(state->dev, "unknown MPP type 0x%x at 0x%x\n",
  588. subtype, pad->base);
  589. return -ENODEV;
  590. }
  591. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_MODE_CTL);
  592. if (val < 0)
  593. return val;
  594. pad->out_value = val & PMIC_MPP_REG_MODE_VALUE_MASK;
  595. dir = val >> PMIC_MPP_REG_MODE_DIR_SHIFT;
  596. dir &= PMIC_MPP_REG_MODE_DIR_MASK;
  597. switch (dir) {
  598. case PMIC_MPP_MODE_DIGITAL_INPUT:
  599. pad->input_enabled = true;
  600. pad->output_enabled = false;
  601. pad->function = PMIC_MPP_DIGITAL;
  602. break;
  603. case PMIC_MPP_MODE_DIGITAL_OUTPUT:
  604. pad->input_enabled = false;
  605. pad->output_enabled = true;
  606. pad->function = PMIC_MPP_DIGITAL;
  607. break;
  608. case PMIC_MPP_MODE_DIGITAL_BIDIR:
  609. pad->input_enabled = true;
  610. pad->output_enabled = true;
  611. pad->function = PMIC_MPP_DIGITAL;
  612. break;
  613. case PMIC_MPP_MODE_ANALOG_BIDIR:
  614. pad->input_enabled = true;
  615. pad->output_enabled = true;
  616. pad->function = PMIC_MPP_ANALOG;
  617. break;
  618. case PMIC_MPP_MODE_ANALOG_INPUT:
  619. pad->input_enabled = true;
  620. pad->output_enabled = false;
  621. pad->function = PMIC_MPP_ANALOG;
  622. break;
  623. case PMIC_MPP_MODE_ANALOG_OUTPUT:
  624. pad->input_enabled = false;
  625. pad->output_enabled = true;
  626. pad->function = PMIC_MPP_ANALOG;
  627. break;
  628. case PMIC_MPP_MODE_CURRENT_SINK:
  629. pad->input_enabled = false;
  630. pad->output_enabled = true;
  631. pad->function = PMIC_MPP_SINK;
  632. break;
  633. default:
  634. dev_err(state->dev, "unknown MPP direction\n");
  635. return -ENODEV;
  636. }
  637. sel = val >> PMIC_MPP_REG_MODE_FUNCTION_SHIFT;
  638. sel &= PMIC_MPP_REG_MODE_FUNCTION_MASK;
  639. if (sel >= PMIC_MPP_SELECTOR_DTEST_FIRST)
  640. pad->dtest = sel + 1;
  641. else if (sel == PMIC_MPP_SELECTOR_PAIRED)
  642. pad->paired = true;
  643. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_VIN_CTL);
  644. if (val < 0)
  645. return val;
  646. pad->power_source = val >> PMIC_MPP_REG_VIN_SHIFT;
  647. pad->power_source &= PMIC_MPP_REG_VIN_MASK;
  648. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_DIG_PULL_CTL);
  649. if (val < 0)
  650. return val;
  651. pad->pullup = val >> PMIC_MPP_REG_PULL_SHIFT;
  652. pad->pullup &= PMIC_MPP_REG_PULL_MASK;
  653. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AIN_CTL);
  654. if (val < 0)
  655. return val;
  656. pad->amux_input = val >> PMIC_MPP_REG_AIN_ROUTE_SHIFT;
  657. pad->amux_input &= PMIC_MPP_REG_AIN_ROUTE_MASK;
  658. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_SINK_CTL);
  659. if (val < 0)
  660. return val;
  661. pad->drive_strength = val;
  662. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_AOUT_CTL);
  663. if (val < 0)
  664. return val;
  665. pad->aout_level = val;
  666. val = pmic_mpp_read(state, pad, PMIC_MPP_REG_EN_CTL);
  667. if (val < 0)
  668. return val;
  669. pad->is_enabled = !!val;
  670. return 0;
  671. }
  672. static int pmic_mpp_probe(struct platform_device *pdev)
  673. {
  674. struct device *dev = &pdev->dev;
  675. struct pinctrl_pin_desc *pindesc;
  676. struct pinctrl_desc *pctrldesc;
  677. struct pmic_mpp_pad *pad, *pads;
  678. struct pmic_mpp_state *state;
  679. int ret, npins, i;
  680. u32 res[2];
  681. ret = of_property_read_u32_array(dev->of_node, "reg", res, 2);
  682. if (ret < 0) {
  683. dev_err(dev, "missing base address and/or range");
  684. return ret;
  685. }
  686. npins = res[1] / PMIC_MPP_ADDRESS_RANGE;
  687. if (!npins)
  688. return -EINVAL;
  689. BUG_ON(npins > ARRAY_SIZE(pmic_mpp_groups));
  690. state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
  691. if (!state)
  692. return -ENOMEM;
  693. platform_set_drvdata(pdev, state);
  694. state->dev = &pdev->dev;
  695. state->map = dev_get_regmap(dev->parent, NULL);
  696. pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
  697. if (!pindesc)
  698. return -ENOMEM;
  699. pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
  700. if (!pads)
  701. return -ENOMEM;
  702. pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
  703. if (!pctrldesc)
  704. return -ENOMEM;
  705. pctrldesc->pctlops = &pmic_mpp_pinctrl_ops;
  706. pctrldesc->pmxops = &pmic_mpp_pinmux_ops;
  707. pctrldesc->confops = &pmic_mpp_pinconf_ops;
  708. pctrldesc->owner = THIS_MODULE;
  709. pctrldesc->name = dev_name(dev);
  710. pctrldesc->pins = pindesc;
  711. pctrldesc->npins = npins;
  712. pctrldesc->num_custom_params = ARRAY_SIZE(pmic_mpp_bindings);
  713. pctrldesc->custom_params = pmic_mpp_bindings;
  714. #ifdef CONFIG_DEBUG_FS
  715. pctrldesc->custom_conf_items = pmic_conf_items;
  716. #endif
  717. for (i = 0; i < npins; i++, pindesc++) {
  718. pad = &pads[i];
  719. pindesc->drv_data = pad;
  720. pindesc->number = i;
  721. pindesc->name = pmic_mpp_groups[i];
  722. pad->irq = platform_get_irq(pdev, i);
  723. if (pad->irq < 0)
  724. return pad->irq;
  725. pad->base = res[0] + i * PMIC_MPP_ADDRESS_RANGE;
  726. ret = pmic_mpp_populate(state, pad);
  727. if (ret < 0)
  728. return ret;
  729. }
  730. state->chip = pmic_mpp_gpio_template;
  731. state->chip.dev = dev;
  732. state->chip.base = -1;
  733. state->chip.ngpio = npins;
  734. state->chip.label = dev_name(dev);
  735. state->chip.of_gpio_n_cells = 2;
  736. state->chip.can_sleep = false;
  737. state->ctrl = pinctrl_register(pctrldesc, dev, state);
  738. if (IS_ERR(state->ctrl))
  739. return PTR_ERR(state->ctrl);
  740. ret = gpiochip_add(&state->chip);
  741. if (ret) {
  742. dev_err(state->dev, "can't add gpio chip\n");
  743. goto err_chip;
  744. }
  745. ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins);
  746. if (ret) {
  747. dev_err(dev, "failed to add pin range\n");
  748. goto err_range;
  749. }
  750. return 0;
  751. err_range:
  752. gpiochip_remove(&state->chip);
  753. err_chip:
  754. pinctrl_unregister(state->ctrl);
  755. return ret;
  756. }
  757. static int pmic_mpp_remove(struct platform_device *pdev)
  758. {
  759. struct pmic_mpp_state *state = platform_get_drvdata(pdev);
  760. gpiochip_remove(&state->chip);
  761. pinctrl_unregister(state->ctrl);
  762. return 0;
  763. }
  764. static const struct of_device_id pmic_mpp_of_match[] = {
  765. { .compatible = "qcom,pm8841-mpp" }, /* 4 MPP's */
  766. { .compatible = "qcom,pm8916-mpp" }, /* 4 MPP's */
  767. { .compatible = "qcom,pm8941-mpp" }, /* 8 MPP's */
  768. { .compatible = "qcom,pma8084-mpp" }, /* 8 MPP's */
  769. { },
  770. };
  771. MODULE_DEVICE_TABLE(of, pmic_mpp_of_match);
  772. static struct platform_driver pmic_mpp_driver = {
  773. .driver = {
  774. .name = "qcom-spmi-mpp",
  775. .of_match_table = pmic_mpp_of_match,
  776. },
  777. .probe = pmic_mpp_probe,
  778. .remove = pmic_mpp_remove,
  779. };
  780. module_platform_driver(pmic_mpp_driver);
  781. MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
  782. MODULE_DESCRIPTION("Qualcomm SPMI PMIC MPP pin control driver");
  783. MODULE_ALIAS("platform:qcom-spmi-mpp");
  784. MODULE_LICENSE("GPL v2");