pfc-r8a73a4.c 82 KB

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  1. /*
  2. * Copyright (C) 2012-2013 Renesas Solutions Corp.
  3. * Copyright (C) 2013 Magnus Damm
  4. * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License as
  8. * published by the Free Software Foundation; version 2 of the
  9. * License.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/io.h>
  21. #include <linux/kernel.h>
  22. #include <linux/pinctrl/pinconf-generic.h>
  23. #include "core.h"
  24. #include "sh_pfc.h"
  25. #define CPU_ALL_PORT(fn, pfx, sfx) \
  26. /* Port0 - Port30 */ \
  27. PORT_10(0, fn, pfx, sfx), \
  28. PORT_10(10, fn, pfx##1, sfx), \
  29. PORT_10(20, fn, pfx##2, sfx), \
  30. PORT_1(30, fn, pfx##30, sfx), \
  31. /* Port32 - Port40 */ \
  32. PORT_1(32, fn, pfx##32, sfx), PORT_1(33, fn, pfx##33, sfx), \
  33. PORT_1(34, fn, pfx##34, sfx), PORT_1(35, fn, pfx##35, sfx), \
  34. PORT_1(36, fn, pfx##36, sfx), PORT_1(37, fn, pfx##37, sfx), \
  35. PORT_1(38, fn, pfx##38, sfx), PORT_1(39, fn, pfx##39, sfx), \
  36. PORT_1(40, fn, pfx##40, sfx), \
  37. /* Port64 - Port85 */ \
  38. PORT_1(64, fn, pfx##64, sfx), PORT_1(65, fn, pfx##65, sfx), \
  39. PORT_1(66, fn, pfx##66, sfx), PORT_1(67, fn, pfx##67, sfx), \
  40. PORT_1(68, fn, pfx##68, sfx), PORT_1(69, fn, pfx##69, sfx), \
  41. PORT_10(70, fn, pfx##7, sfx), \
  42. PORT_1(80, fn, pfx##80, sfx), PORT_1(81, fn, pfx##81, sfx), \
  43. PORT_1(82, fn, pfx##82, sfx), PORT_1(83, fn, pfx##83, sfx), \
  44. PORT_1(84, fn, pfx##84, sfx), PORT_1(85, fn, pfx##85, sfx), \
  45. /* Port96 - Port126 */ \
  46. PORT_1(96, fn, pfx##96, sfx), PORT_1(97, fn, pfx##97, sfx), \
  47. PORT_1(98, fn, pfx##98, sfx), PORT_1(99, fn, pfx##99, sfx), \
  48. PORT_10(100, fn, pfx##10, sfx), \
  49. PORT_10(110, fn, pfx##11, sfx), \
  50. PORT_1(120, fn, pfx##120, sfx), PORT_1(121, fn, pfx##121, sfx), \
  51. PORT_1(122, fn, pfx##122, sfx), PORT_1(123, fn, pfx##123, sfx), \
  52. PORT_1(124, fn, pfx##124, sfx), PORT_1(125, fn, pfx##125, sfx), \
  53. PORT_1(126, fn, pfx##126, sfx), \
  54. /* Port128 - Port134 */ \
  55. PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  56. PORT_1(130, fn, pfx##130, sfx), PORT_1(131, fn, pfx##131, sfx), \
  57. PORT_1(132, fn, pfx##132, sfx), PORT_1(133, fn, pfx##133, sfx), \
  58. PORT_1(134, fn, pfx##134, sfx), \
  59. /* Port160 - Port178 */ \
  60. PORT_10(160, fn, pfx##16, sfx), \
  61. PORT_1(170, fn, pfx##170, sfx), PORT_1(171, fn, pfx##171, sfx), \
  62. PORT_1(172, fn, pfx##172, sfx), PORT_1(173, fn, pfx##173, sfx), \
  63. PORT_1(174, fn, pfx##174, sfx), PORT_1(175, fn, pfx##175, sfx), \
  64. PORT_1(176, fn, pfx##176, sfx), PORT_1(177, fn, pfx##177, sfx), \
  65. PORT_1(178, fn, pfx##178, sfx), \
  66. /* Port192 - Port222 */ \
  67. PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  68. PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  69. PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  70. PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  71. PORT_10(200, fn, pfx##20, sfx), \
  72. PORT_10(210, fn, pfx##21, sfx), \
  73. PORT_1(220, fn, pfx##220, sfx), PORT_1(221, fn, pfx##221, sfx), \
  74. PORT_1(222, fn, pfx##222, sfx), \
  75. /* Port224 - Port250 */ \
  76. PORT_1(224, fn, pfx##224, sfx), PORT_1(225, fn, pfx##225, sfx), \
  77. PORT_1(226, fn, pfx##226, sfx), PORT_1(227, fn, pfx##227, sfx), \
  78. PORT_1(228, fn, pfx##228, sfx), PORT_1(229, fn, pfx##229, sfx), \
  79. PORT_10(230, fn, pfx##23, sfx), \
  80. PORT_10(240, fn, pfx##24, sfx), \
  81. PORT_1(250, fn, pfx##250, sfx), \
  82. /* Port256 - Port283 */ \
  83. PORT_1(256, fn, pfx##256, sfx), PORT_1(257, fn, pfx##257, sfx), \
  84. PORT_1(258, fn, pfx##258, sfx), PORT_1(259, fn, pfx##259, sfx), \
  85. PORT_10(260, fn, pfx##26, sfx), \
  86. PORT_10(270, fn, pfx##27, sfx), \
  87. PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  88. PORT_1(282, fn, pfx##282, sfx), PORT_1(283, fn, pfx##283, sfx), \
  89. /* Port288 - Port308 */ \
  90. PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  91. PORT_10(290, fn, pfx##29, sfx), \
  92. PORT_1(300, fn, pfx##300, sfx), PORT_1(301, fn, pfx##301, sfx), \
  93. PORT_1(302, fn, pfx##302, sfx), PORT_1(303, fn, pfx##303, sfx), \
  94. PORT_1(304, fn, pfx##304, sfx), PORT_1(305, fn, pfx##305, sfx), \
  95. PORT_1(306, fn, pfx##306, sfx), PORT_1(307, fn, pfx##307, sfx), \
  96. PORT_1(308, fn, pfx##308, sfx), \
  97. /* Port320 - Port329 */ \
  98. PORT_10(320, fn, pfx##32, sfx)
  99. enum {
  100. PINMUX_RESERVED = 0,
  101. /* PORT0_DATA -> PORT329_DATA */
  102. PINMUX_DATA_BEGIN,
  103. PORT_ALL(DATA),
  104. PINMUX_DATA_END,
  105. /* PORT0_IN -> PORT329_IN */
  106. PINMUX_INPUT_BEGIN,
  107. PORT_ALL(IN),
  108. PINMUX_INPUT_END,
  109. /* PORT0_OUT -> PORT329_OUT */
  110. PINMUX_OUTPUT_BEGIN,
  111. PORT_ALL(OUT),
  112. PINMUX_OUTPUT_END,
  113. PINMUX_FUNCTION_BEGIN,
  114. PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
  115. PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
  116. PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
  117. PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
  118. PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
  119. PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
  120. PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
  121. PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
  122. PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
  123. PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
  124. MSEL1CR_31_0, MSEL1CR_31_1,
  125. MSEL1CR_27_0, MSEL1CR_27_1,
  126. MSEL1CR_25_0, MSEL1CR_25_1,
  127. MSEL1CR_24_0, MSEL1CR_24_1,
  128. MSEL1CR_22_0, MSEL1CR_22_1,
  129. MSEL1CR_21_0, MSEL1CR_21_1,
  130. MSEL1CR_20_0, MSEL1CR_20_1,
  131. MSEL1CR_19_0, MSEL1CR_19_1,
  132. MSEL1CR_18_0, MSEL1CR_18_1,
  133. MSEL1CR_17_0, MSEL1CR_17_1,
  134. MSEL1CR_16_0, MSEL1CR_16_1,
  135. MSEL1CR_15_0, MSEL1CR_15_1,
  136. MSEL1CR_14_0, MSEL1CR_14_1,
  137. MSEL1CR_13_0, MSEL1CR_13_1,
  138. MSEL1CR_12_0, MSEL1CR_12_1,
  139. MSEL1CR_11_0, MSEL1CR_11_1,
  140. MSEL1CR_10_0, MSEL1CR_10_1,
  141. MSEL1CR_09_0, MSEL1CR_09_1,
  142. MSEL1CR_08_0, MSEL1CR_08_1,
  143. MSEL1CR_07_0, MSEL1CR_07_1,
  144. MSEL1CR_06_0, MSEL1CR_06_1,
  145. MSEL1CR_05_0, MSEL1CR_05_1,
  146. MSEL1CR_04_0, MSEL1CR_04_1,
  147. MSEL1CR_03_0, MSEL1CR_03_1,
  148. MSEL1CR_02_0, MSEL1CR_02_1,
  149. MSEL1CR_01_0, MSEL1CR_01_1,
  150. MSEL1CR_00_0, MSEL1CR_00_1,
  151. MSEL3CR_31_0, MSEL3CR_31_1,
  152. MSEL3CR_28_0, MSEL3CR_28_1,
  153. MSEL3CR_27_0, MSEL3CR_27_1,
  154. MSEL3CR_26_0, MSEL3CR_26_1,
  155. MSEL3CR_23_0, MSEL3CR_23_1,
  156. MSEL3CR_22_0, MSEL3CR_22_1,
  157. MSEL3CR_21_0, MSEL3CR_21_1,
  158. MSEL3CR_20_0, MSEL3CR_20_1,
  159. MSEL3CR_19_0, MSEL3CR_19_1,
  160. MSEL3CR_18_0, MSEL3CR_18_1,
  161. MSEL3CR_17_0, MSEL3CR_17_1,
  162. MSEL3CR_16_0, MSEL3CR_16_1,
  163. MSEL3CR_15_0, MSEL3CR_15_1,
  164. MSEL3CR_12_0, MSEL3CR_12_1,
  165. MSEL3CR_11_0, MSEL3CR_11_1,
  166. MSEL3CR_10_0, MSEL3CR_10_1,
  167. MSEL3CR_09_0, MSEL3CR_09_1,
  168. MSEL3CR_06_0, MSEL3CR_06_1,
  169. MSEL3CR_03_0, MSEL3CR_03_1,
  170. MSEL3CR_01_0, MSEL3CR_01_1,
  171. MSEL3CR_00_0, MSEL3CR_00_1,
  172. MSEL4CR_30_0, MSEL4CR_30_1,
  173. MSEL4CR_29_0, MSEL4CR_29_1,
  174. MSEL4CR_28_0, MSEL4CR_28_1,
  175. MSEL4CR_27_0, MSEL4CR_27_1,
  176. MSEL4CR_26_0, MSEL4CR_26_1,
  177. MSEL4CR_25_0, MSEL4CR_25_1,
  178. MSEL4CR_24_0, MSEL4CR_24_1,
  179. MSEL4CR_23_0, MSEL4CR_23_1,
  180. MSEL4CR_22_0, MSEL4CR_22_1,
  181. MSEL4CR_21_0, MSEL4CR_21_1,
  182. MSEL4CR_20_0, MSEL4CR_20_1,
  183. MSEL4CR_19_0, MSEL4CR_19_1,
  184. MSEL4CR_18_0, MSEL4CR_18_1,
  185. MSEL4CR_17_0, MSEL4CR_17_1,
  186. MSEL4CR_16_0, MSEL4CR_16_1,
  187. MSEL4CR_15_0, MSEL4CR_15_1,
  188. MSEL4CR_14_0, MSEL4CR_14_1,
  189. MSEL4CR_13_0, MSEL4CR_13_1,
  190. MSEL4CR_12_0, MSEL4CR_12_1,
  191. MSEL4CR_11_0, MSEL4CR_11_1,
  192. MSEL4CR_10_0, MSEL4CR_10_1,
  193. MSEL4CR_09_0, MSEL4CR_09_1,
  194. MSEL4CR_07_0, MSEL4CR_07_1,
  195. MSEL4CR_04_0, MSEL4CR_04_1,
  196. MSEL4CR_01_0, MSEL4CR_01_1,
  197. MSEL5CR_31_0, MSEL5CR_31_1,
  198. MSEL5CR_30_0, MSEL5CR_30_1,
  199. MSEL5CR_29_0, MSEL5CR_29_1,
  200. MSEL5CR_28_0, MSEL5CR_28_1,
  201. MSEL5CR_27_0, MSEL5CR_27_1,
  202. MSEL5CR_26_0, MSEL5CR_26_1,
  203. MSEL5CR_25_0, MSEL5CR_25_1,
  204. MSEL5CR_24_0, MSEL5CR_24_1,
  205. MSEL5CR_23_0, MSEL5CR_23_1,
  206. MSEL5CR_22_0, MSEL5CR_22_1,
  207. MSEL5CR_21_0, MSEL5CR_21_1,
  208. MSEL5CR_20_0, MSEL5CR_20_1,
  209. MSEL5CR_19_0, MSEL5CR_19_1,
  210. MSEL5CR_18_0, MSEL5CR_18_1,
  211. MSEL5CR_17_0, MSEL5CR_17_1,
  212. MSEL5CR_16_0, MSEL5CR_16_1,
  213. MSEL5CR_15_0, MSEL5CR_15_1,
  214. MSEL5CR_14_0, MSEL5CR_14_1,
  215. MSEL5CR_13_0, MSEL5CR_13_1,
  216. MSEL5CR_12_0, MSEL5CR_12_1,
  217. MSEL5CR_11_0, MSEL5CR_11_1,
  218. MSEL5CR_10_0, MSEL5CR_10_1,
  219. MSEL5CR_09_0, MSEL5CR_09_1,
  220. MSEL5CR_08_0, MSEL5CR_08_1,
  221. MSEL5CR_07_0, MSEL5CR_07_1,
  222. MSEL5CR_06_0, MSEL5CR_06_1,
  223. MSEL8CR_16_0, MSEL8CR_16_1,
  224. MSEL8CR_01_0, MSEL8CR_01_1,
  225. MSEL8CR_00_0, MSEL8CR_00_1,
  226. PINMUX_FUNCTION_END,
  227. PINMUX_MARK_BEGIN,
  228. #define F1(a) a##_MARK
  229. #define F2(a) a##_MARK
  230. #define F3(a) a##_MARK
  231. #define F4(a) a##_MARK
  232. #define F5(a) a##_MARK
  233. #define F6(a) a##_MARK
  234. #define F7(a) a##_MARK
  235. #define IRQ(a) IRQ##a##_MARK
  236. F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
  237. F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
  238. F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
  239. F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
  240. F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
  241. F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
  242. F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
  243. F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
  244. F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
  245. F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
  246. F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
  247. F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
  248. F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
  249. F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
  250. F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
  251. F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
  252. F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
  253. F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
  254. F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
  255. F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
  256. F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
  257. F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
  258. F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
  259. F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
  260. F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
  261. F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
  262. F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
  263. F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
  264. F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
  265. F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
  266. F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
  267. F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
  268. F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
  269. F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
  270. F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
  271. F1(SCIFA1_RTS), F7(CSCIF1_RTS),
  272. F1(SCIFA1_CTS), F7(CSCIF1_CTS),
  273. F1(SCIFA1_SCK), F7(CSCIF1_SCK),
  274. F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
  275. F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
  276. F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
  277. F7(CHSCIF0_HSCK), /* Port40 */
  278. F1(PDM0_DATA), /* Port64 */
  279. F1(PDM1_DATA),
  280. F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
  281. IRQ(40),
  282. F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
  283. F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
  284. F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
  285. F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
  286. F7(CHSCIF1_HRTS), /* Port70 */
  287. F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
  288. F7(CHSCIF1_HCTS),
  289. F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
  290. F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
  291. F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
  292. F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
  293. F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
  294. F1(KEYIN0), /* Port96 */
  295. F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
  296. F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
  297. F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
  298. F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
  299. F2(KEYOUT7), F5(RFANAEN), IRQ(45),
  300. F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
  301. F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
  302. F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
  303. F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
  304. F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
  305. F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
  306. F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
  307. F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
  308. F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
  309. F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
  310. F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
  311. F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
  312. F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
  313. F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
  314. F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
  315. F5(SIM0_VOLTSEL1), /* Port130 */
  316. F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
  317. F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
  318. F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
  319. IRQ(20), /* Port160 */
  320. IRQ(21), IRQ(22), IRQ(23),
  321. F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
  322. F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
  323. F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
  324. IRQ(24), IRQ(25), IRQ(26), IRQ(27),
  325. F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
  326. F1(A9), F2(MMCD1_6), IRQ(32),
  327. F1(A8), F2(MMCD1_5), IRQ(33),
  328. F1(A7), F2(MMCD1_4), IRQ(34),
  329. F1(A6), F2(MMCD1_3), IRQ(35),
  330. F1(A5), F2(MMCD1_2), IRQ(36),
  331. F1(A4), F2(MMCD1_1), IRQ(37),
  332. F1(A3), F2(MMCD1_0), IRQ(38),
  333. F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
  334. F1(A1),
  335. F1(A0), F2(BS),
  336. F1(CKO), F2(MMCCLK1),
  337. F1(CS0_N), F5(SIM0_GPO1),
  338. F1(CS2_N), F5(SIM0_GPO2),
  339. F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
  340. F1(D15), F5(GIO_OUT15),
  341. F1(D14), F5(GIO_OUT14),
  342. F1(D13), F5(GIO_OUT13),
  343. F1(D12), F5(GIO_OUT12), /* Port210 */
  344. F1(D11), F5(WGM_TXP2),
  345. F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
  346. F1(D9), F2(VIO_D9), F5(GIO_OUT9),
  347. F1(D8), F2(VIO_D8), F5(GIO_OUT8),
  348. F1(D7), F2(VIO_D7), F5(GIO_OUT7),
  349. F1(D6), F2(VIO_D6), F5(GIO_OUT6),
  350. F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
  351. F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
  352. F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
  353. F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
  354. F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
  355. F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
  356. F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
  357. F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
  358. F1(WE0_N), F2(RDWR_227),
  359. F1(WE1_N), F5(SIM0_GPO0),
  360. F1(PWMO), F2(VIO_CKO1_229),
  361. F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
  362. F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
  363. F2(VIO_CKO3_233), F4(SF_PORT_1_233),
  364. F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
  365. F1(FSIAISLD), F2(PDM3_DATA_235),
  366. F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
  367. F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
  368. F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
  369. F1(FSIBISLD), /* Port240 */
  370. F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
  371. F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
  372. F1(FSIBCK), F3(ISP_SHUTTER0_245),
  373. F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
  374. F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
  375. F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
  376. F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
  377. F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
  378. F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
  379. F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
  380. F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
  381. F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
  382. F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
  383. F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
  384. F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
  385. F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
  386. F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
  387. F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
  388. F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
  389. F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
  390. F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
  391. F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
  392. F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
  393. F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
  394. F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
  395. F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
  396. F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
  397. F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
  398. F4(MSIOF6_SS1), /* Port300 */
  399. F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
  400. F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
  401. F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
  402. F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
  403. IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
  404. IRQ(55), IRQ(56), IRQ(57),
  405. PINMUX_MARK_END,
  406. };
  407. static const u16 pinmux_data[] = {
  408. /* specify valid pin states for each pin in GPIO mode */
  409. PINMUX_DATA_ALL(),
  410. /* Port0 */
  411. PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
  412. PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
  413. PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
  414. PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
  415. /* Port1 */
  416. PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
  417. PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
  418. PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
  419. PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
  420. /* Port2 */
  421. PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
  422. PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
  423. PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
  424. PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
  425. /* Port3 */
  426. PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
  427. PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
  428. PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
  429. PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
  430. /* Port4 */
  431. PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
  432. PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
  433. PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
  434. PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
  435. /* Port5 */
  436. PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
  437. PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
  438. PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
  439. PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
  440. /* Port6 */
  441. PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
  442. PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
  443. PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
  444. PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
  445. /* Port7 */
  446. PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
  447. PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
  448. PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
  449. PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
  450. /* Port8 */
  451. PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
  452. PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
  453. PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
  454. PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
  455. /* Port9 */
  456. PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
  457. PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
  458. PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
  459. PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
  460. /* Port10 */
  461. PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
  462. PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
  463. PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
  464. PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
  465. /* Port11 */
  466. PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
  467. PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
  468. PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
  469. PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
  470. /* Port12 */
  471. PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
  472. PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
  473. PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
  474. PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
  475. /* Port13 */
  476. PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
  477. PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
  478. PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
  479. PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
  480. PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
  481. /* Port14 */
  482. PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
  483. PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
  484. PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
  485. PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
  486. PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
  487. /* Port15 */
  488. PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
  489. PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
  490. PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
  491. PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
  492. /* Port16 */
  493. PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
  494. PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
  495. PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
  496. /* Port17 */
  497. PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
  498. PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
  499. PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
  500. /* Port18 */
  501. PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
  502. PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
  503. PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
  504. /* Port19 */
  505. PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
  506. PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
  507. PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
  508. /* Port20 */
  509. PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
  510. PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
  511. PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
  512. /* Port21 */
  513. PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
  514. PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
  515. PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
  516. /* Port22 */
  517. PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
  518. PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
  519. PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
  520. /* Port23 */
  521. PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
  522. PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
  523. PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
  524. /* Port24 */
  525. PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
  526. PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
  527. PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
  528. PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
  529. /* Port25 */
  530. PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
  531. PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
  532. PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
  533. /* Port26 */
  534. PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
  535. PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
  536. PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
  537. PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
  538. /* Port27 */
  539. PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
  540. PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
  541. PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
  542. PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
  543. /* Port28 */
  544. PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
  545. PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
  546. PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
  547. /* Port29 */
  548. PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
  549. PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
  550. PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
  551. /* Port30 */
  552. PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
  553. PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
  554. PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
  555. /* Port32 */
  556. PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
  557. PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
  558. PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
  559. /* Port33 */
  560. PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
  561. PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
  562. PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
  563. /* Port34 */
  564. PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
  565. PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
  566. PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
  567. /* Port35 */
  568. PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
  569. PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
  570. /* Port36 */
  571. PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
  572. PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
  573. /* Port37 */
  574. PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
  575. PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
  576. /* Port38 */
  577. PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
  578. PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
  579. PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
  580. PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
  581. /* Port39 */
  582. PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
  583. PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
  584. PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
  585. PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
  586. /* Port40 */
  587. PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
  588. PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
  589. PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
  590. PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
  591. /* Port64 */
  592. PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
  593. /* Port65 */
  594. PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
  595. /* Port66 */
  596. PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
  597. PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
  598. PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
  599. PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
  600. PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
  601. /* Port67 */
  602. PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
  603. PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
  604. PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
  605. PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
  606. /* Port68 */
  607. PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
  608. PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
  609. PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
  610. PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
  611. /* Port69 */
  612. PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
  613. PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
  614. PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
  615. PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
  616. /* Port70 */
  617. PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
  618. PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
  619. PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
  620. PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
  621. PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
  622. /* Port71 */
  623. PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
  624. PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
  625. PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
  626. PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
  627. PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
  628. /* Port72 */
  629. PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
  630. PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
  631. PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
  632. PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
  633. /* Port73 */
  634. PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
  635. PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
  636. PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
  637. PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
  638. /* Port74 - Port85 */
  639. PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
  640. PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
  641. PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
  642. PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
  643. PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
  644. PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
  645. PINMUX_DATA(TXP_MARK, PORT80_FN1),
  646. PINMUX_DATA(TXP2_MARK, PORT81_FN1),
  647. PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
  648. PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
  649. PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
  650. PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
  651. /* Port96 - Port101 */
  652. PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
  653. PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
  654. PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
  655. PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
  656. PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
  657. PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
  658. /* Port102 */
  659. PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
  660. PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
  661. /* Port103 */
  662. PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
  663. PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
  664. /* Port104 - Port108 */
  665. PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
  666. PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
  667. PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
  668. PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
  669. PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
  670. /* Port109 */
  671. PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
  672. PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
  673. /* Port110 */
  674. PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
  675. PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
  676. /* Port111 */
  677. PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
  678. PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
  679. PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
  680. /* Port112 */
  681. PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
  682. PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
  683. PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
  684. PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
  685. /* Port113 */
  686. PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
  687. PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
  688. PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
  689. PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
  690. /* Port114 */
  691. PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
  692. PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
  693. PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
  694. PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
  695. /* Port115 */
  696. PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
  697. PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
  698. PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
  699. PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
  700. /* Port116 */
  701. PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
  702. PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
  703. /* Port117 */
  704. PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
  705. PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
  706. /* Port118 */
  707. PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
  708. PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
  709. /* Port119 */
  710. PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
  711. PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
  712. /* Port120 */
  713. PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
  714. PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
  715. PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
  716. /* Port121 */
  717. PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
  718. PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
  719. /* Port122 */
  720. PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
  721. PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
  722. /* Port123 */
  723. PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
  724. PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
  725. /* Port124 */
  726. PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
  727. /* Port125 */
  728. PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
  729. PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
  730. PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
  731. PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
  732. /* Port126 */
  733. PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
  734. PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
  735. PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
  736. /* Port128 */
  737. PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
  738. PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
  739. PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
  740. PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
  741. /* Port129 */
  742. PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
  743. PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
  744. PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
  745. /* Port130 */
  746. PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
  747. PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
  748. PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
  749. PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
  750. /* Port131 */
  751. PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
  752. PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
  753. /* Port132 */
  754. PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
  755. PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
  756. PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
  757. /* Port133 */
  758. PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
  759. PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
  760. PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
  761. PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
  762. /* Port134 */
  763. PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
  764. PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
  765. PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
  766. /* Port160 - Port178 */
  767. PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
  768. PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
  769. PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
  770. PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
  771. PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
  772. PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
  773. PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
  774. PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
  775. PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
  776. PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
  777. PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
  778. PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
  779. PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
  780. PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
  781. PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
  782. PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
  783. PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
  784. PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
  785. PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
  786. /* Port192 - Port200 FN1 */
  787. PINMUX_DATA(A10_MARK, PORT192_FN1),
  788. PINMUX_DATA(A9_MARK, PORT193_FN1),
  789. PINMUX_DATA(A8_MARK, PORT194_FN1),
  790. PINMUX_DATA(A7_MARK, PORT195_FN1),
  791. PINMUX_DATA(A6_MARK, PORT196_FN1),
  792. PINMUX_DATA(A5_MARK, PORT197_FN1),
  793. PINMUX_DATA(A4_MARK, PORT198_FN1),
  794. PINMUX_DATA(A3_MARK, PORT199_FN1),
  795. PINMUX_DATA(A2_MARK, PORT200_FN1),
  796. /* Port192 - Port200 FN2 */
  797. PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
  798. PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
  799. PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
  800. PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
  801. PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
  802. PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
  803. PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
  804. PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
  805. PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
  806. /* Port192 - Port200 IRQ */
  807. PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
  808. PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
  809. PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
  810. PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
  811. PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
  812. PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
  813. PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
  814. PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
  815. PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
  816. /* Port201 */
  817. PINMUX_DATA(A1_MARK, PORT201_FN1),
  818. /* Port202 */
  819. PINMUX_DATA(A0_MARK, PORT202_FN1),
  820. PINMUX_DATA(BS_MARK, PORT202_FN2),
  821. /* Port203 */
  822. PINMUX_DATA(CKO_MARK, PORT203_FN1),
  823. PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
  824. /* Port204 */
  825. PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
  826. PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
  827. /* Port205 */
  828. PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
  829. PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
  830. /* Port206 */
  831. PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
  832. PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
  833. PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
  834. /* Port207 - Port212 FN1 */
  835. PINMUX_DATA(D15_MARK, PORT207_FN1),
  836. PINMUX_DATA(D14_MARK, PORT208_FN1),
  837. PINMUX_DATA(D13_MARK, PORT209_FN1),
  838. PINMUX_DATA(D12_MARK, PORT210_FN1),
  839. PINMUX_DATA(D11_MARK, PORT211_FN1),
  840. PINMUX_DATA(D10_MARK, PORT212_FN1),
  841. /* Port207 - Port212 FN5 */
  842. PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
  843. PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
  844. PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
  845. PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
  846. PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
  847. PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
  848. /* Port213 - Port222 FN1 */
  849. PINMUX_DATA(D9_MARK, PORT213_FN1),
  850. PINMUX_DATA(D8_MARK, PORT214_FN1),
  851. PINMUX_DATA(D7_MARK, PORT215_FN1),
  852. PINMUX_DATA(D6_MARK, PORT216_FN1),
  853. PINMUX_DATA(D5_MARK, PORT217_FN1),
  854. PINMUX_DATA(D4_MARK, PORT218_FN1),
  855. PINMUX_DATA(D3_MARK, PORT219_FN1),
  856. PINMUX_DATA(D2_MARK, PORT220_FN1),
  857. PINMUX_DATA(D1_MARK, PORT221_FN1),
  858. PINMUX_DATA(D0_MARK, PORT222_FN1),
  859. /* Port213 - Port222 FN2 */
  860. PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
  861. PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
  862. PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
  863. PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
  864. PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
  865. PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
  866. PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
  867. PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
  868. PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
  869. PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
  870. /* Port213 - Port222 FN5 */
  871. PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
  872. PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
  873. PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
  874. PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
  875. PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
  876. PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
  877. PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
  878. PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
  879. PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
  880. PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
  881. /* Port224 */
  882. PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
  883. PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
  884. PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
  885. /* Port225 */
  886. PINMUX_DATA(RD_N_MARK, PORT225_FN1),
  887. /* Port226 */
  888. PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
  889. PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
  890. PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
  891. /* Port227 */
  892. PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
  893. PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
  894. /* Port228 */
  895. PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
  896. PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
  897. /* Port229 */
  898. PINMUX_DATA(PWMO_MARK, PORT229_FN1),
  899. PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
  900. /* Port230 */
  901. PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
  902. PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
  903. /* Port231 */
  904. PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
  905. PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
  906. /* Port232 */
  907. PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
  908. PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
  909. /* Port233 */
  910. PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
  911. PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
  912. /* Port234 */
  913. PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
  914. PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
  915. PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
  916. /* Port235 */
  917. PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
  918. PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
  919. /* Port236 */
  920. PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
  921. PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
  922. PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
  923. /* Port237 */
  924. PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
  925. PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
  926. /* Port238 */
  927. PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
  928. PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
  929. /* Port239 */
  930. PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
  931. PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
  932. /* Port240 */
  933. PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
  934. /* Port241 */
  935. PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
  936. PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
  937. /* Port242 */
  938. PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
  939. PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
  940. /* Port243 */
  941. PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
  942. PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
  943. /* Port244 */
  944. PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
  945. PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
  946. /* Port245 */
  947. PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
  948. PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
  949. /* Port246 - Port250 FN1 */
  950. PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
  951. PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
  952. PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
  953. PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
  954. PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
  955. /* Port256 - Port258 */
  956. PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
  957. PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
  958. PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
  959. /* Port259 */
  960. PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
  961. PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
  962. /* Port260 */
  963. PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
  964. /* Port261 */
  965. PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
  966. PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
  967. /* Port262 */
  968. PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
  969. /* Port263 - Port266 FN1 */
  970. PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
  971. PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
  972. PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
  973. PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
  974. /* Port263 - Port266 FN4 */
  975. PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
  976. PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
  977. PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
  978. PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
  979. /* Port267 */
  980. PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
  981. /* Port268 */
  982. PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
  983. PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
  984. /* Port269 */
  985. PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
  986. PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
  987. /* Port270 - Port273 FN1 */
  988. PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
  989. PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
  990. PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
  991. PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
  992. /* Port270 - Port273 FN3 */
  993. PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
  994. PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
  995. PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
  996. PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
  997. /* Port274 */
  998. PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
  999. PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
  1000. /* Port275 - Port280 */
  1001. PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
  1002. PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
  1003. PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
  1004. PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
  1005. PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
  1006. PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
  1007. /* Port281 */
  1008. PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
  1009. PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
  1010. /* Port282 */
  1011. PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
  1012. PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
  1013. /* Port283 */
  1014. PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
  1015. /* Port289 */
  1016. PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
  1017. PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
  1018. /* Port290 */
  1019. PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
  1020. PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
  1021. PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
  1022. /* Port291 - Port294 FN1 */
  1023. PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
  1024. PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
  1025. PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
  1026. PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
  1027. /* Port291 - Port294 FN3 */
  1028. PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
  1029. PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
  1030. PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
  1031. PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
  1032. /* Port295 */
  1033. PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
  1034. PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
  1035. PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
  1036. PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
  1037. /* Port296 */
  1038. PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
  1039. PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
  1040. PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
  1041. /* Port297 - Port300 FN1 */
  1042. PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
  1043. PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
  1044. PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
  1045. PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
  1046. /* Port297 - Port300 FN2 */
  1047. PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
  1048. PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
  1049. PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
  1050. PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
  1051. /* Port297 - Port300 FN3 */
  1052. PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
  1053. PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
  1054. PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
  1055. PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
  1056. /* Port297 - Port300 FN4 */
  1057. PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
  1058. PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
  1059. PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
  1060. PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
  1061. /* Port301 */
  1062. PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
  1063. PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
  1064. /* Port302 - Port306 FN1 */
  1065. PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
  1066. PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
  1067. PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
  1068. PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
  1069. PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
  1070. /* Port302 - Port306 FN3 */
  1071. PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
  1072. PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
  1073. PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
  1074. PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
  1075. PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
  1076. /* Port307 */
  1077. PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
  1078. /* Port308 */
  1079. PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
  1080. PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
  1081. /* Port320 - Port329 */
  1082. PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
  1083. PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
  1084. PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
  1085. PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
  1086. PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
  1087. PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
  1088. PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
  1089. PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
  1090. PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
  1091. PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
  1092. };
  1093. #define __O (SH_PFC_PIN_CFG_OUTPUT)
  1094. #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
  1095. #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
  1096. #define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
  1097. #define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
  1098. static const struct sh_pfc_pin pinmux_pins[] = {
  1099. R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
  1100. R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
  1101. R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
  1102. R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
  1103. R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
  1104. R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
  1105. R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
  1106. R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
  1107. R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
  1108. R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
  1109. R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
  1110. R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
  1111. R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
  1112. R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
  1113. R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
  1114. R8A73A4_PIN_IO_PU_PD(30),
  1115. R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
  1116. R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
  1117. R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
  1118. R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
  1119. R8A73A4_PIN_IO_PU_PD(40),
  1120. R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
  1121. R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
  1122. R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
  1123. R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
  1124. R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
  1125. R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
  1126. R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
  1127. R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
  1128. R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
  1129. R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
  1130. R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
  1131. R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
  1132. R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
  1133. R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
  1134. R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
  1135. R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
  1136. R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
  1137. R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
  1138. R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
  1139. R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
  1140. R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
  1141. R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
  1142. R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
  1143. R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
  1144. R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
  1145. R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
  1146. R8A73A4_PIN_IO_PU_PD(126),
  1147. R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
  1148. R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
  1149. R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
  1150. R8A73A4_PIN_IO_PU_PD(134),
  1151. R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
  1152. R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
  1153. R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
  1154. R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
  1155. R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
  1156. R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
  1157. R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
  1158. R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
  1159. R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
  1160. R8A73A4_PIN_IO_PU_PD(178),
  1161. R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
  1162. R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
  1163. R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
  1164. R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
  1165. R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
  1166. R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
  1167. R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
  1168. R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
  1169. R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
  1170. R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
  1171. R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
  1172. R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
  1173. R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
  1174. R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
  1175. R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
  1176. R8A73A4_PIN_IO_PU_PD(222),
  1177. R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
  1178. R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
  1179. R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
  1180. R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
  1181. R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
  1182. R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
  1183. R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
  1184. R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
  1185. R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
  1186. R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
  1187. R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
  1188. R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
  1189. R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
  1190. R8A73A4_PIN_IO_PU_PD(250),
  1191. R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
  1192. R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
  1193. R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
  1194. R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
  1195. R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
  1196. R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
  1197. R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
  1198. R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
  1199. R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
  1200. R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
  1201. R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
  1202. R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
  1203. R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
  1204. R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
  1205. R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
  1206. R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
  1207. R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
  1208. R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
  1209. R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
  1210. R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
  1211. R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
  1212. R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
  1213. R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
  1214. R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
  1215. R8A73A4_PIN_IO_PU_PD(308),
  1216. R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
  1217. R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
  1218. R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
  1219. R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
  1220. R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
  1221. };
  1222. /* - IRQC ------------------------------------------------------------------- */
  1223. #define IRQC_PINS_MUX(pin, irq_mark) \
  1224. static const unsigned int irqc_irq##irq_mark##_pins[] = { \
  1225. pin, \
  1226. }; \
  1227. static const unsigned int irqc_irq##irq_mark##_mux[] = { \
  1228. IRQ##irq_mark##_MARK, \
  1229. }
  1230. IRQC_PINS_MUX(0, 0);
  1231. IRQC_PINS_MUX(1, 1);
  1232. IRQC_PINS_MUX(2, 2);
  1233. IRQC_PINS_MUX(3, 3);
  1234. IRQC_PINS_MUX(4, 4);
  1235. IRQC_PINS_MUX(5, 5);
  1236. IRQC_PINS_MUX(6, 6);
  1237. IRQC_PINS_MUX(7, 7);
  1238. IRQC_PINS_MUX(8, 8);
  1239. IRQC_PINS_MUX(9, 9);
  1240. IRQC_PINS_MUX(10, 10);
  1241. IRQC_PINS_MUX(11, 11);
  1242. IRQC_PINS_MUX(12, 12);
  1243. IRQC_PINS_MUX(13, 13);
  1244. IRQC_PINS_MUX(14, 14);
  1245. IRQC_PINS_MUX(15, 15);
  1246. IRQC_PINS_MUX(66, 40);
  1247. IRQC_PINS_MUX(84, 19);
  1248. IRQC_PINS_MUX(85, 18);
  1249. IRQC_PINS_MUX(102, 41);
  1250. IRQC_PINS_MUX(103, 42);
  1251. IRQC_PINS_MUX(109, 43);
  1252. IRQC_PINS_MUX(110, 44);
  1253. IRQC_PINS_MUX(111, 45);
  1254. IRQC_PINS_MUX(112, 46);
  1255. IRQC_PINS_MUX(113, 47);
  1256. IRQC_PINS_MUX(114, 48);
  1257. IRQC_PINS_MUX(115, 49);
  1258. IRQC_PINS_MUX(160, 20);
  1259. IRQC_PINS_MUX(161, 21);
  1260. IRQC_PINS_MUX(162, 22);
  1261. IRQC_PINS_MUX(163, 23);
  1262. IRQC_PINS_MUX(175, 24);
  1263. IRQC_PINS_MUX(176, 25);
  1264. IRQC_PINS_MUX(177, 26);
  1265. IRQC_PINS_MUX(178, 27);
  1266. IRQC_PINS_MUX(192, 31);
  1267. IRQC_PINS_MUX(193, 32);
  1268. IRQC_PINS_MUX(194, 33);
  1269. IRQC_PINS_MUX(195, 34);
  1270. IRQC_PINS_MUX(196, 35);
  1271. IRQC_PINS_MUX(197, 36);
  1272. IRQC_PINS_MUX(198, 37);
  1273. IRQC_PINS_MUX(199, 38);
  1274. IRQC_PINS_MUX(200, 39);
  1275. IRQC_PINS_MUX(290, 51);
  1276. IRQC_PINS_MUX(296, 52);
  1277. IRQC_PINS_MUX(301, 50);
  1278. IRQC_PINS_MUX(320, 16);
  1279. IRQC_PINS_MUX(321, 17);
  1280. IRQC_PINS_MUX(322, 28);
  1281. IRQC_PINS_MUX(323, 29);
  1282. IRQC_PINS_MUX(324, 30);
  1283. IRQC_PINS_MUX(325, 53);
  1284. IRQC_PINS_MUX(326, 54);
  1285. IRQC_PINS_MUX(327, 55);
  1286. IRQC_PINS_MUX(328, 56);
  1287. IRQC_PINS_MUX(329, 57);
  1288. /* - MMCIF0 ----------------------------------------------------------------- */
  1289. static const unsigned int mmc0_data1_pins[] = {
  1290. /* D[0] */
  1291. 164,
  1292. };
  1293. static const unsigned int mmc0_data1_mux[] = {
  1294. MMCD0_0_MARK,
  1295. };
  1296. static const unsigned int mmc0_data4_pins[] = {
  1297. /* D[0:3] */
  1298. 164, 165, 166, 167,
  1299. };
  1300. static const unsigned int mmc0_data4_mux[] = {
  1301. MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
  1302. };
  1303. static const unsigned int mmc0_data8_pins[] = {
  1304. /* D[0:7] */
  1305. 164, 165, 166, 167, 168, 169, 170, 171,
  1306. };
  1307. static const unsigned int mmc0_data8_mux[] = {
  1308. MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
  1309. MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
  1310. };
  1311. static const unsigned int mmc0_ctrl_pins[] = {
  1312. /* CMD, CLK */
  1313. 172, 173,
  1314. };
  1315. static const unsigned int mmc0_ctrl_mux[] = {
  1316. MMCCMD0_MARK, MMCCLK0_MARK,
  1317. };
  1318. /* - MMCIF1 ----------------------------------------------------------------- */
  1319. static const unsigned int mmc1_data1_pins[] = {
  1320. /* D[0] */
  1321. 199,
  1322. };
  1323. static const unsigned int mmc1_data1_mux[] = {
  1324. MMCD1_0_MARK,
  1325. };
  1326. static const unsigned int mmc1_data4_pins[] = {
  1327. /* D[0:3] */
  1328. 199, 198, 197, 196,
  1329. };
  1330. static const unsigned int mmc1_data4_mux[] = {
  1331. MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
  1332. };
  1333. static const unsigned int mmc1_data8_pins[] = {
  1334. /* D[0:7] */
  1335. 199, 198, 197, 196, 195, 194, 193, 192,
  1336. };
  1337. static const unsigned int mmc1_data8_mux[] = {
  1338. MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
  1339. MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
  1340. };
  1341. static const unsigned int mmc1_ctrl_pins[] = {
  1342. /* CMD, CLK */
  1343. 200, 203,
  1344. };
  1345. static const unsigned int mmc1_ctrl_mux[] = {
  1346. MMCCMD1_MARK, MMCCLK1_MARK,
  1347. };
  1348. /* - SCIFA0 ----------------------------------------------------------------- */
  1349. static const unsigned int scifa0_data_pins[] = {
  1350. /* SCIFA0_RXD, SCIFA0_TXD */
  1351. 117, 116,
  1352. };
  1353. static const unsigned int scifa0_data_mux[] = {
  1354. SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
  1355. };
  1356. static const unsigned int scifa0_clk_pins[] = {
  1357. /* SCIFA0_SCK */
  1358. 34,
  1359. };
  1360. static const unsigned int scifa0_clk_mux[] = {
  1361. SCIFA0_SCK_MARK,
  1362. };
  1363. static const unsigned int scifa0_ctrl_pins[] = {
  1364. /* SCIFA0_RTS, SCIFA0_CTS */
  1365. 32, 33,
  1366. };
  1367. static const unsigned int scifa0_ctrl_mux[] = {
  1368. SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
  1369. };
  1370. /* - SCIFA1 ----------------------------------------------------------------- */
  1371. static const unsigned int scifa1_data_pins[] = {
  1372. /* SCIFA1_RXD, SCIFA1_TXD */
  1373. 119, 118,
  1374. };
  1375. static const unsigned int scifa1_data_mux[] = {
  1376. SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
  1377. };
  1378. static const unsigned int scifa1_clk_pins[] = {
  1379. /* SCIFA1_SCK */
  1380. 37,
  1381. };
  1382. static const unsigned int scifa1_clk_mux[] = {
  1383. SCIFA1_SCK_MARK,
  1384. };
  1385. static const unsigned int scifa1_ctrl_pins[] = {
  1386. /* SCIFA1_RTS, SCIFA1_CTS */
  1387. 35, 36,
  1388. };
  1389. static const unsigned int scifa1_ctrl_mux[] = {
  1390. SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
  1391. };
  1392. /* - SCIFB0 ----------------------------------------------------------------- */
  1393. static const unsigned int scifb0_data_pins[] = {
  1394. /* SCIFB0_RXD, SCIFB0_TXD */
  1395. 123, 122,
  1396. };
  1397. static const unsigned int scifb0_data_mux[] = {
  1398. SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
  1399. };
  1400. static const unsigned int scifb0_clk_pins[] = {
  1401. /* SCIFB0_SCK */
  1402. 40,
  1403. };
  1404. static const unsigned int scifb0_clk_mux[] = {
  1405. SCIFB0_SCK_MARK,
  1406. };
  1407. static const unsigned int scifb0_ctrl_pins[] = {
  1408. /* SCIFB0_RTS, SCIFB0_CTS */
  1409. 38, 39,
  1410. };
  1411. static const unsigned int scifb0_ctrl_mux[] = {
  1412. SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
  1413. };
  1414. /* - SCIFB1 ----------------------------------------------------------------- */
  1415. static const unsigned int scifb1_data_pins[] = {
  1416. /* SCIFB1_RXD, SCIFB1_TXD */
  1417. 27, 26,
  1418. };
  1419. static const unsigned int scifb1_data_mux[] = {
  1420. SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
  1421. };
  1422. static const unsigned int scifb1_clk_pins[] = {
  1423. /* SCIFB1_SCK */
  1424. 28,
  1425. };
  1426. static const unsigned int scifb1_clk_mux[] = {
  1427. SCIFB1_SCK_28_MARK,
  1428. };
  1429. static const unsigned int scifb1_ctrl_pins[] = {
  1430. /* SCIFB1_RTS, SCIFB1_CTS */
  1431. 24, 25,
  1432. };
  1433. static const unsigned int scifb1_ctrl_mux[] = {
  1434. SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
  1435. };
  1436. static const unsigned int scifb1_data_b_pins[] = {
  1437. /* SCIFB1_RXD, SCIFB1_TXD */
  1438. 72, 67,
  1439. };
  1440. static const unsigned int scifb1_data_b_mux[] = {
  1441. SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
  1442. };
  1443. static const unsigned int scifb1_clk_b_pins[] = {
  1444. /* SCIFB1_SCK */
  1445. 261,
  1446. };
  1447. static const unsigned int scifb1_clk_b_mux[] = {
  1448. SCIFB1_SCK_261_MARK,
  1449. };
  1450. static const unsigned int scifb1_ctrl_b_pins[] = {
  1451. /* SCIFB1_RTS, SCIFB1_CTS */
  1452. 70, 71,
  1453. };
  1454. static const unsigned int scifb1_ctrl_b_mux[] = {
  1455. SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
  1456. };
  1457. /* - SCIFB2 ----------------------------------------------------------------- */
  1458. static const unsigned int scifb2_data_pins[] = {
  1459. /* SCIFB2_RXD, SCIFB2_TXD */
  1460. 69, 68,
  1461. };
  1462. static const unsigned int scifb2_data_mux[] = {
  1463. SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
  1464. };
  1465. static const unsigned int scifb2_clk_pins[] = {
  1466. /* SCIFB2_SCK */
  1467. 262,
  1468. };
  1469. static const unsigned int scifb2_clk_mux[] = {
  1470. SCIFB2_SCK_262_MARK,
  1471. };
  1472. static const unsigned int scifb2_ctrl_pins[] = {
  1473. /* SCIFB2_RTS, SCIFB2_CTS */
  1474. 73, 66,
  1475. };
  1476. static const unsigned int scifb2_ctrl_mux[] = {
  1477. SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
  1478. };
  1479. static const unsigned int scifb2_data_b_pins[] = {
  1480. /* SCIFB2_RXD, SCIFB2_TXD */
  1481. 297, 295,
  1482. };
  1483. static const unsigned int scifb2_data_b_mux[] = {
  1484. SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
  1485. };
  1486. static const unsigned int scifb2_clk_b_pins[] = {
  1487. /* SCIFB2_SCK */
  1488. 299,
  1489. };
  1490. static const unsigned int scifb2_clk_b_mux[] = {
  1491. SCIFB2_SCK_299_MARK,
  1492. };
  1493. static const unsigned int scifb2_ctrl_b_pins[] = {
  1494. /* SCIFB2_RTS, SCIFB2_CTS */
  1495. 300, 298,
  1496. };
  1497. static const unsigned int scifb2_ctrl_b_mux[] = {
  1498. SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
  1499. };
  1500. /* - SCIFB3 ----------------------------------------------------------------- */
  1501. static const unsigned int scifb3_data_pins[] = {
  1502. /* SCIFB3_RXD, SCIFB3_TXD */
  1503. 22, 21,
  1504. };
  1505. static const unsigned int scifb3_data_mux[] = {
  1506. SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
  1507. };
  1508. static const unsigned int scifb3_clk_pins[] = {
  1509. /* SCIFB3_SCK */
  1510. 23,
  1511. };
  1512. static const unsigned int scifb3_clk_mux[] = {
  1513. SCIFB3_SCK_23_MARK,
  1514. };
  1515. static const unsigned int scifb3_ctrl_pins[] = {
  1516. /* SCIFB3_RTS, SCIFB3_CTS */
  1517. 19, 20,
  1518. };
  1519. static const unsigned int scifb3_ctrl_mux[] = {
  1520. SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
  1521. };
  1522. static const unsigned int scifb3_data_b_pins[] = {
  1523. /* SCIFB3_RXD, SCIFB3_TXD */
  1524. 120, 121,
  1525. };
  1526. static const unsigned int scifb3_data_b_mux[] = {
  1527. SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
  1528. };
  1529. static const unsigned int scifb3_clk_b_pins[] = {
  1530. /* SCIFB3_SCK */
  1531. 40,
  1532. };
  1533. static const unsigned int scifb3_clk_b_mux[] = {
  1534. SCIFB3_SCK_40_MARK,
  1535. };
  1536. static const unsigned int scifb3_ctrl_b_pins[] = {
  1537. /* SCIFB3_RTS, SCIFB3_CTS */
  1538. 38, 39,
  1539. };
  1540. static const unsigned int scifb3_ctrl_b_mux[] = {
  1541. SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
  1542. };
  1543. /* - SDHI0 ------------------------------------------------------------------ */
  1544. static const unsigned int sdhi0_data1_pins[] = {
  1545. /* D0 */
  1546. 302,
  1547. };
  1548. static const unsigned int sdhi0_data1_mux[] = {
  1549. SDHID0_0_MARK,
  1550. };
  1551. static const unsigned int sdhi0_data4_pins[] = {
  1552. /* D[0:3] */
  1553. 302, 303, 304, 305,
  1554. };
  1555. static const unsigned int sdhi0_data4_mux[] = {
  1556. SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
  1557. };
  1558. static const unsigned int sdhi0_ctrl_pins[] = {
  1559. /* CLK, CMD */
  1560. 308, 306,
  1561. };
  1562. static const unsigned int sdhi0_ctrl_mux[] = {
  1563. SDHICLK0_MARK, SDHICMD0_MARK,
  1564. };
  1565. static const unsigned int sdhi0_cd_pins[] = {
  1566. /* CD */
  1567. 301,
  1568. };
  1569. static const unsigned int sdhi0_cd_mux[] = {
  1570. SDHICD0_MARK,
  1571. };
  1572. static const unsigned int sdhi0_wp_pins[] = {
  1573. /* WP */
  1574. 307,
  1575. };
  1576. static const unsigned int sdhi0_wp_mux[] = {
  1577. SDHIWP0_MARK,
  1578. };
  1579. /* - SDHI1 ------------------------------------------------------------------ */
  1580. static const unsigned int sdhi1_data1_pins[] = {
  1581. /* D0 */
  1582. 289,
  1583. };
  1584. static const unsigned int sdhi1_data1_mux[] = {
  1585. SDHID1_0_MARK,
  1586. };
  1587. static const unsigned int sdhi1_data4_pins[] = {
  1588. /* D[0:3] */
  1589. 289, 290, 291, 292,
  1590. };
  1591. static const unsigned int sdhi1_data4_mux[] = {
  1592. SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
  1593. };
  1594. static const unsigned int sdhi1_ctrl_pins[] = {
  1595. /* CLK, CMD */
  1596. 293, 294,
  1597. };
  1598. static const unsigned int sdhi1_ctrl_mux[] = {
  1599. SDHICLK1_MARK, SDHICMD1_MARK,
  1600. };
  1601. /* - SDHI2 ------------------------------------------------------------------ */
  1602. static const unsigned int sdhi2_data1_pins[] = {
  1603. /* D0 */
  1604. 295,
  1605. };
  1606. static const unsigned int sdhi2_data1_mux[] = {
  1607. SDHID2_0_MARK,
  1608. };
  1609. static const unsigned int sdhi2_data4_pins[] = {
  1610. /* D[0:3] */
  1611. 295, 296, 297, 298,
  1612. };
  1613. static const unsigned int sdhi2_data4_mux[] = {
  1614. SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
  1615. };
  1616. static const unsigned int sdhi2_ctrl_pins[] = {
  1617. /* CLK, CMD */
  1618. 299, 300,
  1619. };
  1620. static const unsigned int sdhi2_ctrl_mux[] = {
  1621. SDHICLK2_MARK, SDHICMD2_MARK,
  1622. };
  1623. static const struct sh_pfc_pin_group pinmux_groups[] = {
  1624. SH_PFC_PIN_GROUP(irqc_irq0),
  1625. SH_PFC_PIN_GROUP(irqc_irq1),
  1626. SH_PFC_PIN_GROUP(irqc_irq2),
  1627. SH_PFC_PIN_GROUP(irqc_irq3),
  1628. SH_PFC_PIN_GROUP(irqc_irq4),
  1629. SH_PFC_PIN_GROUP(irqc_irq5),
  1630. SH_PFC_PIN_GROUP(irqc_irq6),
  1631. SH_PFC_PIN_GROUP(irqc_irq7),
  1632. SH_PFC_PIN_GROUP(irqc_irq8),
  1633. SH_PFC_PIN_GROUP(irqc_irq9),
  1634. SH_PFC_PIN_GROUP(irqc_irq10),
  1635. SH_PFC_PIN_GROUP(irqc_irq11),
  1636. SH_PFC_PIN_GROUP(irqc_irq12),
  1637. SH_PFC_PIN_GROUP(irqc_irq13),
  1638. SH_PFC_PIN_GROUP(irqc_irq14),
  1639. SH_PFC_PIN_GROUP(irqc_irq15),
  1640. SH_PFC_PIN_GROUP(irqc_irq16),
  1641. SH_PFC_PIN_GROUP(irqc_irq17),
  1642. SH_PFC_PIN_GROUP(irqc_irq18),
  1643. SH_PFC_PIN_GROUP(irqc_irq19),
  1644. SH_PFC_PIN_GROUP(irqc_irq20),
  1645. SH_PFC_PIN_GROUP(irqc_irq21),
  1646. SH_PFC_PIN_GROUP(irqc_irq22),
  1647. SH_PFC_PIN_GROUP(irqc_irq23),
  1648. SH_PFC_PIN_GROUP(irqc_irq24),
  1649. SH_PFC_PIN_GROUP(irqc_irq25),
  1650. SH_PFC_PIN_GROUP(irqc_irq26),
  1651. SH_PFC_PIN_GROUP(irqc_irq27),
  1652. SH_PFC_PIN_GROUP(irqc_irq28),
  1653. SH_PFC_PIN_GROUP(irqc_irq29),
  1654. SH_PFC_PIN_GROUP(irqc_irq30),
  1655. SH_PFC_PIN_GROUP(irqc_irq31),
  1656. SH_PFC_PIN_GROUP(irqc_irq32),
  1657. SH_PFC_PIN_GROUP(irqc_irq33),
  1658. SH_PFC_PIN_GROUP(irqc_irq34),
  1659. SH_PFC_PIN_GROUP(irqc_irq35),
  1660. SH_PFC_PIN_GROUP(irqc_irq36),
  1661. SH_PFC_PIN_GROUP(irqc_irq37),
  1662. SH_PFC_PIN_GROUP(irqc_irq38),
  1663. SH_PFC_PIN_GROUP(irqc_irq39),
  1664. SH_PFC_PIN_GROUP(irqc_irq40),
  1665. SH_PFC_PIN_GROUP(irqc_irq41),
  1666. SH_PFC_PIN_GROUP(irqc_irq42),
  1667. SH_PFC_PIN_GROUP(irqc_irq43),
  1668. SH_PFC_PIN_GROUP(irqc_irq44),
  1669. SH_PFC_PIN_GROUP(irqc_irq45),
  1670. SH_PFC_PIN_GROUP(irqc_irq46),
  1671. SH_PFC_PIN_GROUP(irqc_irq47),
  1672. SH_PFC_PIN_GROUP(irqc_irq48),
  1673. SH_PFC_PIN_GROUP(irqc_irq49),
  1674. SH_PFC_PIN_GROUP(irqc_irq50),
  1675. SH_PFC_PIN_GROUP(irqc_irq51),
  1676. SH_PFC_PIN_GROUP(irqc_irq52),
  1677. SH_PFC_PIN_GROUP(irqc_irq53),
  1678. SH_PFC_PIN_GROUP(irqc_irq54),
  1679. SH_PFC_PIN_GROUP(irqc_irq55),
  1680. SH_PFC_PIN_GROUP(irqc_irq56),
  1681. SH_PFC_PIN_GROUP(irqc_irq57),
  1682. SH_PFC_PIN_GROUP(mmc0_data1),
  1683. SH_PFC_PIN_GROUP(mmc0_data4),
  1684. SH_PFC_PIN_GROUP(mmc0_data8),
  1685. SH_PFC_PIN_GROUP(mmc0_ctrl),
  1686. SH_PFC_PIN_GROUP(mmc1_data1),
  1687. SH_PFC_PIN_GROUP(mmc1_data4),
  1688. SH_PFC_PIN_GROUP(mmc1_data8),
  1689. SH_PFC_PIN_GROUP(mmc1_ctrl),
  1690. SH_PFC_PIN_GROUP(scifa0_data),
  1691. SH_PFC_PIN_GROUP(scifa0_clk),
  1692. SH_PFC_PIN_GROUP(scifa0_ctrl),
  1693. SH_PFC_PIN_GROUP(scifa1_data),
  1694. SH_PFC_PIN_GROUP(scifa1_clk),
  1695. SH_PFC_PIN_GROUP(scifa1_ctrl),
  1696. SH_PFC_PIN_GROUP(scifb0_data),
  1697. SH_PFC_PIN_GROUP(scifb0_clk),
  1698. SH_PFC_PIN_GROUP(scifb0_ctrl),
  1699. SH_PFC_PIN_GROUP(scifb1_data),
  1700. SH_PFC_PIN_GROUP(scifb1_clk),
  1701. SH_PFC_PIN_GROUP(scifb1_ctrl),
  1702. SH_PFC_PIN_GROUP(scifb1_data_b),
  1703. SH_PFC_PIN_GROUP(scifb1_clk_b),
  1704. SH_PFC_PIN_GROUP(scifb1_ctrl_b),
  1705. SH_PFC_PIN_GROUP(scifb2_data),
  1706. SH_PFC_PIN_GROUP(scifb2_clk),
  1707. SH_PFC_PIN_GROUP(scifb2_ctrl),
  1708. SH_PFC_PIN_GROUP(scifb2_data_b),
  1709. SH_PFC_PIN_GROUP(scifb2_clk_b),
  1710. SH_PFC_PIN_GROUP(scifb2_ctrl_b),
  1711. SH_PFC_PIN_GROUP(scifb3_data),
  1712. SH_PFC_PIN_GROUP(scifb3_clk),
  1713. SH_PFC_PIN_GROUP(scifb3_ctrl),
  1714. SH_PFC_PIN_GROUP(scifb3_data_b),
  1715. SH_PFC_PIN_GROUP(scifb3_clk_b),
  1716. SH_PFC_PIN_GROUP(scifb3_ctrl_b),
  1717. SH_PFC_PIN_GROUP(sdhi0_data1),
  1718. SH_PFC_PIN_GROUP(sdhi0_data4),
  1719. SH_PFC_PIN_GROUP(sdhi0_ctrl),
  1720. SH_PFC_PIN_GROUP(sdhi0_cd),
  1721. SH_PFC_PIN_GROUP(sdhi0_wp),
  1722. SH_PFC_PIN_GROUP(sdhi1_data1),
  1723. SH_PFC_PIN_GROUP(sdhi1_data4),
  1724. SH_PFC_PIN_GROUP(sdhi1_ctrl),
  1725. SH_PFC_PIN_GROUP(sdhi2_data1),
  1726. SH_PFC_PIN_GROUP(sdhi2_data4),
  1727. SH_PFC_PIN_GROUP(sdhi2_ctrl),
  1728. };
  1729. static const char * const irqc_groups[] = {
  1730. "irqc_irq0",
  1731. "irqc_irq1",
  1732. "irqc_irq2",
  1733. "irqc_irq3",
  1734. "irqc_irq4",
  1735. "irqc_irq5",
  1736. "irqc_irq6",
  1737. "irqc_irq7",
  1738. "irqc_irq8",
  1739. "irqc_irq9",
  1740. "irqc_irq10",
  1741. "irqc_irq11",
  1742. "irqc_irq12",
  1743. "irqc_irq13",
  1744. "irqc_irq14",
  1745. "irqc_irq15",
  1746. "irqc_irq16",
  1747. "irqc_irq17",
  1748. "irqc_irq18",
  1749. "irqc_irq19",
  1750. "irqc_irq20",
  1751. "irqc_irq21",
  1752. "irqc_irq22",
  1753. "irqc_irq23",
  1754. "irqc_irq24",
  1755. "irqc_irq25",
  1756. "irqc_irq26",
  1757. "irqc_irq27",
  1758. "irqc_irq28",
  1759. "irqc_irq29",
  1760. "irqc_irq30",
  1761. "irqc_irq31",
  1762. "irqc_irq32",
  1763. "irqc_irq33",
  1764. "irqc_irq34",
  1765. "irqc_irq35",
  1766. "irqc_irq36",
  1767. "irqc_irq37",
  1768. "irqc_irq38",
  1769. "irqc_irq39",
  1770. "irqc_irq40",
  1771. "irqc_irq41",
  1772. "irqc_irq42",
  1773. "irqc_irq43",
  1774. "irqc_irq44",
  1775. "irqc_irq45",
  1776. "irqc_irq46",
  1777. "irqc_irq47",
  1778. "irqc_irq48",
  1779. "irqc_irq49",
  1780. "irqc_irq50",
  1781. "irqc_irq51",
  1782. "irqc_irq52",
  1783. "irqc_irq53",
  1784. "irqc_irq54",
  1785. "irqc_irq55",
  1786. "irqc_irq56",
  1787. "irqc_irq57",
  1788. };
  1789. static const char * const mmc0_groups[] = {
  1790. "mmc0_data1",
  1791. "mmc0_data4",
  1792. "mmc0_data8",
  1793. "mmc0_ctrl",
  1794. };
  1795. static const char * const mmc1_groups[] = {
  1796. "mmc1_data1",
  1797. "mmc1_data4",
  1798. "mmc1_data8",
  1799. "mmc1_ctrl",
  1800. };
  1801. static const char * const scifa0_groups[] = {
  1802. "scifa0_data",
  1803. "scifa0_clk",
  1804. "scifa0_ctrl",
  1805. };
  1806. static const char * const scifa1_groups[] = {
  1807. "scifa1_data",
  1808. "scifa1_clk",
  1809. "scifa1_ctrl",
  1810. };
  1811. static const char * const scifb0_groups[] = {
  1812. "scifb0_data",
  1813. "scifb0_clk",
  1814. "scifb0_ctrl",
  1815. };
  1816. static const char * const scifb1_groups[] = {
  1817. "scifb1_data",
  1818. "scifb1_clk",
  1819. "scifb1_ctrl",
  1820. "scifb1_data_b",
  1821. "scifb1_clk_b",
  1822. "scifb1_ctrl_b",
  1823. };
  1824. static const char * const scifb2_groups[] = {
  1825. "scifb2_data",
  1826. "scifb2_clk",
  1827. "scifb2_ctrl",
  1828. "scifb2_data_b",
  1829. "scifb2_clk_b",
  1830. "scifb2_ctrl_b",
  1831. };
  1832. static const char * const scifb3_groups[] = {
  1833. "scifb3_data",
  1834. "scifb3_clk",
  1835. "scifb3_ctrl",
  1836. "scifb3_data_b",
  1837. "scifb3_clk_b",
  1838. "scifb3_ctrl_b",
  1839. };
  1840. static const char * const sdhi0_groups[] = {
  1841. "sdhi0_data1",
  1842. "sdhi0_data4",
  1843. "sdhi0_ctrl",
  1844. "sdhi0_cd",
  1845. "sdhi0_wp",
  1846. };
  1847. static const char * const sdhi1_groups[] = {
  1848. "sdhi1_data1",
  1849. "sdhi1_data4",
  1850. "sdhi1_ctrl",
  1851. };
  1852. static const char * const sdhi2_groups[] = {
  1853. "sdhi2_data1",
  1854. "sdhi2_data4",
  1855. "sdhi2_ctrl",
  1856. };
  1857. static const struct sh_pfc_function pinmux_functions[] = {
  1858. SH_PFC_FUNCTION(irqc),
  1859. SH_PFC_FUNCTION(mmc0),
  1860. SH_PFC_FUNCTION(mmc1),
  1861. SH_PFC_FUNCTION(scifa0),
  1862. SH_PFC_FUNCTION(scifa1),
  1863. SH_PFC_FUNCTION(scifb0),
  1864. SH_PFC_FUNCTION(scifb1),
  1865. SH_PFC_FUNCTION(scifb2),
  1866. SH_PFC_FUNCTION(scifb3),
  1867. SH_PFC_FUNCTION(sdhi0),
  1868. SH_PFC_FUNCTION(sdhi1),
  1869. SH_PFC_FUNCTION(sdhi2),
  1870. };
  1871. static const struct pinmux_cfg_reg pinmux_config_regs[] = {
  1872. PORTCR(0, 0xe6050000),
  1873. PORTCR(1, 0xe6050001),
  1874. PORTCR(2, 0xe6050002),
  1875. PORTCR(3, 0xe6050003),
  1876. PORTCR(4, 0xe6050004),
  1877. PORTCR(5, 0xe6050005),
  1878. PORTCR(6, 0xe6050006),
  1879. PORTCR(7, 0xe6050007),
  1880. PORTCR(8, 0xe6050008),
  1881. PORTCR(9, 0xe6050009),
  1882. PORTCR(10, 0xe605000A),
  1883. PORTCR(11, 0xe605000B),
  1884. PORTCR(12, 0xe605000C),
  1885. PORTCR(13, 0xe605000D),
  1886. PORTCR(14, 0xe605000E),
  1887. PORTCR(15, 0xe605000F),
  1888. PORTCR(16, 0xe6050010),
  1889. PORTCR(17, 0xe6050011),
  1890. PORTCR(18, 0xe6050012),
  1891. PORTCR(19, 0xe6050013),
  1892. PORTCR(20, 0xe6050014),
  1893. PORTCR(21, 0xe6050015),
  1894. PORTCR(22, 0xe6050016),
  1895. PORTCR(23, 0xe6050017),
  1896. PORTCR(24, 0xe6050018),
  1897. PORTCR(25, 0xe6050019),
  1898. PORTCR(26, 0xe605001A),
  1899. PORTCR(27, 0xe605001B),
  1900. PORTCR(28, 0xe605001C),
  1901. PORTCR(29, 0xe605001D),
  1902. PORTCR(30, 0xe605001E),
  1903. PORTCR(32, 0xe6051020),
  1904. PORTCR(33, 0xe6051021),
  1905. PORTCR(34, 0xe6051022),
  1906. PORTCR(35, 0xe6051023),
  1907. PORTCR(36, 0xe6051024),
  1908. PORTCR(37, 0xe6051025),
  1909. PORTCR(38, 0xe6051026),
  1910. PORTCR(39, 0xe6051027),
  1911. PORTCR(40, 0xe6051028),
  1912. PORTCR(64, 0xe6050040),
  1913. PORTCR(65, 0xe6050041),
  1914. PORTCR(66, 0xe6050042),
  1915. PORTCR(67, 0xe6050043),
  1916. PORTCR(68, 0xe6050044),
  1917. PORTCR(69, 0xe6050045),
  1918. PORTCR(70, 0xe6050046),
  1919. PORTCR(71, 0xe6050047),
  1920. PORTCR(72, 0xe6050048),
  1921. PORTCR(73, 0xe6050049),
  1922. PORTCR(74, 0xe605004A),
  1923. PORTCR(75, 0xe605004B),
  1924. PORTCR(76, 0xe605004C),
  1925. PORTCR(77, 0xe605004D),
  1926. PORTCR(78, 0xe605004E),
  1927. PORTCR(79, 0xe605004F),
  1928. PORTCR(80, 0xe6050050),
  1929. PORTCR(81, 0xe6050051),
  1930. PORTCR(82, 0xe6050052),
  1931. PORTCR(83, 0xe6050053),
  1932. PORTCR(84, 0xe6050054),
  1933. PORTCR(85, 0xe6050055),
  1934. PORTCR(96, 0xe6051060),
  1935. PORTCR(97, 0xe6051061),
  1936. PORTCR(98, 0xe6051062),
  1937. PORTCR(99, 0xe6051063),
  1938. PORTCR(100, 0xe6051064),
  1939. PORTCR(101, 0xe6051065),
  1940. PORTCR(102, 0xe6051066),
  1941. PORTCR(103, 0xe6051067),
  1942. PORTCR(104, 0xe6051068),
  1943. PORTCR(105, 0xe6051069),
  1944. PORTCR(106, 0xe605106A),
  1945. PORTCR(107, 0xe605106B),
  1946. PORTCR(108, 0xe605106C),
  1947. PORTCR(109, 0xe605106D),
  1948. PORTCR(110, 0xe605106E),
  1949. PORTCR(111, 0xe605106F),
  1950. PORTCR(112, 0xe6051070),
  1951. PORTCR(113, 0xe6051071),
  1952. PORTCR(114, 0xe6051072),
  1953. PORTCR(115, 0xe6051073),
  1954. PORTCR(116, 0xe6051074),
  1955. PORTCR(117, 0xe6051075),
  1956. PORTCR(118, 0xe6051076),
  1957. PORTCR(119, 0xe6051077),
  1958. PORTCR(120, 0xe6051078),
  1959. PORTCR(121, 0xe6051079),
  1960. PORTCR(122, 0xe605107A),
  1961. PORTCR(123, 0xe605107B),
  1962. PORTCR(124, 0xe605107C),
  1963. PORTCR(125, 0xe605107D),
  1964. PORTCR(126, 0xe605107E),
  1965. PORTCR(128, 0xe6051080),
  1966. PORTCR(129, 0xe6051081),
  1967. PORTCR(130, 0xe6051082),
  1968. PORTCR(131, 0xe6051083),
  1969. PORTCR(132, 0xe6051084),
  1970. PORTCR(133, 0xe6051085),
  1971. PORTCR(134, 0xe6051086),
  1972. PORTCR(160, 0xe60520A0),
  1973. PORTCR(161, 0xe60520A1),
  1974. PORTCR(162, 0xe60520A2),
  1975. PORTCR(163, 0xe60520A3),
  1976. PORTCR(164, 0xe60520A4),
  1977. PORTCR(165, 0xe60520A5),
  1978. PORTCR(166, 0xe60520A6),
  1979. PORTCR(167, 0xe60520A7),
  1980. PORTCR(168, 0xe60520A8),
  1981. PORTCR(169, 0xe60520A9),
  1982. PORTCR(170, 0xe60520AA),
  1983. PORTCR(171, 0xe60520AB),
  1984. PORTCR(172, 0xe60520AC),
  1985. PORTCR(173, 0xe60520AD),
  1986. PORTCR(174, 0xe60520AE),
  1987. PORTCR(175, 0xe60520AF),
  1988. PORTCR(176, 0xe60520B0),
  1989. PORTCR(177, 0xe60520B1),
  1990. PORTCR(178, 0xe60520B2),
  1991. PORTCR(192, 0xe60520C0),
  1992. PORTCR(193, 0xe60520C1),
  1993. PORTCR(194, 0xe60520C2),
  1994. PORTCR(195, 0xe60520C3),
  1995. PORTCR(196, 0xe60520C4),
  1996. PORTCR(197, 0xe60520C5),
  1997. PORTCR(198, 0xe60520C6),
  1998. PORTCR(199, 0xe60520C7),
  1999. PORTCR(200, 0xe60520C8),
  2000. PORTCR(201, 0xe60520C9),
  2001. PORTCR(202, 0xe60520CA),
  2002. PORTCR(203, 0xe60520CB),
  2003. PORTCR(204, 0xe60520CC),
  2004. PORTCR(205, 0xe60520CD),
  2005. PORTCR(206, 0xe60520CE),
  2006. PORTCR(207, 0xe60520CF),
  2007. PORTCR(208, 0xe60520D0),
  2008. PORTCR(209, 0xe60520D1),
  2009. PORTCR(210, 0xe60520D2),
  2010. PORTCR(211, 0xe60520D3),
  2011. PORTCR(212, 0xe60520D4),
  2012. PORTCR(213, 0xe60520D5),
  2013. PORTCR(214, 0xe60520D6),
  2014. PORTCR(215, 0xe60520D7),
  2015. PORTCR(216, 0xe60520D8),
  2016. PORTCR(217, 0xe60520D9),
  2017. PORTCR(218, 0xe60520DA),
  2018. PORTCR(219, 0xe60520DB),
  2019. PORTCR(220, 0xe60520DC),
  2020. PORTCR(221, 0xe60520DD),
  2021. PORTCR(222, 0xe60520DE),
  2022. PORTCR(224, 0xe60520E0),
  2023. PORTCR(225, 0xe60520E1),
  2024. PORTCR(226, 0xe60520E2),
  2025. PORTCR(227, 0xe60520E3),
  2026. PORTCR(228, 0xe60520E4),
  2027. PORTCR(229, 0xe60520E5),
  2028. PORTCR(230, 0xe60520e6),
  2029. PORTCR(231, 0xe60520E7),
  2030. PORTCR(232, 0xe60520E8),
  2031. PORTCR(233, 0xe60520E9),
  2032. PORTCR(234, 0xe60520EA),
  2033. PORTCR(235, 0xe60520EB),
  2034. PORTCR(236, 0xe60520EC),
  2035. PORTCR(237, 0xe60520ED),
  2036. PORTCR(238, 0xe60520EE),
  2037. PORTCR(239, 0xe60520EF),
  2038. PORTCR(240, 0xe60520F0),
  2039. PORTCR(241, 0xe60520F1),
  2040. PORTCR(242, 0xe60520F2),
  2041. PORTCR(243, 0xe60520F3),
  2042. PORTCR(244, 0xe60520F4),
  2043. PORTCR(245, 0xe60520F5),
  2044. PORTCR(246, 0xe60520F6),
  2045. PORTCR(247, 0xe60520F7),
  2046. PORTCR(248, 0xe60520F8),
  2047. PORTCR(249, 0xe60520F9),
  2048. PORTCR(250, 0xe60520FA),
  2049. PORTCR(256, 0xe6052100),
  2050. PORTCR(257, 0xe6052101),
  2051. PORTCR(258, 0xe6052102),
  2052. PORTCR(259, 0xe6052103),
  2053. PORTCR(260, 0xe6052104),
  2054. PORTCR(261, 0xe6052105),
  2055. PORTCR(262, 0xe6052106),
  2056. PORTCR(263, 0xe6052107),
  2057. PORTCR(264, 0xe6052108),
  2058. PORTCR(265, 0xe6052109),
  2059. PORTCR(266, 0xe605210A),
  2060. PORTCR(267, 0xe605210B),
  2061. PORTCR(268, 0xe605210C),
  2062. PORTCR(269, 0xe605210D),
  2063. PORTCR(270, 0xe605210E),
  2064. PORTCR(271, 0xe605210F),
  2065. PORTCR(272, 0xe6052110),
  2066. PORTCR(273, 0xe6052111),
  2067. PORTCR(274, 0xe6052112),
  2068. PORTCR(275, 0xe6052113),
  2069. PORTCR(276, 0xe6052114),
  2070. PORTCR(277, 0xe6052115),
  2071. PORTCR(278, 0xe6052116),
  2072. PORTCR(279, 0xe6052117),
  2073. PORTCR(280, 0xe6052118),
  2074. PORTCR(281, 0xe6052119),
  2075. PORTCR(282, 0xe605211A),
  2076. PORTCR(283, 0xe605211B),
  2077. PORTCR(288, 0xe6053120),
  2078. PORTCR(289, 0xe6053121),
  2079. PORTCR(290, 0xe6053122),
  2080. PORTCR(291, 0xe6053123),
  2081. PORTCR(292, 0xe6053124),
  2082. PORTCR(293, 0xe6053125),
  2083. PORTCR(294, 0xe6053126),
  2084. PORTCR(295, 0xe6053127),
  2085. PORTCR(296, 0xe6053128),
  2086. PORTCR(297, 0xe6053129),
  2087. PORTCR(298, 0xe605312A),
  2088. PORTCR(299, 0xe605312B),
  2089. PORTCR(300, 0xe605312C),
  2090. PORTCR(301, 0xe605312D),
  2091. PORTCR(302, 0xe605312E),
  2092. PORTCR(303, 0xe605312F),
  2093. PORTCR(304, 0xe6053130),
  2094. PORTCR(305, 0xe6053131),
  2095. PORTCR(306, 0xe6053132),
  2096. PORTCR(307, 0xe6053133),
  2097. PORTCR(308, 0xe6053134),
  2098. PORTCR(320, 0xe6053140),
  2099. PORTCR(321, 0xe6053141),
  2100. PORTCR(322, 0xe6053142),
  2101. PORTCR(323, 0xe6053143),
  2102. PORTCR(324, 0xe6053144),
  2103. PORTCR(325, 0xe6053145),
  2104. PORTCR(326, 0xe6053146),
  2105. PORTCR(327, 0xe6053147),
  2106. PORTCR(328, 0xe6053148),
  2107. PORTCR(329, 0xe6053149),
  2108. { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
  2109. MSEL1CR_31_0, MSEL1CR_31_1,
  2110. 0, 0,
  2111. 0, 0,
  2112. 0, 0,
  2113. MSEL1CR_27_0, MSEL1CR_27_1,
  2114. 0, 0,
  2115. MSEL1CR_25_0, MSEL1CR_25_1,
  2116. MSEL1CR_24_0, MSEL1CR_24_1,
  2117. 0, 0,
  2118. MSEL1CR_22_0, MSEL1CR_22_1,
  2119. MSEL1CR_21_0, MSEL1CR_21_1,
  2120. MSEL1CR_20_0, MSEL1CR_20_1,
  2121. MSEL1CR_19_0, MSEL1CR_19_1,
  2122. MSEL1CR_18_0, MSEL1CR_18_1,
  2123. MSEL1CR_17_0, MSEL1CR_17_1,
  2124. MSEL1CR_16_0, MSEL1CR_16_1,
  2125. MSEL1CR_15_0, MSEL1CR_15_1,
  2126. MSEL1CR_14_0, MSEL1CR_14_1,
  2127. MSEL1CR_13_0, MSEL1CR_13_1,
  2128. MSEL1CR_12_0, MSEL1CR_12_1,
  2129. MSEL1CR_11_0, MSEL1CR_11_1,
  2130. MSEL1CR_10_0, MSEL1CR_10_1,
  2131. MSEL1CR_09_0, MSEL1CR_09_1,
  2132. MSEL1CR_08_0, MSEL1CR_08_1,
  2133. MSEL1CR_07_0, MSEL1CR_07_1,
  2134. MSEL1CR_06_0, MSEL1CR_06_1,
  2135. MSEL1CR_05_0, MSEL1CR_05_1,
  2136. MSEL1CR_04_0, MSEL1CR_04_1,
  2137. MSEL1CR_03_0, MSEL1CR_03_1,
  2138. MSEL1CR_02_0, MSEL1CR_02_1,
  2139. MSEL1CR_01_0, MSEL1CR_01_1,
  2140. MSEL1CR_00_0, MSEL1CR_00_1,
  2141. }
  2142. },
  2143. { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
  2144. MSEL3CR_31_0, MSEL3CR_31_1,
  2145. 0, 0,
  2146. 0, 0,
  2147. MSEL3CR_28_0, MSEL3CR_28_1,
  2148. MSEL3CR_27_0, MSEL3CR_27_1,
  2149. MSEL3CR_26_0, MSEL3CR_26_1,
  2150. 0, 0,
  2151. 0, 0,
  2152. MSEL3CR_23_0, MSEL3CR_23_1,
  2153. MSEL3CR_22_0, MSEL3CR_22_1,
  2154. MSEL3CR_21_0, MSEL3CR_21_1,
  2155. MSEL3CR_20_0, MSEL3CR_20_1,
  2156. MSEL3CR_19_0, MSEL3CR_19_1,
  2157. MSEL3CR_18_0, MSEL3CR_18_1,
  2158. MSEL3CR_17_0, MSEL3CR_17_1,
  2159. MSEL3CR_16_0, MSEL3CR_16_1,
  2160. MSEL3CR_15_0, MSEL3CR_15_1,
  2161. 0, 0,
  2162. 0, 0,
  2163. MSEL3CR_12_0, MSEL3CR_12_1,
  2164. MSEL3CR_11_0, MSEL3CR_11_1,
  2165. MSEL3CR_10_0, MSEL3CR_10_1,
  2166. MSEL3CR_09_0, MSEL3CR_09_1,
  2167. 0, 0,
  2168. 0, 0,
  2169. MSEL3CR_06_0, MSEL3CR_06_1,
  2170. 0, 0,
  2171. 0, 0,
  2172. MSEL3CR_03_0, MSEL3CR_03_1,
  2173. 0, 0,
  2174. MSEL3CR_01_0, MSEL3CR_01_1,
  2175. MSEL3CR_00_0, MSEL3CR_00_1,
  2176. }
  2177. },
  2178. { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
  2179. 0, 0,
  2180. MSEL4CR_30_0, MSEL4CR_30_1,
  2181. MSEL4CR_29_0, MSEL4CR_29_1,
  2182. MSEL4CR_28_0, MSEL4CR_28_1,
  2183. MSEL4CR_27_0, MSEL4CR_27_1,
  2184. MSEL4CR_26_0, MSEL4CR_26_1,
  2185. MSEL4CR_25_0, MSEL4CR_25_1,
  2186. MSEL4CR_24_0, MSEL4CR_24_1,
  2187. MSEL4CR_23_0, MSEL4CR_23_1,
  2188. MSEL4CR_22_0, MSEL4CR_22_1,
  2189. MSEL4CR_21_0, MSEL4CR_21_1,
  2190. MSEL4CR_20_0, MSEL4CR_20_1,
  2191. MSEL4CR_19_0, MSEL4CR_19_1,
  2192. MSEL4CR_18_0, MSEL4CR_18_1,
  2193. MSEL4CR_17_0, MSEL4CR_17_1,
  2194. MSEL4CR_16_0, MSEL4CR_16_1,
  2195. MSEL4CR_15_0, MSEL4CR_15_1,
  2196. MSEL4CR_14_0, MSEL4CR_14_1,
  2197. MSEL4CR_13_0, MSEL4CR_13_1,
  2198. MSEL4CR_12_0, MSEL4CR_12_1,
  2199. MSEL4CR_11_0, MSEL4CR_11_1,
  2200. MSEL4CR_10_0, MSEL4CR_10_1,
  2201. MSEL4CR_09_0, MSEL4CR_09_1,
  2202. 0, 0,
  2203. MSEL4CR_07_0, MSEL4CR_07_1,
  2204. 0, 0,
  2205. 0, 0,
  2206. MSEL4CR_04_0, MSEL4CR_04_1,
  2207. 0, 0,
  2208. 0, 0,
  2209. MSEL4CR_01_0, MSEL4CR_01_1,
  2210. 0, 0,
  2211. }
  2212. },
  2213. { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
  2214. MSEL5CR_31_0, MSEL5CR_31_1,
  2215. MSEL5CR_30_0, MSEL5CR_30_1,
  2216. MSEL5CR_29_0, MSEL5CR_29_1,
  2217. MSEL5CR_28_0, MSEL5CR_28_1,
  2218. MSEL5CR_27_0, MSEL5CR_27_1,
  2219. MSEL5CR_26_0, MSEL5CR_26_1,
  2220. MSEL5CR_25_0, MSEL5CR_25_1,
  2221. MSEL5CR_24_0, MSEL5CR_24_1,
  2222. MSEL5CR_23_0, MSEL5CR_23_1,
  2223. MSEL5CR_22_0, MSEL5CR_22_1,
  2224. MSEL5CR_21_0, MSEL5CR_21_1,
  2225. MSEL5CR_20_0, MSEL5CR_20_1,
  2226. MSEL5CR_19_0, MSEL5CR_19_1,
  2227. MSEL5CR_18_0, MSEL5CR_18_1,
  2228. MSEL5CR_17_0, MSEL5CR_17_1,
  2229. MSEL5CR_16_0, MSEL5CR_16_1,
  2230. MSEL5CR_15_0, MSEL5CR_15_1,
  2231. MSEL5CR_14_0, MSEL5CR_14_1,
  2232. MSEL5CR_13_0, MSEL5CR_13_1,
  2233. MSEL5CR_12_0, MSEL5CR_12_1,
  2234. MSEL5CR_11_0, MSEL5CR_11_1,
  2235. MSEL5CR_10_0, MSEL5CR_10_1,
  2236. MSEL5CR_09_0, MSEL5CR_09_1,
  2237. MSEL5CR_08_0, MSEL5CR_08_1,
  2238. MSEL5CR_07_0, MSEL5CR_07_1,
  2239. MSEL5CR_06_0, MSEL5CR_06_1,
  2240. 0, 0,
  2241. 0, 0,
  2242. 0, 0,
  2243. 0, 0,
  2244. 0, 0,
  2245. 0, 0,
  2246. }
  2247. },
  2248. { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
  2249. 0, 0,
  2250. 0, 0,
  2251. 0, 0,
  2252. 0, 0,
  2253. 0, 0,
  2254. 0, 0,
  2255. 0, 0,
  2256. 0, 0,
  2257. 0, 0,
  2258. 0, 0,
  2259. 0, 0,
  2260. 0, 0,
  2261. 0, 0,
  2262. 0, 0,
  2263. 0, 0,
  2264. MSEL8CR_16_0, MSEL8CR_16_1,
  2265. 0, 0,
  2266. 0, 0,
  2267. 0, 0,
  2268. 0, 0,
  2269. 0, 0,
  2270. 0, 0,
  2271. 0, 0,
  2272. 0, 0,
  2273. 0, 0,
  2274. 0, 0,
  2275. 0, 0,
  2276. 0, 0,
  2277. 0, 0,
  2278. 0, 0,
  2279. MSEL8CR_01_0, MSEL8CR_01_1,
  2280. MSEL8CR_00_0, MSEL8CR_00_1,
  2281. }
  2282. },
  2283. { },
  2284. };
  2285. static const struct pinmux_data_reg pinmux_data_regs[] = {
  2286. { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
  2287. 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
  2288. PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
  2289. PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
  2290. PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
  2291. PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
  2292. PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
  2293. PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
  2294. PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
  2295. }
  2296. },
  2297. { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
  2298. 0, 0, 0, 0,
  2299. 0, 0, 0, 0,
  2300. 0, 0, 0, 0,
  2301. 0, 0, 0, 0,
  2302. 0, 0, 0, 0,
  2303. 0, 0, 0, PORT40_DATA,
  2304. PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
  2305. PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
  2306. }
  2307. },
  2308. { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
  2309. 0, 0, 0, 0,
  2310. 0, 0, 0, 0,
  2311. 0, 0, PORT85_DATA, PORT84_DATA,
  2312. PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
  2313. PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
  2314. PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
  2315. PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
  2316. PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
  2317. }
  2318. },
  2319. { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
  2320. 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
  2321. PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
  2322. PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
  2323. PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
  2324. PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
  2325. PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
  2326. PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
  2327. PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
  2328. }
  2329. },
  2330. { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
  2331. 0, 0, 0, 0,
  2332. 0, 0, 0, 0,
  2333. 0, 0, 0, 0,
  2334. 0, 0, 0, 0,
  2335. 0, 0, 0, 0,
  2336. 0, 0, 0, 0,
  2337. 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
  2338. PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
  2339. }
  2340. },
  2341. { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
  2342. 0, 0, 0, 0,
  2343. 0, 0, 0, 0,
  2344. 0, 0, 0, 0,
  2345. 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
  2346. PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
  2347. PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
  2348. PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
  2349. PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
  2350. }
  2351. },
  2352. { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
  2353. 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
  2354. PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
  2355. PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
  2356. PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
  2357. PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
  2358. PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
  2359. PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
  2360. PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
  2361. }
  2362. },
  2363. { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
  2364. 0, 0, 0, 0,
  2365. 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
  2366. PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
  2367. PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
  2368. PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
  2369. PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
  2370. PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
  2371. PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
  2372. }
  2373. },
  2374. { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
  2375. 0, 0, 0, 0,
  2376. PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
  2377. PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
  2378. PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
  2379. PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
  2380. PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
  2381. PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
  2382. PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
  2383. }
  2384. },
  2385. { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
  2386. 0, 0, 0, 0,
  2387. 0, 0, 0, 0,
  2388. 0, 0, 0, PORT308_DATA,
  2389. PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
  2390. PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
  2391. PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
  2392. PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
  2393. PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
  2394. }
  2395. },
  2396. { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
  2397. 0, 0, 0, 0,
  2398. 0, 0, 0, 0,
  2399. 0, 0, 0, 0,
  2400. 0, 0, 0, 0,
  2401. 0, 0, 0, 0,
  2402. 0, 0, PORT329_DATA, PORT328_DATA,
  2403. PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
  2404. PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
  2405. }
  2406. },
  2407. { },
  2408. };
  2409. static const struct pinmux_irq pinmux_irqs[] = {
  2410. PINMUX_IRQ(0), /* IRQ0 */
  2411. PINMUX_IRQ(1), /* IRQ1 */
  2412. PINMUX_IRQ(2), /* IRQ2 */
  2413. PINMUX_IRQ(3), /* IRQ3 */
  2414. PINMUX_IRQ(4), /* IRQ4 */
  2415. PINMUX_IRQ(5), /* IRQ5 */
  2416. PINMUX_IRQ(6), /* IRQ6 */
  2417. PINMUX_IRQ(7), /* IRQ7 */
  2418. PINMUX_IRQ(8), /* IRQ8 */
  2419. PINMUX_IRQ(9), /* IRQ9 */
  2420. PINMUX_IRQ(10), /* IRQ10 */
  2421. PINMUX_IRQ(11), /* IRQ11 */
  2422. PINMUX_IRQ(12), /* IRQ12 */
  2423. PINMUX_IRQ(13), /* IRQ13 */
  2424. PINMUX_IRQ(14), /* IRQ14 */
  2425. PINMUX_IRQ(15), /* IRQ15 */
  2426. PINMUX_IRQ(320), /* IRQ16 */
  2427. PINMUX_IRQ(321), /* IRQ17 */
  2428. PINMUX_IRQ(85), /* IRQ18 */
  2429. PINMUX_IRQ(84), /* IRQ19 */
  2430. PINMUX_IRQ(160), /* IRQ20 */
  2431. PINMUX_IRQ(161), /* IRQ21 */
  2432. PINMUX_IRQ(162), /* IRQ22 */
  2433. PINMUX_IRQ(163), /* IRQ23 */
  2434. PINMUX_IRQ(175), /* IRQ24 */
  2435. PINMUX_IRQ(176), /* IRQ25 */
  2436. PINMUX_IRQ(177), /* IRQ26 */
  2437. PINMUX_IRQ(178), /* IRQ27 */
  2438. PINMUX_IRQ(322), /* IRQ28 */
  2439. PINMUX_IRQ(323), /* IRQ29 */
  2440. PINMUX_IRQ(324), /* IRQ30 */
  2441. PINMUX_IRQ(192), /* IRQ31 */
  2442. PINMUX_IRQ(193), /* IRQ32 */
  2443. PINMUX_IRQ(194), /* IRQ33 */
  2444. PINMUX_IRQ(195), /* IRQ34 */
  2445. PINMUX_IRQ(196), /* IRQ35 */
  2446. PINMUX_IRQ(197), /* IRQ36 */
  2447. PINMUX_IRQ(198), /* IRQ37 */
  2448. PINMUX_IRQ(199), /* IRQ38 */
  2449. PINMUX_IRQ(200), /* IRQ39 */
  2450. PINMUX_IRQ(66), /* IRQ40 */
  2451. PINMUX_IRQ(102), /* IRQ41 */
  2452. PINMUX_IRQ(103), /* IRQ42 */
  2453. PINMUX_IRQ(109), /* IRQ43 */
  2454. PINMUX_IRQ(110), /* IRQ44 */
  2455. PINMUX_IRQ(111), /* IRQ45 */
  2456. PINMUX_IRQ(112), /* IRQ46 */
  2457. PINMUX_IRQ(113), /* IRQ47 */
  2458. PINMUX_IRQ(114), /* IRQ48 */
  2459. PINMUX_IRQ(115), /* IRQ49 */
  2460. PINMUX_IRQ(301), /* IRQ50 */
  2461. PINMUX_IRQ(290), /* IRQ51 */
  2462. PINMUX_IRQ(296), /* IRQ52 */
  2463. PINMUX_IRQ(325), /* IRQ53 */
  2464. PINMUX_IRQ(326), /* IRQ54 */
  2465. PINMUX_IRQ(327), /* IRQ55 */
  2466. PINMUX_IRQ(328), /* IRQ56 */
  2467. PINMUX_IRQ(329), /* IRQ57 */
  2468. };
  2469. #define PORTCR_PULMD_OFF (0 << 6)
  2470. #define PORTCR_PULMD_DOWN (2 << 6)
  2471. #define PORTCR_PULMD_UP (3 << 6)
  2472. #define PORTCR_PULMD_MASK (3 << 6)
  2473. static const unsigned int r8a73a4_portcr_offsets[] = {
  2474. 0x00000000, 0x00001000, 0x00000000, 0x00001000,
  2475. 0x00001000, 0x00002000, 0x00002000, 0x00002000,
  2476. 0x00002000, 0x00003000, 0x00003000,
  2477. };
  2478. static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
  2479. unsigned int pin)
  2480. {
  2481. void __iomem *addr;
  2482. addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
  2483. switch (ioread8(addr) & PORTCR_PULMD_MASK) {
  2484. case PORTCR_PULMD_UP:
  2485. return PIN_CONFIG_BIAS_PULL_UP;
  2486. case PORTCR_PULMD_DOWN:
  2487. return PIN_CONFIG_BIAS_PULL_DOWN;
  2488. case PORTCR_PULMD_OFF:
  2489. default:
  2490. return PIN_CONFIG_BIAS_DISABLE;
  2491. }
  2492. }
  2493. static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
  2494. unsigned int bias)
  2495. {
  2496. void __iomem *addr;
  2497. u32 value;
  2498. addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
  2499. value = ioread8(addr) & ~PORTCR_PULMD_MASK;
  2500. switch (bias) {
  2501. case PIN_CONFIG_BIAS_PULL_UP:
  2502. value |= PORTCR_PULMD_UP;
  2503. break;
  2504. case PIN_CONFIG_BIAS_PULL_DOWN:
  2505. value |= PORTCR_PULMD_DOWN;
  2506. break;
  2507. }
  2508. iowrite8(value, addr);
  2509. }
  2510. static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
  2511. .get_bias = r8a73a4_pinmux_get_bias,
  2512. .set_bias = r8a73a4_pinmux_set_bias,
  2513. };
  2514. const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
  2515. .name = "r8a73a4_pfc",
  2516. .ops = &r8a73a4_pfc_ops,
  2517. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  2518. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  2519. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  2520. .pins = pinmux_pins,
  2521. .nr_pins = ARRAY_SIZE(pinmux_pins),
  2522. .groups = pinmux_groups,
  2523. .nr_groups = ARRAY_SIZE(pinmux_groups),
  2524. .functions = pinmux_functions,
  2525. .nr_functions = ARRAY_SIZE(pinmux_functions),
  2526. .cfg_regs = pinmux_config_regs,
  2527. .data_regs = pinmux_data_regs,
  2528. .pinmux_data = pinmux_data,
  2529. .pinmux_data_size = ARRAY_SIZE(pinmux_data),
  2530. .gpio_irq = pinmux_irqs,
  2531. .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
  2532. };