intel_rapl.c 41 KB

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  1. /*
  2. * Intel Running Average Power Limit (RAPL) Driver
  3. * Copyright (c) 2013, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.
  16. *
  17. */
  18. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  19. #include <linux/kernel.h>
  20. #include <linux/module.h>
  21. #include <linux/list.h>
  22. #include <linux/types.h>
  23. #include <linux/device.h>
  24. #include <linux/slab.h>
  25. #include <linux/log2.h>
  26. #include <linux/bitmap.h>
  27. #include <linux/delay.h>
  28. #include <linux/sysfs.h>
  29. #include <linux/cpu.h>
  30. #include <linux/powercap.h>
  31. #include <asm/iosf_mbi.h>
  32. #include <asm/processor.h>
  33. #include <asm/cpu_device_id.h>
  34. /* bitmasks for RAPL MSRs, used by primitive access functions */
  35. #define ENERGY_STATUS_MASK 0xffffffff
  36. #define POWER_LIMIT1_MASK 0x7FFF
  37. #define POWER_LIMIT1_ENABLE BIT(15)
  38. #define POWER_LIMIT1_CLAMP BIT(16)
  39. #define POWER_LIMIT2_MASK (0x7FFFULL<<32)
  40. #define POWER_LIMIT2_ENABLE BIT_ULL(47)
  41. #define POWER_LIMIT2_CLAMP BIT_ULL(48)
  42. #define POWER_PACKAGE_LOCK BIT_ULL(63)
  43. #define POWER_PP_LOCK BIT(31)
  44. #define TIME_WINDOW1_MASK (0x7FULL<<17)
  45. #define TIME_WINDOW2_MASK (0x7FULL<<49)
  46. #define POWER_UNIT_OFFSET 0
  47. #define POWER_UNIT_MASK 0x0F
  48. #define ENERGY_UNIT_OFFSET 0x08
  49. #define ENERGY_UNIT_MASK 0x1F00
  50. #define TIME_UNIT_OFFSET 0x10
  51. #define TIME_UNIT_MASK 0xF0000
  52. #define POWER_INFO_MAX_MASK (0x7fffULL<<32)
  53. #define POWER_INFO_MIN_MASK (0x7fffULL<<16)
  54. #define POWER_INFO_MAX_TIME_WIN_MASK (0x3fULL<<48)
  55. #define POWER_INFO_THERMAL_SPEC_MASK 0x7fff
  56. #define PERF_STATUS_THROTTLE_TIME_MASK 0xffffffff
  57. #define PP_POLICY_MASK 0x1F
  58. /* Non HW constants */
  59. #define RAPL_PRIMITIVE_DERIVED BIT(1) /* not from raw data */
  60. #define RAPL_PRIMITIVE_DUMMY BIT(2)
  61. #define TIME_WINDOW_MAX_MSEC 40000
  62. #define TIME_WINDOW_MIN_MSEC 250
  63. #define ENERGY_UNIT_SCALE 1000 /* scale from driver unit to powercap unit */
  64. enum unit_type {
  65. ARBITRARY_UNIT, /* no translation */
  66. POWER_UNIT,
  67. ENERGY_UNIT,
  68. TIME_UNIT,
  69. };
  70. enum rapl_domain_type {
  71. RAPL_DOMAIN_PACKAGE, /* entire package/socket */
  72. RAPL_DOMAIN_PP0, /* core power plane */
  73. RAPL_DOMAIN_PP1, /* graphics uncore */
  74. RAPL_DOMAIN_DRAM,/* DRAM control_type */
  75. RAPL_DOMAIN_MAX,
  76. };
  77. enum rapl_domain_msr_id {
  78. RAPL_DOMAIN_MSR_LIMIT,
  79. RAPL_DOMAIN_MSR_STATUS,
  80. RAPL_DOMAIN_MSR_PERF,
  81. RAPL_DOMAIN_MSR_POLICY,
  82. RAPL_DOMAIN_MSR_INFO,
  83. RAPL_DOMAIN_MSR_MAX,
  84. };
  85. /* per domain data, some are optional */
  86. enum rapl_primitives {
  87. ENERGY_COUNTER,
  88. POWER_LIMIT1,
  89. POWER_LIMIT2,
  90. FW_LOCK,
  91. PL1_ENABLE, /* power limit 1, aka long term */
  92. PL1_CLAMP, /* allow frequency to go below OS request */
  93. PL2_ENABLE, /* power limit 2, aka short term, instantaneous */
  94. PL2_CLAMP,
  95. TIME_WINDOW1, /* long term */
  96. TIME_WINDOW2, /* short term */
  97. THERMAL_SPEC_POWER,
  98. MAX_POWER,
  99. MIN_POWER,
  100. MAX_TIME_WINDOW,
  101. THROTTLED_TIME,
  102. PRIORITY_LEVEL,
  103. /* below are not raw primitive data */
  104. AVERAGE_POWER,
  105. NR_RAPL_PRIMITIVES,
  106. };
  107. #define NR_RAW_PRIMITIVES (NR_RAPL_PRIMITIVES - 2)
  108. /* Can be expanded to include events, etc.*/
  109. struct rapl_domain_data {
  110. u64 primitives[NR_RAPL_PRIMITIVES];
  111. unsigned long timestamp;
  112. };
  113. #define DOMAIN_STATE_INACTIVE BIT(0)
  114. #define DOMAIN_STATE_POWER_LIMIT_SET BIT(1)
  115. #define DOMAIN_STATE_BIOS_LOCKED BIT(2)
  116. #define NR_POWER_LIMITS (2)
  117. struct rapl_power_limit {
  118. struct powercap_zone_constraint *constraint;
  119. int prim_id; /* primitive ID used to enable */
  120. struct rapl_domain *domain;
  121. const char *name;
  122. };
  123. static const char pl1_name[] = "long_term";
  124. static const char pl2_name[] = "short_term";
  125. struct rapl_domain {
  126. const char *name;
  127. enum rapl_domain_type id;
  128. int msrs[RAPL_DOMAIN_MSR_MAX];
  129. struct powercap_zone power_zone;
  130. struct rapl_domain_data rdd;
  131. struct rapl_power_limit rpl[NR_POWER_LIMITS];
  132. u64 attr_map; /* track capabilities */
  133. unsigned int state;
  134. unsigned int domain_energy_unit;
  135. int package_id;
  136. };
  137. #define power_zone_to_rapl_domain(_zone) \
  138. container_of(_zone, struct rapl_domain, power_zone)
  139. /* Each physical package contains multiple domains, these are the common
  140. * data across RAPL domains within a package.
  141. */
  142. struct rapl_package {
  143. unsigned int id; /* physical package/socket id */
  144. unsigned int nr_domains;
  145. unsigned long domain_map; /* bit map of active domains */
  146. unsigned int power_unit;
  147. unsigned int energy_unit;
  148. unsigned int time_unit;
  149. struct rapl_domain *domains; /* array of domains, sized at runtime */
  150. struct powercap_zone *power_zone; /* keep track of parent zone */
  151. int nr_cpus; /* active cpus on the package, topology info is lost during
  152. * cpu hotplug. so we have to track ourselves.
  153. */
  154. unsigned long power_limit_irq; /* keep track of package power limit
  155. * notify interrupt enable status.
  156. */
  157. struct list_head plist;
  158. };
  159. struct rapl_defaults {
  160. u8 floor_freq_reg_addr;
  161. int (*check_unit)(struct rapl_package *rp, int cpu);
  162. void (*set_floor_freq)(struct rapl_domain *rd, bool mode);
  163. u64 (*compute_time_window)(struct rapl_package *rp, u64 val,
  164. bool to_raw);
  165. unsigned int dram_domain_energy_unit;
  166. };
  167. static struct rapl_defaults *rapl_defaults;
  168. /* Sideband MBI registers */
  169. #define IOSF_CPU_POWER_BUDGET_CTL_BYT (0x2)
  170. #define IOSF_CPU_POWER_BUDGET_CTL_TNG (0xdf)
  171. #define PACKAGE_PLN_INT_SAVED BIT(0)
  172. #define MAX_PRIM_NAME (32)
  173. /* per domain data. used to describe individual knobs such that access function
  174. * can be consolidated into one instead of many inline functions.
  175. */
  176. struct rapl_primitive_info {
  177. const char *name;
  178. u64 mask;
  179. int shift;
  180. enum rapl_domain_msr_id id;
  181. enum unit_type unit;
  182. u32 flag;
  183. };
  184. #define PRIMITIVE_INFO_INIT(p, m, s, i, u, f) { \
  185. .name = #p, \
  186. .mask = m, \
  187. .shift = s, \
  188. .id = i, \
  189. .unit = u, \
  190. .flag = f \
  191. }
  192. static void rapl_init_domains(struct rapl_package *rp);
  193. static int rapl_read_data_raw(struct rapl_domain *rd,
  194. enum rapl_primitives prim,
  195. bool xlate, u64 *data);
  196. static int rapl_write_data_raw(struct rapl_domain *rd,
  197. enum rapl_primitives prim,
  198. unsigned long long value);
  199. static u64 rapl_unit_xlate(struct rapl_domain *rd, int package,
  200. enum unit_type type, u64 value,
  201. int to_raw);
  202. static void package_power_limit_irq_save(int package_id);
  203. static LIST_HEAD(rapl_packages); /* guarded by CPU hotplug lock */
  204. static const char * const rapl_domain_names[] = {
  205. "package",
  206. "core",
  207. "uncore",
  208. "dram",
  209. };
  210. static struct powercap_control_type *control_type; /* PowerCap Controller */
  211. /* caller to ensure CPU hotplug lock is held */
  212. static struct rapl_package *find_package_by_id(int id)
  213. {
  214. struct rapl_package *rp;
  215. list_for_each_entry(rp, &rapl_packages, plist) {
  216. if (rp->id == id)
  217. return rp;
  218. }
  219. return NULL;
  220. }
  221. /* caller to ensure CPU hotplug lock is held */
  222. static int find_active_cpu_on_package(int package_id)
  223. {
  224. int i;
  225. for_each_online_cpu(i) {
  226. if (topology_physical_package_id(i) == package_id)
  227. return i;
  228. }
  229. /* all CPUs on this package are offline */
  230. return -ENODEV;
  231. }
  232. /* caller must hold cpu hotplug lock */
  233. static void rapl_cleanup_data(void)
  234. {
  235. struct rapl_package *p, *tmp;
  236. list_for_each_entry_safe(p, tmp, &rapl_packages, plist) {
  237. kfree(p->domains);
  238. list_del(&p->plist);
  239. kfree(p);
  240. }
  241. }
  242. static int get_energy_counter(struct powercap_zone *power_zone, u64 *energy_raw)
  243. {
  244. struct rapl_domain *rd;
  245. u64 energy_now;
  246. /* prevent CPU hotplug, make sure the RAPL domain does not go
  247. * away while reading the counter.
  248. */
  249. get_online_cpus();
  250. rd = power_zone_to_rapl_domain(power_zone);
  251. if (!rapl_read_data_raw(rd, ENERGY_COUNTER, true, &energy_now)) {
  252. *energy_raw = energy_now;
  253. put_online_cpus();
  254. return 0;
  255. }
  256. put_online_cpus();
  257. return -EIO;
  258. }
  259. static int get_max_energy_counter(struct powercap_zone *pcd_dev, u64 *energy)
  260. {
  261. struct rapl_domain *rd = power_zone_to_rapl_domain(pcd_dev);
  262. *energy = rapl_unit_xlate(rd, 0, ENERGY_UNIT, ENERGY_STATUS_MASK, 0);
  263. return 0;
  264. }
  265. static int release_zone(struct powercap_zone *power_zone)
  266. {
  267. struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
  268. struct rapl_package *rp;
  269. /* package zone is the last zone of a package, we can free
  270. * memory here since all children has been unregistered.
  271. */
  272. if (rd->id == RAPL_DOMAIN_PACKAGE) {
  273. rp = find_package_by_id(rd->package_id);
  274. if (!rp) {
  275. dev_warn(&power_zone->dev, "no package id %s\n",
  276. rd->name);
  277. return -ENODEV;
  278. }
  279. kfree(rd);
  280. rp->domains = NULL;
  281. }
  282. return 0;
  283. }
  284. static int find_nr_power_limit(struct rapl_domain *rd)
  285. {
  286. int i;
  287. for (i = 0; i < NR_POWER_LIMITS; i++) {
  288. if (rd->rpl[i].name == NULL)
  289. break;
  290. }
  291. return i;
  292. }
  293. static int set_domain_enable(struct powercap_zone *power_zone, bool mode)
  294. {
  295. struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
  296. if (rd->state & DOMAIN_STATE_BIOS_LOCKED)
  297. return -EACCES;
  298. get_online_cpus();
  299. rapl_write_data_raw(rd, PL1_ENABLE, mode);
  300. if (rapl_defaults->set_floor_freq)
  301. rapl_defaults->set_floor_freq(rd, mode);
  302. put_online_cpus();
  303. return 0;
  304. }
  305. static int get_domain_enable(struct powercap_zone *power_zone, bool *mode)
  306. {
  307. struct rapl_domain *rd = power_zone_to_rapl_domain(power_zone);
  308. u64 val;
  309. if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
  310. *mode = false;
  311. return 0;
  312. }
  313. get_online_cpus();
  314. if (rapl_read_data_raw(rd, PL1_ENABLE, true, &val)) {
  315. put_online_cpus();
  316. return -EIO;
  317. }
  318. *mode = val;
  319. put_online_cpus();
  320. return 0;
  321. }
  322. /* per RAPL domain ops, in the order of rapl_domain_type */
  323. static struct powercap_zone_ops zone_ops[] = {
  324. /* RAPL_DOMAIN_PACKAGE */
  325. {
  326. .get_energy_uj = get_energy_counter,
  327. .get_max_energy_range_uj = get_max_energy_counter,
  328. .release = release_zone,
  329. .set_enable = set_domain_enable,
  330. .get_enable = get_domain_enable,
  331. },
  332. /* RAPL_DOMAIN_PP0 */
  333. {
  334. .get_energy_uj = get_energy_counter,
  335. .get_max_energy_range_uj = get_max_energy_counter,
  336. .release = release_zone,
  337. .set_enable = set_domain_enable,
  338. .get_enable = get_domain_enable,
  339. },
  340. /* RAPL_DOMAIN_PP1 */
  341. {
  342. .get_energy_uj = get_energy_counter,
  343. .get_max_energy_range_uj = get_max_energy_counter,
  344. .release = release_zone,
  345. .set_enable = set_domain_enable,
  346. .get_enable = get_domain_enable,
  347. },
  348. /* RAPL_DOMAIN_DRAM */
  349. {
  350. .get_energy_uj = get_energy_counter,
  351. .get_max_energy_range_uj = get_max_energy_counter,
  352. .release = release_zone,
  353. .set_enable = set_domain_enable,
  354. .get_enable = get_domain_enable,
  355. },
  356. };
  357. static int set_power_limit(struct powercap_zone *power_zone, int id,
  358. u64 power_limit)
  359. {
  360. struct rapl_domain *rd;
  361. struct rapl_package *rp;
  362. int ret = 0;
  363. get_online_cpus();
  364. rd = power_zone_to_rapl_domain(power_zone);
  365. rp = find_package_by_id(rd->package_id);
  366. if (!rp) {
  367. ret = -ENODEV;
  368. goto set_exit;
  369. }
  370. if (rd->state & DOMAIN_STATE_BIOS_LOCKED) {
  371. dev_warn(&power_zone->dev, "%s locked by BIOS, monitoring only\n",
  372. rd->name);
  373. ret = -EACCES;
  374. goto set_exit;
  375. }
  376. switch (rd->rpl[id].prim_id) {
  377. case PL1_ENABLE:
  378. rapl_write_data_raw(rd, POWER_LIMIT1, power_limit);
  379. break;
  380. case PL2_ENABLE:
  381. rapl_write_data_raw(rd, POWER_LIMIT2, power_limit);
  382. break;
  383. default:
  384. ret = -EINVAL;
  385. }
  386. if (!ret)
  387. package_power_limit_irq_save(rd->package_id);
  388. set_exit:
  389. put_online_cpus();
  390. return ret;
  391. }
  392. static int get_current_power_limit(struct powercap_zone *power_zone, int id,
  393. u64 *data)
  394. {
  395. struct rapl_domain *rd;
  396. u64 val;
  397. int prim;
  398. int ret = 0;
  399. get_online_cpus();
  400. rd = power_zone_to_rapl_domain(power_zone);
  401. switch (rd->rpl[id].prim_id) {
  402. case PL1_ENABLE:
  403. prim = POWER_LIMIT1;
  404. break;
  405. case PL2_ENABLE:
  406. prim = POWER_LIMIT2;
  407. break;
  408. default:
  409. put_online_cpus();
  410. return -EINVAL;
  411. }
  412. if (rapl_read_data_raw(rd, prim, true, &val))
  413. ret = -EIO;
  414. else
  415. *data = val;
  416. put_online_cpus();
  417. return ret;
  418. }
  419. static int set_time_window(struct powercap_zone *power_zone, int id,
  420. u64 window)
  421. {
  422. struct rapl_domain *rd;
  423. int ret = 0;
  424. get_online_cpus();
  425. rd = power_zone_to_rapl_domain(power_zone);
  426. switch (rd->rpl[id].prim_id) {
  427. case PL1_ENABLE:
  428. rapl_write_data_raw(rd, TIME_WINDOW1, window);
  429. break;
  430. case PL2_ENABLE:
  431. rapl_write_data_raw(rd, TIME_WINDOW2, window);
  432. break;
  433. default:
  434. ret = -EINVAL;
  435. }
  436. put_online_cpus();
  437. return ret;
  438. }
  439. static int get_time_window(struct powercap_zone *power_zone, int id, u64 *data)
  440. {
  441. struct rapl_domain *rd;
  442. u64 val;
  443. int ret = 0;
  444. get_online_cpus();
  445. rd = power_zone_to_rapl_domain(power_zone);
  446. switch (rd->rpl[id].prim_id) {
  447. case PL1_ENABLE:
  448. ret = rapl_read_data_raw(rd, TIME_WINDOW1, true, &val);
  449. break;
  450. case PL2_ENABLE:
  451. ret = rapl_read_data_raw(rd, TIME_WINDOW2, true, &val);
  452. break;
  453. default:
  454. put_online_cpus();
  455. return -EINVAL;
  456. }
  457. if (!ret)
  458. *data = val;
  459. put_online_cpus();
  460. return ret;
  461. }
  462. static const char *get_constraint_name(struct powercap_zone *power_zone, int id)
  463. {
  464. struct rapl_power_limit *rpl;
  465. struct rapl_domain *rd;
  466. rd = power_zone_to_rapl_domain(power_zone);
  467. rpl = (struct rapl_power_limit *) &rd->rpl[id];
  468. return rpl->name;
  469. }
  470. static int get_max_power(struct powercap_zone *power_zone, int id,
  471. u64 *data)
  472. {
  473. struct rapl_domain *rd;
  474. u64 val;
  475. int prim;
  476. int ret = 0;
  477. get_online_cpus();
  478. rd = power_zone_to_rapl_domain(power_zone);
  479. switch (rd->rpl[id].prim_id) {
  480. case PL1_ENABLE:
  481. prim = THERMAL_SPEC_POWER;
  482. break;
  483. case PL2_ENABLE:
  484. prim = MAX_POWER;
  485. break;
  486. default:
  487. put_online_cpus();
  488. return -EINVAL;
  489. }
  490. if (rapl_read_data_raw(rd, prim, true, &val))
  491. ret = -EIO;
  492. else
  493. *data = val;
  494. put_online_cpus();
  495. return ret;
  496. }
  497. static struct powercap_zone_constraint_ops constraint_ops = {
  498. .set_power_limit_uw = set_power_limit,
  499. .get_power_limit_uw = get_current_power_limit,
  500. .set_time_window_us = set_time_window,
  501. .get_time_window_us = get_time_window,
  502. .get_max_power_uw = get_max_power,
  503. .get_name = get_constraint_name,
  504. };
  505. /* called after domain detection and package level data are set */
  506. static void rapl_init_domains(struct rapl_package *rp)
  507. {
  508. int i;
  509. struct rapl_domain *rd = rp->domains;
  510. for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
  511. unsigned int mask = rp->domain_map & (1 << i);
  512. switch (mask) {
  513. case BIT(RAPL_DOMAIN_PACKAGE):
  514. rd->name = rapl_domain_names[RAPL_DOMAIN_PACKAGE];
  515. rd->id = RAPL_DOMAIN_PACKAGE;
  516. rd->msrs[0] = MSR_PKG_POWER_LIMIT;
  517. rd->msrs[1] = MSR_PKG_ENERGY_STATUS;
  518. rd->msrs[2] = MSR_PKG_PERF_STATUS;
  519. rd->msrs[3] = 0;
  520. rd->msrs[4] = MSR_PKG_POWER_INFO;
  521. rd->rpl[0].prim_id = PL1_ENABLE;
  522. rd->rpl[0].name = pl1_name;
  523. rd->rpl[1].prim_id = PL2_ENABLE;
  524. rd->rpl[1].name = pl2_name;
  525. break;
  526. case BIT(RAPL_DOMAIN_PP0):
  527. rd->name = rapl_domain_names[RAPL_DOMAIN_PP0];
  528. rd->id = RAPL_DOMAIN_PP0;
  529. rd->msrs[0] = MSR_PP0_POWER_LIMIT;
  530. rd->msrs[1] = MSR_PP0_ENERGY_STATUS;
  531. rd->msrs[2] = 0;
  532. rd->msrs[3] = MSR_PP0_POLICY;
  533. rd->msrs[4] = 0;
  534. rd->rpl[0].prim_id = PL1_ENABLE;
  535. rd->rpl[0].name = pl1_name;
  536. break;
  537. case BIT(RAPL_DOMAIN_PP1):
  538. rd->name = rapl_domain_names[RAPL_DOMAIN_PP1];
  539. rd->id = RAPL_DOMAIN_PP1;
  540. rd->msrs[0] = MSR_PP1_POWER_LIMIT;
  541. rd->msrs[1] = MSR_PP1_ENERGY_STATUS;
  542. rd->msrs[2] = 0;
  543. rd->msrs[3] = MSR_PP1_POLICY;
  544. rd->msrs[4] = 0;
  545. rd->rpl[0].prim_id = PL1_ENABLE;
  546. rd->rpl[0].name = pl1_name;
  547. break;
  548. case BIT(RAPL_DOMAIN_DRAM):
  549. rd->name = rapl_domain_names[RAPL_DOMAIN_DRAM];
  550. rd->id = RAPL_DOMAIN_DRAM;
  551. rd->msrs[0] = MSR_DRAM_POWER_LIMIT;
  552. rd->msrs[1] = MSR_DRAM_ENERGY_STATUS;
  553. rd->msrs[2] = MSR_DRAM_PERF_STATUS;
  554. rd->msrs[3] = 0;
  555. rd->msrs[4] = MSR_DRAM_POWER_INFO;
  556. rd->rpl[0].prim_id = PL1_ENABLE;
  557. rd->rpl[0].name = pl1_name;
  558. rd->domain_energy_unit =
  559. rapl_defaults->dram_domain_energy_unit;
  560. if (rd->domain_energy_unit)
  561. pr_info("DRAM domain energy unit %dpj\n",
  562. rd->domain_energy_unit);
  563. break;
  564. }
  565. if (mask) {
  566. rd->package_id = rp->id;
  567. rd++;
  568. }
  569. }
  570. }
  571. static u64 rapl_unit_xlate(struct rapl_domain *rd, int package,
  572. enum unit_type type, u64 value,
  573. int to_raw)
  574. {
  575. u64 units = 1;
  576. struct rapl_package *rp;
  577. u64 scale = 1;
  578. rp = find_package_by_id(package);
  579. if (!rp)
  580. return value;
  581. switch (type) {
  582. case POWER_UNIT:
  583. units = rp->power_unit;
  584. break;
  585. case ENERGY_UNIT:
  586. scale = ENERGY_UNIT_SCALE;
  587. /* per domain unit takes precedence */
  588. if (rd && rd->domain_energy_unit)
  589. units = rd->domain_energy_unit;
  590. else
  591. units = rp->energy_unit;
  592. break;
  593. case TIME_UNIT:
  594. return rapl_defaults->compute_time_window(rp, value, to_raw);
  595. case ARBITRARY_UNIT:
  596. default:
  597. return value;
  598. };
  599. if (to_raw)
  600. return div64_u64(value, units) * scale;
  601. value *= units;
  602. return div64_u64(value, scale);
  603. }
  604. /* in the order of enum rapl_primitives */
  605. static struct rapl_primitive_info rpi[] = {
  606. /* name, mask, shift, msr index, unit divisor */
  607. PRIMITIVE_INFO_INIT(ENERGY_COUNTER, ENERGY_STATUS_MASK, 0,
  608. RAPL_DOMAIN_MSR_STATUS, ENERGY_UNIT, 0),
  609. PRIMITIVE_INFO_INIT(POWER_LIMIT1, POWER_LIMIT1_MASK, 0,
  610. RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
  611. PRIMITIVE_INFO_INIT(POWER_LIMIT2, POWER_LIMIT2_MASK, 32,
  612. RAPL_DOMAIN_MSR_LIMIT, POWER_UNIT, 0),
  613. PRIMITIVE_INFO_INIT(FW_LOCK, POWER_PP_LOCK, 31,
  614. RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
  615. PRIMITIVE_INFO_INIT(PL1_ENABLE, POWER_LIMIT1_ENABLE, 15,
  616. RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
  617. PRIMITIVE_INFO_INIT(PL1_CLAMP, POWER_LIMIT1_CLAMP, 16,
  618. RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
  619. PRIMITIVE_INFO_INIT(PL2_ENABLE, POWER_LIMIT2_ENABLE, 47,
  620. RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
  621. PRIMITIVE_INFO_INIT(PL2_CLAMP, POWER_LIMIT2_CLAMP, 48,
  622. RAPL_DOMAIN_MSR_LIMIT, ARBITRARY_UNIT, 0),
  623. PRIMITIVE_INFO_INIT(TIME_WINDOW1, TIME_WINDOW1_MASK, 17,
  624. RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
  625. PRIMITIVE_INFO_INIT(TIME_WINDOW2, TIME_WINDOW2_MASK, 49,
  626. RAPL_DOMAIN_MSR_LIMIT, TIME_UNIT, 0),
  627. PRIMITIVE_INFO_INIT(THERMAL_SPEC_POWER, POWER_INFO_THERMAL_SPEC_MASK,
  628. 0, RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
  629. PRIMITIVE_INFO_INIT(MAX_POWER, POWER_INFO_MAX_MASK, 32,
  630. RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
  631. PRIMITIVE_INFO_INIT(MIN_POWER, POWER_INFO_MIN_MASK, 16,
  632. RAPL_DOMAIN_MSR_INFO, POWER_UNIT, 0),
  633. PRIMITIVE_INFO_INIT(MAX_TIME_WINDOW, POWER_INFO_MAX_TIME_WIN_MASK, 48,
  634. RAPL_DOMAIN_MSR_INFO, TIME_UNIT, 0),
  635. PRIMITIVE_INFO_INIT(THROTTLED_TIME, PERF_STATUS_THROTTLE_TIME_MASK, 0,
  636. RAPL_DOMAIN_MSR_PERF, TIME_UNIT, 0),
  637. PRIMITIVE_INFO_INIT(PRIORITY_LEVEL, PP_POLICY_MASK, 0,
  638. RAPL_DOMAIN_MSR_POLICY, ARBITRARY_UNIT, 0),
  639. /* non-hardware */
  640. PRIMITIVE_INFO_INIT(AVERAGE_POWER, 0, 0, 0, POWER_UNIT,
  641. RAPL_PRIMITIVE_DERIVED),
  642. {NULL, 0, 0, 0},
  643. };
  644. /* Read primitive data based on its related struct rapl_primitive_info.
  645. * if xlate flag is set, return translated data based on data units, i.e.
  646. * time, energy, and power.
  647. * RAPL MSRs are non-architectual and are laid out not consistently across
  648. * domains. Here we use primitive info to allow writing consolidated access
  649. * functions.
  650. * For a given primitive, it is processed by MSR mask and shift. Unit conversion
  651. * is pre-assigned based on RAPL unit MSRs read at init time.
  652. * 63-------------------------- 31--------------------------- 0
  653. * | xxxxx (mask) |
  654. * | |<- shift ----------------|
  655. * 63-------------------------- 31--------------------------- 0
  656. */
  657. static int rapl_read_data_raw(struct rapl_domain *rd,
  658. enum rapl_primitives prim,
  659. bool xlate, u64 *data)
  660. {
  661. u64 value, final;
  662. u32 msr;
  663. struct rapl_primitive_info *rp = &rpi[prim];
  664. int cpu;
  665. if (!rp->name || rp->flag & RAPL_PRIMITIVE_DUMMY)
  666. return -EINVAL;
  667. msr = rd->msrs[rp->id];
  668. if (!msr)
  669. return -EINVAL;
  670. /* use physical package id to look up active cpus */
  671. cpu = find_active_cpu_on_package(rd->package_id);
  672. if (cpu < 0)
  673. return cpu;
  674. /* special-case package domain, which uses a different bit*/
  675. if (prim == FW_LOCK && rd->id == RAPL_DOMAIN_PACKAGE) {
  676. rp->mask = POWER_PACKAGE_LOCK;
  677. rp->shift = 63;
  678. }
  679. /* non-hardware data are collected by the polling thread */
  680. if (rp->flag & RAPL_PRIMITIVE_DERIVED) {
  681. *data = rd->rdd.primitives[prim];
  682. return 0;
  683. }
  684. if (rdmsrl_safe_on_cpu(cpu, msr, &value)) {
  685. pr_debug("failed to read msr 0x%x on cpu %d\n", msr, cpu);
  686. return -EIO;
  687. }
  688. final = value & rp->mask;
  689. final = final >> rp->shift;
  690. if (xlate)
  691. *data = rapl_unit_xlate(rd, rd->package_id, rp->unit, final, 0);
  692. else
  693. *data = final;
  694. return 0;
  695. }
  696. /* Similar use of primitive info in the read counterpart */
  697. static int rapl_write_data_raw(struct rapl_domain *rd,
  698. enum rapl_primitives prim,
  699. unsigned long long value)
  700. {
  701. u64 msr_val;
  702. u32 msr;
  703. struct rapl_primitive_info *rp = &rpi[prim];
  704. int cpu;
  705. cpu = find_active_cpu_on_package(rd->package_id);
  706. if (cpu < 0)
  707. return cpu;
  708. msr = rd->msrs[rp->id];
  709. if (rdmsrl_safe_on_cpu(cpu, msr, &msr_val)) {
  710. dev_dbg(&rd->power_zone.dev,
  711. "failed to read msr 0x%x on cpu %d\n", msr, cpu);
  712. return -EIO;
  713. }
  714. value = rapl_unit_xlate(rd, rd->package_id, rp->unit, value, 1);
  715. msr_val &= ~rp->mask;
  716. msr_val |= value << rp->shift;
  717. if (wrmsrl_safe_on_cpu(cpu, msr, msr_val)) {
  718. dev_dbg(&rd->power_zone.dev,
  719. "failed to write msr 0x%x on cpu %d\n", msr, cpu);
  720. return -EIO;
  721. }
  722. return 0;
  723. }
  724. /*
  725. * Raw RAPL data stored in MSRs are in certain scales. We need to
  726. * convert them into standard units based on the units reported in
  727. * the RAPL unit MSRs. This is specific to CPUs as the method to
  728. * calculate units differ on different CPUs.
  729. * We convert the units to below format based on CPUs.
  730. * i.e.
  731. * energy unit: picoJoules : Represented in picoJoules by default
  732. * power unit : microWatts : Represented in milliWatts by default
  733. * time unit : microseconds: Represented in seconds by default
  734. */
  735. static int rapl_check_unit_core(struct rapl_package *rp, int cpu)
  736. {
  737. u64 msr_val;
  738. u32 value;
  739. if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
  740. pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
  741. MSR_RAPL_POWER_UNIT, cpu);
  742. return -ENODEV;
  743. }
  744. value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
  745. rp->energy_unit = ENERGY_UNIT_SCALE * 1000000 / (1 << value);
  746. value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
  747. rp->power_unit = 1000000 / (1 << value);
  748. value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
  749. rp->time_unit = 1000000 / (1 << value);
  750. pr_debug("Core CPU package %d energy=%dpJ, time=%dus, power=%duW\n",
  751. rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
  752. return 0;
  753. }
  754. static int rapl_check_unit_atom(struct rapl_package *rp, int cpu)
  755. {
  756. u64 msr_val;
  757. u32 value;
  758. if (rdmsrl_safe_on_cpu(cpu, MSR_RAPL_POWER_UNIT, &msr_val)) {
  759. pr_err("Failed to read power unit MSR 0x%x on CPU %d, exit.\n",
  760. MSR_RAPL_POWER_UNIT, cpu);
  761. return -ENODEV;
  762. }
  763. value = (msr_val & ENERGY_UNIT_MASK) >> ENERGY_UNIT_OFFSET;
  764. rp->energy_unit = ENERGY_UNIT_SCALE * 1 << value;
  765. value = (msr_val & POWER_UNIT_MASK) >> POWER_UNIT_OFFSET;
  766. rp->power_unit = (1 << value) * 1000;
  767. value = (msr_val & TIME_UNIT_MASK) >> TIME_UNIT_OFFSET;
  768. rp->time_unit = 1000000 / (1 << value);
  769. pr_debug("Atom package %d energy=%dpJ, time=%dus, power=%duW\n",
  770. rp->id, rp->energy_unit, rp->time_unit, rp->power_unit);
  771. return 0;
  772. }
  773. /* REVISIT:
  774. * When package power limit is set artificially low by RAPL, LVT
  775. * thermal interrupt for package power limit should be ignored
  776. * since we are not really exceeding the real limit. The intention
  777. * is to avoid excessive interrupts while we are trying to save power.
  778. * A useful feature might be routing the package_power_limit interrupt
  779. * to userspace via eventfd. once we have a usecase, this is simple
  780. * to do by adding an atomic notifier.
  781. */
  782. static void package_power_limit_irq_save(int package_id)
  783. {
  784. u32 l, h = 0;
  785. int cpu;
  786. struct rapl_package *rp;
  787. rp = find_package_by_id(package_id);
  788. if (!rp)
  789. return;
  790. if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
  791. return;
  792. cpu = find_active_cpu_on_package(package_id);
  793. if (cpu < 0)
  794. return;
  795. /* save the state of PLN irq mask bit before disabling it */
  796. rdmsr_safe_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
  797. if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED)) {
  798. rp->power_limit_irq = l & PACKAGE_THERM_INT_PLN_ENABLE;
  799. rp->power_limit_irq |= PACKAGE_PLN_INT_SAVED;
  800. }
  801. l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
  802. wrmsr_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
  803. }
  804. /* restore per package power limit interrupt enable state */
  805. static void package_power_limit_irq_restore(int package_id)
  806. {
  807. u32 l, h;
  808. int cpu;
  809. struct rapl_package *rp;
  810. rp = find_package_by_id(package_id);
  811. if (!rp)
  812. return;
  813. if (!boot_cpu_has(X86_FEATURE_PTS) || !boot_cpu_has(X86_FEATURE_PLN))
  814. return;
  815. cpu = find_active_cpu_on_package(package_id);
  816. if (cpu < 0)
  817. return;
  818. /* irq enable state not saved, nothing to restore */
  819. if (!(rp->power_limit_irq & PACKAGE_PLN_INT_SAVED))
  820. return;
  821. rdmsr_safe_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, &l, &h);
  822. if (rp->power_limit_irq & PACKAGE_THERM_INT_PLN_ENABLE)
  823. l |= PACKAGE_THERM_INT_PLN_ENABLE;
  824. else
  825. l &= ~PACKAGE_THERM_INT_PLN_ENABLE;
  826. wrmsr_on_cpu(cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
  827. }
  828. static void set_floor_freq_default(struct rapl_domain *rd, bool mode)
  829. {
  830. int nr_powerlimit = find_nr_power_limit(rd);
  831. /* always enable clamp such that p-state can go below OS requested
  832. * range. power capping priority over guranteed frequency.
  833. */
  834. rapl_write_data_raw(rd, PL1_CLAMP, mode);
  835. /* some domains have pl2 */
  836. if (nr_powerlimit > 1) {
  837. rapl_write_data_raw(rd, PL2_ENABLE, mode);
  838. rapl_write_data_raw(rd, PL2_CLAMP, mode);
  839. }
  840. }
  841. static void set_floor_freq_atom(struct rapl_domain *rd, bool enable)
  842. {
  843. static u32 power_ctrl_orig_val;
  844. u32 mdata;
  845. if (!rapl_defaults->floor_freq_reg_addr) {
  846. pr_err("Invalid floor frequency config register\n");
  847. return;
  848. }
  849. if (!power_ctrl_orig_val)
  850. iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_PMC_READ,
  851. rapl_defaults->floor_freq_reg_addr,
  852. &power_ctrl_orig_val);
  853. mdata = power_ctrl_orig_val;
  854. if (enable) {
  855. mdata &= ~(0x7f << 8);
  856. mdata |= 1 << 8;
  857. }
  858. iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_PMC_WRITE,
  859. rapl_defaults->floor_freq_reg_addr, mdata);
  860. }
  861. static u64 rapl_compute_time_window_core(struct rapl_package *rp, u64 value,
  862. bool to_raw)
  863. {
  864. u64 f, y; /* fraction and exp. used for time unit */
  865. /*
  866. * Special processing based on 2^Y*(1+F/4), refer
  867. * to Intel Software Developer's manual Vol.3B: CH 14.9.3.
  868. */
  869. if (!to_raw) {
  870. f = (value & 0x60) >> 5;
  871. y = value & 0x1f;
  872. value = (1 << y) * (4 + f) * rp->time_unit / 4;
  873. } else {
  874. do_div(value, rp->time_unit);
  875. y = ilog2(value);
  876. f = div64_u64(4 * (value - (1 << y)), 1 << y);
  877. value = (y & 0x1f) | ((f & 0x3) << 5);
  878. }
  879. return value;
  880. }
  881. static u64 rapl_compute_time_window_atom(struct rapl_package *rp, u64 value,
  882. bool to_raw)
  883. {
  884. /*
  885. * Atom time unit encoding is straight forward val * time_unit,
  886. * where time_unit is default to 1 sec. Never 0.
  887. */
  888. if (!to_raw)
  889. return (value) ? value *= rp->time_unit : rp->time_unit;
  890. else
  891. value = div64_u64(value, rp->time_unit);
  892. return value;
  893. }
  894. static const struct rapl_defaults rapl_defaults_core = {
  895. .floor_freq_reg_addr = 0,
  896. .check_unit = rapl_check_unit_core,
  897. .set_floor_freq = set_floor_freq_default,
  898. .compute_time_window = rapl_compute_time_window_core,
  899. };
  900. static const struct rapl_defaults rapl_defaults_hsw_server = {
  901. .check_unit = rapl_check_unit_core,
  902. .set_floor_freq = set_floor_freq_default,
  903. .compute_time_window = rapl_compute_time_window_core,
  904. .dram_domain_energy_unit = 15300,
  905. };
  906. static const struct rapl_defaults rapl_defaults_byt = {
  907. .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_BYT,
  908. .check_unit = rapl_check_unit_atom,
  909. .set_floor_freq = set_floor_freq_atom,
  910. .compute_time_window = rapl_compute_time_window_atom,
  911. };
  912. static const struct rapl_defaults rapl_defaults_tng = {
  913. .floor_freq_reg_addr = IOSF_CPU_POWER_BUDGET_CTL_TNG,
  914. .check_unit = rapl_check_unit_atom,
  915. .set_floor_freq = set_floor_freq_atom,
  916. .compute_time_window = rapl_compute_time_window_atom,
  917. };
  918. static const struct rapl_defaults rapl_defaults_ann = {
  919. .floor_freq_reg_addr = 0,
  920. .check_unit = rapl_check_unit_atom,
  921. .set_floor_freq = NULL,
  922. .compute_time_window = rapl_compute_time_window_atom,
  923. };
  924. static const struct rapl_defaults rapl_defaults_cht = {
  925. .floor_freq_reg_addr = 0,
  926. .check_unit = rapl_check_unit_atom,
  927. .set_floor_freq = NULL,
  928. .compute_time_window = rapl_compute_time_window_atom,
  929. };
  930. #define RAPL_CPU(_model, _ops) { \
  931. .vendor = X86_VENDOR_INTEL, \
  932. .family = 6, \
  933. .model = _model, \
  934. .driver_data = (kernel_ulong_t)&_ops, \
  935. }
  936. static const struct x86_cpu_id rapl_ids[] __initconst = {
  937. RAPL_CPU(0x2a, rapl_defaults_core),/* Sandy Bridge */
  938. RAPL_CPU(0x2d, rapl_defaults_core),/* Sandy Bridge EP */
  939. RAPL_CPU(0x37, rapl_defaults_byt),/* Valleyview */
  940. RAPL_CPU(0x3a, rapl_defaults_core),/* Ivy Bridge */
  941. RAPL_CPU(0x3c, rapl_defaults_core),/* Haswell */
  942. RAPL_CPU(0x3d, rapl_defaults_core),/* Broadwell */
  943. RAPL_CPU(0x3f, rapl_defaults_hsw_server),/* Haswell servers */
  944. RAPL_CPU(0x4f, rapl_defaults_hsw_server),/* Broadwell servers */
  945. RAPL_CPU(0x45, rapl_defaults_core),/* Haswell ULT */
  946. RAPL_CPU(0x47, rapl_defaults_core),/* Broadwell-H */
  947. RAPL_CPU(0x4E, rapl_defaults_core),/* Skylake */
  948. RAPL_CPU(0x4C, rapl_defaults_cht),/* Braswell/Cherryview */
  949. RAPL_CPU(0x4A, rapl_defaults_tng),/* Tangier */
  950. RAPL_CPU(0x56, rapl_defaults_core),/* Future Xeon */
  951. RAPL_CPU(0x5A, rapl_defaults_ann),/* Annidale */
  952. RAPL_CPU(0X5C, rapl_defaults_core),/* Broxton */
  953. RAPL_CPU(0x5E, rapl_defaults_core),/* Skylake-H/S */
  954. RAPL_CPU(0x57, rapl_defaults_hsw_server),/* Knights Landing */
  955. {}
  956. };
  957. MODULE_DEVICE_TABLE(x86cpu, rapl_ids);
  958. /* read once for all raw primitive data for all packages, domains */
  959. static void rapl_update_domain_data(void)
  960. {
  961. int dmn, prim;
  962. u64 val;
  963. struct rapl_package *rp;
  964. list_for_each_entry(rp, &rapl_packages, plist) {
  965. for (dmn = 0; dmn < rp->nr_domains; dmn++) {
  966. pr_debug("update package %d domain %s data\n", rp->id,
  967. rp->domains[dmn].name);
  968. /* exclude non-raw primitives */
  969. for (prim = 0; prim < NR_RAW_PRIMITIVES; prim++)
  970. if (!rapl_read_data_raw(&rp->domains[dmn], prim,
  971. rpi[prim].unit,
  972. &val))
  973. rp->domains[dmn].rdd.primitives[prim] =
  974. val;
  975. }
  976. }
  977. }
  978. static int rapl_unregister_powercap(void)
  979. {
  980. struct rapl_package *rp;
  981. struct rapl_domain *rd, *rd_package = NULL;
  982. /* unregister all active rapl packages from the powercap layer,
  983. * hotplug lock held
  984. */
  985. list_for_each_entry(rp, &rapl_packages, plist) {
  986. package_power_limit_irq_restore(rp->id);
  987. for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
  988. rd++) {
  989. pr_debug("remove package, undo power limit on %d: %s\n",
  990. rp->id, rd->name);
  991. rapl_write_data_raw(rd, PL1_ENABLE, 0);
  992. rapl_write_data_raw(rd, PL1_CLAMP, 0);
  993. if (find_nr_power_limit(rd) > 1) {
  994. rapl_write_data_raw(rd, PL2_ENABLE, 0);
  995. rapl_write_data_raw(rd, PL2_CLAMP, 0);
  996. }
  997. if (rd->id == RAPL_DOMAIN_PACKAGE) {
  998. rd_package = rd;
  999. continue;
  1000. }
  1001. powercap_unregister_zone(control_type, &rd->power_zone);
  1002. }
  1003. /* do the package zone last */
  1004. if (rd_package)
  1005. powercap_unregister_zone(control_type,
  1006. &rd_package->power_zone);
  1007. }
  1008. powercap_unregister_control_type(control_type);
  1009. return 0;
  1010. }
  1011. static int rapl_package_register_powercap(struct rapl_package *rp)
  1012. {
  1013. struct rapl_domain *rd;
  1014. int ret = 0;
  1015. char dev_name[17]; /* max domain name = 7 + 1 + 8 for int + 1 for null*/
  1016. struct powercap_zone *power_zone = NULL;
  1017. int nr_pl;
  1018. /* first we register package domain as the parent zone*/
  1019. for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
  1020. if (rd->id == RAPL_DOMAIN_PACKAGE) {
  1021. nr_pl = find_nr_power_limit(rd);
  1022. pr_debug("register socket %d package domain %s\n",
  1023. rp->id, rd->name);
  1024. memset(dev_name, 0, sizeof(dev_name));
  1025. snprintf(dev_name, sizeof(dev_name), "%s-%d",
  1026. rd->name, rp->id);
  1027. power_zone = powercap_register_zone(&rd->power_zone,
  1028. control_type,
  1029. dev_name, NULL,
  1030. &zone_ops[rd->id],
  1031. nr_pl,
  1032. &constraint_ops);
  1033. if (IS_ERR(power_zone)) {
  1034. pr_debug("failed to register package, %d\n",
  1035. rp->id);
  1036. ret = PTR_ERR(power_zone);
  1037. goto exit_package;
  1038. }
  1039. /* track parent zone in per package/socket data */
  1040. rp->power_zone = power_zone;
  1041. /* done, only one package domain per socket */
  1042. break;
  1043. }
  1044. }
  1045. if (!power_zone) {
  1046. pr_err("no package domain found, unknown topology!\n");
  1047. ret = -ENODEV;
  1048. goto exit_package;
  1049. }
  1050. /* now register domains as children of the socket/package*/
  1051. for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
  1052. if (rd->id == RAPL_DOMAIN_PACKAGE)
  1053. continue;
  1054. /* number of power limits per domain varies */
  1055. nr_pl = find_nr_power_limit(rd);
  1056. power_zone = powercap_register_zone(&rd->power_zone,
  1057. control_type, rd->name,
  1058. rp->power_zone,
  1059. &zone_ops[rd->id], nr_pl,
  1060. &constraint_ops);
  1061. if (IS_ERR(power_zone)) {
  1062. pr_debug("failed to register power_zone, %d:%s:%s\n",
  1063. rp->id, rd->name, dev_name);
  1064. ret = PTR_ERR(power_zone);
  1065. goto err_cleanup;
  1066. }
  1067. }
  1068. exit_package:
  1069. return ret;
  1070. err_cleanup:
  1071. /* clean up previously initialized domains within the package if we
  1072. * failed after the first domain setup.
  1073. */
  1074. while (--rd >= rp->domains) {
  1075. pr_debug("unregister package %d domain %s\n", rp->id, rd->name);
  1076. powercap_unregister_zone(control_type, &rd->power_zone);
  1077. }
  1078. return ret;
  1079. }
  1080. static int rapl_register_powercap(void)
  1081. {
  1082. struct rapl_domain *rd;
  1083. struct rapl_package *rp;
  1084. int ret = 0;
  1085. control_type = powercap_register_control_type(NULL, "intel-rapl", NULL);
  1086. if (IS_ERR(control_type)) {
  1087. pr_debug("failed to register powercap control_type.\n");
  1088. return PTR_ERR(control_type);
  1089. }
  1090. /* read the initial data */
  1091. rapl_update_domain_data();
  1092. list_for_each_entry(rp, &rapl_packages, plist)
  1093. if (rapl_package_register_powercap(rp))
  1094. goto err_cleanup_package;
  1095. return ret;
  1096. err_cleanup_package:
  1097. /* clean up previously initialized packages */
  1098. list_for_each_entry_continue_reverse(rp, &rapl_packages, plist) {
  1099. for (rd = rp->domains; rd < rp->domains + rp->nr_domains;
  1100. rd++) {
  1101. pr_debug("unregister zone/package %d, %s domain\n",
  1102. rp->id, rd->name);
  1103. powercap_unregister_zone(control_type, &rd->power_zone);
  1104. }
  1105. }
  1106. return ret;
  1107. }
  1108. static int rapl_check_domain(int cpu, int domain)
  1109. {
  1110. unsigned msr;
  1111. u64 val = 0;
  1112. switch (domain) {
  1113. case RAPL_DOMAIN_PACKAGE:
  1114. msr = MSR_PKG_ENERGY_STATUS;
  1115. break;
  1116. case RAPL_DOMAIN_PP0:
  1117. msr = MSR_PP0_ENERGY_STATUS;
  1118. break;
  1119. case RAPL_DOMAIN_PP1:
  1120. msr = MSR_PP1_ENERGY_STATUS;
  1121. break;
  1122. case RAPL_DOMAIN_DRAM:
  1123. msr = MSR_DRAM_ENERGY_STATUS;
  1124. break;
  1125. default:
  1126. pr_err("invalid domain id %d\n", domain);
  1127. return -EINVAL;
  1128. }
  1129. /* make sure domain counters are available and contains non-zero
  1130. * values, otherwise skip it.
  1131. */
  1132. if (rdmsrl_safe_on_cpu(cpu, msr, &val) || !val)
  1133. return -ENODEV;
  1134. return 0;
  1135. }
  1136. /* Detect active and valid domains for the given CPU, caller must
  1137. * ensure the CPU belongs to the targeted package and CPU hotlug is disabled.
  1138. */
  1139. static int rapl_detect_domains(struct rapl_package *rp, int cpu)
  1140. {
  1141. int i;
  1142. int ret = 0;
  1143. struct rapl_domain *rd;
  1144. u64 locked;
  1145. for (i = 0; i < RAPL_DOMAIN_MAX; i++) {
  1146. /* use physical package id to read counters */
  1147. if (!rapl_check_domain(cpu, i)) {
  1148. rp->domain_map |= 1 << i;
  1149. pr_info("Found RAPL domain %s\n", rapl_domain_names[i]);
  1150. }
  1151. }
  1152. rp->nr_domains = bitmap_weight(&rp->domain_map, RAPL_DOMAIN_MAX);
  1153. if (!rp->nr_domains) {
  1154. pr_err("no valid rapl domains found in package %d\n", rp->id);
  1155. ret = -ENODEV;
  1156. goto done;
  1157. }
  1158. pr_debug("found %d domains on package %d\n", rp->nr_domains, rp->id);
  1159. rp->domains = kcalloc(rp->nr_domains + 1, sizeof(struct rapl_domain),
  1160. GFP_KERNEL);
  1161. if (!rp->domains) {
  1162. ret = -ENOMEM;
  1163. goto done;
  1164. }
  1165. rapl_init_domains(rp);
  1166. for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
  1167. /* check if the domain is locked by BIOS */
  1168. ret = rapl_read_data_raw(rd, FW_LOCK, false, &locked);
  1169. if (ret)
  1170. return ret;
  1171. if (locked) {
  1172. pr_info("RAPL package %d domain %s locked by BIOS\n",
  1173. rp->id, rd->name);
  1174. rd->state |= DOMAIN_STATE_BIOS_LOCKED;
  1175. }
  1176. }
  1177. done:
  1178. return ret;
  1179. }
  1180. static bool is_package_new(int package)
  1181. {
  1182. struct rapl_package *rp;
  1183. /* caller prevents cpu hotplug, there will be no new packages added
  1184. * or deleted while traversing the package list, no need for locking.
  1185. */
  1186. list_for_each_entry(rp, &rapl_packages, plist)
  1187. if (package == rp->id)
  1188. return false;
  1189. return true;
  1190. }
  1191. /* RAPL interface can be made of a two-level hierarchy: package level and domain
  1192. * level. We first detect the number of packages then domains of each package.
  1193. * We have to consider the possiblity of CPU online/offline due to hotplug and
  1194. * other scenarios.
  1195. */
  1196. static int rapl_detect_topology(void)
  1197. {
  1198. int i;
  1199. int phy_package_id;
  1200. struct rapl_package *new_package, *rp;
  1201. for_each_online_cpu(i) {
  1202. phy_package_id = topology_physical_package_id(i);
  1203. if (is_package_new(phy_package_id)) {
  1204. new_package = kzalloc(sizeof(*rp), GFP_KERNEL);
  1205. if (!new_package) {
  1206. rapl_cleanup_data();
  1207. return -ENOMEM;
  1208. }
  1209. /* add the new package to the list */
  1210. new_package->id = phy_package_id;
  1211. new_package->nr_cpus = 1;
  1212. /* check if the package contains valid domains */
  1213. if (rapl_detect_domains(new_package, i) ||
  1214. rapl_defaults->check_unit(new_package, i)) {
  1215. kfree(new_package->domains);
  1216. kfree(new_package);
  1217. /* free up the packages already initialized */
  1218. rapl_cleanup_data();
  1219. return -ENODEV;
  1220. }
  1221. INIT_LIST_HEAD(&new_package->plist);
  1222. list_add(&new_package->plist, &rapl_packages);
  1223. } else {
  1224. rp = find_package_by_id(phy_package_id);
  1225. if (rp)
  1226. ++rp->nr_cpus;
  1227. }
  1228. }
  1229. return 0;
  1230. }
  1231. /* called from CPU hotplug notifier, hotplug lock held */
  1232. static void rapl_remove_package(struct rapl_package *rp)
  1233. {
  1234. struct rapl_domain *rd, *rd_package = NULL;
  1235. for (rd = rp->domains; rd < rp->domains + rp->nr_domains; rd++) {
  1236. if (rd->id == RAPL_DOMAIN_PACKAGE) {
  1237. rd_package = rd;
  1238. continue;
  1239. }
  1240. pr_debug("remove package %d, %s domain\n", rp->id, rd->name);
  1241. powercap_unregister_zone(control_type, &rd->power_zone);
  1242. }
  1243. /* do parent zone last */
  1244. powercap_unregister_zone(control_type, &rd_package->power_zone);
  1245. list_del(&rp->plist);
  1246. kfree(rp);
  1247. }
  1248. /* called from CPU hotplug notifier, hotplug lock held */
  1249. static int rapl_add_package(int cpu)
  1250. {
  1251. int ret = 0;
  1252. int phy_package_id;
  1253. struct rapl_package *rp;
  1254. phy_package_id = topology_physical_package_id(cpu);
  1255. rp = kzalloc(sizeof(struct rapl_package), GFP_KERNEL);
  1256. if (!rp)
  1257. return -ENOMEM;
  1258. /* add the new package to the list */
  1259. rp->id = phy_package_id;
  1260. rp->nr_cpus = 1;
  1261. /* check if the package contains valid domains */
  1262. if (rapl_detect_domains(rp, cpu) ||
  1263. rapl_defaults->check_unit(rp, cpu)) {
  1264. ret = -ENODEV;
  1265. goto err_free_package;
  1266. }
  1267. if (!rapl_package_register_powercap(rp)) {
  1268. INIT_LIST_HEAD(&rp->plist);
  1269. list_add(&rp->plist, &rapl_packages);
  1270. return ret;
  1271. }
  1272. err_free_package:
  1273. kfree(rp->domains);
  1274. kfree(rp);
  1275. return ret;
  1276. }
  1277. /* Handles CPU hotplug on multi-socket systems.
  1278. * If a CPU goes online as the first CPU of the physical package
  1279. * we add the RAPL package to the system. Similarly, when the last
  1280. * CPU of the package is removed, we remove the RAPL package and its
  1281. * associated domains. Cooling devices are handled accordingly at
  1282. * per-domain level.
  1283. */
  1284. static int rapl_cpu_callback(struct notifier_block *nfb,
  1285. unsigned long action, void *hcpu)
  1286. {
  1287. unsigned long cpu = (unsigned long)hcpu;
  1288. int phy_package_id;
  1289. struct rapl_package *rp;
  1290. phy_package_id = topology_physical_package_id(cpu);
  1291. switch (action) {
  1292. case CPU_ONLINE:
  1293. case CPU_ONLINE_FROZEN:
  1294. case CPU_DOWN_FAILED:
  1295. case CPU_DOWN_FAILED_FROZEN:
  1296. rp = find_package_by_id(phy_package_id);
  1297. if (rp)
  1298. ++rp->nr_cpus;
  1299. else
  1300. rapl_add_package(cpu);
  1301. break;
  1302. case CPU_DOWN_PREPARE:
  1303. case CPU_DOWN_PREPARE_FROZEN:
  1304. rp = find_package_by_id(phy_package_id);
  1305. if (!rp)
  1306. break;
  1307. if (--rp->nr_cpus == 0)
  1308. rapl_remove_package(rp);
  1309. }
  1310. return NOTIFY_OK;
  1311. }
  1312. static struct notifier_block rapl_cpu_notifier = {
  1313. .notifier_call = rapl_cpu_callback,
  1314. };
  1315. static int __init rapl_init(void)
  1316. {
  1317. int ret = 0;
  1318. const struct x86_cpu_id *id;
  1319. id = x86_match_cpu(rapl_ids);
  1320. if (!id) {
  1321. pr_err("driver does not support CPU family %d model %d\n",
  1322. boot_cpu_data.x86, boot_cpu_data.x86_model);
  1323. return -ENODEV;
  1324. }
  1325. rapl_defaults = (struct rapl_defaults *)id->driver_data;
  1326. cpu_notifier_register_begin();
  1327. /* prevent CPU hotplug during detection */
  1328. get_online_cpus();
  1329. ret = rapl_detect_topology();
  1330. if (ret)
  1331. goto done;
  1332. if (rapl_register_powercap()) {
  1333. rapl_cleanup_data();
  1334. ret = -ENODEV;
  1335. goto done;
  1336. }
  1337. __register_hotcpu_notifier(&rapl_cpu_notifier);
  1338. done:
  1339. put_online_cpus();
  1340. cpu_notifier_register_done();
  1341. return ret;
  1342. }
  1343. static void __exit rapl_exit(void)
  1344. {
  1345. cpu_notifier_register_begin();
  1346. get_online_cpus();
  1347. __unregister_hotcpu_notifier(&rapl_cpu_notifier);
  1348. rapl_unregister_powercap();
  1349. rapl_cleanup_data();
  1350. put_online_cpus();
  1351. cpu_notifier_register_done();
  1352. }
  1353. module_init(rapl_init);
  1354. module_exit(rapl_exit);
  1355. MODULE_DESCRIPTION("Driver for Intel RAPL (Running Average Power Limit)");
  1356. MODULE_AUTHOR("Jacob Pan <jacob.jun.pan@intel.com>");
  1357. MODULE_LICENSE("GPL v2");