pwm-brcmstb.c 8.3 KB

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  1. /*
  2. * Broadcom BCM7038 PWM driver
  3. * Author: Florian Fainelli
  4. *
  5. * Copyright (C) 2015 Broadcom Corporation
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18. #include <linux/clk.h>
  19. #include <linux/export.h>
  20. #include <linux/init.h>
  21. #include <linux/io.h>
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/of.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/pwm.h>
  27. #include <linux/spinlock.h>
  28. #define PWM_CTRL 0x00
  29. #define CTRL_START BIT(0)
  30. #define CTRL_OEB BIT(1)
  31. #define CTRL_FORCE_HIGH BIT(2)
  32. #define CTRL_OPENDRAIN BIT(3)
  33. #define CTRL_CHAN_OFFS 4
  34. #define PWM_CTRL2 0x04
  35. #define CTRL2_OUT_SELECT BIT(0)
  36. #define PWM_CH_SIZE 0x8
  37. #define PWM_CWORD_MSB(ch) (0x08 + ((ch) * PWM_CH_SIZE))
  38. #define PWM_CWORD_LSB(ch) (0x0c + ((ch) * PWM_CH_SIZE))
  39. /* Number of bits for the CWORD value */
  40. #define CWORD_BIT_SIZE 16
  41. /*
  42. * Maximum control word value allowed when variable-frequency PWM is used as a
  43. * clock for the constant-frequency PMW.
  44. */
  45. #define CONST_VAR_F_MAX 32768
  46. #define CONST_VAR_F_MIN 1
  47. #define PWM_ON(ch) (0x18 + ((ch) * PWM_CH_SIZE))
  48. #define PWM_ON_MIN 1
  49. #define PWM_PERIOD(ch) (0x1c + ((ch) * PWM_CH_SIZE))
  50. #define PWM_PERIOD_MIN 0
  51. #define PWM_ON_PERIOD_MAX 0xff
  52. struct brcmstb_pwm {
  53. void __iomem *base;
  54. spinlock_t lock;
  55. struct clk *clk;
  56. struct pwm_chip chip;
  57. };
  58. static inline u32 brcmstb_pwm_readl(struct brcmstb_pwm *p,
  59. unsigned int offset)
  60. {
  61. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  62. return __raw_readl(p->base + offset);
  63. else
  64. return readl_relaxed(p->base + offset);
  65. }
  66. static inline void brcmstb_pwm_writel(struct brcmstb_pwm *p, u32 value,
  67. unsigned int offset)
  68. {
  69. if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  70. __raw_writel(value, p->base + offset);
  71. else
  72. writel_relaxed(value, p->base + offset);
  73. }
  74. static inline struct brcmstb_pwm *to_brcmstb_pwm(struct pwm_chip *chip)
  75. {
  76. return container_of(chip, struct brcmstb_pwm, chip);
  77. }
  78. /*
  79. * Fv is derived from the variable frequency output. The variable frequency
  80. * output is configured using this formula:
  81. *
  82. * W = cword, if cword < 2 ^ 15 else 16-bit 2's complement of cword
  83. *
  84. * Fv = W x 2 ^ -16 x 27Mhz (reference clock)
  85. *
  86. * The period is: (period + 1) / Fv and "on" time is on / (period + 1)
  87. *
  88. * The PWM core framework specifies that the "duty_ns" parameter is in fact the
  89. * "on" time, so this translates directly into our HW programming here.
  90. */
  91. static int brcmstb_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
  92. int duty_ns, int period_ns)
  93. {
  94. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  95. unsigned long pc, dc, cword = CONST_VAR_F_MAX;
  96. unsigned int channel = pwm->hwpwm;
  97. u32 value;
  98. /*
  99. * If asking for a duty_ns equal to period_ns, we need to substract
  100. * the period value by 1 to make it shorter than the "on" time and
  101. * produce a flat 100% duty cycle signal, and max out the "on" time
  102. */
  103. if (duty_ns == period_ns) {
  104. dc = PWM_ON_PERIOD_MAX;
  105. pc = PWM_ON_PERIOD_MAX - 1;
  106. goto done;
  107. }
  108. while (1) {
  109. u64 rate, tmp;
  110. /*
  111. * Calculate the base rate from base frequency and current
  112. * cword
  113. */
  114. rate = (u64)clk_get_rate(p->clk) * (u64)cword;
  115. do_div(rate, 1 << CWORD_BIT_SIZE);
  116. tmp = period_ns * rate;
  117. do_div(tmp, NSEC_PER_SEC);
  118. pc = tmp;
  119. tmp = (duty_ns + 1) * rate;
  120. do_div(tmp, NSEC_PER_SEC);
  121. dc = tmp;
  122. /*
  123. * We can be called with separate duty and period updates,
  124. * so do not reject dc == 0 right away
  125. */
  126. if (pc == PWM_PERIOD_MIN || (dc < PWM_ON_MIN && duty_ns))
  127. return -EINVAL;
  128. /* We converged on a calculation */
  129. if (pc <= PWM_ON_PERIOD_MAX && dc <= PWM_ON_PERIOD_MAX)
  130. break;
  131. /*
  132. * The cword needs to be a power of 2 for the variable
  133. * frequency generator to output a 50% duty cycle variable
  134. * frequency which is used as input clock to the fixed
  135. * frequency generator.
  136. */
  137. cword >>= 1;
  138. /*
  139. * Desired periods are too large, we do not have a divider
  140. * for them
  141. */
  142. if (cword < CONST_VAR_F_MIN)
  143. return -EINVAL;
  144. }
  145. done:
  146. /*
  147. * Configure the defined "cword" value to have the variable frequency
  148. * generator output a base frequency for the constant frequency
  149. * generator to derive from.
  150. */
  151. spin_lock(&p->lock);
  152. brcmstb_pwm_writel(p, cword >> 8, PWM_CWORD_MSB(channel));
  153. brcmstb_pwm_writel(p, cword & 0xff, PWM_CWORD_LSB(channel));
  154. /* Select constant frequency signal output */
  155. value = brcmstb_pwm_readl(p, PWM_CTRL2);
  156. value |= CTRL2_OUT_SELECT << (channel * CTRL_CHAN_OFFS);
  157. brcmstb_pwm_writel(p, value, PWM_CTRL2);
  158. /* Configure on and period value */
  159. brcmstb_pwm_writel(p, pc, PWM_PERIOD(channel));
  160. brcmstb_pwm_writel(p, dc, PWM_ON(channel));
  161. spin_unlock(&p->lock);
  162. return 0;
  163. }
  164. static inline void brcmstb_pwm_enable_set(struct brcmstb_pwm *p,
  165. unsigned int channel, bool enable)
  166. {
  167. unsigned int shift = channel * CTRL_CHAN_OFFS;
  168. u32 value;
  169. spin_lock(&p->lock);
  170. value = brcmstb_pwm_readl(p, PWM_CTRL);
  171. if (enable) {
  172. value &= ~(CTRL_OEB << shift);
  173. value |= (CTRL_START | CTRL_OPENDRAIN) << shift;
  174. } else {
  175. value &= ~((CTRL_START | CTRL_OPENDRAIN) << shift);
  176. value |= CTRL_OEB << shift;
  177. }
  178. brcmstb_pwm_writel(p, value, PWM_CTRL);
  179. spin_unlock(&p->lock);
  180. }
  181. static int brcmstb_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  182. {
  183. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  184. brcmstb_pwm_enable_set(p, pwm->hwpwm, true);
  185. return 0;
  186. }
  187. static void brcmstb_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  188. {
  189. struct brcmstb_pwm *p = to_brcmstb_pwm(chip);
  190. brcmstb_pwm_enable_set(p, pwm->hwpwm, false);
  191. }
  192. static const struct pwm_ops brcmstb_pwm_ops = {
  193. .config = brcmstb_pwm_config,
  194. .enable = brcmstb_pwm_enable,
  195. .disable = brcmstb_pwm_disable,
  196. .owner = THIS_MODULE,
  197. };
  198. static const struct of_device_id brcmstb_pwm_of_match[] = {
  199. { .compatible = "brcm,bcm7038-pwm", },
  200. { /* sentinel */ }
  201. };
  202. MODULE_DEVICE_TABLE(of, brcmstb_pwm_of_match);
  203. static int brcmstb_pwm_probe(struct platform_device *pdev)
  204. {
  205. struct brcmstb_pwm *p;
  206. struct resource *res;
  207. int ret;
  208. p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
  209. if (!p)
  210. return -ENOMEM;
  211. spin_lock_init(&p->lock);
  212. p->clk = devm_clk_get(&pdev->dev, NULL);
  213. if (IS_ERR(p->clk)) {
  214. dev_err(&pdev->dev, "failed to obtain clock\n");
  215. return PTR_ERR(p->clk);
  216. }
  217. ret = clk_prepare_enable(p->clk);
  218. if (ret < 0) {
  219. dev_err(&pdev->dev, "failed to enable clock: %d\n", ret);
  220. return ret;
  221. }
  222. platform_set_drvdata(pdev, p);
  223. p->chip.dev = &pdev->dev;
  224. p->chip.ops = &brcmstb_pwm_ops;
  225. p->chip.base = -1;
  226. p->chip.npwm = 2;
  227. p->chip.can_sleep = true;
  228. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  229. p->base = devm_ioremap_resource(&pdev->dev, res);
  230. if (IS_ERR(p->base)) {
  231. ret = PTR_ERR(p->base);
  232. goto out_clk;
  233. }
  234. ret = pwmchip_add(&p->chip);
  235. if (ret) {
  236. dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
  237. goto out_clk;
  238. }
  239. return 0;
  240. out_clk:
  241. clk_disable_unprepare(p->clk);
  242. return ret;
  243. }
  244. static int brcmstb_pwm_remove(struct platform_device *pdev)
  245. {
  246. struct brcmstb_pwm *p = platform_get_drvdata(pdev);
  247. int ret;
  248. ret = pwmchip_remove(&p->chip);
  249. clk_disable_unprepare(p->clk);
  250. return ret;
  251. }
  252. #ifdef CONFIG_PM_SLEEP
  253. static int brcmstb_pwm_suspend(struct device *dev)
  254. {
  255. struct brcmstb_pwm *p = dev_get_drvdata(dev);
  256. clk_disable(p->clk);
  257. return 0;
  258. }
  259. static int brcmstb_pwm_resume(struct device *dev)
  260. {
  261. struct brcmstb_pwm *p = dev_get_drvdata(dev);
  262. clk_enable(p->clk);
  263. return 0;
  264. }
  265. #endif
  266. static SIMPLE_DEV_PM_OPS(brcmstb_pwm_pm_ops, brcmstb_pwm_suspend,
  267. brcmstb_pwm_resume);
  268. static struct platform_driver brcmstb_pwm_driver = {
  269. .probe = brcmstb_pwm_probe,
  270. .remove = brcmstb_pwm_remove,
  271. .driver = {
  272. .name = "pwm-brcmstb",
  273. .of_match_table = brcmstb_pwm_of_match,
  274. .pm = &brcmstb_pwm_pm_ops,
  275. },
  276. };
  277. module_platform_driver(brcmstb_pwm_driver);
  278. MODULE_AUTHOR("Florian Fainelli <f.fainelli@gmail.com>");
  279. MODULE_DESCRIPTION("Broadcom STB PWM driver");
  280. MODULE_ALIAS("platform:pwm-brcmstb");
  281. MODULE_LICENSE("GPL");