pwm-lpss.c 4.4 KB

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  1. /*
  2. * Intel Low Power Subsystem PWM controller driver
  3. *
  4. * Copyright (C) 2014, Intel Corporation
  5. * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  6. * Author: Chew Kean Ho <kean.ho.chew@intel.com>
  7. * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com>
  8. * Author: Chew Chiau Ee <chiau.ee.chew@intel.com>
  9. * Author: Alan Cox <alan@linux.intel.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/io.h>
  16. #include <linux/kernel.h>
  17. #include <linux/module.h>
  18. #include <linux/pm_runtime.h>
  19. #include "pwm-lpss.h"
  20. #define PWM 0x00000000
  21. #define PWM_ENABLE BIT(31)
  22. #define PWM_SW_UPDATE BIT(30)
  23. #define PWM_BASE_UNIT_SHIFT 8
  24. #define PWM_BASE_UNIT_MASK 0x00ffff00
  25. #define PWM_ON_TIME_DIV_MASK 0x000000ff
  26. #define PWM_DIVISION_CORRECTION 0x2
  27. #define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION)
  28. #define NSECS_PER_SEC 1000000000UL
  29. /* Size of each PWM register space if multiple */
  30. #define PWM_SIZE 0x400
  31. struct pwm_lpss_chip {
  32. struct pwm_chip chip;
  33. void __iomem *regs;
  34. unsigned long clk_rate;
  35. };
  36. /* BayTrail */
  37. const struct pwm_lpss_boardinfo pwm_lpss_byt_info = {
  38. .clk_rate = 25000000,
  39. .npwm = 1,
  40. };
  41. EXPORT_SYMBOL_GPL(pwm_lpss_byt_info);
  42. /* Braswell */
  43. const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = {
  44. .clk_rate = 19200000,
  45. .npwm = 1,
  46. };
  47. EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info);
  48. /* Broxton */
  49. const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = {
  50. .clk_rate = 19200000,
  51. .npwm = 4,
  52. };
  53. EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info);
  54. static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip)
  55. {
  56. return container_of(chip, struct pwm_lpss_chip, chip);
  57. }
  58. static inline u32 pwm_lpss_read(const struct pwm_device *pwm)
  59. {
  60. struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  61. return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  62. }
  63. static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value)
  64. {
  65. struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip);
  66. writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM);
  67. }
  68. static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm,
  69. int duty_ns, int period_ns)
  70. {
  71. struct pwm_lpss_chip *lpwm = to_lpwm(chip);
  72. u8 on_time_div;
  73. unsigned long c;
  74. unsigned long long base_unit, freq = NSECS_PER_SEC;
  75. u32 ctrl;
  76. do_div(freq, period_ns);
  77. /* The equation is: base_unit = ((freq / c) * 65536) + correction */
  78. base_unit = freq * 65536;
  79. c = lpwm->clk_rate;
  80. if (!c)
  81. return -EINVAL;
  82. do_div(base_unit, c);
  83. base_unit += PWM_DIVISION_CORRECTION;
  84. if (base_unit > PWM_LIMIT)
  85. return -EINVAL;
  86. if (duty_ns <= 0)
  87. duty_ns = 1;
  88. on_time_div = 255 - (255 * duty_ns / period_ns);
  89. pm_runtime_get_sync(chip->dev);
  90. ctrl = pwm_lpss_read(pwm);
  91. ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK);
  92. ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT;
  93. ctrl |= on_time_div;
  94. /* request PWM to update on next cycle */
  95. ctrl |= PWM_SW_UPDATE;
  96. pwm_lpss_write(pwm, ctrl);
  97. pm_runtime_put(chip->dev);
  98. return 0;
  99. }
  100. static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  101. {
  102. pm_runtime_get_sync(chip->dev);
  103. pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE);
  104. return 0;
  105. }
  106. static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  107. {
  108. pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE);
  109. pm_runtime_put(chip->dev);
  110. }
  111. static const struct pwm_ops pwm_lpss_ops = {
  112. .free = pwm_lpss_disable,
  113. .config = pwm_lpss_config,
  114. .enable = pwm_lpss_enable,
  115. .disable = pwm_lpss_disable,
  116. .owner = THIS_MODULE,
  117. };
  118. struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r,
  119. const struct pwm_lpss_boardinfo *info)
  120. {
  121. struct pwm_lpss_chip *lpwm;
  122. int ret;
  123. lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL);
  124. if (!lpwm)
  125. return ERR_PTR(-ENOMEM);
  126. lpwm->regs = devm_ioremap_resource(dev, r);
  127. if (IS_ERR(lpwm->regs))
  128. return ERR_CAST(lpwm->regs);
  129. lpwm->clk_rate = info->clk_rate;
  130. lpwm->chip.dev = dev;
  131. lpwm->chip.ops = &pwm_lpss_ops;
  132. lpwm->chip.base = -1;
  133. lpwm->chip.npwm = info->npwm;
  134. ret = pwmchip_add(&lpwm->chip);
  135. if (ret) {
  136. dev_err(dev, "failed to add PWM chip: %d\n", ret);
  137. return ERR_PTR(ret);
  138. }
  139. return lpwm;
  140. }
  141. EXPORT_SYMBOL_GPL(pwm_lpss_probe);
  142. int pwm_lpss_remove(struct pwm_lpss_chip *lpwm)
  143. {
  144. return pwmchip_remove(&lpwm->chip);
  145. }
  146. EXPORT_SYMBOL_GPL(pwm_lpss_remove);
  147. MODULE_DESCRIPTION("PWM driver for Intel LPSS");
  148. MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
  149. MODULE_LICENSE("GPL v2");