reset-socfpga.c 4.3 KB

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  1. /*
  2. * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  3. *
  4. * based on
  5. * Allwinner SoCs Reset Controller driver
  6. *
  7. * Copyright 2013 Maxime Ripard
  8. *
  9. * Maxime Ripard <maxime.ripard@free-electrons.com>
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. */
  16. #include <linux/err.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/of.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/reset-controller.h>
  22. #include <linux/spinlock.h>
  23. #include <linux/types.h>
  24. #define NR_BANKS 4
  25. struct socfpga_reset_data {
  26. spinlock_t lock;
  27. void __iomem *membase;
  28. u32 modrst_offset;
  29. struct reset_controller_dev rcdev;
  30. };
  31. static int socfpga_reset_assert(struct reset_controller_dev *rcdev,
  32. unsigned long id)
  33. {
  34. struct socfpga_reset_data *data = container_of(rcdev,
  35. struct socfpga_reset_data,
  36. rcdev);
  37. int bank = id / BITS_PER_LONG;
  38. int offset = id % BITS_PER_LONG;
  39. unsigned long flags;
  40. u32 reg;
  41. spin_lock_irqsave(&data->lock, flags);
  42. reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
  43. writel(reg | BIT(offset), data->membase + data->modrst_offset +
  44. (bank * NR_BANKS));
  45. spin_unlock_irqrestore(&data->lock, flags);
  46. return 0;
  47. }
  48. static int socfpga_reset_deassert(struct reset_controller_dev *rcdev,
  49. unsigned long id)
  50. {
  51. struct socfpga_reset_data *data = container_of(rcdev,
  52. struct socfpga_reset_data,
  53. rcdev);
  54. int bank = id / BITS_PER_LONG;
  55. int offset = id % BITS_PER_LONG;
  56. unsigned long flags;
  57. u32 reg;
  58. spin_lock_irqsave(&data->lock, flags);
  59. reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
  60. writel(reg & ~BIT(offset), data->membase + data->modrst_offset +
  61. (bank * NR_BANKS));
  62. spin_unlock_irqrestore(&data->lock, flags);
  63. return 0;
  64. }
  65. static int socfpga_reset_status(struct reset_controller_dev *rcdev,
  66. unsigned long id)
  67. {
  68. struct socfpga_reset_data *data = container_of(rcdev,
  69. struct socfpga_reset_data, rcdev);
  70. int bank = id / BITS_PER_LONG;
  71. int offset = id % BITS_PER_LONG;
  72. u32 reg;
  73. reg = readl(data->membase + data->modrst_offset + (bank * NR_BANKS));
  74. return !(reg & BIT(offset));
  75. }
  76. static struct reset_control_ops socfpga_reset_ops = {
  77. .assert = socfpga_reset_assert,
  78. .deassert = socfpga_reset_deassert,
  79. .status = socfpga_reset_status,
  80. };
  81. static int socfpga_reset_probe(struct platform_device *pdev)
  82. {
  83. struct socfpga_reset_data *data;
  84. struct resource *res;
  85. struct device *dev = &pdev->dev;
  86. struct device_node *np = dev->of_node;
  87. /*
  88. * The binding was mainlined without the required property.
  89. * Do not continue, when we encounter an old DT.
  90. */
  91. if (!of_find_property(pdev->dev.of_node, "#reset-cells", NULL)) {
  92. dev_err(&pdev->dev, "%s missing #reset-cells property\n",
  93. pdev->dev.of_node->full_name);
  94. return -EINVAL;
  95. }
  96. data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
  97. if (!data)
  98. return -ENOMEM;
  99. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  100. data->membase = devm_ioremap_resource(&pdev->dev, res);
  101. if (IS_ERR(data->membase))
  102. return PTR_ERR(data->membase);
  103. if (of_property_read_u32(np, "altr,modrst-offset", &data->modrst_offset)) {
  104. dev_warn(dev, "missing altr,modrst-offset property, assuming 0x10!\n");
  105. data->modrst_offset = 0x10;
  106. }
  107. spin_lock_init(&data->lock);
  108. data->rcdev.owner = THIS_MODULE;
  109. data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG;
  110. data->rcdev.ops = &socfpga_reset_ops;
  111. data->rcdev.of_node = pdev->dev.of_node;
  112. reset_controller_register(&data->rcdev);
  113. return 0;
  114. }
  115. static int socfpga_reset_remove(struct platform_device *pdev)
  116. {
  117. struct socfpga_reset_data *data = platform_get_drvdata(pdev);
  118. reset_controller_unregister(&data->rcdev);
  119. return 0;
  120. }
  121. static const struct of_device_id socfpga_reset_dt_ids[] = {
  122. { .compatible = "altr,rst-mgr", },
  123. { /* sentinel */ },
  124. };
  125. static struct platform_driver socfpga_reset_driver = {
  126. .probe = socfpga_reset_probe,
  127. .remove = socfpga_reset_remove,
  128. .driver = {
  129. .name = "socfpga-reset",
  130. .of_match_table = socfpga_reset_dt_ids,
  131. },
  132. };
  133. module_platform_driver(socfpga_reset_driver);
  134. MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de");
  135. MODULE_DESCRIPTION("Socfpga Reset Controller Driver");
  136. MODULE_LICENSE("GPL");