rtc-at91sam9.c 15 KB

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  1. /*
  2. * "RTT as Real Time Clock" driver for AT91SAM9 SoC family
  3. *
  4. * (C) 2007 Michel Benoit
  5. *
  6. * Based on rtc-at91rm9200.c by Rick Bronson
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version
  11. * 2 of the License, or (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/ioctl.h>
  16. #include <linux/io.h>
  17. #include <linux/kernel.h>
  18. #include <linux/mfd/syscon.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/regmap.h>
  23. #include <linux/rtc.h>
  24. #include <linux/slab.h>
  25. #include <linux/suspend.h>
  26. #include <linux/time.h>
  27. /*
  28. * This driver uses two configurable hardware resources that live in the
  29. * AT91SAM9 backup power domain (intended to be powered at all times)
  30. * to implement the Real Time Clock interfaces
  31. *
  32. * - A "Real-time Timer" (RTT) counts up in seconds from a base time.
  33. * We can't assign the counter value (CRTV) ... but we can reset it.
  34. *
  35. * - One of the "General Purpose Backup Registers" (GPBRs) holds the
  36. * base time, normally an offset from the beginning of the POSIX
  37. * epoch (1970-Jan-1 00:00:00 UTC). Some systems also include the
  38. * local timezone's offset.
  39. *
  40. * The RTC's value is the RTT counter plus that offset. The RTC's alarm
  41. * is likewise a base (ALMV) plus that offset.
  42. *
  43. * Not all RTTs will be used as RTCs; some systems have multiple RTTs to
  44. * choose from, or a "real" RTC module. All systems have multiple GPBR
  45. * registers available, likewise usable for more than "RTC" support.
  46. */
  47. #define AT91_RTT_MR 0x00 /* Real-time Mode Register */
  48. #define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
  49. #define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
  50. #define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
  51. #define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
  52. #define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
  53. #define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
  54. #define AT91_RTT_VR 0x08 /* Real-time Value Register */
  55. #define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
  56. #define AT91_RTT_SR 0x0c /* Real-time Status Register */
  57. #define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
  58. #define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
  59. /*
  60. * We store ALARM_DISABLED in ALMV to record that no alarm is set.
  61. * It's also the reset value for that field.
  62. */
  63. #define ALARM_DISABLED ((u32)~0)
  64. struct sam9_rtc {
  65. void __iomem *rtt;
  66. struct rtc_device *rtcdev;
  67. u32 imr;
  68. struct regmap *gpbr;
  69. unsigned int gpbr_offset;
  70. int irq;
  71. struct clk *sclk;
  72. bool suspended;
  73. unsigned long events;
  74. spinlock_t lock;
  75. };
  76. #define rtt_readl(rtc, field) \
  77. readl((rtc)->rtt + AT91_RTT_ ## field)
  78. #define rtt_writel(rtc, field, val) \
  79. writel((val), (rtc)->rtt + AT91_RTT_ ## field)
  80. static inline unsigned int gpbr_readl(struct sam9_rtc *rtc)
  81. {
  82. unsigned int val;
  83. regmap_read(rtc->gpbr, rtc->gpbr_offset, &val);
  84. return val;
  85. }
  86. static inline void gpbr_writel(struct sam9_rtc *rtc, unsigned int val)
  87. {
  88. regmap_write(rtc->gpbr, rtc->gpbr_offset, val);
  89. }
  90. /*
  91. * Read current time and date in RTC
  92. */
  93. static int at91_rtc_readtime(struct device *dev, struct rtc_time *tm)
  94. {
  95. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  96. u32 secs, secs2;
  97. u32 offset;
  98. /* read current time offset */
  99. offset = gpbr_readl(rtc);
  100. if (offset == 0)
  101. return -EILSEQ;
  102. /* reread the counter to help sync the two clock domains */
  103. secs = rtt_readl(rtc, VR);
  104. secs2 = rtt_readl(rtc, VR);
  105. if (secs != secs2)
  106. secs = rtt_readl(rtc, VR);
  107. rtc_time_to_tm(offset + secs, tm);
  108. dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readtime",
  109. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  110. tm->tm_hour, tm->tm_min, tm->tm_sec);
  111. return 0;
  112. }
  113. /*
  114. * Set current time and date in RTC
  115. */
  116. static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
  117. {
  118. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  119. int err;
  120. u32 offset, alarm, mr;
  121. unsigned long secs;
  122. dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "settime",
  123. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  124. tm->tm_hour, tm->tm_min, tm->tm_sec);
  125. err = rtc_tm_to_time(tm, &secs);
  126. if (err != 0)
  127. return err;
  128. mr = rtt_readl(rtc, MR);
  129. /* disable interrupts */
  130. rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
  131. /* read current time offset */
  132. offset = gpbr_readl(rtc);
  133. /* store the new base time in a battery backup register */
  134. secs += 1;
  135. gpbr_writel(rtc, secs);
  136. /* adjust the alarm time for the new base */
  137. alarm = rtt_readl(rtc, AR);
  138. if (alarm != ALARM_DISABLED) {
  139. if (offset > secs) {
  140. /* time jumped backwards, increase time until alarm */
  141. alarm += (offset - secs);
  142. } else if ((alarm + offset) > secs) {
  143. /* time jumped forwards, decrease time until alarm */
  144. alarm -= (secs - offset);
  145. } else {
  146. /* time jumped past the alarm, disable alarm */
  147. alarm = ALARM_DISABLED;
  148. mr &= ~AT91_RTT_ALMIEN;
  149. }
  150. rtt_writel(rtc, AR, alarm);
  151. }
  152. /* reset the timer, and re-enable interrupts */
  153. rtt_writel(rtc, MR, mr | AT91_RTT_RTTRST);
  154. return 0;
  155. }
  156. static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
  157. {
  158. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  159. struct rtc_time *tm = &alrm->time;
  160. u32 alarm = rtt_readl(rtc, AR);
  161. u32 offset;
  162. offset = gpbr_readl(rtc);
  163. if (offset == 0)
  164. return -EILSEQ;
  165. memset(alrm, 0, sizeof(*alrm));
  166. if (alarm != ALARM_DISABLED && offset != 0) {
  167. rtc_time_to_tm(offset + alarm, tm);
  168. dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "readalarm",
  169. 1900 + tm->tm_year, tm->tm_mon, tm->tm_mday,
  170. tm->tm_hour, tm->tm_min, tm->tm_sec);
  171. if (rtt_readl(rtc, MR) & AT91_RTT_ALMIEN)
  172. alrm->enabled = 1;
  173. }
  174. return 0;
  175. }
  176. static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
  177. {
  178. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  179. struct rtc_time *tm = &alrm->time;
  180. unsigned long secs;
  181. u32 offset;
  182. u32 mr;
  183. int err;
  184. err = rtc_tm_to_time(tm, &secs);
  185. if (err != 0)
  186. return err;
  187. offset = gpbr_readl(rtc);
  188. if (offset == 0) {
  189. /* time is not set */
  190. return -EILSEQ;
  191. }
  192. mr = rtt_readl(rtc, MR);
  193. rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
  194. /* alarm in the past? finish and leave disabled */
  195. if (secs <= offset) {
  196. rtt_writel(rtc, AR, ALARM_DISABLED);
  197. return 0;
  198. }
  199. /* else set alarm and maybe enable it */
  200. rtt_writel(rtc, AR, secs - offset);
  201. if (alrm->enabled)
  202. rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
  203. dev_dbg(dev, "%s: %4d-%02d-%02d %02d:%02d:%02d\n", "setalarm",
  204. tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour,
  205. tm->tm_min, tm->tm_sec);
  206. return 0;
  207. }
  208. static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  209. {
  210. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  211. u32 mr = rtt_readl(rtc, MR);
  212. dev_dbg(dev, "alarm_irq_enable: enabled=%08x, mr %08x\n", enabled, mr);
  213. if (enabled)
  214. rtt_writel(rtc, MR, mr | AT91_RTT_ALMIEN);
  215. else
  216. rtt_writel(rtc, MR, mr & ~AT91_RTT_ALMIEN);
  217. return 0;
  218. }
  219. /*
  220. * Provide additional RTC information in /proc/driver/rtc
  221. */
  222. static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
  223. {
  224. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  225. u32 mr = mr = rtt_readl(rtc, MR);
  226. seq_printf(seq, "update_IRQ\t: %s\n",
  227. (mr & AT91_RTT_RTTINCIEN) ? "yes" : "no");
  228. return 0;
  229. }
  230. static irqreturn_t at91_rtc_cache_events(struct sam9_rtc *rtc)
  231. {
  232. u32 sr, mr;
  233. /* Shared interrupt may be for another device. Note: reading
  234. * SR clears it, so we must only read it in this irq handler!
  235. */
  236. mr = rtt_readl(rtc, MR) & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  237. sr = rtt_readl(rtc, SR) & (mr >> 16);
  238. if (!sr)
  239. return IRQ_NONE;
  240. /* alarm status */
  241. if (sr & AT91_RTT_ALMS)
  242. rtc->events |= (RTC_AF | RTC_IRQF);
  243. /* timer update/increment */
  244. if (sr & AT91_RTT_RTTINC)
  245. rtc->events |= (RTC_UF | RTC_IRQF);
  246. return IRQ_HANDLED;
  247. }
  248. static void at91_rtc_flush_events(struct sam9_rtc *rtc)
  249. {
  250. if (!rtc->events)
  251. return;
  252. rtc_update_irq(rtc->rtcdev, 1, rtc->events);
  253. rtc->events = 0;
  254. pr_debug("%s: num=%ld, events=0x%02lx\n", __func__,
  255. rtc->events >> 8, rtc->events & 0x000000FF);
  256. }
  257. /*
  258. * IRQ handler for the RTC
  259. */
  260. static irqreturn_t at91_rtc_interrupt(int irq, void *_rtc)
  261. {
  262. struct sam9_rtc *rtc = _rtc;
  263. int ret;
  264. spin_lock(&rtc->lock);
  265. ret = at91_rtc_cache_events(rtc);
  266. /* We're called in suspended state */
  267. if (rtc->suspended) {
  268. /* Mask irqs coming from this peripheral */
  269. rtt_writel(rtc, MR,
  270. rtt_readl(rtc, MR) &
  271. ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
  272. /* Trigger a system wakeup */
  273. pm_system_wakeup();
  274. } else {
  275. at91_rtc_flush_events(rtc);
  276. }
  277. spin_unlock(&rtc->lock);
  278. return ret;
  279. }
  280. static const struct rtc_class_ops at91_rtc_ops = {
  281. .read_time = at91_rtc_readtime,
  282. .set_time = at91_rtc_settime,
  283. .read_alarm = at91_rtc_readalarm,
  284. .set_alarm = at91_rtc_setalarm,
  285. .proc = at91_rtc_proc,
  286. .alarm_irq_enable = at91_rtc_alarm_irq_enable,
  287. };
  288. static const struct regmap_config gpbr_regmap_config = {
  289. .reg_bits = 32,
  290. .val_bits = 32,
  291. .reg_stride = 4,
  292. };
  293. /*
  294. * Initialize and install RTC driver
  295. */
  296. static int at91_rtc_probe(struct platform_device *pdev)
  297. {
  298. struct resource *r;
  299. struct sam9_rtc *rtc;
  300. int ret, irq;
  301. u32 mr;
  302. unsigned int sclk_rate;
  303. irq = platform_get_irq(pdev, 0);
  304. if (irq < 0) {
  305. dev_err(&pdev->dev, "failed to get interrupt resource\n");
  306. return irq;
  307. }
  308. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  309. if (!rtc)
  310. return -ENOMEM;
  311. rtc->irq = irq;
  312. /* platform setup code should have handled this; sigh */
  313. if (!device_can_wakeup(&pdev->dev))
  314. device_init_wakeup(&pdev->dev, 1);
  315. platform_set_drvdata(pdev, rtc);
  316. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  317. rtc->rtt = devm_ioremap_resource(&pdev->dev, r);
  318. if (IS_ERR(rtc->rtt))
  319. return PTR_ERR(rtc->rtt);
  320. if (!pdev->dev.of_node) {
  321. /*
  322. * TODO: Remove this code chunk when removing non DT board
  323. * support. Remember to remove the gpbr_regmap_config
  324. * variable too.
  325. */
  326. void __iomem *gpbr;
  327. r = platform_get_resource(pdev, IORESOURCE_MEM, 1);
  328. gpbr = devm_ioremap_resource(&pdev->dev, r);
  329. if (IS_ERR(gpbr))
  330. return PTR_ERR(gpbr);
  331. rtc->gpbr = regmap_init_mmio(NULL, gpbr,
  332. &gpbr_regmap_config);
  333. } else {
  334. struct of_phandle_args args;
  335. ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
  336. "atmel,rtt-rtc-time-reg", 1, 0,
  337. &args);
  338. if (ret)
  339. return ret;
  340. rtc->gpbr = syscon_node_to_regmap(args.np);
  341. rtc->gpbr_offset = args.args[0];
  342. }
  343. if (IS_ERR(rtc->gpbr)) {
  344. dev_err(&pdev->dev, "failed to retrieve gpbr regmap, aborting.\n");
  345. return -ENOMEM;
  346. }
  347. rtc->sclk = devm_clk_get(&pdev->dev, NULL);
  348. if (IS_ERR(rtc->sclk))
  349. return PTR_ERR(rtc->sclk);
  350. ret = clk_prepare_enable(rtc->sclk);
  351. if (ret) {
  352. dev_err(&pdev->dev, "Could not enable slow clock\n");
  353. return ret;
  354. }
  355. sclk_rate = clk_get_rate(rtc->sclk);
  356. if (!sclk_rate || sclk_rate > AT91_RTT_RTPRES) {
  357. dev_err(&pdev->dev, "Invalid slow clock rate\n");
  358. ret = -EINVAL;
  359. goto err_clk;
  360. }
  361. mr = rtt_readl(rtc, MR);
  362. /* unless RTT is counting at 1 Hz, re-initialize it */
  363. if ((mr & AT91_RTT_RTPRES) != sclk_rate) {
  364. mr = AT91_RTT_RTTRST | (sclk_rate & AT91_RTT_RTPRES);
  365. gpbr_writel(rtc, 0);
  366. }
  367. /* disable all interrupts (same as on shutdown path) */
  368. mr &= ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  369. rtt_writel(rtc, MR, mr);
  370. rtc->rtcdev = devm_rtc_device_register(&pdev->dev, pdev->name,
  371. &at91_rtc_ops, THIS_MODULE);
  372. if (IS_ERR(rtc->rtcdev)) {
  373. ret = PTR_ERR(rtc->rtcdev);
  374. goto err_clk;
  375. }
  376. /* register irq handler after we know what name we'll use */
  377. ret = devm_request_irq(&pdev->dev, rtc->irq, at91_rtc_interrupt,
  378. IRQF_SHARED | IRQF_COND_SUSPEND,
  379. dev_name(&rtc->rtcdev->dev), rtc);
  380. if (ret) {
  381. dev_dbg(&pdev->dev, "can't share IRQ %d?\n", rtc->irq);
  382. goto err_clk;
  383. }
  384. /* NOTE: sam9260 rev A silicon has a ROM bug which resets the
  385. * RTT on at least some reboots. If you have that chip, you must
  386. * initialize the time from some external source like a GPS, wall
  387. * clock, discrete RTC, etc
  388. */
  389. if (gpbr_readl(rtc) == 0)
  390. dev_warn(&pdev->dev, "%s: SET TIME!\n",
  391. dev_name(&rtc->rtcdev->dev));
  392. return 0;
  393. err_clk:
  394. clk_disable_unprepare(rtc->sclk);
  395. return ret;
  396. }
  397. /*
  398. * Disable and remove the RTC driver
  399. */
  400. static int at91_rtc_remove(struct platform_device *pdev)
  401. {
  402. struct sam9_rtc *rtc = platform_get_drvdata(pdev);
  403. u32 mr = rtt_readl(rtc, MR);
  404. /* disable all interrupts */
  405. rtt_writel(rtc, MR, mr & ~(AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN));
  406. clk_disable_unprepare(rtc->sclk);
  407. return 0;
  408. }
  409. static void at91_rtc_shutdown(struct platform_device *pdev)
  410. {
  411. struct sam9_rtc *rtc = platform_get_drvdata(pdev);
  412. u32 mr = rtt_readl(rtc, MR);
  413. rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  414. rtt_writel(rtc, MR, mr & ~rtc->imr);
  415. }
  416. #ifdef CONFIG_PM_SLEEP
  417. /* AT91SAM9 RTC Power management control */
  418. static int at91_rtc_suspend(struct device *dev)
  419. {
  420. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  421. u32 mr = rtt_readl(rtc, MR);
  422. /*
  423. * This IRQ is shared with DBGU and other hardware which isn't
  424. * necessarily a wakeup event source.
  425. */
  426. rtc->imr = mr & (AT91_RTT_ALMIEN | AT91_RTT_RTTINCIEN);
  427. if (rtc->imr) {
  428. if (device_may_wakeup(dev) && (mr & AT91_RTT_ALMIEN)) {
  429. unsigned long flags;
  430. enable_irq_wake(rtc->irq);
  431. spin_lock_irqsave(&rtc->lock, flags);
  432. rtc->suspended = true;
  433. spin_unlock_irqrestore(&rtc->lock, flags);
  434. /* don't let RTTINC cause wakeups */
  435. if (mr & AT91_RTT_RTTINCIEN)
  436. rtt_writel(rtc, MR, mr & ~AT91_RTT_RTTINCIEN);
  437. } else
  438. rtt_writel(rtc, MR, mr & ~rtc->imr);
  439. }
  440. return 0;
  441. }
  442. static int at91_rtc_resume(struct device *dev)
  443. {
  444. struct sam9_rtc *rtc = dev_get_drvdata(dev);
  445. u32 mr;
  446. if (rtc->imr) {
  447. unsigned long flags;
  448. if (device_may_wakeup(dev))
  449. disable_irq_wake(rtc->irq);
  450. mr = rtt_readl(rtc, MR);
  451. rtt_writel(rtc, MR, mr | rtc->imr);
  452. spin_lock_irqsave(&rtc->lock, flags);
  453. rtc->suspended = false;
  454. at91_rtc_cache_events(rtc);
  455. at91_rtc_flush_events(rtc);
  456. spin_unlock_irqrestore(&rtc->lock, flags);
  457. }
  458. return 0;
  459. }
  460. #endif
  461. static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
  462. #ifdef CONFIG_OF
  463. static const struct of_device_id at91_rtc_dt_ids[] = {
  464. { .compatible = "atmel,at91sam9260-rtt" },
  465. { /* sentinel */ }
  466. };
  467. MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
  468. #endif
  469. static struct platform_driver at91_rtc_driver = {
  470. .probe = at91_rtc_probe,
  471. .remove = at91_rtc_remove,
  472. .shutdown = at91_rtc_shutdown,
  473. .driver = {
  474. .name = "rtc-at91sam9",
  475. .pm = &at91_rtc_pm_ops,
  476. .of_match_table = of_match_ptr(at91_rtc_dt_ids),
  477. },
  478. };
  479. module_platform_driver(at91_rtc_driver);
  480. MODULE_AUTHOR("Michel Benoit");
  481. MODULE_DESCRIPTION("RTC driver for Atmel AT91SAM9x");
  482. MODULE_LICENSE("GPL");