rtc-rp5c01.c 7.9 KB

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  1. /*
  2. * Ricoh RP5C01 RTC Driver
  3. *
  4. * Copyright 2009 Geert Uytterhoeven
  5. *
  6. * Based on the A3000 TOD code in arch/m68k/amiga/config.c
  7. * Copyright (C) 1993 Hamish Macdonald
  8. */
  9. #include <linux/io.h>
  10. #include <linux/kernel.h>
  11. #include <linux/module.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/rtc.h>
  14. #include <linux/slab.h>
  15. enum {
  16. RP5C01_1_SECOND = 0x0, /* MODE 00 */
  17. RP5C01_10_SECOND = 0x1, /* MODE 00 */
  18. RP5C01_1_MINUTE = 0x2, /* MODE 00 and MODE 01 */
  19. RP5C01_10_MINUTE = 0x3, /* MODE 00 and MODE 01 */
  20. RP5C01_1_HOUR = 0x4, /* MODE 00 and MODE 01 */
  21. RP5C01_10_HOUR = 0x5, /* MODE 00 and MODE 01 */
  22. RP5C01_DAY_OF_WEEK = 0x6, /* MODE 00 and MODE 01 */
  23. RP5C01_1_DAY = 0x7, /* MODE 00 and MODE 01 */
  24. RP5C01_10_DAY = 0x8, /* MODE 00 and MODE 01 */
  25. RP5C01_1_MONTH = 0x9, /* MODE 00 */
  26. RP5C01_10_MONTH = 0xa, /* MODE 00 */
  27. RP5C01_1_YEAR = 0xb, /* MODE 00 */
  28. RP5C01_10_YEAR = 0xc, /* MODE 00 */
  29. RP5C01_12_24_SELECT = 0xa, /* MODE 01 */
  30. RP5C01_LEAP_YEAR = 0xb, /* MODE 01 */
  31. RP5C01_MODE = 0xd, /* all modes */
  32. RP5C01_TEST = 0xe, /* all modes */
  33. RP5C01_RESET = 0xf, /* all modes */
  34. };
  35. #define RP5C01_12_24_SELECT_12 (0 << 0)
  36. #define RP5C01_12_24_SELECT_24 (1 << 0)
  37. #define RP5C01_10_HOUR_AM (0 << 1)
  38. #define RP5C01_10_HOUR_PM (1 << 1)
  39. #define RP5C01_MODE_TIMER_EN (1 << 3) /* timer enable */
  40. #define RP5C01_MODE_ALARM_EN (1 << 2) /* alarm enable */
  41. #define RP5C01_MODE_MODE_MASK (3 << 0)
  42. #define RP5C01_MODE_MODE00 (0 << 0) /* time */
  43. #define RP5C01_MODE_MODE01 (1 << 0) /* alarm, 12h/24h, leap year */
  44. #define RP5C01_MODE_RAM_BLOCK10 (2 << 0) /* RAM 4 bits x 13 */
  45. #define RP5C01_MODE_RAM_BLOCK11 (3 << 0) /* RAM 4 bits x 13 */
  46. #define RP5C01_RESET_1HZ_PULSE (1 << 3)
  47. #define RP5C01_RESET_16HZ_PULSE (1 << 2)
  48. #define RP5C01_RESET_SECOND (1 << 1) /* reset divider stages for */
  49. /* seconds or smaller units */
  50. #define RP5C01_RESET_ALARM (1 << 0) /* reset all alarm registers */
  51. struct rp5c01_priv {
  52. u32 __iomem *regs;
  53. struct rtc_device *rtc;
  54. spinlock_t lock; /* against concurrent RTC/NVRAM access */
  55. struct bin_attribute nvram_attr;
  56. };
  57. static inline unsigned int rp5c01_read(struct rp5c01_priv *priv,
  58. unsigned int reg)
  59. {
  60. return __raw_readl(&priv->regs[reg]) & 0xf;
  61. }
  62. static inline void rp5c01_write(struct rp5c01_priv *priv, unsigned int val,
  63. unsigned int reg)
  64. {
  65. __raw_writel(val, &priv->regs[reg]);
  66. }
  67. static void rp5c01_lock(struct rp5c01_priv *priv)
  68. {
  69. rp5c01_write(priv, RP5C01_MODE_MODE00, RP5C01_MODE);
  70. }
  71. static void rp5c01_unlock(struct rp5c01_priv *priv)
  72. {
  73. rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
  74. RP5C01_MODE);
  75. }
  76. static int rp5c01_read_time(struct device *dev, struct rtc_time *tm)
  77. {
  78. struct rp5c01_priv *priv = dev_get_drvdata(dev);
  79. spin_lock_irq(&priv->lock);
  80. rp5c01_lock(priv);
  81. tm->tm_sec = rp5c01_read(priv, RP5C01_10_SECOND) * 10 +
  82. rp5c01_read(priv, RP5C01_1_SECOND);
  83. tm->tm_min = rp5c01_read(priv, RP5C01_10_MINUTE) * 10 +
  84. rp5c01_read(priv, RP5C01_1_MINUTE);
  85. tm->tm_hour = rp5c01_read(priv, RP5C01_10_HOUR) * 10 +
  86. rp5c01_read(priv, RP5C01_1_HOUR);
  87. tm->tm_mday = rp5c01_read(priv, RP5C01_10_DAY) * 10 +
  88. rp5c01_read(priv, RP5C01_1_DAY);
  89. tm->tm_wday = rp5c01_read(priv, RP5C01_DAY_OF_WEEK);
  90. tm->tm_mon = rp5c01_read(priv, RP5C01_10_MONTH) * 10 +
  91. rp5c01_read(priv, RP5C01_1_MONTH) - 1;
  92. tm->tm_year = rp5c01_read(priv, RP5C01_10_YEAR) * 10 +
  93. rp5c01_read(priv, RP5C01_1_YEAR);
  94. if (tm->tm_year <= 69)
  95. tm->tm_year += 100;
  96. rp5c01_unlock(priv);
  97. spin_unlock_irq(&priv->lock);
  98. return rtc_valid_tm(tm);
  99. }
  100. static int rp5c01_set_time(struct device *dev, struct rtc_time *tm)
  101. {
  102. struct rp5c01_priv *priv = dev_get_drvdata(dev);
  103. spin_lock_irq(&priv->lock);
  104. rp5c01_lock(priv);
  105. rp5c01_write(priv, tm->tm_sec / 10, RP5C01_10_SECOND);
  106. rp5c01_write(priv, tm->tm_sec % 10, RP5C01_1_SECOND);
  107. rp5c01_write(priv, tm->tm_min / 10, RP5C01_10_MINUTE);
  108. rp5c01_write(priv, tm->tm_min % 10, RP5C01_1_MINUTE);
  109. rp5c01_write(priv, tm->tm_hour / 10, RP5C01_10_HOUR);
  110. rp5c01_write(priv, tm->tm_hour % 10, RP5C01_1_HOUR);
  111. rp5c01_write(priv, tm->tm_mday / 10, RP5C01_10_DAY);
  112. rp5c01_write(priv, tm->tm_mday % 10, RP5C01_1_DAY);
  113. if (tm->tm_wday != -1)
  114. rp5c01_write(priv, tm->tm_wday, RP5C01_DAY_OF_WEEK);
  115. rp5c01_write(priv, (tm->tm_mon + 1) / 10, RP5C01_10_MONTH);
  116. rp5c01_write(priv, (tm->tm_mon + 1) % 10, RP5C01_1_MONTH);
  117. if (tm->tm_year >= 100)
  118. tm->tm_year -= 100;
  119. rp5c01_write(priv, tm->tm_year / 10, RP5C01_10_YEAR);
  120. rp5c01_write(priv, tm->tm_year % 10, RP5C01_1_YEAR);
  121. rp5c01_unlock(priv);
  122. spin_unlock_irq(&priv->lock);
  123. return 0;
  124. }
  125. static const struct rtc_class_ops rp5c01_rtc_ops = {
  126. .read_time = rp5c01_read_time,
  127. .set_time = rp5c01_set_time,
  128. };
  129. /*
  130. * The NVRAM is organized as 2 blocks of 13 nibbles of 4 bits.
  131. * We provide access to them like AmigaOS does: the high nibble of each 8-bit
  132. * byte is stored in BLOCK10, the low nibble in BLOCK11.
  133. */
  134. static ssize_t rp5c01_nvram_read(struct file *filp, struct kobject *kobj,
  135. struct bin_attribute *bin_attr,
  136. char *buf, loff_t pos, size_t size)
  137. {
  138. struct device *dev = container_of(kobj, struct device, kobj);
  139. struct rp5c01_priv *priv = dev_get_drvdata(dev);
  140. ssize_t count;
  141. spin_lock_irq(&priv->lock);
  142. for (count = 0; count < size; count++) {
  143. u8 data;
  144. rp5c01_write(priv,
  145. RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
  146. RP5C01_MODE);
  147. data = rp5c01_read(priv, pos) << 4;
  148. rp5c01_write(priv,
  149. RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
  150. RP5C01_MODE);
  151. data |= rp5c01_read(priv, pos++);
  152. rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
  153. RP5C01_MODE);
  154. *buf++ = data;
  155. }
  156. spin_unlock_irq(&priv->lock);
  157. return count;
  158. }
  159. static ssize_t rp5c01_nvram_write(struct file *filp, struct kobject *kobj,
  160. struct bin_attribute *bin_attr,
  161. char *buf, loff_t pos, size_t size)
  162. {
  163. struct device *dev = container_of(kobj, struct device, kobj);
  164. struct rp5c01_priv *priv = dev_get_drvdata(dev);
  165. ssize_t count;
  166. spin_lock_irq(&priv->lock);
  167. for (count = 0; count < size; count++) {
  168. u8 data = *buf++;
  169. rp5c01_write(priv,
  170. RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK10,
  171. RP5C01_MODE);
  172. rp5c01_write(priv, data >> 4, pos);
  173. rp5c01_write(priv,
  174. RP5C01_MODE_TIMER_EN | RP5C01_MODE_RAM_BLOCK11,
  175. RP5C01_MODE);
  176. rp5c01_write(priv, data & 0xf, pos++);
  177. rp5c01_write(priv, RP5C01_MODE_TIMER_EN | RP5C01_MODE_MODE01,
  178. RP5C01_MODE);
  179. }
  180. spin_unlock_irq(&priv->lock);
  181. return count;
  182. }
  183. static int __init rp5c01_rtc_probe(struct platform_device *dev)
  184. {
  185. struct resource *res;
  186. struct rp5c01_priv *priv;
  187. struct rtc_device *rtc;
  188. int error;
  189. res = platform_get_resource(dev, IORESOURCE_MEM, 0);
  190. if (!res)
  191. return -ENODEV;
  192. priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
  193. if (!priv)
  194. return -ENOMEM;
  195. priv->regs = devm_ioremap(&dev->dev, res->start, resource_size(res));
  196. if (!priv->regs)
  197. return -ENOMEM;
  198. sysfs_bin_attr_init(&priv->nvram_attr);
  199. priv->nvram_attr.attr.name = "nvram";
  200. priv->nvram_attr.attr.mode = S_IRUGO | S_IWUSR;
  201. priv->nvram_attr.read = rp5c01_nvram_read;
  202. priv->nvram_attr.write = rp5c01_nvram_write;
  203. priv->nvram_attr.size = RP5C01_MODE;
  204. spin_lock_init(&priv->lock);
  205. platform_set_drvdata(dev, priv);
  206. rtc = devm_rtc_device_register(&dev->dev, "rtc-rp5c01", &rp5c01_rtc_ops,
  207. THIS_MODULE);
  208. if (IS_ERR(rtc))
  209. return PTR_ERR(rtc);
  210. priv->rtc = rtc;
  211. error = sysfs_create_bin_file(&dev->dev.kobj, &priv->nvram_attr);
  212. if (error)
  213. return error;
  214. return 0;
  215. }
  216. static int __exit rp5c01_rtc_remove(struct platform_device *dev)
  217. {
  218. struct rp5c01_priv *priv = platform_get_drvdata(dev);
  219. sysfs_remove_bin_file(&dev->dev.kobj, &priv->nvram_attr);
  220. return 0;
  221. }
  222. static struct platform_driver rp5c01_rtc_driver = {
  223. .driver = {
  224. .name = "rtc-rp5c01",
  225. },
  226. .remove = __exit_p(rp5c01_rtc_remove),
  227. };
  228. module_platform_driver_probe(rp5c01_rtc_driver, rp5c01_rtc_probe);
  229. MODULE_AUTHOR("Geert Uytterhoeven <geert@linux-m68k.org>");
  230. MODULE_LICENSE("GPL");
  231. MODULE_DESCRIPTION("Ricoh RP5C01 RTC driver");
  232. MODULE_ALIAS("platform:rtc-rp5c01");