rtc-sh.c 19 KB

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  1. /*
  2. * SuperH On-Chip RTC Support
  3. *
  4. * Copyright (C) 2006 - 2009 Paul Mundt
  5. * Copyright (C) 2006 Jamie Lenehan
  6. * Copyright (C) 2008 Angelo Castello
  7. *
  8. * Based on the old arch/sh/kernel/cpu/rtc.c by:
  9. *
  10. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  11. * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
  12. *
  13. * This file is subject to the terms and conditions of the GNU General Public
  14. * License. See the file "COPYING" in the main directory of this archive
  15. * for more details.
  16. */
  17. #include <linux/module.h>
  18. #include <linux/kernel.h>
  19. #include <linux/bcd.h>
  20. #include <linux/rtc.h>
  21. #include <linux/init.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/seq_file.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/io.h>
  27. #include <linux/log2.h>
  28. #include <linux/clk.h>
  29. #include <linux/slab.h>
  30. #include <asm/rtc.h>
  31. #define DRV_NAME "sh-rtc"
  32. #define DRV_VERSION "0.2.3"
  33. #define RTC_REG(r) ((r) * rtc_reg_size)
  34. #define R64CNT RTC_REG(0)
  35. #define RSECCNT RTC_REG(1) /* RTC sec */
  36. #define RMINCNT RTC_REG(2) /* RTC min */
  37. #define RHRCNT RTC_REG(3) /* RTC hour */
  38. #define RWKCNT RTC_REG(4) /* RTC week */
  39. #define RDAYCNT RTC_REG(5) /* RTC day */
  40. #define RMONCNT RTC_REG(6) /* RTC month */
  41. #define RYRCNT RTC_REG(7) /* RTC year */
  42. #define RSECAR RTC_REG(8) /* ALARM sec */
  43. #define RMINAR RTC_REG(9) /* ALARM min */
  44. #define RHRAR RTC_REG(10) /* ALARM hour */
  45. #define RWKAR RTC_REG(11) /* ALARM week */
  46. #define RDAYAR RTC_REG(12) /* ALARM day */
  47. #define RMONAR RTC_REG(13) /* ALARM month */
  48. #define RCR1 RTC_REG(14) /* Control */
  49. #define RCR2 RTC_REG(15) /* Control */
  50. /*
  51. * Note on RYRAR and RCR3: Up until this point most of the register
  52. * definitions are consistent across all of the available parts. However,
  53. * the placement of the optional RYRAR and RCR3 (the RYRAR control
  54. * register used to control RYRCNT/RYRAR compare) varies considerably
  55. * across various parts, occasionally being mapped in to a completely
  56. * unrelated address space. For proper RYRAR support a separate resource
  57. * would have to be handed off, but as this is purely optional in
  58. * practice, we simply opt not to support it, thereby keeping the code
  59. * quite a bit more simplified.
  60. */
  61. /* ALARM Bits - or with BCD encoded value */
  62. #define AR_ENB 0x80 /* Enable for alarm cmp */
  63. /* Period Bits */
  64. #define PF_HP 0x100 /* Enable Half Period to support 8,32,128Hz */
  65. #define PF_COUNT 0x200 /* Half periodic counter */
  66. #define PF_OXS 0x400 /* Periodic One x Second */
  67. #define PF_KOU 0x800 /* Kernel or User periodic request 1=kernel */
  68. #define PF_MASK 0xf00
  69. /* RCR1 Bits */
  70. #define RCR1_CF 0x80 /* Carry Flag */
  71. #define RCR1_CIE 0x10 /* Carry Interrupt Enable */
  72. #define RCR1_AIE 0x08 /* Alarm Interrupt Enable */
  73. #define RCR1_AF 0x01 /* Alarm Flag */
  74. /* RCR2 Bits */
  75. #define RCR2_PEF 0x80 /* PEriodic interrupt Flag */
  76. #define RCR2_PESMASK 0x70 /* Periodic interrupt Set */
  77. #define RCR2_RTCEN 0x08 /* ENable RTC */
  78. #define RCR2_ADJ 0x04 /* ADJustment (30-second) */
  79. #define RCR2_RESET 0x02 /* Reset bit */
  80. #define RCR2_START 0x01 /* Start bit */
  81. struct sh_rtc {
  82. void __iomem *regbase;
  83. unsigned long regsize;
  84. struct resource *res;
  85. int alarm_irq;
  86. int periodic_irq;
  87. int carry_irq;
  88. struct clk *clk;
  89. struct rtc_device *rtc_dev;
  90. spinlock_t lock;
  91. unsigned long capabilities; /* See asm/rtc.h for cap bits */
  92. unsigned short periodic_freq;
  93. };
  94. static int __sh_rtc_interrupt(struct sh_rtc *rtc)
  95. {
  96. unsigned int tmp, pending;
  97. tmp = readb(rtc->regbase + RCR1);
  98. pending = tmp & RCR1_CF;
  99. tmp &= ~RCR1_CF;
  100. writeb(tmp, rtc->regbase + RCR1);
  101. /* Users have requested One x Second IRQ */
  102. if (pending && rtc->periodic_freq & PF_OXS)
  103. rtc_update_irq(rtc->rtc_dev, 1, RTC_UF | RTC_IRQF);
  104. return pending;
  105. }
  106. static int __sh_rtc_alarm(struct sh_rtc *rtc)
  107. {
  108. unsigned int tmp, pending;
  109. tmp = readb(rtc->regbase + RCR1);
  110. pending = tmp & RCR1_AF;
  111. tmp &= ~(RCR1_AF | RCR1_AIE);
  112. writeb(tmp, rtc->regbase + RCR1);
  113. if (pending)
  114. rtc_update_irq(rtc->rtc_dev, 1, RTC_AF | RTC_IRQF);
  115. return pending;
  116. }
  117. static int __sh_rtc_periodic(struct sh_rtc *rtc)
  118. {
  119. struct rtc_device *rtc_dev = rtc->rtc_dev;
  120. struct rtc_task *irq_task;
  121. unsigned int tmp, pending;
  122. tmp = readb(rtc->regbase + RCR2);
  123. pending = tmp & RCR2_PEF;
  124. tmp &= ~RCR2_PEF;
  125. writeb(tmp, rtc->regbase + RCR2);
  126. if (!pending)
  127. return 0;
  128. /* Half period enabled than one skipped and the next notified */
  129. if ((rtc->periodic_freq & PF_HP) && (rtc->periodic_freq & PF_COUNT))
  130. rtc->periodic_freq &= ~PF_COUNT;
  131. else {
  132. if (rtc->periodic_freq & PF_HP)
  133. rtc->periodic_freq |= PF_COUNT;
  134. if (rtc->periodic_freq & PF_KOU) {
  135. spin_lock(&rtc_dev->irq_task_lock);
  136. irq_task = rtc_dev->irq_task;
  137. if (irq_task)
  138. irq_task->func(irq_task->private_data);
  139. spin_unlock(&rtc_dev->irq_task_lock);
  140. } else
  141. rtc_update_irq(rtc->rtc_dev, 1, RTC_PF | RTC_IRQF);
  142. }
  143. return pending;
  144. }
  145. static irqreturn_t sh_rtc_interrupt(int irq, void *dev_id)
  146. {
  147. struct sh_rtc *rtc = dev_id;
  148. int ret;
  149. spin_lock(&rtc->lock);
  150. ret = __sh_rtc_interrupt(rtc);
  151. spin_unlock(&rtc->lock);
  152. return IRQ_RETVAL(ret);
  153. }
  154. static irqreturn_t sh_rtc_alarm(int irq, void *dev_id)
  155. {
  156. struct sh_rtc *rtc = dev_id;
  157. int ret;
  158. spin_lock(&rtc->lock);
  159. ret = __sh_rtc_alarm(rtc);
  160. spin_unlock(&rtc->lock);
  161. return IRQ_RETVAL(ret);
  162. }
  163. static irqreturn_t sh_rtc_periodic(int irq, void *dev_id)
  164. {
  165. struct sh_rtc *rtc = dev_id;
  166. int ret;
  167. spin_lock(&rtc->lock);
  168. ret = __sh_rtc_periodic(rtc);
  169. spin_unlock(&rtc->lock);
  170. return IRQ_RETVAL(ret);
  171. }
  172. static irqreturn_t sh_rtc_shared(int irq, void *dev_id)
  173. {
  174. struct sh_rtc *rtc = dev_id;
  175. int ret;
  176. spin_lock(&rtc->lock);
  177. ret = __sh_rtc_interrupt(rtc);
  178. ret |= __sh_rtc_alarm(rtc);
  179. ret |= __sh_rtc_periodic(rtc);
  180. spin_unlock(&rtc->lock);
  181. return IRQ_RETVAL(ret);
  182. }
  183. static int sh_rtc_irq_set_state(struct device *dev, int enable)
  184. {
  185. struct sh_rtc *rtc = dev_get_drvdata(dev);
  186. unsigned int tmp;
  187. spin_lock_irq(&rtc->lock);
  188. tmp = readb(rtc->regbase + RCR2);
  189. if (enable) {
  190. rtc->periodic_freq |= PF_KOU;
  191. tmp &= ~RCR2_PEF; /* Clear PES bit */
  192. tmp |= (rtc->periodic_freq & ~PF_HP); /* Set PES2-0 */
  193. } else {
  194. rtc->periodic_freq &= ~PF_KOU;
  195. tmp &= ~(RCR2_PESMASK | RCR2_PEF);
  196. }
  197. writeb(tmp, rtc->regbase + RCR2);
  198. spin_unlock_irq(&rtc->lock);
  199. return 0;
  200. }
  201. static int sh_rtc_irq_set_freq(struct device *dev, int freq)
  202. {
  203. struct sh_rtc *rtc = dev_get_drvdata(dev);
  204. int tmp, ret = 0;
  205. spin_lock_irq(&rtc->lock);
  206. tmp = rtc->periodic_freq & PF_MASK;
  207. switch (freq) {
  208. case 0:
  209. rtc->periodic_freq = 0x00;
  210. break;
  211. case 1:
  212. rtc->periodic_freq = 0x60;
  213. break;
  214. case 2:
  215. rtc->periodic_freq = 0x50;
  216. break;
  217. case 4:
  218. rtc->periodic_freq = 0x40;
  219. break;
  220. case 8:
  221. rtc->periodic_freq = 0x30 | PF_HP;
  222. break;
  223. case 16:
  224. rtc->periodic_freq = 0x30;
  225. break;
  226. case 32:
  227. rtc->periodic_freq = 0x20 | PF_HP;
  228. break;
  229. case 64:
  230. rtc->periodic_freq = 0x20;
  231. break;
  232. case 128:
  233. rtc->periodic_freq = 0x10 | PF_HP;
  234. break;
  235. case 256:
  236. rtc->periodic_freq = 0x10;
  237. break;
  238. default:
  239. ret = -ENOTSUPP;
  240. }
  241. if (ret == 0)
  242. rtc->periodic_freq |= tmp;
  243. spin_unlock_irq(&rtc->lock);
  244. return ret;
  245. }
  246. static inline void sh_rtc_setaie(struct device *dev, unsigned int enable)
  247. {
  248. struct sh_rtc *rtc = dev_get_drvdata(dev);
  249. unsigned int tmp;
  250. spin_lock_irq(&rtc->lock);
  251. tmp = readb(rtc->regbase + RCR1);
  252. if (enable)
  253. tmp |= RCR1_AIE;
  254. else
  255. tmp &= ~RCR1_AIE;
  256. writeb(tmp, rtc->regbase + RCR1);
  257. spin_unlock_irq(&rtc->lock);
  258. }
  259. static int sh_rtc_proc(struct device *dev, struct seq_file *seq)
  260. {
  261. struct sh_rtc *rtc = dev_get_drvdata(dev);
  262. unsigned int tmp;
  263. tmp = readb(rtc->regbase + RCR1);
  264. seq_printf(seq, "carry_IRQ\t: %s\n", (tmp & RCR1_CIE) ? "yes" : "no");
  265. tmp = readb(rtc->regbase + RCR2);
  266. seq_printf(seq, "periodic_IRQ\t: %s\n",
  267. (tmp & RCR2_PESMASK) ? "yes" : "no");
  268. return 0;
  269. }
  270. static inline void sh_rtc_setcie(struct device *dev, unsigned int enable)
  271. {
  272. struct sh_rtc *rtc = dev_get_drvdata(dev);
  273. unsigned int tmp;
  274. spin_lock_irq(&rtc->lock);
  275. tmp = readb(rtc->regbase + RCR1);
  276. if (!enable)
  277. tmp &= ~RCR1_CIE;
  278. else
  279. tmp |= RCR1_CIE;
  280. writeb(tmp, rtc->regbase + RCR1);
  281. spin_unlock_irq(&rtc->lock);
  282. }
  283. static int sh_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  284. {
  285. sh_rtc_setaie(dev, enabled);
  286. return 0;
  287. }
  288. static int sh_rtc_read_time(struct device *dev, struct rtc_time *tm)
  289. {
  290. struct platform_device *pdev = to_platform_device(dev);
  291. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  292. unsigned int sec128, sec2, yr, yr100, cf_bit;
  293. do {
  294. unsigned int tmp;
  295. spin_lock_irq(&rtc->lock);
  296. tmp = readb(rtc->regbase + RCR1);
  297. tmp &= ~RCR1_CF; /* Clear CF-bit */
  298. tmp |= RCR1_CIE;
  299. writeb(tmp, rtc->regbase + RCR1);
  300. sec128 = readb(rtc->regbase + R64CNT);
  301. tm->tm_sec = bcd2bin(readb(rtc->regbase + RSECCNT));
  302. tm->tm_min = bcd2bin(readb(rtc->regbase + RMINCNT));
  303. tm->tm_hour = bcd2bin(readb(rtc->regbase + RHRCNT));
  304. tm->tm_wday = bcd2bin(readb(rtc->regbase + RWKCNT));
  305. tm->tm_mday = bcd2bin(readb(rtc->regbase + RDAYCNT));
  306. tm->tm_mon = bcd2bin(readb(rtc->regbase + RMONCNT)) - 1;
  307. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  308. yr = readw(rtc->regbase + RYRCNT);
  309. yr100 = bcd2bin(yr >> 8);
  310. yr &= 0xff;
  311. } else {
  312. yr = readb(rtc->regbase + RYRCNT);
  313. yr100 = bcd2bin((yr == 0x99) ? 0x19 : 0x20);
  314. }
  315. tm->tm_year = (yr100 * 100 + bcd2bin(yr)) - 1900;
  316. sec2 = readb(rtc->regbase + R64CNT);
  317. cf_bit = readb(rtc->regbase + RCR1) & RCR1_CF;
  318. spin_unlock_irq(&rtc->lock);
  319. } while (cf_bit != 0 || ((sec128 ^ sec2) & RTC_BIT_INVERTED) != 0);
  320. #if RTC_BIT_INVERTED != 0
  321. if ((sec128 & RTC_BIT_INVERTED))
  322. tm->tm_sec--;
  323. #endif
  324. /* only keep the carry interrupt enabled if UIE is on */
  325. if (!(rtc->periodic_freq & PF_OXS))
  326. sh_rtc_setcie(dev, 0);
  327. dev_dbg(dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
  328. "mday=%d, mon=%d, year=%d, wday=%d\n",
  329. __func__,
  330. tm->tm_sec, tm->tm_min, tm->tm_hour,
  331. tm->tm_mday, tm->tm_mon + 1, tm->tm_year, tm->tm_wday);
  332. return rtc_valid_tm(tm);
  333. }
  334. static int sh_rtc_set_time(struct device *dev, struct rtc_time *tm)
  335. {
  336. struct platform_device *pdev = to_platform_device(dev);
  337. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  338. unsigned int tmp;
  339. int year;
  340. spin_lock_irq(&rtc->lock);
  341. /* Reset pre-scaler & stop RTC */
  342. tmp = readb(rtc->regbase + RCR2);
  343. tmp |= RCR2_RESET;
  344. tmp &= ~RCR2_START;
  345. writeb(tmp, rtc->regbase + RCR2);
  346. writeb(bin2bcd(tm->tm_sec), rtc->regbase + RSECCNT);
  347. writeb(bin2bcd(tm->tm_min), rtc->regbase + RMINCNT);
  348. writeb(bin2bcd(tm->tm_hour), rtc->regbase + RHRCNT);
  349. writeb(bin2bcd(tm->tm_wday), rtc->regbase + RWKCNT);
  350. writeb(bin2bcd(tm->tm_mday), rtc->regbase + RDAYCNT);
  351. writeb(bin2bcd(tm->tm_mon + 1), rtc->regbase + RMONCNT);
  352. if (rtc->capabilities & RTC_CAP_4_DIGIT_YEAR) {
  353. year = (bin2bcd((tm->tm_year + 1900) / 100) << 8) |
  354. bin2bcd(tm->tm_year % 100);
  355. writew(year, rtc->regbase + RYRCNT);
  356. } else {
  357. year = tm->tm_year % 100;
  358. writeb(bin2bcd(year), rtc->regbase + RYRCNT);
  359. }
  360. /* Start RTC */
  361. tmp = readb(rtc->regbase + RCR2);
  362. tmp &= ~RCR2_RESET;
  363. tmp |= RCR2_RTCEN | RCR2_START;
  364. writeb(tmp, rtc->regbase + RCR2);
  365. spin_unlock_irq(&rtc->lock);
  366. return 0;
  367. }
  368. static inline int sh_rtc_read_alarm_value(struct sh_rtc *rtc, int reg_off)
  369. {
  370. unsigned int byte;
  371. int value = 0xff; /* return 0xff for ignored values */
  372. byte = readb(rtc->regbase + reg_off);
  373. if (byte & AR_ENB) {
  374. byte &= ~AR_ENB; /* strip the enable bit */
  375. value = bcd2bin(byte);
  376. }
  377. return value;
  378. }
  379. static int sh_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  380. {
  381. struct platform_device *pdev = to_platform_device(dev);
  382. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  383. struct rtc_time *tm = &wkalrm->time;
  384. spin_lock_irq(&rtc->lock);
  385. tm->tm_sec = sh_rtc_read_alarm_value(rtc, RSECAR);
  386. tm->tm_min = sh_rtc_read_alarm_value(rtc, RMINAR);
  387. tm->tm_hour = sh_rtc_read_alarm_value(rtc, RHRAR);
  388. tm->tm_wday = sh_rtc_read_alarm_value(rtc, RWKAR);
  389. tm->tm_mday = sh_rtc_read_alarm_value(rtc, RDAYAR);
  390. tm->tm_mon = sh_rtc_read_alarm_value(rtc, RMONAR);
  391. if (tm->tm_mon > 0)
  392. tm->tm_mon -= 1; /* RTC is 1-12, tm_mon is 0-11 */
  393. tm->tm_year = 0xffff;
  394. wkalrm->enabled = (readb(rtc->regbase + RCR1) & RCR1_AIE) ? 1 : 0;
  395. spin_unlock_irq(&rtc->lock);
  396. return 0;
  397. }
  398. static inline void sh_rtc_write_alarm_value(struct sh_rtc *rtc,
  399. int value, int reg_off)
  400. {
  401. /* < 0 for a value that is ignored */
  402. if (value < 0)
  403. writeb(0, rtc->regbase + reg_off);
  404. else
  405. writeb(bin2bcd(value) | AR_ENB, rtc->regbase + reg_off);
  406. }
  407. static int sh_rtc_check_alarm(struct rtc_time *tm)
  408. {
  409. /*
  410. * The original rtc says anything > 0xc0 is "don't care" or "match
  411. * all" - most users use 0xff but rtc-dev uses -1 for the same thing.
  412. * The original rtc doesn't support years - some things use -1 and
  413. * some 0xffff. We use -1 to make out tests easier.
  414. */
  415. if (tm->tm_year == 0xffff)
  416. tm->tm_year = -1;
  417. if (tm->tm_mon >= 0xff)
  418. tm->tm_mon = -1;
  419. if (tm->tm_mday >= 0xff)
  420. tm->tm_mday = -1;
  421. if (tm->tm_wday >= 0xff)
  422. tm->tm_wday = -1;
  423. if (tm->tm_hour >= 0xff)
  424. tm->tm_hour = -1;
  425. if (tm->tm_min >= 0xff)
  426. tm->tm_min = -1;
  427. if (tm->tm_sec >= 0xff)
  428. tm->tm_sec = -1;
  429. if (tm->tm_year > 9999 ||
  430. tm->tm_mon >= 12 ||
  431. tm->tm_mday == 0 || tm->tm_mday >= 32 ||
  432. tm->tm_wday >= 7 ||
  433. tm->tm_hour >= 24 ||
  434. tm->tm_min >= 60 ||
  435. tm->tm_sec >= 60)
  436. return -EINVAL;
  437. return 0;
  438. }
  439. static int sh_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  440. {
  441. struct platform_device *pdev = to_platform_device(dev);
  442. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  443. unsigned int rcr1;
  444. struct rtc_time *tm = &wkalrm->time;
  445. int mon, err;
  446. err = sh_rtc_check_alarm(tm);
  447. if (unlikely(err < 0))
  448. return err;
  449. spin_lock_irq(&rtc->lock);
  450. /* disable alarm interrupt and clear the alarm flag */
  451. rcr1 = readb(rtc->regbase + RCR1);
  452. rcr1 &= ~(RCR1_AF | RCR1_AIE);
  453. writeb(rcr1, rtc->regbase + RCR1);
  454. /* set alarm time */
  455. sh_rtc_write_alarm_value(rtc, tm->tm_sec, RSECAR);
  456. sh_rtc_write_alarm_value(rtc, tm->tm_min, RMINAR);
  457. sh_rtc_write_alarm_value(rtc, tm->tm_hour, RHRAR);
  458. sh_rtc_write_alarm_value(rtc, tm->tm_wday, RWKAR);
  459. sh_rtc_write_alarm_value(rtc, tm->tm_mday, RDAYAR);
  460. mon = tm->tm_mon;
  461. if (mon >= 0)
  462. mon += 1;
  463. sh_rtc_write_alarm_value(rtc, mon, RMONAR);
  464. if (wkalrm->enabled) {
  465. rcr1 |= RCR1_AIE;
  466. writeb(rcr1, rtc->regbase + RCR1);
  467. }
  468. spin_unlock_irq(&rtc->lock);
  469. return 0;
  470. }
  471. static struct rtc_class_ops sh_rtc_ops = {
  472. .read_time = sh_rtc_read_time,
  473. .set_time = sh_rtc_set_time,
  474. .read_alarm = sh_rtc_read_alarm,
  475. .set_alarm = sh_rtc_set_alarm,
  476. .proc = sh_rtc_proc,
  477. .alarm_irq_enable = sh_rtc_alarm_irq_enable,
  478. };
  479. static int __init sh_rtc_probe(struct platform_device *pdev)
  480. {
  481. struct sh_rtc *rtc;
  482. struct resource *res;
  483. struct rtc_time r;
  484. char clk_name[6];
  485. int clk_id, ret;
  486. rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
  487. if (unlikely(!rtc))
  488. return -ENOMEM;
  489. spin_lock_init(&rtc->lock);
  490. /* get periodic/carry/alarm irqs */
  491. ret = platform_get_irq(pdev, 0);
  492. if (unlikely(ret <= 0)) {
  493. dev_err(&pdev->dev, "No IRQ resource\n");
  494. return -ENOENT;
  495. }
  496. rtc->periodic_irq = ret;
  497. rtc->carry_irq = platform_get_irq(pdev, 1);
  498. rtc->alarm_irq = platform_get_irq(pdev, 2);
  499. res = platform_get_resource(pdev, IORESOURCE_IO, 0);
  500. if (unlikely(res == NULL)) {
  501. dev_err(&pdev->dev, "No IO resource\n");
  502. return -ENOENT;
  503. }
  504. rtc->regsize = resource_size(res);
  505. rtc->res = devm_request_mem_region(&pdev->dev, res->start,
  506. rtc->regsize, pdev->name);
  507. if (unlikely(!rtc->res))
  508. return -EBUSY;
  509. rtc->regbase = devm_ioremap_nocache(&pdev->dev, rtc->res->start,
  510. rtc->regsize);
  511. if (unlikely(!rtc->regbase))
  512. return -EINVAL;
  513. clk_id = pdev->id;
  514. /* With a single device, the clock id is still "rtc0" */
  515. if (clk_id < 0)
  516. clk_id = 0;
  517. snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id);
  518. rtc->clk = devm_clk_get(&pdev->dev, clk_name);
  519. if (IS_ERR(rtc->clk)) {
  520. /*
  521. * No error handling for rtc->clk intentionally, not all
  522. * platforms will have a unique clock for the RTC, and
  523. * the clk API can handle the struct clk pointer being
  524. * NULL.
  525. */
  526. rtc->clk = NULL;
  527. }
  528. clk_enable(rtc->clk);
  529. rtc->capabilities = RTC_DEF_CAPABILITIES;
  530. if (dev_get_platdata(&pdev->dev)) {
  531. struct sh_rtc_platform_info *pinfo =
  532. dev_get_platdata(&pdev->dev);
  533. /*
  534. * Some CPUs have special capabilities in addition to the
  535. * default set. Add those in here.
  536. */
  537. rtc->capabilities |= pinfo->capabilities;
  538. }
  539. if (rtc->carry_irq <= 0) {
  540. /* register shared periodic/carry/alarm irq */
  541. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  542. sh_rtc_shared, 0, "sh-rtc", rtc);
  543. if (unlikely(ret)) {
  544. dev_err(&pdev->dev,
  545. "request IRQ failed with %d, IRQ %d\n", ret,
  546. rtc->periodic_irq);
  547. goto err_unmap;
  548. }
  549. } else {
  550. /* register periodic/carry/alarm irqs */
  551. ret = devm_request_irq(&pdev->dev, rtc->periodic_irq,
  552. sh_rtc_periodic, 0, "sh-rtc period", rtc);
  553. if (unlikely(ret)) {
  554. dev_err(&pdev->dev,
  555. "request period IRQ failed with %d, IRQ %d\n",
  556. ret, rtc->periodic_irq);
  557. goto err_unmap;
  558. }
  559. ret = devm_request_irq(&pdev->dev, rtc->carry_irq,
  560. sh_rtc_interrupt, 0, "sh-rtc carry", rtc);
  561. if (unlikely(ret)) {
  562. dev_err(&pdev->dev,
  563. "request carry IRQ failed with %d, IRQ %d\n",
  564. ret, rtc->carry_irq);
  565. goto err_unmap;
  566. }
  567. ret = devm_request_irq(&pdev->dev, rtc->alarm_irq,
  568. sh_rtc_alarm, 0, "sh-rtc alarm", rtc);
  569. if (unlikely(ret)) {
  570. dev_err(&pdev->dev,
  571. "request alarm IRQ failed with %d, IRQ %d\n",
  572. ret, rtc->alarm_irq);
  573. goto err_unmap;
  574. }
  575. }
  576. platform_set_drvdata(pdev, rtc);
  577. /* everything disabled by default */
  578. sh_rtc_irq_set_freq(&pdev->dev, 0);
  579. sh_rtc_irq_set_state(&pdev->dev, 0);
  580. sh_rtc_setaie(&pdev->dev, 0);
  581. sh_rtc_setcie(&pdev->dev, 0);
  582. rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, "sh",
  583. &sh_rtc_ops, THIS_MODULE);
  584. if (IS_ERR(rtc->rtc_dev)) {
  585. ret = PTR_ERR(rtc->rtc_dev);
  586. goto err_unmap;
  587. }
  588. rtc->rtc_dev->max_user_freq = 256;
  589. /* reset rtc to epoch 0 if time is invalid */
  590. if (rtc_read_time(rtc->rtc_dev, &r) < 0) {
  591. rtc_time_to_tm(0, &r);
  592. rtc_set_time(rtc->rtc_dev, &r);
  593. }
  594. device_init_wakeup(&pdev->dev, 1);
  595. return 0;
  596. err_unmap:
  597. clk_disable(rtc->clk);
  598. return ret;
  599. }
  600. static int __exit sh_rtc_remove(struct platform_device *pdev)
  601. {
  602. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  603. sh_rtc_irq_set_state(&pdev->dev, 0);
  604. sh_rtc_setaie(&pdev->dev, 0);
  605. sh_rtc_setcie(&pdev->dev, 0);
  606. clk_disable(rtc->clk);
  607. return 0;
  608. }
  609. static void sh_rtc_set_irq_wake(struct device *dev, int enabled)
  610. {
  611. struct platform_device *pdev = to_platform_device(dev);
  612. struct sh_rtc *rtc = platform_get_drvdata(pdev);
  613. irq_set_irq_wake(rtc->periodic_irq, enabled);
  614. if (rtc->carry_irq > 0) {
  615. irq_set_irq_wake(rtc->carry_irq, enabled);
  616. irq_set_irq_wake(rtc->alarm_irq, enabled);
  617. }
  618. }
  619. #ifdef CONFIG_PM_SLEEP
  620. static int sh_rtc_suspend(struct device *dev)
  621. {
  622. if (device_may_wakeup(dev))
  623. sh_rtc_set_irq_wake(dev, 1);
  624. return 0;
  625. }
  626. static int sh_rtc_resume(struct device *dev)
  627. {
  628. if (device_may_wakeup(dev))
  629. sh_rtc_set_irq_wake(dev, 0);
  630. return 0;
  631. }
  632. #endif
  633. static SIMPLE_DEV_PM_OPS(sh_rtc_pm_ops, sh_rtc_suspend, sh_rtc_resume);
  634. static struct platform_driver sh_rtc_platform_driver = {
  635. .driver = {
  636. .name = DRV_NAME,
  637. .pm = &sh_rtc_pm_ops,
  638. },
  639. .remove = __exit_p(sh_rtc_remove),
  640. };
  641. module_platform_driver_probe(sh_rtc_platform_driver, sh_rtc_probe);
  642. MODULE_DESCRIPTION("SuperH on-chip RTC driver");
  643. MODULE_VERSION(DRV_VERSION);
  644. MODULE_AUTHOR("Paul Mundt <lethal@linux-sh.org>, "
  645. "Jamie Lenehan <lenehan@twibble.org>, "
  646. "Angelo Castello <angelo.castello@st.com>");
  647. MODULE_LICENSE("GPL");
  648. MODULE_ALIAS("platform:" DRV_NAME);