rtc-sun6i.c 12 KB

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  1. /*
  2. * An RTC driver for Allwinner A31/A23
  3. *
  4. * Copyright (c) 2014, Chen-Yu Tsai <wens@csie.org>
  5. *
  6. * based on rtc-sunxi.c
  7. *
  8. * An RTC driver for Allwinner A10/A20
  9. *
  10. * Copyright (c) 2013, Carlo Caione <carlo.caione@gmail.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License as published by
  14. * the Free Software Foundation; either version 2 of the License, or
  15. * (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful, but WITHOUT
  18. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  20. * more details.
  21. */
  22. #include <linux/delay.h>
  23. #include <linux/err.h>
  24. #include <linux/fs.h>
  25. #include <linux/init.h>
  26. #include <linux/interrupt.h>
  27. #include <linux/io.h>
  28. #include <linux/kernel.h>
  29. #include <linux/module.h>
  30. #include <linux/of.h>
  31. #include <linux/of_address.h>
  32. #include <linux/of_device.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/rtc.h>
  35. #include <linux/types.h>
  36. /* Control register */
  37. #define SUN6I_LOSC_CTRL 0x0000
  38. #define SUN6I_LOSC_CTRL_KEY (0x16aa << 16)
  39. #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC BIT(9)
  40. #define SUN6I_LOSC_CTRL_RTC_HMS_ACC BIT(8)
  41. #define SUN6I_LOSC_CTRL_RTC_YMD_ACC BIT(7)
  42. #define SUN6I_LOSC_CTRL_EXT_OSC BIT(0)
  43. #define SUN6I_LOSC_CTRL_ACC_MASK GENMASK(9, 7)
  44. /* RTC */
  45. #define SUN6I_RTC_YMD 0x0010
  46. #define SUN6I_RTC_HMS 0x0014
  47. /* Alarm 0 (counter) */
  48. #define SUN6I_ALRM_COUNTER 0x0020
  49. #define SUN6I_ALRM_CUR_VAL 0x0024
  50. #define SUN6I_ALRM_EN 0x0028
  51. #define SUN6I_ALRM_EN_CNT_EN BIT(0)
  52. #define SUN6I_ALRM_IRQ_EN 0x002c
  53. #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN BIT(0)
  54. #define SUN6I_ALRM_IRQ_STA 0x0030
  55. #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND BIT(0)
  56. /* Alarm 1 (wall clock) */
  57. #define SUN6I_ALRM1_EN 0x0044
  58. #define SUN6I_ALRM1_IRQ_EN 0x0048
  59. #define SUN6I_ALRM1_IRQ_STA 0x004c
  60. #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND BIT(0)
  61. /* Alarm config */
  62. #define SUN6I_ALARM_CONFIG 0x0050
  63. #define SUN6I_ALARM_CONFIG_WAKEUP BIT(0)
  64. /*
  65. * Get date values
  66. */
  67. #define SUN6I_DATE_GET_DAY_VALUE(x) ((x) & 0x0000001f)
  68. #define SUN6I_DATE_GET_MON_VALUE(x) (((x) & 0x00000f00) >> 8)
  69. #define SUN6I_DATE_GET_YEAR_VALUE(x) (((x) & 0x003f0000) >> 16)
  70. #define SUN6I_LEAP_GET_VALUE(x) (((x) & 0x00400000) >> 22)
  71. /*
  72. * Get time values
  73. */
  74. #define SUN6I_TIME_GET_SEC_VALUE(x) ((x) & 0x0000003f)
  75. #define SUN6I_TIME_GET_MIN_VALUE(x) (((x) & 0x00003f00) >> 8)
  76. #define SUN6I_TIME_GET_HOUR_VALUE(x) (((x) & 0x001f0000) >> 16)
  77. /*
  78. * Set date values
  79. */
  80. #define SUN6I_DATE_SET_DAY_VALUE(x) ((x) & 0x0000001f)
  81. #define SUN6I_DATE_SET_MON_VALUE(x) ((x) << 8 & 0x00000f00)
  82. #define SUN6I_DATE_SET_YEAR_VALUE(x) ((x) << 16 & 0x003f0000)
  83. #define SUN6I_LEAP_SET_VALUE(x) ((x) << 22 & 0x00400000)
  84. /*
  85. * Set time values
  86. */
  87. #define SUN6I_TIME_SET_SEC_VALUE(x) ((x) & 0x0000003f)
  88. #define SUN6I_TIME_SET_MIN_VALUE(x) ((x) << 8 & 0x00003f00)
  89. #define SUN6I_TIME_SET_HOUR_VALUE(x) ((x) << 16 & 0x001f0000)
  90. /*
  91. * The year parameter passed to the driver is usually an offset relative to
  92. * the year 1900. This macro is used to convert this offset to another one
  93. * relative to the minimum year allowed by the hardware.
  94. *
  95. * The year range is 1970 - 2033. This range is selected to match Allwinner's
  96. * driver, even though it is somewhat limited.
  97. */
  98. #define SUN6I_YEAR_MIN 1970
  99. #define SUN6I_YEAR_MAX 2033
  100. #define SUN6I_YEAR_OFF (SUN6I_YEAR_MIN - 1900)
  101. struct sun6i_rtc_dev {
  102. struct rtc_device *rtc;
  103. struct device *dev;
  104. void __iomem *base;
  105. int irq;
  106. unsigned long alarm;
  107. spinlock_t lock;
  108. };
  109. static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id)
  110. {
  111. struct sun6i_rtc_dev *chip = (struct sun6i_rtc_dev *) id;
  112. irqreturn_t ret = IRQ_NONE;
  113. u32 val;
  114. spin_lock(&chip->lock);
  115. val = readl(chip->base + SUN6I_ALRM_IRQ_STA);
  116. if (val & SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND) {
  117. val |= SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND;
  118. writel(val, chip->base + SUN6I_ALRM_IRQ_STA);
  119. rtc_update_irq(chip->rtc, 1, RTC_AF | RTC_IRQF);
  120. ret = IRQ_HANDLED;
  121. }
  122. spin_unlock(&chip->lock);
  123. return ret;
  124. }
  125. static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip)
  126. {
  127. u32 alrm_val = 0;
  128. u32 alrm_irq_val = 0;
  129. u32 alrm_wake_val = 0;
  130. unsigned long flags;
  131. if (to) {
  132. alrm_val = SUN6I_ALRM_EN_CNT_EN;
  133. alrm_irq_val = SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN;
  134. alrm_wake_val = SUN6I_ALARM_CONFIG_WAKEUP;
  135. } else {
  136. writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
  137. chip->base + SUN6I_ALRM_IRQ_STA);
  138. }
  139. spin_lock_irqsave(&chip->lock, flags);
  140. writel(alrm_val, chip->base + SUN6I_ALRM_EN);
  141. writel(alrm_irq_val, chip->base + SUN6I_ALRM_IRQ_EN);
  142. writel(alrm_wake_val, chip->base + SUN6I_ALARM_CONFIG);
  143. spin_unlock_irqrestore(&chip->lock, flags);
  144. }
  145. static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm)
  146. {
  147. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  148. u32 date, time;
  149. /*
  150. * read again in case it changes
  151. */
  152. do {
  153. date = readl(chip->base + SUN6I_RTC_YMD);
  154. time = readl(chip->base + SUN6I_RTC_HMS);
  155. } while ((date != readl(chip->base + SUN6I_RTC_YMD)) ||
  156. (time != readl(chip->base + SUN6I_RTC_HMS)));
  157. rtc_tm->tm_sec = SUN6I_TIME_GET_SEC_VALUE(time);
  158. rtc_tm->tm_min = SUN6I_TIME_GET_MIN_VALUE(time);
  159. rtc_tm->tm_hour = SUN6I_TIME_GET_HOUR_VALUE(time);
  160. rtc_tm->tm_mday = SUN6I_DATE_GET_DAY_VALUE(date);
  161. rtc_tm->tm_mon = SUN6I_DATE_GET_MON_VALUE(date);
  162. rtc_tm->tm_year = SUN6I_DATE_GET_YEAR_VALUE(date);
  163. rtc_tm->tm_mon -= 1;
  164. /*
  165. * switch from (data_year->min)-relative offset to
  166. * a (1900)-relative one
  167. */
  168. rtc_tm->tm_year += SUN6I_YEAR_OFF;
  169. return rtc_valid_tm(rtc_tm);
  170. }
  171. static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  172. {
  173. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  174. unsigned long flags;
  175. u32 alrm_st;
  176. u32 alrm_en;
  177. spin_lock_irqsave(&chip->lock, flags);
  178. alrm_en = readl(chip->base + SUN6I_ALRM_IRQ_EN);
  179. alrm_st = readl(chip->base + SUN6I_ALRM_IRQ_STA);
  180. spin_unlock_irqrestore(&chip->lock, flags);
  181. wkalrm->enabled = !!(alrm_en & SUN6I_ALRM_EN_CNT_EN);
  182. wkalrm->pending = !!(alrm_st & SUN6I_ALRM_EN_CNT_EN);
  183. rtc_time_to_tm(chip->alarm, &wkalrm->time);
  184. return 0;
  185. }
  186. static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm)
  187. {
  188. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  189. struct rtc_time *alrm_tm = &wkalrm->time;
  190. struct rtc_time tm_now;
  191. unsigned long time_now = 0;
  192. unsigned long time_set = 0;
  193. unsigned long time_gap = 0;
  194. int ret = 0;
  195. ret = sun6i_rtc_gettime(dev, &tm_now);
  196. if (ret < 0) {
  197. dev_err(dev, "Error in getting time\n");
  198. return -EINVAL;
  199. }
  200. rtc_tm_to_time(alrm_tm, &time_set);
  201. rtc_tm_to_time(&tm_now, &time_now);
  202. if (time_set <= time_now) {
  203. dev_err(dev, "Date to set in the past\n");
  204. return -EINVAL;
  205. }
  206. time_gap = time_set - time_now;
  207. if (time_gap > U32_MAX) {
  208. dev_err(dev, "Date too far in the future\n");
  209. return -EINVAL;
  210. }
  211. sun6i_rtc_setaie(0, chip);
  212. writel(0, chip->base + SUN6I_ALRM_COUNTER);
  213. usleep_range(100, 300);
  214. writel(time_gap, chip->base + SUN6I_ALRM_COUNTER);
  215. chip->alarm = time_set;
  216. sun6i_rtc_setaie(wkalrm->enabled, chip);
  217. return 0;
  218. }
  219. static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset,
  220. unsigned int mask, unsigned int ms_timeout)
  221. {
  222. const unsigned long timeout = jiffies + msecs_to_jiffies(ms_timeout);
  223. u32 reg;
  224. do {
  225. reg = readl(chip->base + offset);
  226. reg &= mask;
  227. if (!reg)
  228. return 0;
  229. } while (time_before(jiffies, timeout));
  230. return -ETIMEDOUT;
  231. }
  232. static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm)
  233. {
  234. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  235. u32 date = 0;
  236. u32 time = 0;
  237. int year;
  238. year = rtc_tm->tm_year + 1900;
  239. if (year < SUN6I_YEAR_MIN || year > SUN6I_YEAR_MAX) {
  240. dev_err(dev, "rtc only supports year in range %d - %d\n",
  241. SUN6I_YEAR_MIN, SUN6I_YEAR_MAX);
  242. return -EINVAL;
  243. }
  244. rtc_tm->tm_year -= SUN6I_YEAR_OFF;
  245. rtc_tm->tm_mon += 1;
  246. date = SUN6I_DATE_SET_DAY_VALUE(rtc_tm->tm_mday) |
  247. SUN6I_DATE_SET_MON_VALUE(rtc_tm->tm_mon) |
  248. SUN6I_DATE_SET_YEAR_VALUE(rtc_tm->tm_year);
  249. if (is_leap_year(year))
  250. date |= SUN6I_LEAP_SET_VALUE(1);
  251. time = SUN6I_TIME_SET_SEC_VALUE(rtc_tm->tm_sec) |
  252. SUN6I_TIME_SET_MIN_VALUE(rtc_tm->tm_min) |
  253. SUN6I_TIME_SET_HOUR_VALUE(rtc_tm->tm_hour);
  254. /* Check whether registers are writable */
  255. if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
  256. SUN6I_LOSC_CTRL_ACC_MASK, 50)) {
  257. dev_err(dev, "rtc is still busy.\n");
  258. return -EBUSY;
  259. }
  260. writel(time, chip->base + SUN6I_RTC_HMS);
  261. /*
  262. * After writing the RTC HH-MM-SS register, the
  263. * SUN6I_LOSC_CTRL_RTC_HMS_ACC bit is set and it will not
  264. * be cleared until the real writing operation is finished
  265. */
  266. if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
  267. SUN6I_LOSC_CTRL_RTC_HMS_ACC, 50)) {
  268. dev_err(dev, "Failed to set rtc time.\n");
  269. return -ETIMEDOUT;
  270. }
  271. writel(date, chip->base + SUN6I_RTC_YMD);
  272. /*
  273. * After writing the RTC YY-MM-DD register, the
  274. * SUN6I_LOSC_CTRL_RTC_YMD_ACC bit is set and it will not
  275. * be cleared until the real writing operation is finished
  276. */
  277. if (sun6i_rtc_wait(chip, SUN6I_LOSC_CTRL,
  278. SUN6I_LOSC_CTRL_RTC_YMD_ACC, 50)) {
  279. dev_err(dev, "Failed to set rtc time.\n");
  280. return -ETIMEDOUT;
  281. }
  282. return 0;
  283. }
  284. static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  285. {
  286. struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
  287. if (!enabled)
  288. sun6i_rtc_setaie(enabled, chip);
  289. return 0;
  290. }
  291. static const struct rtc_class_ops sun6i_rtc_ops = {
  292. .read_time = sun6i_rtc_gettime,
  293. .set_time = sun6i_rtc_settime,
  294. .read_alarm = sun6i_rtc_getalarm,
  295. .set_alarm = sun6i_rtc_setalarm,
  296. .alarm_irq_enable = sun6i_rtc_alarm_irq_enable
  297. };
  298. static int sun6i_rtc_probe(struct platform_device *pdev)
  299. {
  300. struct sun6i_rtc_dev *chip;
  301. struct resource *res;
  302. int ret;
  303. chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
  304. if (!chip)
  305. return -ENOMEM;
  306. spin_lock_init(&chip->lock);
  307. platform_set_drvdata(pdev, chip);
  308. chip->dev = &pdev->dev;
  309. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  310. chip->base = devm_ioremap_resource(&pdev->dev, res);
  311. if (IS_ERR(chip->base))
  312. return PTR_ERR(chip->base);
  313. chip->irq = platform_get_irq(pdev, 0);
  314. if (chip->irq < 0) {
  315. dev_err(&pdev->dev, "No IRQ resource\n");
  316. return chip->irq;
  317. }
  318. ret = devm_request_irq(&pdev->dev, chip->irq, sun6i_rtc_alarmirq,
  319. 0, dev_name(&pdev->dev), chip);
  320. if (ret) {
  321. dev_err(&pdev->dev, "Could not request IRQ\n");
  322. return ret;
  323. }
  324. /* clear the alarm counter value */
  325. writel(0, chip->base + SUN6I_ALRM_COUNTER);
  326. /* disable counter alarm */
  327. writel(0, chip->base + SUN6I_ALRM_EN);
  328. /* disable counter alarm interrupt */
  329. writel(0, chip->base + SUN6I_ALRM_IRQ_EN);
  330. /* disable week alarm */
  331. writel(0, chip->base + SUN6I_ALRM1_EN);
  332. /* disable week alarm interrupt */
  333. writel(0, chip->base + SUN6I_ALRM1_IRQ_EN);
  334. /* clear counter alarm pending interrupts */
  335. writel(SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND,
  336. chip->base + SUN6I_ALRM_IRQ_STA);
  337. /* clear week alarm pending interrupts */
  338. writel(SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND,
  339. chip->base + SUN6I_ALRM1_IRQ_STA);
  340. /* disable alarm wakeup */
  341. writel(0, chip->base + SUN6I_ALARM_CONFIG);
  342. /* switch to the external, more precise, oscillator */
  343. writel(SUN6I_LOSC_CTRL_KEY | SUN6I_LOSC_CTRL_EXT_OSC,
  344. chip->base + SUN6I_LOSC_CTRL);
  345. chip->rtc = rtc_device_register("rtc-sun6i", &pdev->dev,
  346. &sun6i_rtc_ops, THIS_MODULE);
  347. if (IS_ERR(chip->rtc)) {
  348. dev_err(&pdev->dev, "unable to register device\n");
  349. return PTR_ERR(chip->rtc);
  350. }
  351. dev_info(&pdev->dev, "RTC enabled\n");
  352. return 0;
  353. }
  354. static int sun6i_rtc_remove(struct platform_device *pdev)
  355. {
  356. struct sun6i_rtc_dev *chip = platform_get_drvdata(pdev);
  357. rtc_device_unregister(chip->rtc);
  358. return 0;
  359. }
  360. static const struct of_device_id sun6i_rtc_dt_ids[] = {
  361. { .compatible = "allwinner,sun6i-a31-rtc" },
  362. { /* sentinel */ },
  363. };
  364. MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
  365. static struct platform_driver sun6i_rtc_driver = {
  366. .probe = sun6i_rtc_probe,
  367. .remove = sun6i_rtc_remove,
  368. .driver = {
  369. .name = "sun6i-rtc",
  370. .of_match_table = sun6i_rtc_dt_ids,
  371. },
  372. };
  373. module_platform_driver(sun6i_rtc_driver);
  374. MODULE_DESCRIPTION("sun6i RTC driver");
  375. MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>");
  376. MODULE_LICENSE("GPL");