aic7xxx_osm_pci.c 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470
  1. /*
  2. * Linux driver attachment glue for PCI based controllers.
  3. *
  4. * Copyright (c) 2000-2001 Adaptec Inc.
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions, and the following disclaimer,
  12. * without modification.
  13. * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14. * substantially similar to the "NO WARRANTY" disclaimer below
  15. * ("Disclaimer") and any redistribution must be conditioned upon
  16. * including a substantially similar Disclaimer requirement for further
  17. * binary redistribution.
  18. * 3. Neither the names of the above-listed copyright holders nor the names
  19. * of any contributors may be used to endorse or promote products derived
  20. * from this software without specific prior written permission.
  21. *
  22. * Alternatively, this software may be distributed under the terms of the
  23. * GNU General Public License ("GPL") version 2 as published by the Free
  24. * Software Foundation.
  25. *
  26. * NO WARRANTY
  27. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30. * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31. * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33. * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35. * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36. * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37. * POSSIBILITY OF SUCH DAMAGES.
  38. *
  39. * $Id: //depot/aic7xxx/linux/drivers/scsi/aic7xxx/aic7xxx_osm_pci.c#47 $
  40. */
  41. #include "aic7xxx_osm.h"
  42. #include "aic7xxx_pci.h"
  43. /* Define the macro locally since it's different for different class of chips.
  44. */
  45. #define ID(x) ID_C(x, PCI_CLASS_STORAGE_SCSI)
  46. static const struct pci_device_id ahc_linux_pci_id_table[] = {
  47. /* aic7850 based controllers */
  48. ID(ID_AHA_2902_04_10_15_20C_30C),
  49. /* aic7860 based controllers */
  50. ID(ID_AHA_2930CU),
  51. ID(ID_AHA_1480A & ID_DEV_VENDOR_MASK),
  52. ID(ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK),
  53. ID(ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK),
  54. ID(ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK),
  55. /* aic7870 based controllers */
  56. ID(ID_AHA_2940),
  57. ID(ID_AHA_3940),
  58. ID(ID_AHA_398X),
  59. ID(ID_AHA_2944),
  60. ID(ID_AHA_3944),
  61. ID(ID_AHA_4944),
  62. /* aic7880 based controllers */
  63. ID(ID_AHA_2940U & ID_DEV_VENDOR_MASK),
  64. ID(ID_AHA_3940U & ID_DEV_VENDOR_MASK),
  65. ID(ID_AHA_2944U & ID_DEV_VENDOR_MASK),
  66. ID(ID_AHA_3944U & ID_DEV_VENDOR_MASK),
  67. ID(ID_AHA_398XU & ID_DEV_VENDOR_MASK),
  68. ID(ID_AHA_4944U & ID_DEV_VENDOR_MASK),
  69. ID(ID_AHA_2930U & ID_DEV_VENDOR_MASK),
  70. ID(ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK),
  71. ID(ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK),
  72. /* aic7890 based controllers */
  73. ID(ID_AHA_2930U2),
  74. ID(ID_AHA_2940U2B),
  75. ID(ID_AHA_2940U2_OEM),
  76. ID(ID_AHA_2940U2),
  77. ID(ID_AHA_2950U2B),
  78. ID16(ID_AIC7890_ARO & ID_AIC7895_ARO_MASK),
  79. ID(ID_AAA_131U2),
  80. /* aic7890 based controllers */
  81. ID(ID_AHA_29160),
  82. ID(ID_AHA_29160_CPQ),
  83. ID(ID_AHA_29160N),
  84. ID(ID_AHA_29160C),
  85. ID(ID_AHA_29160B),
  86. ID(ID_AHA_19160B),
  87. ID(ID_AIC7892_ARO),
  88. /* aic7892 based controllers */
  89. ID(ID_AHA_2940U_DUAL),
  90. ID(ID_AHA_3940AU),
  91. ID(ID_AHA_3944AU),
  92. ID(ID_AIC7895_ARO),
  93. ID(ID_AHA_3950U2B_0),
  94. ID(ID_AHA_3950U2B_1),
  95. ID(ID_AHA_3950U2D_0),
  96. ID(ID_AHA_3950U2D_1),
  97. ID(ID_AIC7896_ARO),
  98. /* aic7899 based controllers */
  99. ID(ID_AHA_3960D),
  100. ID(ID_AHA_3960D_CPQ),
  101. ID(ID_AIC7899_ARO),
  102. /* Generic chip probes for devices we don't know exactly. */
  103. ID(ID_AIC7850 & ID_DEV_VENDOR_MASK),
  104. ID(ID_AIC7855 & ID_DEV_VENDOR_MASK),
  105. ID(ID_AIC7859 & ID_DEV_VENDOR_MASK),
  106. ID(ID_AIC7860 & ID_DEV_VENDOR_MASK),
  107. ID(ID_AIC7870 & ID_DEV_VENDOR_MASK),
  108. ID(ID_AIC7880 & ID_DEV_VENDOR_MASK),
  109. ID16(ID_AIC7890 & ID_9005_GENERIC_MASK),
  110. ID16(ID_AIC7892 & ID_9005_GENERIC_MASK),
  111. ID(ID_AIC7895 & ID_DEV_VENDOR_MASK),
  112. ID16(ID_AIC7896 & ID_9005_GENERIC_MASK),
  113. ID16(ID_AIC7899 & ID_9005_GENERIC_MASK),
  114. ID(ID_AIC7810 & ID_DEV_VENDOR_MASK),
  115. ID(ID_AIC7815 & ID_DEV_VENDOR_MASK),
  116. { 0 }
  117. };
  118. MODULE_DEVICE_TABLE(pci, ahc_linux_pci_id_table);
  119. #ifdef CONFIG_PM
  120. static int
  121. ahc_linux_pci_dev_suspend(struct pci_dev *pdev, pm_message_t mesg)
  122. {
  123. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  124. int rc;
  125. if ((rc = ahc_suspend(ahc)))
  126. return rc;
  127. pci_save_state(pdev);
  128. pci_disable_device(pdev);
  129. if (mesg.event & PM_EVENT_SLEEP)
  130. pci_set_power_state(pdev, PCI_D3hot);
  131. return rc;
  132. }
  133. static int
  134. ahc_linux_pci_dev_resume(struct pci_dev *pdev)
  135. {
  136. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  137. int rc;
  138. pci_set_power_state(pdev, PCI_D0);
  139. pci_restore_state(pdev);
  140. if ((rc = pci_enable_device(pdev))) {
  141. dev_printk(KERN_ERR, &pdev->dev,
  142. "failed to enable device after resume (%d)\n", rc);
  143. return rc;
  144. }
  145. pci_set_master(pdev);
  146. ahc_pci_resume(ahc);
  147. return (ahc_resume(ahc));
  148. }
  149. #endif
  150. static void
  151. ahc_linux_pci_dev_remove(struct pci_dev *pdev)
  152. {
  153. struct ahc_softc *ahc = pci_get_drvdata(pdev);
  154. u_long s;
  155. if (ahc->platform_data && ahc->platform_data->host)
  156. scsi_remove_host(ahc->platform_data->host);
  157. ahc_lock(ahc, &s);
  158. ahc_intr_enable(ahc, FALSE);
  159. ahc_unlock(ahc, &s);
  160. ahc_free(ahc);
  161. }
  162. static void
  163. ahc_linux_pci_inherit_flags(struct ahc_softc *ahc)
  164. {
  165. struct pci_dev *pdev = ahc->dev_softc, *master_pdev;
  166. unsigned int master_devfn = PCI_DEVFN(PCI_SLOT(pdev->devfn), 0);
  167. master_pdev = pci_get_slot(pdev->bus, master_devfn);
  168. if (master_pdev) {
  169. struct ahc_softc *master = pci_get_drvdata(master_pdev);
  170. if (master) {
  171. ahc->flags &= ~AHC_BIOS_ENABLED;
  172. ahc->flags |= master->flags & AHC_BIOS_ENABLED;
  173. ahc->flags &= ~AHC_PRIMARY_CHANNEL;
  174. ahc->flags |= master->flags & AHC_PRIMARY_CHANNEL;
  175. } else
  176. printk(KERN_ERR "aic7xxx: no multichannel peer found!\n");
  177. pci_dev_put(master_pdev);
  178. }
  179. }
  180. static int
  181. ahc_linux_pci_dev_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  182. {
  183. char buf[80];
  184. const uint64_t mask_39bit = 0x7FFFFFFFFFULL;
  185. struct ahc_softc *ahc;
  186. ahc_dev_softc_t pci;
  187. const struct ahc_pci_identity *entry;
  188. char *name;
  189. int error;
  190. struct device *dev = &pdev->dev;
  191. pci = pdev;
  192. entry = ahc_find_pci_device(pci);
  193. if (entry == NULL)
  194. return (-ENODEV);
  195. /*
  196. * Allocate a softc for this card and
  197. * set it up for attachment by our
  198. * common detect routine.
  199. */
  200. sprintf(buf, "ahc_pci:%d:%d:%d",
  201. ahc_get_pci_bus(pci),
  202. ahc_get_pci_slot(pci),
  203. ahc_get_pci_function(pci));
  204. name = kstrdup(buf, GFP_ATOMIC);
  205. if (name == NULL)
  206. return (-ENOMEM);
  207. ahc = ahc_alloc(NULL, name);
  208. if (ahc == NULL)
  209. return (-ENOMEM);
  210. if (pci_enable_device(pdev)) {
  211. ahc_free(ahc);
  212. return (-ENODEV);
  213. }
  214. pci_set_master(pdev);
  215. if (sizeof(dma_addr_t) > 4
  216. && ahc->features & AHC_LARGE_SCBS
  217. && dma_set_mask(dev, mask_39bit) == 0
  218. && dma_get_required_mask(dev) > DMA_BIT_MASK(32)) {
  219. ahc->flags |= AHC_39BIT_ADDRESSING;
  220. } else {
  221. if (dma_set_mask(dev, DMA_BIT_MASK(32))) {
  222. ahc_free(ahc);
  223. printk(KERN_WARNING "aic7xxx: No suitable DMA available.\n");
  224. return (-ENODEV);
  225. }
  226. }
  227. ahc->dev_softc = pci;
  228. error = ahc_pci_config(ahc, entry);
  229. if (error != 0) {
  230. ahc_free(ahc);
  231. return (-error);
  232. }
  233. /*
  234. * Second Function PCI devices need to inherit some
  235. * settings from function 0.
  236. */
  237. if ((ahc->features & AHC_MULTI_FUNC) && PCI_FUNC(pdev->devfn) != 0)
  238. ahc_linux_pci_inherit_flags(ahc);
  239. pci_set_drvdata(pdev, ahc);
  240. ahc_linux_register_host(ahc, &aic7xxx_driver_template);
  241. return (0);
  242. }
  243. /******************************* PCI Routines *********************************/
  244. uint32_t
  245. ahc_pci_read_config(ahc_dev_softc_t pci, int reg, int width)
  246. {
  247. switch (width) {
  248. case 1:
  249. {
  250. uint8_t retval;
  251. pci_read_config_byte(pci, reg, &retval);
  252. return (retval);
  253. }
  254. case 2:
  255. {
  256. uint16_t retval;
  257. pci_read_config_word(pci, reg, &retval);
  258. return (retval);
  259. }
  260. case 4:
  261. {
  262. uint32_t retval;
  263. pci_read_config_dword(pci, reg, &retval);
  264. return (retval);
  265. }
  266. default:
  267. panic("ahc_pci_read_config: Read size too big");
  268. /* NOTREACHED */
  269. return (0);
  270. }
  271. }
  272. void
  273. ahc_pci_write_config(ahc_dev_softc_t pci, int reg, uint32_t value, int width)
  274. {
  275. switch (width) {
  276. case 1:
  277. pci_write_config_byte(pci, reg, value);
  278. break;
  279. case 2:
  280. pci_write_config_word(pci, reg, value);
  281. break;
  282. case 4:
  283. pci_write_config_dword(pci, reg, value);
  284. break;
  285. default:
  286. panic("ahc_pci_write_config: Write size too big");
  287. /* NOTREACHED */
  288. }
  289. }
  290. static struct pci_driver aic7xxx_pci_driver = {
  291. .name = "aic7xxx",
  292. .probe = ahc_linux_pci_dev_probe,
  293. #ifdef CONFIG_PM
  294. .suspend = ahc_linux_pci_dev_suspend,
  295. .resume = ahc_linux_pci_dev_resume,
  296. #endif
  297. .remove = ahc_linux_pci_dev_remove,
  298. .id_table = ahc_linux_pci_id_table
  299. };
  300. int
  301. ahc_linux_pci_init(void)
  302. {
  303. return pci_register_driver(&aic7xxx_pci_driver);
  304. }
  305. void
  306. ahc_linux_pci_exit(void)
  307. {
  308. pci_unregister_driver(&aic7xxx_pci_driver);
  309. }
  310. static int
  311. ahc_linux_pci_reserve_io_region(struct ahc_softc *ahc, resource_size_t *base)
  312. {
  313. if (aic7xxx_allow_memio == 0)
  314. return (ENOMEM);
  315. *base = pci_resource_start(ahc->dev_softc, 0);
  316. if (*base == 0)
  317. return (ENOMEM);
  318. if (!request_region(*base, 256, "aic7xxx"))
  319. return (ENOMEM);
  320. return (0);
  321. }
  322. static int
  323. ahc_linux_pci_reserve_mem_region(struct ahc_softc *ahc,
  324. resource_size_t *bus_addr,
  325. uint8_t __iomem **maddr)
  326. {
  327. resource_size_t start;
  328. int error;
  329. error = 0;
  330. start = pci_resource_start(ahc->dev_softc, 1);
  331. if (start != 0) {
  332. *bus_addr = start;
  333. if (!request_mem_region(start, 0x1000, "aic7xxx"))
  334. error = ENOMEM;
  335. if (error == 0) {
  336. *maddr = ioremap_nocache(start, 256);
  337. if (*maddr == NULL) {
  338. error = ENOMEM;
  339. release_mem_region(start, 0x1000);
  340. }
  341. }
  342. } else
  343. error = ENOMEM;
  344. return (error);
  345. }
  346. int
  347. ahc_pci_map_registers(struct ahc_softc *ahc)
  348. {
  349. uint32_t command;
  350. resource_size_t base;
  351. uint8_t __iomem *maddr;
  352. int error;
  353. /*
  354. * If its allowed, we prefer memory mapped access.
  355. */
  356. command = ahc_pci_read_config(ahc->dev_softc, PCIR_COMMAND, 4);
  357. command &= ~(PCIM_CMD_PORTEN|PCIM_CMD_MEMEN);
  358. base = 0;
  359. maddr = NULL;
  360. error = ahc_linux_pci_reserve_mem_region(ahc, &base, &maddr);
  361. if (error == 0) {
  362. ahc->platform_data->mem_busaddr = base;
  363. ahc->tag = BUS_SPACE_MEMIO;
  364. ahc->bsh.maddr = maddr;
  365. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND,
  366. command | PCIM_CMD_MEMEN, 4);
  367. /*
  368. * Do a quick test to see if memory mapped
  369. * I/O is functioning correctly.
  370. */
  371. if (ahc_pci_test_register_access(ahc) != 0) {
  372. printk("aic7xxx: PCI Device %d:%d:%d "
  373. "failed memory mapped test. Using PIO.\n",
  374. ahc_get_pci_bus(ahc->dev_softc),
  375. ahc_get_pci_slot(ahc->dev_softc),
  376. ahc_get_pci_function(ahc->dev_softc));
  377. iounmap(maddr);
  378. release_mem_region(ahc->platform_data->mem_busaddr,
  379. 0x1000);
  380. ahc->bsh.maddr = NULL;
  381. maddr = NULL;
  382. } else
  383. command |= PCIM_CMD_MEMEN;
  384. } else {
  385. printk("aic7xxx: PCI%d:%d:%d MEM region 0x%llx "
  386. "unavailable. Cannot memory map device.\n",
  387. ahc_get_pci_bus(ahc->dev_softc),
  388. ahc_get_pci_slot(ahc->dev_softc),
  389. ahc_get_pci_function(ahc->dev_softc),
  390. (unsigned long long)base);
  391. }
  392. /*
  393. * We always prefer memory mapped access.
  394. */
  395. if (maddr == NULL) {
  396. error = ahc_linux_pci_reserve_io_region(ahc, &base);
  397. if (error == 0) {
  398. ahc->tag = BUS_SPACE_PIO;
  399. ahc->bsh.ioport = (u_long)base;
  400. command |= PCIM_CMD_PORTEN;
  401. } else {
  402. printk("aic7xxx: PCI%d:%d:%d IO region 0x%llx[0..255] "
  403. "unavailable. Cannot map device.\n",
  404. ahc_get_pci_bus(ahc->dev_softc),
  405. ahc_get_pci_slot(ahc->dev_softc),
  406. ahc_get_pci_function(ahc->dev_softc),
  407. (unsigned long long)base);
  408. }
  409. }
  410. ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, command, 4);
  411. return (error);
  412. }
  413. int
  414. ahc_pci_map_int(struct ahc_softc *ahc)
  415. {
  416. int error;
  417. error = request_irq(ahc->dev_softc->irq, ahc_linux_isr,
  418. IRQF_SHARED, "aic7xxx", ahc);
  419. if (error == 0)
  420. ahc->platform_data->irq = ahc->dev_softc->irq;
  421. return (-error);
  422. }