esas2r_init.c 46 KB

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  1. /*
  2. * linux/drivers/scsi/esas2r/esas2r_init.c
  3. * For use with ATTO ExpressSAS R6xx SAS/SATA RAID controllers
  4. *
  5. * Copyright (c) 2001-2013 ATTO Technology, Inc.
  6. * (mailto:linuxdrivers@attotech.com)mpt3sas/mpt3sas_trigger_diag.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version 2
  11. * of the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * NO WARRANTY
  19. * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  20. * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  21. * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  22. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  23. * solely responsible for determining the appropriateness of using and
  24. * distributing the Program and assumes all risks associated with its
  25. * exercise of rights under this Agreement, including but not limited to
  26. * the risks and costs of program errors, damage to or loss of data,
  27. * programs or equipment, and unavailability or interruption of operations.
  28. *
  29. * DISCLAIMER OF LIABILITY
  30. * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  31. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32. * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  33. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  34. * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  35. * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  36. * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  37. *
  38. * You should have received a copy of the GNU General Public License
  39. * along with this program; if not, write to the Free Software
  40. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
  41. * USA.
  42. */
  43. #include "esas2r.h"
  44. static bool esas2r_initmem_alloc(struct esas2r_adapter *a,
  45. struct esas2r_mem_desc *mem_desc,
  46. u32 align)
  47. {
  48. mem_desc->esas2r_param = mem_desc->size + align;
  49. mem_desc->virt_addr = NULL;
  50. mem_desc->phys_addr = 0;
  51. mem_desc->esas2r_data = dma_alloc_coherent(&a->pcid->dev,
  52. (size_t)mem_desc->
  53. esas2r_param,
  54. (dma_addr_t *)&mem_desc->
  55. phys_addr,
  56. GFP_KERNEL);
  57. if (mem_desc->esas2r_data == NULL) {
  58. esas2r_log(ESAS2R_LOG_CRIT,
  59. "failed to allocate %lu bytes of consistent memory!",
  60. (long
  61. unsigned
  62. int)mem_desc->esas2r_param);
  63. return false;
  64. }
  65. mem_desc->virt_addr = PTR_ALIGN(mem_desc->esas2r_data, align);
  66. mem_desc->phys_addr = ALIGN(mem_desc->phys_addr, align);
  67. memset(mem_desc->virt_addr, 0, mem_desc->size);
  68. return true;
  69. }
  70. static void esas2r_initmem_free(struct esas2r_adapter *a,
  71. struct esas2r_mem_desc *mem_desc)
  72. {
  73. if (mem_desc->virt_addr == NULL)
  74. return;
  75. /*
  76. * Careful! phys_addr and virt_addr may have been adjusted from the
  77. * original allocation in order to return the desired alignment. That
  78. * means we have to use the original address (in esas2r_data) and size
  79. * (esas2r_param) and calculate the original physical address based on
  80. * the difference between the requested and actual allocation size.
  81. */
  82. if (mem_desc->phys_addr) {
  83. int unalign = ((u8 *)mem_desc->virt_addr) -
  84. ((u8 *)mem_desc->esas2r_data);
  85. dma_free_coherent(&a->pcid->dev,
  86. (size_t)mem_desc->esas2r_param,
  87. mem_desc->esas2r_data,
  88. (dma_addr_t)(mem_desc->phys_addr - unalign));
  89. } else {
  90. kfree(mem_desc->esas2r_data);
  91. }
  92. mem_desc->virt_addr = NULL;
  93. }
  94. static bool alloc_vda_req(struct esas2r_adapter *a,
  95. struct esas2r_request *rq)
  96. {
  97. struct esas2r_mem_desc *memdesc = kzalloc(
  98. sizeof(struct esas2r_mem_desc), GFP_KERNEL);
  99. if (memdesc == NULL) {
  100. esas2r_hdebug("could not alloc mem for vda request memdesc\n");
  101. return false;
  102. }
  103. memdesc->size = sizeof(union atto_vda_req) +
  104. ESAS2R_DATA_BUF_LEN;
  105. if (!esas2r_initmem_alloc(a, memdesc, 256)) {
  106. esas2r_hdebug("could not alloc mem for vda request\n");
  107. kfree(memdesc);
  108. return false;
  109. }
  110. a->num_vrqs++;
  111. list_add(&memdesc->next_desc, &a->vrq_mds_head);
  112. rq->vrq_md = memdesc;
  113. rq->vrq = (union atto_vda_req *)memdesc->virt_addr;
  114. rq->vrq->scsi.handle = a->num_vrqs;
  115. return true;
  116. }
  117. static void esas2r_unmap_regions(struct esas2r_adapter *a)
  118. {
  119. if (a->regs)
  120. iounmap((void __iomem *)a->regs);
  121. a->regs = NULL;
  122. pci_release_region(a->pcid, 2);
  123. if (a->data_window)
  124. iounmap((void __iomem *)a->data_window);
  125. a->data_window = NULL;
  126. pci_release_region(a->pcid, 0);
  127. }
  128. static int esas2r_map_regions(struct esas2r_adapter *a)
  129. {
  130. int error;
  131. a->regs = NULL;
  132. a->data_window = NULL;
  133. error = pci_request_region(a->pcid, 2, a->name);
  134. if (error != 0) {
  135. esas2r_log(ESAS2R_LOG_CRIT,
  136. "pci_request_region(2) failed, error %d",
  137. error);
  138. return error;
  139. }
  140. a->regs = (void __force *)ioremap(pci_resource_start(a->pcid, 2),
  141. pci_resource_len(a->pcid, 2));
  142. if (a->regs == NULL) {
  143. esas2r_log(ESAS2R_LOG_CRIT,
  144. "ioremap failed for regs mem region\n");
  145. pci_release_region(a->pcid, 2);
  146. return -EFAULT;
  147. }
  148. error = pci_request_region(a->pcid, 0, a->name);
  149. if (error != 0) {
  150. esas2r_log(ESAS2R_LOG_CRIT,
  151. "pci_request_region(2) failed, error %d",
  152. error);
  153. esas2r_unmap_regions(a);
  154. return error;
  155. }
  156. a->data_window = (void __force *)ioremap(pci_resource_start(a->pcid,
  157. 0),
  158. pci_resource_len(a->pcid, 0));
  159. if (a->data_window == NULL) {
  160. esas2r_log(ESAS2R_LOG_CRIT,
  161. "ioremap failed for data_window mem region\n");
  162. esas2r_unmap_regions(a);
  163. return -EFAULT;
  164. }
  165. return 0;
  166. }
  167. static void esas2r_setup_interrupts(struct esas2r_adapter *a, int intr_mode)
  168. {
  169. int i;
  170. /* Set up interrupt mode based on the requested value */
  171. switch (intr_mode) {
  172. case INTR_MODE_LEGACY:
  173. use_legacy_interrupts:
  174. a->intr_mode = INTR_MODE_LEGACY;
  175. break;
  176. case INTR_MODE_MSI:
  177. i = pci_enable_msi(a->pcid);
  178. if (i != 0) {
  179. esas2r_log(ESAS2R_LOG_WARN,
  180. "failed to enable MSI for adapter %d, "
  181. "falling back to legacy interrupts "
  182. "(err=%d)", a->index,
  183. i);
  184. goto use_legacy_interrupts;
  185. }
  186. a->intr_mode = INTR_MODE_MSI;
  187. set_bit(AF2_MSI_ENABLED, &a->flags2);
  188. break;
  189. default:
  190. esas2r_log(ESAS2R_LOG_WARN,
  191. "unknown interrupt_mode %d requested, "
  192. "falling back to legacy interrupt",
  193. interrupt_mode);
  194. goto use_legacy_interrupts;
  195. }
  196. }
  197. static void esas2r_claim_interrupts(struct esas2r_adapter *a)
  198. {
  199. unsigned long flags = 0;
  200. if (a->intr_mode == INTR_MODE_LEGACY)
  201. flags |= IRQF_SHARED;
  202. esas2r_log(ESAS2R_LOG_INFO,
  203. "esas2r_claim_interrupts irq=%d (%p, %s, %x)",
  204. a->pcid->irq, a, a->name, flags);
  205. if (request_irq(a->pcid->irq,
  206. (a->intr_mode ==
  207. INTR_MODE_LEGACY) ? esas2r_interrupt :
  208. esas2r_msi_interrupt,
  209. flags,
  210. a->name,
  211. a)) {
  212. esas2r_log(ESAS2R_LOG_CRIT, "unable to request IRQ %02X",
  213. a->pcid->irq);
  214. return;
  215. }
  216. set_bit(AF2_IRQ_CLAIMED, &a->flags2);
  217. esas2r_log(ESAS2R_LOG_INFO,
  218. "claimed IRQ %d flags: 0x%lx",
  219. a->pcid->irq, flags);
  220. }
  221. int esas2r_init_adapter(struct Scsi_Host *host, struct pci_dev *pcid,
  222. int index)
  223. {
  224. struct esas2r_adapter *a;
  225. u64 bus_addr = 0;
  226. int i;
  227. void *next_uncached;
  228. struct esas2r_request *first_request, *last_request;
  229. if (index >= MAX_ADAPTERS) {
  230. esas2r_log(ESAS2R_LOG_CRIT,
  231. "tried to init invalid adapter index %u!",
  232. index);
  233. return 0;
  234. }
  235. if (esas2r_adapters[index]) {
  236. esas2r_log(ESAS2R_LOG_CRIT,
  237. "tried to init existing adapter index %u!",
  238. index);
  239. return 0;
  240. }
  241. a = (struct esas2r_adapter *)host->hostdata;
  242. memset(a, 0, sizeof(struct esas2r_adapter));
  243. a->pcid = pcid;
  244. a->host = host;
  245. if (sizeof(dma_addr_t) > 4) {
  246. const uint64_t required_mask = dma_get_required_mask
  247. (&pcid->dev);
  248. if (required_mask > DMA_BIT_MASK(32)
  249. && !pci_set_dma_mask(pcid, DMA_BIT_MASK(64))
  250. && !pci_set_consistent_dma_mask(pcid,
  251. DMA_BIT_MASK(64))) {
  252. esas2r_log_dev(ESAS2R_LOG_INFO,
  253. &(a->pcid->dev),
  254. "64-bit PCI addressing enabled\n");
  255. } else if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
  256. && !pci_set_consistent_dma_mask(pcid,
  257. DMA_BIT_MASK(32))) {
  258. esas2r_log_dev(ESAS2R_LOG_INFO,
  259. &(a->pcid->dev),
  260. "32-bit PCI addressing enabled\n");
  261. } else {
  262. esas2r_log(ESAS2R_LOG_CRIT,
  263. "failed to set DMA mask");
  264. esas2r_kill_adapter(index);
  265. return 0;
  266. }
  267. } else {
  268. if (!pci_set_dma_mask(pcid, DMA_BIT_MASK(32))
  269. && !pci_set_consistent_dma_mask(pcid,
  270. DMA_BIT_MASK(32))) {
  271. esas2r_log_dev(ESAS2R_LOG_INFO,
  272. &(a->pcid->dev),
  273. "32-bit PCI addressing enabled\n");
  274. } else {
  275. esas2r_log(ESAS2R_LOG_CRIT,
  276. "failed to set DMA mask");
  277. esas2r_kill_adapter(index);
  278. return 0;
  279. }
  280. }
  281. esas2r_adapters[index] = a;
  282. sprintf(a->name, ESAS2R_DRVR_NAME "_%02d", index);
  283. esas2r_debug("new adapter %p, name %s", a, a->name);
  284. spin_lock_init(&a->request_lock);
  285. spin_lock_init(&a->fw_event_lock);
  286. sema_init(&a->fm_api_semaphore, 1);
  287. sema_init(&a->fs_api_semaphore, 1);
  288. sema_init(&a->nvram_semaphore, 1);
  289. esas2r_fw_event_off(a);
  290. snprintf(a->fw_event_q_name, ESAS2R_KOBJ_NAME_LEN, "esas2r/%d",
  291. a->index);
  292. a->fw_event_q = create_singlethread_workqueue(a->fw_event_q_name);
  293. init_waitqueue_head(&a->buffered_ioctl_waiter);
  294. init_waitqueue_head(&a->nvram_waiter);
  295. init_waitqueue_head(&a->fm_api_waiter);
  296. init_waitqueue_head(&a->fs_api_waiter);
  297. init_waitqueue_head(&a->vda_waiter);
  298. INIT_LIST_HEAD(&a->general_req.req_list);
  299. INIT_LIST_HEAD(&a->active_list);
  300. INIT_LIST_HEAD(&a->defer_list);
  301. INIT_LIST_HEAD(&a->free_sg_list_head);
  302. INIT_LIST_HEAD(&a->avail_request);
  303. INIT_LIST_HEAD(&a->vrq_mds_head);
  304. INIT_LIST_HEAD(&a->fw_event_list);
  305. first_request = (struct esas2r_request *)((u8 *)(a + 1));
  306. for (last_request = first_request, i = 1; i < num_requests;
  307. last_request++, i++) {
  308. INIT_LIST_HEAD(&last_request->req_list);
  309. list_add_tail(&last_request->comp_list, &a->avail_request);
  310. if (!alloc_vda_req(a, last_request)) {
  311. esas2r_log(ESAS2R_LOG_CRIT,
  312. "failed to allocate a VDA request!");
  313. esas2r_kill_adapter(index);
  314. return 0;
  315. }
  316. }
  317. esas2r_debug("requests: %p to %p (%d, %d)", first_request,
  318. last_request,
  319. sizeof(*first_request),
  320. num_requests);
  321. if (esas2r_map_regions(a) != 0) {
  322. esas2r_log(ESAS2R_LOG_CRIT, "could not map PCI regions!");
  323. esas2r_kill_adapter(index);
  324. return 0;
  325. }
  326. a->index = index;
  327. /* interrupts will be disabled until we are done with init */
  328. atomic_inc(&a->dis_ints_cnt);
  329. atomic_inc(&a->disable_cnt);
  330. set_bit(AF_CHPRST_PENDING, &a->flags);
  331. set_bit(AF_DISC_PENDING, &a->flags);
  332. set_bit(AF_FIRST_INIT, &a->flags);
  333. set_bit(AF_LEGACY_SGE_MODE, &a->flags);
  334. a->init_msg = ESAS2R_INIT_MSG_START;
  335. a->max_vdareq_size = 128;
  336. a->build_sgl = esas2r_build_sg_list_sge;
  337. esas2r_setup_interrupts(a, interrupt_mode);
  338. a->uncached_size = esas2r_get_uncached_size(a);
  339. a->uncached = dma_alloc_coherent(&pcid->dev,
  340. (size_t)a->uncached_size,
  341. (dma_addr_t *)&bus_addr,
  342. GFP_KERNEL);
  343. if (a->uncached == NULL) {
  344. esas2r_log(ESAS2R_LOG_CRIT,
  345. "failed to allocate %d bytes of consistent memory!",
  346. a->uncached_size);
  347. esas2r_kill_adapter(index);
  348. return 0;
  349. }
  350. a->uncached_phys = bus_addr;
  351. esas2r_debug("%d bytes uncached memory allocated @ %p (%x:%x)",
  352. a->uncached_size,
  353. a->uncached,
  354. upper_32_bits(bus_addr),
  355. lower_32_bits(bus_addr));
  356. memset(a->uncached, 0, a->uncached_size);
  357. next_uncached = a->uncached;
  358. if (!esas2r_init_adapter_struct(a,
  359. &next_uncached)) {
  360. esas2r_log(ESAS2R_LOG_CRIT,
  361. "failed to initialize adapter structure (2)!");
  362. esas2r_kill_adapter(index);
  363. return 0;
  364. }
  365. tasklet_init(&a->tasklet,
  366. esas2r_adapter_tasklet,
  367. (unsigned long)a);
  368. /*
  369. * Disable chip interrupts to prevent spurious interrupts
  370. * until we claim the IRQ.
  371. */
  372. esas2r_disable_chip_interrupts(a);
  373. esas2r_check_adapter(a);
  374. if (!esas2r_init_adapter_hw(a, true))
  375. esas2r_log(ESAS2R_LOG_CRIT, "failed to initialize hardware!");
  376. else
  377. esas2r_debug("esas2r_init_adapter ok");
  378. esas2r_claim_interrupts(a);
  379. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2))
  380. esas2r_enable_chip_interrupts(a);
  381. set_bit(AF2_INIT_DONE, &a->flags2);
  382. if (!test_bit(AF_DEGRADED_MODE, &a->flags))
  383. esas2r_kickoff_timer(a);
  384. esas2r_debug("esas2r_init_adapter done for %p (%d)",
  385. a, a->disable_cnt);
  386. return 1;
  387. }
  388. static void esas2r_adapter_power_down(struct esas2r_adapter *a,
  389. int power_management)
  390. {
  391. struct esas2r_mem_desc *memdesc, *next;
  392. if ((test_bit(AF2_INIT_DONE, &a->flags2))
  393. && (!test_bit(AF_DEGRADED_MODE, &a->flags))) {
  394. if (!power_management) {
  395. del_timer_sync(&a->timer);
  396. tasklet_kill(&a->tasklet);
  397. }
  398. esas2r_power_down(a);
  399. /*
  400. * There are versions of firmware that do not handle the sync
  401. * cache command correctly. Stall here to ensure that the
  402. * cache is lazily flushed.
  403. */
  404. mdelay(500);
  405. esas2r_debug("chip halted");
  406. }
  407. /* Remove sysfs binary files */
  408. if (a->sysfs_fw_created) {
  409. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fw);
  410. a->sysfs_fw_created = 0;
  411. }
  412. if (a->sysfs_fs_created) {
  413. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_fs);
  414. a->sysfs_fs_created = 0;
  415. }
  416. if (a->sysfs_vda_created) {
  417. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_vda);
  418. a->sysfs_vda_created = 0;
  419. }
  420. if (a->sysfs_hw_created) {
  421. sysfs_remove_bin_file(&a->host->shost_dev.kobj, &bin_attr_hw);
  422. a->sysfs_hw_created = 0;
  423. }
  424. if (a->sysfs_live_nvram_created) {
  425. sysfs_remove_bin_file(&a->host->shost_dev.kobj,
  426. &bin_attr_live_nvram);
  427. a->sysfs_live_nvram_created = 0;
  428. }
  429. if (a->sysfs_default_nvram_created) {
  430. sysfs_remove_bin_file(&a->host->shost_dev.kobj,
  431. &bin_attr_default_nvram);
  432. a->sysfs_default_nvram_created = 0;
  433. }
  434. /* Clean up interrupts */
  435. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
  436. esas2r_log_dev(ESAS2R_LOG_INFO,
  437. &(a->pcid->dev),
  438. "free_irq(%d) called", a->pcid->irq);
  439. free_irq(a->pcid->irq, a);
  440. esas2r_debug("IRQ released");
  441. clear_bit(AF2_IRQ_CLAIMED, &a->flags2);
  442. }
  443. if (test_bit(AF2_MSI_ENABLED, &a->flags2)) {
  444. pci_disable_msi(a->pcid);
  445. clear_bit(AF2_MSI_ENABLED, &a->flags2);
  446. esas2r_debug("MSI disabled");
  447. }
  448. if (a->inbound_list_md.virt_addr)
  449. esas2r_initmem_free(a, &a->inbound_list_md);
  450. if (a->outbound_list_md.virt_addr)
  451. esas2r_initmem_free(a, &a->outbound_list_md);
  452. list_for_each_entry_safe(memdesc, next, &a->free_sg_list_head,
  453. next_desc) {
  454. esas2r_initmem_free(a, memdesc);
  455. }
  456. /* Following frees everything allocated via alloc_vda_req */
  457. list_for_each_entry_safe(memdesc, next, &a->vrq_mds_head, next_desc) {
  458. esas2r_initmem_free(a, memdesc);
  459. list_del(&memdesc->next_desc);
  460. kfree(memdesc);
  461. }
  462. kfree(a->first_ae_req);
  463. a->first_ae_req = NULL;
  464. kfree(a->sg_list_mds);
  465. a->sg_list_mds = NULL;
  466. kfree(a->req_table);
  467. a->req_table = NULL;
  468. if (a->regs) {
  469. esas2r_unmap_regions(a);
  470. a->regs = NULL;
  471. a->data_window = NULL;
  472. esas2r_debug("regions unmapped");
  473. }
  474. }
  475. /* Release/free allocated resources for specified adapters. */
  476. void esas2r_kill_adapter(int i)
  477. {
  478. struct esas2r_adapter *a = esas2r_adapters[i];
  479. if (a) {
  480. unsigned long flags;
  481. struct workqueue_struct *wq;
  482. esas2r_debug("killing adapter %p [%d] ", a, i);
  483. esas2r_fw_event_off(a);
  484. esas2r_adapter_power_down(a, 0);
  485. if (esas2r_buffered_ioctl &&
  486. (a->pcid == esas2r_buffered_ioctl_pcid)) {
  487. dma_free_coherent(&a->pcid->dev,
  488. (size_t)esas2r_buffered_ioctl_size,
  489. esas2r_buffered_ioctl,
  490. esas2r_buffered_ioctl_addr);
  491. esas2r_buffered_ioctl = NULL;
  492. }
  493. if (a->vda_buffer) {
  494. dma_free_coherent(&a->pcid->dev,
  495. (size_t)VDA_MAX_BUFFER_SIZE,
  496. a->vda_buffer,
  497. (dma_addr_t)a->ppvda_buffer);
  498. a->vda_buffer = NULL;
  499. }
  500. if (a->fs_api_buffer) {
  501. dma_free_coherent(&a->pcid->dev,
  502. (size_t)a->fs_api_buffer_size,
  503. a->fs_api_buffer,
  504. (dma_addr_t)a->ppfs_api_buffer);
  505. a->fs_api_buffer = NULL;
  506. }
  507. kfree(a->local_atto_ioctl);
  508. a->local_atto_ioctl = NULL;
  509. spin_lock_irqsave(&a->fw_event_lock, flags);
  510. wq = a->fw_event_q;
  511. a->fw_event_q = NULL;
  512. spin_unlock_irqrestore(&a->fw_event_lock, flags);
  513. if (wq)
  514. destroy_workqueue(wq);
  515. if (a->uncached) {
  516. dma_free_coherent(&a->pcid->dev,
  517. (size_t)a->uncached_size,
  518. a->uncached,
  519. (dma_addr_t)a->uncached_phys);
  520. a->uncached = NULL;
  521. esas2r_debug("uncached area freed");
  522. }
  523. esas2r_log_dev(ESAS2R_LOG_INFO,
  524. &(a->pcid->dev),
  525. "pci_disable_device() called. msix_enabled: %d "
  526. "msi_enabled: %d irq: %d pin: %d",
  527. a->pcid->msix_enabled,
  528. a->pcid->msi_enabled,
  529. a->pcid->irq,
  530. a->pcid->pin);
  531. esas2r_log_dev(ESAS2R_LOG_INFO,
  532. &(a->pcid->dev),
  533. "before pci_disable_device() enable_cnt: %d",
  534. a->pcid->enable_cnt.counter);
  535. pci_disable_device(a->pcid);
  536. esas2r_log_dev(ESAS2R_LOG_INFO,
  537. &(a->pcid->dev),
  538. "after pci_disable_device() enable_cnt: %d",
  539. a->pcid->enable_cnt.counter);
  540. esas2r_log_dev(ESAS2R_LOG_INFO,
  541. &(a->pcid->dev),
  542. "pci_set_drv_data(%p, NULL) called",
  543. a->pcid);
  544. pci_set_drvdata(a->pcid, NULL);
  545. esas2r_adapters[i] = NULL;
  546. if (test_bit(AF2_INIT_DONE, &a->flags2)) {
  547. clear_bit(AF2_INIT_DONE, &a->flags2);
  548. set_bit(AF_DEGRADED_MODE, &a->flags);
  549. esas2r_log_dev(ESAS2R_LOG_INFO,
  550. &(a->host->shost_gendev),
  551. "scsi_remove_host() called");
  552. scsi_remove_host(a->host);
  553. esas2r_log_dev(ESAS2R_LOG_INFO,
  554. &(a->host->shost_gendev),
  555. "scsi_host_put() called");
  556. scsi_host_put(a->host);
  557. }
  558. }
  559. }
  560. int esas2r_cleanup(struct Scsi_Host *host)
  561. {
  562. struct esas2r_adapter *a;
  563. int index;
  564. if (host == NULL) {
  565. int i;
  566. esas2r_debug("esas2r_cleanup everything");
  567. for (i = 0; i < MAX_ADAPTERS; i++)
  568. esas2r_kill_adapter(i);
  569. return -1;
  570. }
  571. esas2r_debug("esas2r_cleanup called for host %p", host);
  572. a = (struct esas2r_adapter *)host->hostdata;
  573. index = a->index;
  574. esas2r_kill_adapter(index);
  575. return index;
  576. }
  577. int esas2r_suspend(struct pci_dev *pdev, pm_message_t state)
  578. {
  579. struct Scsi_Host *host = pci_get_drvdata(pdev);
  580. u32 device_state;
  581. struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
  582. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "suspending adapter()");
  583. if (!a)
  584. return -ENODEV;
  585. esas2r_adapter_power_down(a, 1);
  586. device_state = pci_choose_state(pdev, state);
  587. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  588. "pci_save_state() called");
  589. pci_save_state(pdev);
  590. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  591. "pci_disable_device() called");
  592. pci_disable_device(pdev);
  593. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  594. "pci_set_power_state() called");
  595. pci_set_power_state(pdev, device_state);
  596. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "esas2r_suspend(): 0");
  597. return 0;
  598. }
  599. int esas2r_resume(struct pci_dev *pdev)
  600. {
  601. struct Scsi_Host *host = pci_get_drvdata(pdev);
  602. struct esas2r_adapter *a = (struct esas2r_adapter *)host->hostdata;
  603. int rez;
  604. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev), "resuming adapter()");
  605. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  606. "pci_set_power_state(PCI_D0) "
  607. "called");
  608. pci_set_power_state(pdev, PCI_D0);
  609. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  610. "pci_enable_wake(PCI_D0, 0) "
  611. "called");
  612. pci_enable_wake(pdev, PCI_D0, 0);
  613. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  614. "pci_restore_state() called");
  615. pci_restore_state(pdev);
  616. esas2r_log_dev(ESAS2R_LOG_INFO, &(pdev->dev),
  617. "pci_enable_device() called");
  618. rez = pci_enable_device(pdev);
  619. pci_set_master(pdev);
  620. if (!a) {
  621. rez = -ENODEV;
  622. goto error_exit;
  623. }
  624. if (esas2r_map_regions(a) != 0) {
  625. esas2r_log(ESAS2R_LOG_CRIT, "could not re-map PCI regions!");
  626. rez = -ENOMEM;
  627. goto error_exit;
  628. }
  629. /* Set up interupt mode */
  630. esas2r_setup_interrupts(a, a->intr_mode);
  631. /*
  632. * Disable chip interrupts to prevent spurious interrupts until we
  633. * claim the IRQ.
  634. */
  635. esas2r_disable_chip_interrupts(a);
  636. if (!esas2r_power_up(a, true)) {
  637. esas2r_debug("yikes, esas2r_power_up failed");
  638. rez = -ENOMEM;
  639. goto error_exit;
  640. }
  641. esas2r_claim_interrupts(a);
  642. if (test_bit(AF2_IRQ_CLAIMED, &a->flags2)) {
  643. /*
  644. * Now that system interrupt(s) are claimed, we can enable
  645. * chip interrupts.
  646. */
  647. esas2r_enable_chip_interrupts(a);
  648. esas2r_kickoff_timer(a);
  649. } else {
  650. esas2r_debug("yikes, unable to claim IRQ");
  651. esas2r_log(ESAS2R_LOG_CRIT, "could not re-claim IRQ!");
  652. rez = -ENOMEM;
  653. goto error_exit;
  654. }
  655. error_exit:
  656. esas2r_log_dev(ESAS2R_LOG_CRIT, &(pdev->dev), "esas2r_resume(): %d",
  657. rez);
  658. return rez;
  659. }
  660. bool esas2r_set_degraded_mode(struct esas2r_adapter *a, char *error_str)
  661. {
  662. set_bit(AF_DEGRADED_MODE, &a->flags);
  663. esas2r_log(ESAS2R_LOG_CRIT,
  664. "setting adapter to degraded mode: %s\n", error_str);
  665. return false;
  666. }
  667. u32 esas2r_get_uncached_size(struct esas2r_adapter *a)
  668. {
  669. return sizeof(struct esas2r_sas_nvram)
  670. + ALIGN(ESAS2R_DISC_BUF_LEN, 8)
  671. + ALIGN(sizeof(u32), 8) /* outbound list copy pointer */
  672. + 8
  673. + (num_sg_lists * (u16)sgl_page_size)
  674. + ALIGN((num_requests + num_ae_requests + 1 +
  675. ESAS2R_LIST_EXTRA) *
  676. sizeof(struct esas2r_inbound_list_source_entry),
  677. 8)
  678. + ALIGN((num_requests + num_ae_requests + 1 +
  679. ESAS2R_LIST_EXTRA) *
  680. sizeof(struct atto_vda_ob_rsp), 8)
  681. + 256; /* VDA request and buffer align */
  682. }
  683. static void esas2r_init_pci_cfg_space(struct esas2r_adapter *a)
  684. {
  685. int pcie_cap_reg;
  686. pcie_cap_reg = pci_find_capability(a->pcid, PCI_CAP_ID_EXP);
  687. if (pcie_cap_reg) {
  688. u16 devcontrol;
  689. pci_read_config_word(a->pcid, pcie_cap_reg + PCI_EXP_DEVCTL,
  690. &devcontrol);
  691. if ((devcontrol & PCI_EXP_DEVCTL_READRQ) >
  692. PCI_EXP_DEVCTL_READRQ_512B) {
  693. esas2r_log(ESAS2R_LOG_INFO,
  694. "max read request size > 512B");
  695. devcontrol &= ~PCI_EXP_DEVCTL_READRQ;
  696. devcontrol |= PCI_EXP_DEVCTL_READRQ_512B;
  697. pci_write_config_word(a->pcid,
  698. pcie_cap_reg + PCI_EXP_DEVCTL,
  699. devcontrol);
  700. }
  701. }
  702. }
  703. /*
  704. * Determine the organization of the uncached data area and
  705. * finish initializing the adapter structure
  706. */
  707. bool esas2r_init_adapter_struct(struct esas2r_adapter *a,
  708. void **uncached_area)
  709. {
  710. u32 i;
  711. u8 *high;
  712. struct esas2r_inbound_list_source_entry *element;
  713. struct esas2r_request *rq;
  714. struct esas2r_mem_desc *sgl;
  715. spin_lock_init(&a->sg_list_lock);
  716. spin_lock_init(&a->mem_lock);
  717. spin_lock_init(&a->queue_lock);
  718. a->targetdb_end = &a->targetdb[ESAS2R_MAX_TARGETS];
  719. if (!alloc_vda_req(a, &a->general_req)) {
  720. esas2r_hdebug(
  721. "failed to allocate a VDA request for the general req!");
  722. return false;
  723. }
  724. /* allocate requests for asynchronous events */
  725. a->first_ae_req =
  726. kzalloc(num_ae_requests * sizeof(struct esas2r_request),
  727. GFP_KERNEL);
  728. if (a->first_ae_req == NULL) {
  729. esas2r_log(ESAS2R_LOG_CRIT,
  730. "failed to allocate memory for asynchronous events");
  731. return false;
  732. }
  733. /* allocate the S/G list memory descriptors */
  734. a->sg_list_mds = kzalloc(
  735. num_sg_lists * sizeof(struct esas2r_mem_desc), GFP_KERNEL);
  736. if (a->sg_list_mds == NULL) {
  737. esas2r_log(ESAS2R_LOG_CRIT,
  738. "failed to allocate memory for s/g list descriptors");
  739. return false;
  740. }
  741. /* allocate the request table */
  742. a->req_table =
  743. kzalloc((num_requests + num_ae_requests +
  744. 1) * sizeof(struct esas2r_request *), GFP_KERNEL);
  745. if (a->req_table == NULL) {
  746. esas2r_log(ESAS2R_LOG_CRIT,
  747. "failed to allocate memory for the request table");
  748. return false;
  749. }
  750. /* initialize PCI configuration space */
  751. esas2r_init_pci_cfg_space(a);
  752. /*
  753. * the thunder_stream boards all have a serial flash part that has a
  754. * different base address on the AHB bus.
  755. */
  756. if ((a->pcid->subsystem_vendor == ATTO_VENDOR_ID)
  757. && (a->pcid->subsystem_device & ATTO_SSDID_TBT))
  758. a->flags2 |= AF2_THUNDERBOLT;
  759. if (test_bit(AF2_THUNDERBOLT, &a->flags2))
  760. a->flags2 |= AF2_SERIAL_FLASH;
  761. if (a->pcid->subsystem_device == ATTO_TLSH_1068)
  762. a->flags2 |= AF2_THUNDERLINK;
  763. /* Uncached Area */
  764. high = (u8 *)*uncached_area;
  765. /* initialize the scatter/gather table pages */
  766. for (i = 0, sgl = a->sg_list_mds; i < num_sg_lists; i++, sgl++) {
  767. sgl->size = sgl_page_size;
  768. list_add_tail(&sgl->next_desc, &a->free_sg_list_head);
  769. if (!esas2r_initmem_alloc(a, sgl, ESAS2R_SGL_ALIGN)) {
  770. /* Allow the driver to load if the minimum count met. */
  771. if (i < NUM_SGL_MIN)
  772. return false;
  773. break;
  774. }
  775. }
  776. /* compute the size of the lists */
  777. a->list_size = num_requests + ESAS2R_LIST_EXTRA;
  778. /* allocate the inbound list */
  779. a->inbound_list_md.size = a->list_size *
  780. sizeof(struct
  781. esas2r_inbound_list_source_entry);
  782. if (!esas2r_initmem_alloc(a, &a->inbound_list_md, ESAS2R_LIST_ALIGN)) {
  783. esas2r_hdebug("failed to allocate IB list");
  784. return false;
  785. }
  786. /* allocate the outbound list */
  787. a->outbound_list_md.size = a->list_size *
  788. sizeof(struct atto_vda_ob_rsp);
  789. if (!esas2r_initmem_alloc(a, &a->outbound_list_md,
  790. ESAS2R_LIST_ALIGN)) {
  791. esas2r_hdebug("failed to allocate IB list");
  792. return false;
  793. }
  794. /* allocate the NVRAM structure */
  795. a->nvram = (struct esas2r_sas_nvram *)high;
  796. high += sizeof(struct esas2r_sas_nvram);
  797. /* allocate the discovery buffer */
  798. a->disc_buffer = high;
  799. high += ESAS2R_DISC_BUF_LEN;
  800. high = PTR_ALIGN(high, 8);
  801. /* allocate the outbound list copy pointer */
  802. a->outbound_copy = (u32 volatile *)high;
  803. high += sizeof(u32);
  804. if (!test_bit(AF_NVR_VALID, &a->flags))
  805. esas2r_nvram_set_defaults(a);
  806. /* update the caller's uncached memory area pointer */
  807. *uncached_area = (void *)high;
  808. /* initialize the allocated memory */
  809. if (test_bit(AF_FIRST_INIT, &a->flags)) {
  810. memset(a->req_table, 0,
  811. (num_requests + num_ae_requests +
  812. 1) * sizeof(struct esas2r_request *));
  813. esas2r_targ_db_initialize(a);
  814. /* prime parts of the inbound list */
  815. element =
  816. (struct esas2r_inbound_list_source_entry *)a->
  817. inbound_list_md.
  818. virt_addr;
  819. for (i = 0; i < a->list_size; i++) {
  820. element->address = 0;
  821. element->reserved = 0;
  822. element->length = cpu_to_le32(HWILSE_INTERFACE_F0
  823. | (sizeof(union
  824. atto_vda_req)
  825. /
  826. sizeof(u32)));
  827. element++;
  828. }
  829. /* init the AE requests */
  830. for (rq = a->first_ae_req, i = 0; i < num_ae_requests; rq++,
  831. i++) {
  832. INIT_LIST_HEAD(&rq->req_list);
  833. if (!alloc_vda_req(a, rq)) {
  834. esas2r_hdebug(
  835. "failed to allocate a VDA request!");
  836. return false;
  837. }
  838. esas2r_rq_init_request(rq, a);
  839. /* override the completion function */
  840. rq->comp_cb = esas2r_ae_complete;
  841. }
  842. }
  843. return true;
  844. }
  845. /* This code will verify that the chip is operational. */
  846. bool esas2r_check_adapter(struct esas2r_adapter *a)
  847. {
  848. u32 starttime;
  849. u32 doorbell;
  850. u64 ppaddr;
  851. u32 dw;
  852. /*
  853. * if the chip reset detected flag is set, we can bypass a bunch of
  854. * stuff.
  855. */
  856. if (test_bit(AF_CHPRST_DETECTED, &a->flags))
  857. goto skip_chip_reset;
  858. /*
  859. * BEFORE WE DO ANYTHING, disable the chip interrupts! the boot driver
  860. * may have left them enabled or we may be recovering from a fault.
  861. */
  862. esas2r_write_register_dword(a, MU_INT_MASK_OUT, ESAS2R_INT_DIS_MASK);
  863. esas2r_flush_register_dword(a, MU_INT_MASK_OUT);
  864. /*
  865. * wait for the firmware to become ready by forcing an interrupt and
  866. * waiting for a response.
  867. */
  868. starttime = jiffies_to_msecs(jiffies);
  869. while (true) {
  870. esas2r_force_interrupt(a);
  871. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  872. if (doorbell == 0xFFFFFFFF) {
  873. /*
  874. * Give the firmware up to two seconds to enable
  875. * register access after a reset.
  876. */
  877. if ((jiffies_to_msecs(jiffies) - starttime) > 2000)
  878. return esas2r_set_degraded_mode(a,
  879. "unable to access registers");
  880. } else if (doorbell & DRBL_FORCE_INT) {
  881. u32 ver = (doorbell & DRBL_FW_VER_MSK);
  882. /*
  883. * This driver supports version 0 and version 1 of
  884. * the API
  885. */
  886. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  887. doorbell);
  888. if (ver == DRBL_FW_VER_0) {
  889. set_bit(AF_LEGACY_SGE_MODE, &a->flags);
  890. a->max_vdareq_size = 128;
  891. a->build_sgl = esas2r_build_sg_list_sge;
  892. } else if (ver == DRBL_FW_VER_1) {
  893. clear_bit(AF_LEGACY_SGE_MODE, &a->flags);
  894. a->max_vdareq_size = 1024;
  895. a->build_sgl = esas2r_build_sg_list_prd;
  896. } else {
  897. return esas2r_set_degraded_mode(a,
  898. "unknown firmware version");
  899. }
  900. break;
  901. }
  902. schedule_timeout_interruptible(msecs_to_jiffies(100));
  903. if ((jiffies_to_msecs(jiffies) - starttime) > 180000) {
  904. esas2r_hdebug("FW ready TMO");
  905. esas2r_bugon();
  906. return esas2r_set_degraded_mode(a,
  907. "firmware start has timed out");
  908. }
  909. }
  910. /* purge any asynchronous events since we will repost them later */
  911. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_DOWN);
  912. starttime = jiffies_to_msecs(jiffies);
  913. while (true) {
  914. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  915. if (doorbell & DRBL_MSG_IFC_DOWN) {
  916. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  917. doorbell);
  918. break;
  919. }
  920. schedule_timeout_interruptible(msecs_to_jiffies(50));
  921. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  922. esas2r_hdebug("timeout waiting for interface down");
  923. break;
  924. }
  925. }
  926. skip_chip_reset:
  927. /*
  928. * first things first, before we go changing any of these registers
  929. * disable the communication lists.
  930. */
  931. dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
  932. dw &= ~MU_ILC_ENABLE;
  933. esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
  934. dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
  935. dw &= ~MU_OLC_ENABLE;
  936. esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
  937. /* configure the communication list addresses */
  938. ppaddr = a->inbound_list_md.phys_addr;
  939. esas2r_write_register_dword(a, MU_IN_LIST_ADDR_LO,
  940. lower_32_bits(ppaddr));
  941. esas2r_write_register_dword(a, MU_IN_LIST_ADDR_HI,
  942. upper_32_bits(ppaddr));
  943. ppaddr = a->outbound_list_md.phys_addr;
  944. esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_LO,
  945. lower_32_bits(ppaddr));
  946. esas2r_write_register_dword(a, MU_OUT_LIST_ADDR_HI,
  947. upper_32_bits(ppaddr));
  948. ppaddr = a->uncached_phys +
  949. ((u8 *)a->outbound_copy - a->uncached);
  950. esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_LO,
  951. lower_32_bits(ppaddr));
  952. esas2r_write_register_dword(a, MU_OUT_LIST_COPY_PTR_HI,
  953. upper_32_bits(ppaddr));
  954. /* reset the read and write pointers */
  955. *a->outbound_copy =
  956. a->last_write =
  957. a->last_read = a->list_size - 1;
  958. set_bit(AF_COMM_LIST_TOGGLE, &a->flags);
  959. esas2r_write_register_dword(a, MU_IN_LIST_WRITE, MU_ILW_TOGGLE |
  960. a->last_write);
  961. esas2r_write_register_dword(a, MU_OUT_LIST_COPY, MU_OLC_TOGGLE |
  962. a->last_write);
  963. esas2r_write_register_dword(a, MU_IN_LIST_READ, MU_ILR_TOGGLE |
  964. a->last_write);
  965. esas2r_write_register_dword(a, MU_OUT_LIST_WRITE,
  966. MU_OLW_TOGGLE | a->last_write);
  967. /* configure the interface select fields */
  968. dw = esas2r_read_register_dword(a, MU_IN_LIST_IFC_CONFIG);
  969. dw &= ~(MU_ILIC_LIST | MU_ILIC_DEST);
  970. esas2r_write_register_dword(a, MU_IN_LIST_IFC_CONFIG,
  971. (dw | MU_ILIC_LIST_F0 | MU_ILIC_DEST_DDR));
  972. dw = esas2r_read_register_dword(a, MU_OUT_LIST_IFC_CONFIG);
  973. dw &= ~(MU_OLIC_LIST | MU_OLIC_SOURCE);
  974. esas2r_write_register_dword(a, MU_OUT_LIST_IFC_CONFIG,
  975. (dw | MU_OLIC_LIST_F0 |
  976. MU_OLIC_SOURCE_DDR));
  977. /* finish configuring the communication lists */
  978. dw = esas2r_read_register_dword(a, MU_IN_LIST_CONFIG);
  979. dw &= ~(MU_ILC_ENTRY_MASK | MU_ILC_NUMBER_MASK);
  980. dw |= MU_ILC_ENTRY_4_DW | MU_ILC_DYNAMIC_SRC
  981. | (a->list_size << MU_ILC_NUMBER_SHIFT);
  982. esas2r_write_register_dword(a, MU_IN_LIST_CONFIG, dw);
  983. dw = esas2r_read_register_dword(a, MU_OUT_LIST_CONFIG);
  984. dw &= ~(MU_OLC_ENTRY_MASK | MU_OLC_NUMBER_MASK);
  985. dw |= MU_OLC_ENTRY_4_DW | (a->list_size << MU_OLC_NUMBER_SHIFT);
  986. esas2r_write_register_dword(a, MU_OUT_LIST_CONFIG, dw);
  987. /*
  988. * notify the firmware that we're done setting up the communication
  989. * list registers. wait here until the firmware is done configuring
  990. * its lists. it will signal that it is done by enabling the lists.
  991. */
  992. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_MSG_IFC_INIT);
  993. starttime = jiffies_to_msecs(jiffies);
  994. while (true) {
  995. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  996. if (doorbell & DRBL_MSG_IFC_INIT) {
  997. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  998. doorbell);
  999. break;
  1000. }
  1001. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1002. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  1003. esas2r_hdebug(
  1004. "timeout waiting for communication list init");
  1005. esas2r_bugon();
  1006. return esas2r_set_degraded_mode(a,
  1007. "timeout waiting for communication list init");
  1008. }
  1009. }
  1010. /*
  1011. * flag whether the firmware supports the power down doorbell. we
  1012. * determine this by reading the inbound doorbell enable mask.
  1013. */
  1014. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_IN_ENB);
  1015. if (doorbell & DRBL_POWER_DOWN)
  1016. set_bit(AF2_VDA_POWER_DOWN, &a->flags2);
  1017. else
  1018. clear_bit(AF2_VDA_POWER_DOWN, &a->flags2);
  1019. /*
  1020. * enable assertion of outbound queue and doorbell interrupts in the
  1021. * main interrupt cause register.
  1022. */
  1023. esas2r_write_register_dword(a, MU_OUT_LIST_INT_MASK, MU_OLIS_MASK);
  1024. esas2r_write_register_dword(a, MU_DOORBELL_OUT_ENB, DRBL_ENB_MASK);
  1025. return true;
  1026. }
  1027. /* Process the initialization message just completed and format the next one. */
  1028. static bool esas2r_format_init_msg(struct esas2r_adapter *a,
  1029. struct esas2r_request *rq)
  1030. {
  1031. u32 msg = a->init_msg;
  1032. struct atto_vda_cfg_init *ci;
  1033. a->init_msg = 0;
  1034. switch (msg) {
  1035. case ESAS2R_INIT_MSG_START:
  1036. case ESAS2R_INIT_MSG_REINIT:
  1037. {
  1038. struct timeval now;
  1039. do_gettimeofday(&now);
  1040. esas2r_hdebug("CFG init");
  1041. esas2r_build_cfg_req(a,
  1042. rq,
  1043. VDA_CFG_INIT,
  1044. 0,
  1045. NULL);
  1046. ci = (struct atto_vda_cfg_init *)&rq->vrq->cfg.data.init;
  1047. ci->sgl_page_size = cpu_to_le32(sgl_page_size);
  1048. ci->epoch_time = cpu_to_le32(now.tv_sec);
  1049. rq->flags |= RF_FAILURE_OK;
  1050. a->init_msg = ESAS2R_INIT_MSG_INIT;
  1051. break;
  1052. }
  1053. case ESAS2R_INIT_MSG_INIT:
  1054. if (rq->req_stat == RS_SUCCESS) {
  1055. u32 major;
  1056. u32 minor;
  1057. u16 fw_release;
  1058. a->fw_version = le16_to_cpu(
  1059. rq->func_rsp.cfg_rsp.vda_version);
  1060. a->fw_build = rq->func_rsp.cfg_rsp.fw_build;
  1061. fw_release = le16_to_cpu(
  1062. rq->func_rsp.cfg_rsp.fw_release);
  1063. major = LOBYTE(fw_release);
  1064. minor = HIBYTE(fw_release);
  1065. a->fw_version += (major << 16) + (minor << 24);
  1066. } else {
  1067. esas2r_hdebug("FAILED");
  1068. }
  1069. /*
  1070. * the 2.71 and earlier releases of R6xx firmware did not error
  1071. * unsupported config requests correctly.
  1072. */
  1073. if ((test_bit(AF2_THUNDERBOLT, &a->flags2))
  1074. || (be32_to_cpu(a->fw_version) > 0x00524702)) {
  1075. esas2r_hdebug("CFG get init");
  1076. esas2r_build_cfg_req(a,
  1077. rq,
  1078. VDA_CFG_GET_INIT2,
  1079. sizeof(struct atto_vda_cfg_init),
  1080. NULL);
  1081. rq->vrq->cfg.sg_list_offset = offsetof(
  1082. struct atto_vda_cfg_req,
  1083. data.sge);
  1084. rq->vrq->cfg.data.prde.ctl_len =
  1085. cpu_to_le32(sizeof(struct atto_vda_cfg_init));
  1086. rq->vrq->cfg.data.prde.address = cpu_to_le64(
  1087. rq->vrq_md->phys_addr +
  1088. sizeof(union atto_vda_req));
  1089. rq->flags |= RF_FAILURE_OK;
  1090. a->init_msg = ESAS2R_INIT_MSG_GET_INIT;
  1091. break;
  1092. }
  1093. case ESAS2R_INIT_MSG_GET_INIT:
  1094. if (msg == ESAS2R_INIT_MSG_GET_INIT) {
  1095. ci = (struct atto_vda_cfg_init *)rq->data_buf;
  1096. if (rq->req_stat == RS_SUCCESS) {
  1097. a->num_targets_backend =
  1098. le32_to_cpu(ci->num_targets_backend);
  1099. a->ioctl_tunnel =
  1100. le32_to_cpu(ci->ioctl_tunnel);
  1101. } else {
  1102. esas2r_hdebug("FAILED");
  1103. }
  1104. }
  1105. /* fall through */
  1106. default:
  1107. rq->req_stat = RS_SUCCESS;
  1108. return false;
  1109. }
  1110. return true;
  1111. }
  1112. /*
  1113. * Perform initialization messages via the request queue. Messages are
  1114. * performed with interrupts disabled.
  1115. */
  1116. bool esas2r_init_msgs(struct esas2r_adapter *a)
  1117. {
  1118. bool success = true;
  1119. struct esas2r_request *rq = &a->general_req;
  1120. esas2r_rq_init_request(rq, a);
  1121. rq->comp_cb = esas2r_dummy_complete;
  1122. if (a->init_msg == 0)
  1123. a->init_msg = ESAS2R_INIT_MSG_REINIT;
  1124. while (a->init_msg) {
  1125. if (esas2r_format_init_msg(a, rq)) {
  1126. unsigned long flags;
  1127. while (true) {
  1128. spin_lock_irqsave(&a->queue_lock, flags);
  1129. esas2r_start_vda_request(a, rq);
  1130. spin_unlock_irqrestore(&a->queue_lock, flags);
  1131. esas2r_wait_request(a, rq);
  1132. if (rq->req_stat != RS_PENDING)
  1133. break;
  1134. }
  1135. }
  1136. if (rq->req_stat == RS_SUCCESS
  1137. || ((rq->flags & RF_FAILURE_OK)
  1138. && rq->req_stat != RS_TIMEOUT))
  1139. continue;
  1140. esas2r_log(ESAS2R_LOG_CRIT, "init message %x failed (%x, %x)",
  1141. a->init_msg, rq->req_stat, rq->flags);
  1142. a->init_msg = ESAS2R_INIT_MSG_START;
  1143. success = false;
  1144. break;
  1145. }
  1146. esas2r_rq_destroy_request(rq, a);
  1147. return success;
  1148. }
  1149. /* Initialize the adapter chip */
  1150. bool esas2r_init_adapter_hw(struct esas2r_adapter *a, bool init_poll)
  1151. {
  1152. bool rslt = false;
  1153. struct esas2r_request *rq;
  1154. u32 i;
  1155. if (test_bit(AF_DEGRADED_MODE, &a->flags))
  1156. goto exit;
  1157. if (!test_bit(AF_NVR_VALID, &a->flags)) {
  1158. if (!esas2r_nvram_read_direct(a))
  1159. esas2r_log(ESAS2R_LOG_WARN,
  1160. "invalid/missing NVRAM parameters");
  1161. }
  1162. if (!esas2r_init_msgs(a)) {
  1163. esas2r_set_degraded_mode(a, "init messages failed");
  1164. goto exit;
  1165. }
  1166. /* The firmware is ready. */
  1167. clear_bit(AF_DEGRADED_MODE, &a->flags);
  1168. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1169. /* Post all the async event requests */
  1170. for (i = 0, rq = a->first_ae_req; i < num_ae_requests; i++, rq++)
  1171. esas2r_start_ae_request(a, rq);
  1172. if (!a->flash_rev[0])
  1173. esas2r_read_flash_rev(a);
  1174. if (!a->image_type[0])
  1175. esas2r_read_image_type(a);
  1176. if (a->fw_version == 0)
  1177. a->fw_rev[0] = 0;
  1178. else
  1179. sprintf(a->fw_rev, "%1d.%02d",
  1180. (int)LOBYTE(HIWORD(a->fw_version)),
  1181. (int)HIBYTE(HIWORD(a->fw_version)));
  1182. esas2r_hdebug("firmware revision: %s", a->fw_rev);
  1183. if (test_bit(AF_CHPRST_DETECTED, &a->flags)
  1184. && (test_bit(AF_FIRST_INIT, &a->flags))) {
  1185. esas2r_enable_chip_interrupts(a);
  1186. return true;
  1187. }
  1188. /* initialize discovery */
  1189. esas2r_disc_initialize(a);
  1190. /*
  1191. * wait for the device wait time to expire here if requested. this is
  1192. * usually requested during initial driver load and possibly when
  1193. * resuming from a low power state. deferred device waiting will use
  1194. * interrupts. chip reset recovery always defers device waiting to
  1195. * avoid being in a TASKLET too long.
  1196. */
  1197. if (init_poll) {
  1198. u32 currtime = a->disc_start_time;
  1199. u32 nexttick = 100;
  1200. u32 deltatime;
  1201. /*
  1202. * Block Tasklets from getting scheduled and indicate this is
  1203. * polled discovery.
  1204. */
  1205. set_bit(AF_TASKLET_SCHEDULED, &a->flags);
  1206. set_bit(AF_DISC_POLLED, &a->flags);
  1207. /*
  1208. * Temporarily bring the disable count to zero to enable
  1209. * deferred processing. Note that the count is already zero
  1210. * after the first initialization.
  1211. */
  1212. if (test_bit(AF_FIRST_INIT, &a->flags))
  1213. atomic_dec(&a->disable_cnt);
  1214. while (test_bit(AF_DISC_PENDING, &a->flags)) {
  1215. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1216. /*
  1217. * Determine the need for a timer tick based on the
  1218. * delta time between this and the last iteration of
  1219. * this loop. We don't use the absolute time because
  1220. * then we would have to worry about when nexttick
  1221. * wraps and currtime hasn't yet.
  1222. */
  1223. deltatime = jiffies_to_msecs(jiffies) - currtime;
  1224. currtime += deltatime;
  1225. /*
  1226. * Process any waiting discovery as long as the chip is
  1227. * up. If a chip reset happens during initial polling,
  1228. * we have to make sure the timer tick processes the
  1229. * doorbell indicating the firmware is ready.
  1230. */
  1231. if (!test_bit(AF_CHPRST_PENDING, &a->flags))
  1232. esas2r_disc_check_for_work(a);
  1233. /* Simulate a timer tick. */
  1234. if (nexttick <= deltatime) {
  1235. /* Time for a timer tick */
  1236. nexttick += 100;
  1237. esas2r_timer_tick(a);
  1238. }
  1239. if (nexttick > deltatime)
  1240. nexttick -= deltatime;
  1241. /* Do any deferred processing */
  1242. if (esas2r_is_tasklet_pending(a))
  1243. esas2r_do_tasklet_tasks(a);
  1244. }
  1245. if (test_bit(AF_FIRST_INIT, &a->flags))
  1246. atomic_inc(&a->disable_cnt);
  1247. clear_bit(AF_DISC_POLLED, &a->flags);
  1248. clear_bit(AF_TASKLET_SCHEDULED, &a->flags);
  1249. }
  1250. esas2r_targ_db_report_changes(a);
  1251. /*
  1252. * For cases where (a) the initialization messages processing may
  1253. * handle an interrupt for a port event and a discovery is waiting, but
  1254. * we are not waiting for devices, or (b) the device wait time has been
  1255. * exhausted but there is still discovery pending, start any leftover
  1256. * discovery in interrupt driven mode.
  1257. */
  1258. esas2r_disc_start_waiting(a);
  1259. /* Enable chip interrupts */
  1260. a->int_mask = ESAS2R_INT_STS_MASK;
  1261. esas2r_enable_chip_interrupts(a);
  1262. esas2r_enable_heartbeat(a);
  1263. rslt = true;
  1264. exit:
  1265. /*
  1266. * Regardless of whether initialization was successful, certain things
  1267. * need to get done before we exit.
  1268. */
  1269. if (test_bit(AF_CHPRST_DETECTED, &a->flags) &&
  1270. test_bit(AF_FIRST_INIT, &a->flags)) {
  1271. /*
  1272. * Reinitialization was performed during the first
  1273. * initialization. Only clear the chip reset flag so the
  1274. * original device polling is not cancelled.
  1275. */
  1276. if (!rslt)
  1277. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1278. } else {
  1279. /* First initialization or a subsequent re-init is complete. */
  1280. if (!rslt) {
  1281. clear_bit(AF_CHPRST_PENDING, &a->flags);
  1282. clear_bit(AF_DISC_PENDING, &a->flags);
  1283. }
  1284. /* Enable deferred processing after the first initialization. */
  1285. if (test_bit(AF_FIRST_INIT, &a->flags)) {
  1286. clear_bit(AF_FIRST_INIT, &a->flags);
  1287. if (atomic_dec_return(&a->disable_cnt) == 0)
  1288. esas2r_do_deferred_processes(a);
  1289. }
  1290. }
  1291. return rslt;
  1292. }
  1293. void esas2r_reset_adapter(struct esas2r_adapter *a)
  1294. {
  1295. set_bit(AF_OS_RESET, &a->flags);
  1296. esas2r_local_reset_adapter(a);
  1297. esas2r_schedule_tasklet(a);
  1298. }
  1299. void esas2r_reset_chip(struct esas2r_adapter *a)
  1300. {
  1301. if (!esas2r_is_adapter_present(a))
  1302. return;
  1303. /*
  1304. * Before we reset the chip, save off the VDA core dump. The VDA core
  1305. * dump is located in the upper 512KB of the onchip SRAM. Make sure
  1306. * to not overwrite a previous crash that was saved.
  1307. */
  1308. if (test_bit(AF2_COREDUMP_AVAIL, &a->flags2) &&
  1309. !test_bit(AF2_COREDUMP_SAVED, &a->flags2)) {
  1310. esas2r_read_mem_block(a,
  1311. a->fw_coredump_buff,
  1312. MW_DATA_ADDR_SRAM + 0x80000,
  1313. ESAS2R_FWCOREDUMP_SZ);
  1314. set_bit(AF2_COREDUMP_SAVED, &a->flags2);
  1315. }
  1316. clear_bit(AF2_COREDUMP_AVAIL, &a->flags2);
  1317. /* Reset the chip */
  1318. if (a->pcid->revision == MVR_FREY_B2)
  1319. esas2r_write_register_dword(a, MU_CTL_STATUS_IN_B2,
  1320. MU_CTL_IN_FULL_RST2);
  1321. else
  1322. esas2r_write_register_dword(a, MU_CTL_STATUS_IN,
  1323. MU_CTL_IN_FULL_RST);
  1324. /* Stall a little while to let the reset condition clear */
  1325. mdelay(10);
  1326. }
  1327. static void esas2r_power_down_notify_firmware(struct esas2r_adapter *a)
  1328. {
  1329. u32 starttime;
  1330. u32 doorbell;
  1331. esas2r_write_register_dword(a, MU_DOORBELL_IN, DRBL_POWER_DOWN);
  1332. starttime = jiffies_to_msecs(jiffies);
  1333. while (true) {
  1334. doorbell = esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  1335. if (doorbell & DRBL_POWER_DOWN) {
  1336. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  1337. doorbell);
  1338. break;
  1339. }
  1340. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1341. if ((jiffies_to_msecs(jiffies) - starttime) > 30000) {
  1342. esas2r_hdebug("Timeout waiting for power down");
  1343. break;
  1344. }
  1345. }
  1346. }
  1347. /*
  1348. * Perform power management processing including managing device states, adapter
  1349. * states, interrupts, and I/O.
  1350. */
  1351. void esas2r_power_down(struct esas2r_adapter *a)
  1352. {
  1353. set_bit(AF_POWER_MGT, &a->flags);
  1354. set_bit(AF_POWER_DOWN, &a->flags);
  1355. if (!test_bit(AF_DEGRADED_MODE, &a->flags)) {
  1356. u32 starttime;
  1357. u32 doorbell;
  1358. /*
  1359. * We are currently running OK and will be reinitializing later.
  1360. * increment the disable count to coordinate with
  1361. * esas2r_init_adapter. We don't have to do this in degraded
  1362. * mode since we never enabled interrupts in the first place.
  1363. */
  1364. esas2r_disable_chip_interrupts(a);
  1365. esas2r_disable_heartbeat(a);
  1366. /* wait for any VDA activity to clear before continuing */
  1367. esas2r_write_register_dword(a, MU_DOORBELL_IN,
  1368. DRBL_MSG_IFC_DOWN);
  1369. starttime = jiffies_to_msecs(jiffies);
  1370. while (true) {
  1371. doorbell =
  1372. esas2r_read_register_dword(a, MU_DOORBELL_OUT);
  1373. if (doorbell & DRBL_MSG_IFC_DOWN) {
  1374. esas2r_write_register_dword(a, MU_DOORBELL_OUT,
  1375. doorbell);
  1376. break;
  1377. }
  1378. schedule_timeout_interruptible(msecs_to_jiffies(100));
  1379. if ((jiffies_to_msecs(jiffies) - starttime) > 3000) {
  1380. esas2r_hdebug(
  1381. "timeout waiting for interface down");
  1382. break;
  1383. }
  1384. }
  1385. /*
  1386. * For versions of firmware that support it tell them the driver
  1387. * is powering down.
  1388. */
  1389. if (test_bit(AF2_VDA_POWER_DOWN, &a->flags2))
  1390. esas2r_power_down_notify_firmware(a);
  1391. }
  1392. /* Suspend I/O processing. */
  1393. set_bit(AF_OS_RESET, &a->flags);
  1394. set_bit(AF_DISC_PENDING, &a->flags);
  1395. set_bit(AF_CHPRST_PENDING, &a->flags);
  1396. esas2r_process_adapter_reset(a);
  1397. /* Remove devices now that I/O is cleaned up. */
  1398. a->prev_dev_cnt = esas2r_targ_db_get_tgt_cnt(a);
  1399. esas2r_targ_db_remove_all(a, false);
  1400. }
  1401. /*
  1402. * Perform power management processing including managing device states, adapter
  1403. * states, interrupts, and I/O.
  1404. */
  1405. bool esas2r_power_up(struct esas2r_adapter *a, bool init_poll)
  1406. {
  1407. bool ret;
  1408. clear_bit(AF_POWER_DOWN, &a->flags);
  1409. esas2r_init_pci_cfg_space(a);
  1410. set_bit(AF_FIRST_INIT, &a->flags);
  1411. atomic_inc(&a->disable_cnt);
  1412. /* reinitialize the adapter */
  1413. ret = esas2r_check_adapter(a);
  1414. if (!esas2r_init_adapter_hw(a, init_poll))
  1415. ret = false;
  1416. /* send the reset asynchronous event */
  1417. esas2r_send_reset_ae(a, true);
  1418. /* clear this flag after initialization. */
  1419. clear_bit(AF_POWER_MGT, &a->flags);
  1420. return ret;
  1421. }
  1422. bool esas2r_is_adapter_present(struct esas2r_adapter *a)
  1423. {
  1424. if (test_bit(AF_NOT_PRESENT, &a->flags))
  1425. return false;
  1426. if (esas2r_read_register_dword(a, MU_DOORBELL_OUT) == 0xFFFFFFFF) {
  1427. set_bit(AF_NOT_PRESENT, &a->flags);
  1428. return false;
  1429. }
  1430. return true;
  1431. }
  1432. const char *esas2r_get_model_name(struct esas2r_adapter *a)
  1433. {
  1434. switch (a->pcid->subsystem_device) {
  1435. case ATTO_ESAS_R680:
  1436. return "ATTO ExpressSAS R680";
  1437. case ATTO_ESAS_R608:
  1438. return "ATTO ExpressSAS R608";
  1439. case ATTO_ESAS_R60F:
  1440. return "ATTO ExpressSAS R60F";
  1441. case ATTO_ESAS_R6F0:
  1442. return "ATTO ExpressSAS R6F0";
  1443. case ATTO_ESAS_R644:
  1444. return "ATTO ExpressSAS R644";
  1445. case ATTO_ESAS_R648:
  1446. return "ATTO ExpressSAS R648";
  1447. case ATTO_TSSC_3808:
  1448. return "ATTO ThunderStream SC 3808D";
  1449. case ATTO_TSSC_3808E:
  1450. return "ATTO ThunderStream SC 3808E";
  1451. case ATTO_TLSH_1068:
  1452. return "ATTO ThunderLink SH 1068";
  1453. }
  1454. return "ATTO SAS Controller";
  1455. }
  1456. const char *esas2r_get_model_name_short(struct esas2r_adapter *a)
  1457. {
  1458. switch (a->pcid->subsystem_device) {
  1459. case ATTO_ESAS_R680:
  1460. return "R680";
  1461. case ATTO_ESAS_R608:
  1462. return "R608";
  1463. case ATTO_ESAS_R60F:
  1464. return "R60F";
  1465. case ATTO_ESAS_R6F0:
  1466. return "R6F0";
  1467. case ATTO_ESAS_R644:
  1468. return "R644";
  1469. case ATTO_ESAS_R648:
  1470. return "R648";
  1471. case ATTO_TSSC_3808:
  1472. return "SC 3808D";
  1473. case ATTO_TSSC_3808E:
  1474. return "SC 3808E";
  1475. case ATTO_TLSH_1068:
  1476. return "SH 1068";
  1477. }
  1478. return "unknown";
  1479. }