mv_sas.c 54 KB

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  1. /*
  2. * Marvell 88SE64xx/88SE94xx main function
  3. *
  4. * Copyright 2007 Red Hat, Inc.
  5. * Copyright 2008 Marvell. <kewei@marvell.com>
  6. * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
  7. *
  8. * This file is licensed under GPLv2.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; version 2 of the
  13. * License.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  18. * General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307
  23. * USA
  24. */
  25. #include "mv_sas.h"
  26. static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
  27. {
  28. if (task->lldd_task) {
  29. struct mvs_slot_info *slot;
  30. slot = task->lldd_task;
  31. *tag = slot->slot_tag;
  32. return 1;
  33. }
  34. return 0;
  35. }
  36. void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
  37. {
  38. void *bitmap = mvi->tags;
  39. clear_bit(tag, bitmap);
  40. }
  41. void mvs_tag_free(struct mvs_info *mvi, u32 tag)
  42. {
  43. mvs_tag_clear(mvi, tag);
  44. }
  45. void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
  46. {
  47. void *bitmap = mvi->tags;
  48. set_bit(tag, bitmap);
  49. }
  50. inline int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
  51. {
  52. unsigned int index, tag;
  53. void *bitmap = mvi->tags;
  54. index = find_first_zero_bit(bitmap, mvi->tags_num);
  55. tag = index;
  56. if (tag >= mvi->tags_num)
  57. return -SAS_QUEUE_FULL;
  58. mvs_tag_set(mvi, tag);
  59. *tag_out = tag;
  60. return 0;
  61. }
  62. void mvs_tag_init(struct mvs_info *mvi)
  63. {
  64. int i;
  65. for (i = 0; i < mvi->tags_num; ++i)
  66. mvs_tag_clear(mvi, i);
  67. }
  68. struct mvs_info *mvs_find_dev_mvi(struct domain_device *dev)
  69. {
  70. unsigned long i = 0, j = 0, hi = 0;
  71. struct sas_ha_struct *sha = dev->port->ha;
  72. struct mvs_info *mvi = NULL;
  73. struct asd_sas_phy *phy;
  74. while (sha->sas_port[i]) {
  75. if (sha->sas_port[i] == dev->port) {
  76. phy = container_of(sha->sas_port[i]->phy_list.next,
  77. struct asd_sas_phy, port_phy_el);
  78. j = 0;
  79. while (sha->sas_phy[j]) {
  80. if (sha->sas_phy[j] == phy)
  81. break;
  82. j++;
  83. }
  84. break;
  85. }
  86. i++;
  87. }
  88. hi = j/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  89. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  90. return mvi;
  91. }
  92. int mvs_find_dev_phyno(struct domain_device *dev, int *phyno)
  93. {
  94. unsigned long i = 0, j = 0, n = 0, num = 0;
  95. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  96. struct mvs_info *mvi = mvi_dev->mvi_info;
  97. struct sas_ha_struct *sha = dev->port->ha;
  98. while (sha->sas_port[i]) {
  99. if (sha->sas_port[i] == dev->port) {
  100. struct asd_sas_phy *phy;
  101. list_for_each_entry(phy,
  102. &sha->sas_port[i]->phy_list, port_phy_el) {
  103. j = 0;
  104. while (sha->sas_phy[j]) {
  105. if (sha->sas_phy[j] == phy)
  106. break;
  107. j++;
  108. }
  109. phyno[n] = (j >= mvi->chip->n_phy) ?
  110. (j - mvi->chip->n_phy) : j;
  111. num++;
  112. n++;
  113. }
  114. break;
  115. }
  116. i++;
  117. }
  118. return num;
  119. }
  120. struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi,
  121. u8 reg_set)
  122. {
  123. u32 dev_no;
  124. for (dev_no = 0; dev_no < MVS_MAX_DEVICES; dev_no++) {
  125. if (mvi->devices[dev_no].taskfileset == MVS_ID_NOT_MAPPED)
  126. continue;
  127. if (mvi->devices[dev_no].taskfileset == reg_set)
  128. return &mvi->devices[dev_no];
  129. }
  130. return NULL;
  131. }
  132. static inline void mvs_free_reg_set(struct mvs_info *mvi,
  133. struct mvs_device *dev)
  134. {
  135. if (!dev) {
  136. mv_printk("device has been free.\n");
  137. return;
  138. }
  139. if (dev->taskfileset == MVS_ID_NOT_MAPPED)
  140. return;
  141. MVS_CHIP_DISP->free_reg_set(mvi, &dev->taskfileset);
  142. }
  143. static inline u8 mvs_assign_reg_set(struct mvs_info *mvi,
  144. struct mvs_device *dev)
  145. {
  146. if (dev->taskfileset != MVS_ID_NOT_MAPPED)
  147. return 0;
  148. return MVS_CHIP_DISP->assign_reg_set(mvi, &dev->taskfileset);
  149. }
  150. void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard)
  151. {
  152. u32 no;
  153. for_each_phy(phy_mask, phy_mask, no) {
  154. if (!(phy_mask & 1))
  155. continue;
  156. MVS_CHIP_DISP->phy_reset(mvi, no, hard);
  157. }
  158. }
  159. int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
  160. void *funcdata)
  161. {
  162. int rc = 0, phy_id = sas_phy->id;
  163. u32 tmp, i = 0, hi;
  164. struct sas_ha_struct *sha = sas_phy->ha;
  165. struct mvs_info *mvi = NULL;
  166. while (sha->sas_phy[i]) {
  167. if (sha->sas_phy[i] == sas_phy)
  168. break;
  169. i++;
  170. }
  171. hi = i/((struct mvs_prv_info *)sha->lldd_ha)->n_phy;
  172. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[hi];
  173. switch (func) {
  174. case PHY_FUNC_SET_LINK_RATE:
  175. MVS_CHIP_DISP->phy_set_link_rate(mvi, phy_id, funcdata);
  176. break;
  177. case PHY_FUNC_HARD_RESET:
  178. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_id);
  179. if (tmp & PHY_RST_HARD)
  180. break;
  181. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_HARD_RESET);
  182. break;
  183. case PHY_FUNC_LINK_RESET:
  184. MVS_CHIP_DISP->phy_enable(mvi, phy_id);
  185. MVS_CHIP_DISP->phy_reset(mvi, phy_id, MVS_SOFT_RESET);
  186. break;
  187. case PHY_FUNC_DISABLE:
  188. MVS_CHIP_DISP->phy_disable(mvi, phy_id);
  189. break;
  190. case PHY_FUNC_RELEASE_SPINUP_HOLD:
  191. default:
  192. rc = -ENOSYS;
  193. }
  194. msleep(200);
  195. return rc;
  196. }
  197. void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
  198. u32 off_hi, u64 sas_addr)
  199. {
  200. u32 lo = (u32)sas_addr;
  201. u32 hi = (u32)(sas_addr>>32);
  202. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_lo);
  203. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, lo);
  204. MVS_CHIP_DISP->write_port_cfg_addr(mvi, port_id, off_hi);
  205. MVS_CHIP_DISP->write_port_cfg_data(mvi, port_id, hi);
  206. }
  207. static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
  208. {
  209. struct mvs_phy *phy = &mvi->phy[i];
  210. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  211. struct sas_ha_struct *sas_ha;
  212. if (!phy->phy_attached)
  213. return;
  214. if (!(phy->att_dev_info & PORT_DEV_TRGT_MASK)
  215. && phy->phy_type & PORT_TYPE_SAS) {
  216. return;
  217. }
  218. sas_ha = mvi->sas;
  219. sas_ha->notify_phy_event(sas_phy, PHYE_OOB_DONE);
  220. if (sas_phy->phy) {
  221. struct sas_phy *sphy = sas_phy->phy;
  222. sphy->negotiated_linkrate = sas_phy->linkrate;
  223. sphy->minimum_linkrate = phy->minimum_linkrate;
  224. sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
  225. sphy->maximum_linkrate = phy->maximum_linkrate;
  226. sphy->maximum_linkrate_hw = MVS_CHIP_DISP->phy_max_link_rate();
  227. }
  228. if (phy->phy_type & PORT_TYPE_SAS) {
  229. struct sas_identify_frame *id;
  230. id = (struct sas_identify_frame *)phy->frame_rcvd;
  231. id->dev_type = phy->identify.device_type;
  232. id->initiator_bits = SAS_PROTOCOL_ALL;
  233. id->target_bits = phy->identify.target_port_protocols;
  234. /* direct attached SAS device */
  235. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  236. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  237. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x00);
  238. }
  239. } else if (phy->phy_type & PORT_TYPE_SATA) {
  240. /*Nothing*/
  241. }
  242. mv_dprintk("phy %d byte dmaded.\n", i + mvi->id * mvi->chip->n_phy);
  243. sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
  244. mvi->sas->notify_port_event(sas_phy,
  245. PORTE_BYTES_DMAED);
  246. }
  247. void mvs_scan_start(struct Scsi_Host *shost)
  248. {
  249. int i, j;
  250. unsigned short core_nr;
  251. struct mvs_info *mvi;
  252. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  253. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  254. core_nr = ((struct mvs_prv_info *)sha->lldd_ha)->n_host;
  255. for (j = 0; j < core_nr; j++) {
  256. mvi = ((struct mvs_prv_info *)sha->lldd_ha)->mvi[j];
  257. for (i = 0; i < mvi->chip->n_phy; ++i)
  258. mvs_bytes_dmaed(mvi, i);
  259. }
  260. mvs_prv->scan_finished = 1;
  261. }
  262. int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
  263. {
  264. struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
  265. struct mvs_prv_info *mvs_prv = sha->lldd_ha;
  266. if (mvs_prv->scan_finished == 0)
  267. return 0;
  268. sas_drain_work(sha);
  269. return 1;
  270. }
  271. static int mvs_task_prep_smp(struct mvs_info *mvi,
  272. struct mvs_task_exec_info *tei)
  273. {
  274. int elem, rc, i;
  275. struct sas_ha_struct *sha = mvi->sas;
  276. struct sas_task *task = tei->task;
  277. struct mvs_cmd_hdr *hdr = tei->hdr;
  278. struct domain_device *dev = task->dev;
  279. struct asd_sas_port *sas_port = dev->port;
  280. struct sas_phy *sphy = dev->phy;
  281. struct asd_sas_phy *sas_phy = sha->sas_phy[sphy->number];
  282. struct scatterlist *sg_req, *sg_resp;
  283. u32 req_len, resp_len, tag = tei->tag;
  284. void *buf_tmp;
  285. u8 *buf_oaf;
  286. dma_addr_t buf_tmp_dma;
  287. void *buf_prd;
  288. struct mvs_slot_info *slot = &mvi->slot_info[tag];
  289. u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  290. /*
  291. * DMA-map SMP request, response buffers
  292. */
  293. sg_req = &task->smp_task.smp_req;
  294. elem = dma_map_sg(mvi->dev, sg_req, 1, PCI_DMA_TODEVICE);
  295. if (!elem)
  296. return -ENOMEM;
  297. req_len = sg_dma_len(sg_req);
  298. sg_resp = &task->smp_task.smp_resp;
  299. elem = dma_map_sg(mvi->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
  300. if (!elem) {
  301. rc = -ENOMEM;
  302. goto err_out;
  303. }
  304. resp_len = SB_RFB_MAX;
  305. /* must be in dwords */
  306. if ((req_len & 0x3) || (resp_len & 0x3)) {
  307. rc = -EINVAL;
  308. goto err_out_2;
  309. }
  310. /*
  311. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  312. */
  313. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ***** */
  314. buf_tmp = slot->buf;
  315. buf_tmp_dma = slot->buf_dma;
  316. hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
  317. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  318. buf_oaf = buf_tmp;
  319. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  320. buf_tmp += MVS_OAF_SZ;
  321. buf_tmp_dma += MVS_OAF_SZ;
  322. /* region 3: PRD table *********************************** */
  323. buf_prd = buf_tmp;
  324. if (tei->n_elem)
  325. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  326. else
  327. hdr->prd_tbl = 0;
  328. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  329. buf_tmp += i;
  330. buf_tmp_dma += i;
  331. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  332. slot->response = buf_tmp;
  333. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  334. if (mvi->flags & MVF_FLAG_SOC)
  335. hdr->reserved[0] = 0;
  336. /*
  337. * Fill in TX ring and command slot header
  338. */
  339. slot->tx = mvi->tx_prod;
  340. mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
  341. TXQ_MODE_I | tag |
  342. (MVS_PHY_ID << TXQ_PHY_SHIFT));
  343. hdr->flags |= flags;
  344. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
  345. hdr->tags = cpu_to_le32(tag);
  346. hdr->data_len = 0;
  347. /* generate open address frame hdr (first 12 bytes) */
  348. /* initiator, SMP, ftype 1h */
  349. buf_oaf[0] = (1 << 7) | (PROTOCOL_SMP << 4) | 0x01;
  350. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  351. *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
  352. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  353. /* fill in PRD (scatter/gather) table, if any */
  354. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  355. return 0;
  356. err_out_2:
  357. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_resp, 1,
  358. PCI_DMA_FROMDEVICE);
  359. err_out:
  360. dma_unmap_sg(mvi->dev, &tei->task->smp_task.smp_req, 1,
  361. PCI_DMA_TODEVICE);
  362. return rc;
  363. }
  364. static u32 mvs_get_ncq_tag(struct sas_task *task, u32 *tag)
  365. {
  366. struct ata_queued_cmd *qc = task->uldd_task;
  367. if (qc) {
  368. if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
  369. qc->tf.command == ATA_CMD_FPDMA_READ) {
  370. *tag = qc->tag;
  371. return 1;
  372. }
  373. }
  374. return 0;
  375. }
  376. static int mvs_task_prep_ata(struct mvs_info *mvi,
  377. struct mvs_task_exec_info *tei)
  378. {
  379. struct sas_task *task = tei->task;
  380. struct domain_device *dev = task->dev;
  381. struct mvs_device *mvi_dev = dev->lldd_dev;
  382. struct mvs_cmd_hdr *hdr = tei->hdr;
  383. struct asd_sas_port *sas_port = dev->port;
  384. struct mvs_slot_info *slot;
  385. void *buf_prd;
  386. u32 tag = tei->tag, hdr_tag;
  387. u32 flags, del_q;
  388. void *buf_tmp;
  389. u8 *buf_cmd, *buf_oaf;
  390. dma_addr_t buf_tmp_dma;
  391. u32 i, req_len, resp_len;
  392. const u32 max_resp_len = SB_RFB_MAX;
  393. if (mvs_assign_reg_set(mvi, mvi_dev) == MVS_ID_NOT_MAPPED) {
  394. mv_dprintk("Have not enough regiset for dev %d.\n",
  395. mvi_dev->device_id);
  396. return -EBUSY;
  397. }
  398. slot = &mvi->slot_info[tag];
  399. slot->tx = mvi->tx_prod;
  400. del_q = TXQ_MODE_I | tag |
  401. (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
  402. ((sas_port->phy_mask & TXQ_PHY_MASK) << TXQ_PHY_SHIFT) |
  403. (mvi_dev->taskfileset << TXQ_SRS_SHIFT);
  404. mvi->tx[mvi->tx_prod] = cpu_to_le32(del_q);
  405. if (task->data_dir == DMA_FROM_DEVICE)
  406. flags = (MVS_CHIP_DISP->prd_count() << MCH_PRD_LEN_SHIFT);
  407. else
  408. flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
  409. if (task->ata_task.use_ncq)
  410. flags |= MCH_FPDMA;
  411. if (dev->sata_dev.class == ATA_DEV_ATAPI) {
  412. if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
  413. flags |= MCH_ATAPI;
  414. }
  415. hdr->flags = cpu_to_le32(flags);
  416. if (task->ata_task.use_ncq && mvs_get_ncq_tag(task, &hdr_tag))
  417. task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
  418. else
  419. hdr_tag = tag;
  420. hdr->tags = cpu_to_le32(hdr_tag);
  421. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  422. /*
  423. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  424. */
  425. /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
  426. buf_cmd = buf_tmp = slot->buf;
  427. buf_tmp_dma = slot->buf_dma;
  428. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  429. buf_tmp += MVS_ATA_CMD_SZ;
  430. buf_tmp_dma += MVS_ATA_CMD_SZ;
  431. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  432. /* used for STP. unused for SATA? */
  433. buf_oaf = buf_tmp;
  434. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  435. buf_tmp += MVS_OAF_SZ;
  436. buf_tmp_dma += MVS_OAF_SZ;
  437. /* region 3: PRD table ********************************************* */
  438. buf_prd = buf_tmp;
  439. if (tei->n_elem)
  440. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  441. else
  442. hdr->prd_tbl = 0;
  443. i = MVS_CHIP_DISP->prd_size() * MVS_CHIP_DISP->prd_count();
  444. buf_tmp += i;
  445. buf_tmp_dma += i;
  446. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  447. slot->response = buf_tmp;
  448. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  449. if (mvi->flags & MVF_FLAG_SOC)
  450. hdr->reserved[0] = 0;
  451. req_len = sizeof(struct host_to_dev_fis);
  452. resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
  453. sizeof(struct mvs_err_info) - i;
  454. /* request, response lengths */
  455. resp_len = min(resp_len, max_resp_len);
  456. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  457. if (likely(!task->ata_task.device_control_reg_update))
  458. task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
  459. /* fill in command FIS and ATAPI CDB */
  460. memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
  461. if (dev->sata_dev.class == ATA_DEV_ATAPI)
  462. memcpy(buf_cmd + STP_ATAPI_CMD,
  463. task->ata_task.atapi_packet, 16);
  464. /* generate open address frame hdr (first 12 bytes) */
  465. /* initiator, STP, ftype 1h */
  466. buf_oaf[0] = (1 << 7) | (PROTOCOL_STP << 4) | 0x1;
  467. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  468. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  469. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  470. /* fill in PRD (scatter/gather) table, if any */
  471. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  472. if (task->data_dir == DMA_FROM_DEVICE)
  473. MVS_CHIP_DISP->dma_fix(mvi, sas_port->phy_mask,
  474. TRASH_BUCKET_SIZE, tei->n_elem, buf_prd);
  475. return 0;
  476. }
  477. static int mvs_task_prep_ssp(struct mvs_info *mvi,
  478. struct mvs_task_exec_info *tei, int is_tmf,
  479. struct mvs_tmf_task *tmf)
  480. {
  481. struct sas_task *task = tei->task;
  482. struct mvs_cmd_hdr *hdr = tei->hdr;
  483. struct mvs_port *port = tei->port;
  484. struct domain_device *dev = task->dev;
  485. struct mvs_device *mvi_dev = dev->lldd_dev;
  486. struct asd_sas_port *sas_port = dev->port;
  487. struct mvs_slot_info *slot;
  488. void *buf_prd;
  489. struct ssp_frame_hdr *ssp_hdr;
  490. void *buf_tmp;
  491. u8 *buf_cmd, *buf_oaf, fburst = 0;
  492. dma_addr_t buf_tmp_dma;
  493. u32 flags;
  494. u32 resp_len, req_len, i, tag = tei->tag;
  495. const u32 max_resp_len = SB_RFB_MAX;
  496. u32 phy_mask;
  497. slot = &mvi->slot_info[tag];
  498. phy_mask = ((port->wide_port_phymap) ? port->wide_port_phymap :
  499. sas_port->phy_mask) & TXQ_PHY_MASK;
  500. slot->tx = mvi->tx_prod;
  501. mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
  502. (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
  503. (phy_mask << TXQ_PHY_SHIFT));
  504. flags = MCH_RETRY;
  505. if (task->ssp_task.enable_first_burst) {
  506. flags |= MCH_FBURST;
  507. fburst = (1 << 7);
  508. }
  509. if (is_tmf)
  510. flags |= (MCH_SSP_FR_TASK << MCH_SSP_FR_TYPE_SHIFT);
  511. else
  512. flags |= (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT);
  513. hdr->flags = cpu_to_le32(flags | (tei->n_elem << MCH_PRD_LEN_SHIFT));
  514. hdr->tags = cpu_to_le32(tag);
  515. hdr->data_len = cpu_to_le32(task->total_xfer_len);
  516. /*
  517. * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
  518. */
  519. /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
  520. buf_cmd = buf_tmp = slot->buf;
  521. buf_tmp_dma = slot->buf_dma;
  522. hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
  523. buf_tmp += MVS_SSP_CMD_SZ;
  524. buf_tmp_dma += MVS_SSP_CMD_SZ;
  525. /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
  526. buf_oaf = buf_tmp;
  527. hdr->open_frame = cpu_to_le64(buf_tmp_dma);
  528. buf_tmp += MVS_OAF_SZ;
  529. buf_tmp_dma += MVS_OAF_SZ;
  530. /* region 3: PRD table ********************************************* */
  531. buf_prd = buf_tmp;
  532. if (tei->n_elem)
  533. hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
  534. else
  535. hdr->prd_tbl = 0;
  536. i = MVS_CHIP_DISP->prd_size() * tei->n_elem;
  537. buf_tmp += i;
  538. buf_tmp_dma += i;
  539. /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
  540. slot->response = buf_tmp;
  541. hdr->status_buf = cpu_to_le64(buf_tmp_dma);
  542. if (mvi->flags & MVF_FLAG_SOC)
  543. hdr->reserved[0] = 0;
  544. resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
  545. sizeof(struct mvs_err_info) - i;
  546. resp_len = min(resp_len, max_resp_len);
  547. req_len = sizeof(struct ssp_frame_hdr) + 28;
  548. /* request, response lengths */
  549. hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
  550. /* generate open address frame hdr (first 12 bytes) */
  551. /* initiator, SSP, ftype 1h */
  552. buf_oaf[0] = (1 << 7) | (PROTOCOL_SSP << 4) | 0x1;
  553. buf_oaf[1] = min(sas_port->linkrate, dev->linkrate) & 0xf;
  554. *(u16 *)(buf_oaf + 2) = cpu_to_be16(mvi_dev->device_id + 1);
  555. memcpy(buf_oaf + 4, dev->sas_addr, SAS_ADDR_SIZE);
  556. /* fill in SSP frame header (Command Table.SSP frame header) */
  557. ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
  558. if (is_tmf)
  559. ssp_hdr->frame_type = SSP_TASK;
  560. else
  561. ssp_hdr->frame_type = SSP_COMMAND;
  562. memcpy(ssp_hdr->hashed_dest_addr, dev->hashed_sas_addr,
  563. HASHED_SAS_ADDR_SIZE);
  564. memcpy(ssp_hdr->hashed_src_addr,
  565. dev->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
  566. ssp_hdr->tag = cpu_to_be16(tag);
  567. /* fill in IU for TASK and Command Frame */
  568. buf_cmd += sizeof(*ssp_hdr);
  569. memcpy(buf_cmd, &task->ssp_task.LUN, 8);
  570. if (ssp_hdr->frame_type != SSP_TASK) {
  571. buf_cmd[9] = fburst | task->ssp_task.task_attr |
  572. (task->ssp_task.task_prio << 3);
  573. memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
  574. task->ssp_task.cmd->cmd_len);
  575. } else{
  576. buf_cmd[10] = tmf->tmf;
  577. switch (tmf->tmf) {
  578. case TMF_ABORT_TASK:
  579. case TMF_QUERY_TASK:
  580. buf_cmd[12] =
  581. (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
  582. buf_cmd[13] =
  583. tmf->tag_of_task_to_be_managed & 0xff;
  584. break;
  585. default:
  586. break;
  587. }
  588. }
  589. /* fill in PRD (scatter/gather) table, if any */
  590. MVS_CHIP_DISP->make_prd(task->scatter, tei->n_elem, buf_prd);
  591. return 0;
  592. }
  593. #define DEV_IS_GONE(mvi_dev) ((!mvi_dev || (mvi_dev->dev_type == SAS_PHY_UNUSED)))
  594. static int mvs_task_prep(struct sas_task *task, struct mvs_info *mvi, int is_tmf,
  595. struct mvs_tmf_task *tmf, int *pass)
  596. {
  597. struct domain_device *dev = task->dev;
  598. struct mvs_device *mvi_dev = dev->lldd_dev;
  599. struct mvs_task_exec_info tei;
  600. struct mvs_slot_info *slot;
  601. u32 tag = 0xdeadbeef, n_elem = 0;
  602. int rc = 0;
  603. if (!dev->port) {
  604. struct task_status_struct *tsm = &task->task_status;
  605. tsm->resp = SAS_TASK_UNDELIVERED;
  606. tsm->stat = SAS_PHY_DOWN;
  607. /*
  608. * libsas will use dev->port, should
  609. * not call task_done for sata
  610. */
  611. if (dev->dev_type != SAS_SATA_DEV)
  612. task->task_done(task);
  613. return rc;
  614. }
  615. if (DEV_IS_GONE(mvi_dev)) {
  616. if (mvi_dev)
  617. mv_dprintk("device %d not ready.\n",
  618. mvi_dev->device_id);
  619. else
  620. mv_dprintk("device %016llx not ready.\n",
  621. SAS_ADDR(dev->sas_addr));
  622. rc = SAS_PHY_DOWN;
  623. return rc;
  624. }
  625. tei.port = dev->port->lldd_port;
  626. if (tei.port && !tei.port->port_attached && !tmf) {
  627. if (sas_protocol_ata(task->task_proto)) {
  628. struct task_status_struct *ts = &task->task_status;
  629. mv_dprintk("SATA/STP port %d does not attach"
  630. "device.\n", dev->port->id);
  631. ts->resp = SAS_TASK_COMPLETE;
  632. ts->stat = SAS_PHY_DOWN;
  633. task->task_done(task);
  634. } else {
  635. struct task_status_struct *ts = &task->task_status;
  636. mv_dprintk("SAS port %d does not attach"
  637. "device.\n", dev->port->id);
  638. ts->resp = SAS_TASK_UNDELIVERED;
  639. ts->stat = SAS_PHY_DOWN;
  640. task->task_done(task);
  641. }
  642. return rc;
  643. }
  644. if (!sas_protocol_ata(task->task_proto)) {
  645. if (task->num_scatter) {
  646. n_elem = dma_map_sg(mvi->dev,
  647. task->scatter,
  648. task->num_scatter,
  649. task->data_dir);
  650. if (!n_elem) {
  651. rc = -ENOMEM;
  652. goto prep_out;
  653. }
  654. }
  655. } else {
  656. n_elem = task->num_scatter;
  657. }
  658. rc = mvs_tag_alloc(mvi, &tag);
  659. if (rc)
  660. goto err_out;
  661. slot = &mvi->slot_info[tag];
  662. task->lldd_task = NULL;
  663. slot->n_elem = n_elem;
  664. slot->slot_tag = tag;
  665. slot->buf = pci_pool_alloc(mvi->dma_pool, GFP_ATOMIC, &slot->buf_dma);
  666. if (!slot->buf)
  667. goto err_out_tag;
  668. memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
  669. tei.task = task;
  670. tei.hdr = &mvi->slot[tag];
  671. tei.tag = tag;
  672. tei.n_elem = n_elem;
  673. switch (task->task_proto) {
  674. case SAS_PROTOCOL_SMP:
  675. rc = mvs_task_prep_smp(mvi, &tei);
  676. break;
  677. case SAS_PROTOCOL_SSP:
  678. rc = mvs_task_prep_ssp(mvi, &tei, is_tmf, tmf);
  679. break;
  680. case SAS_PROTOCOL_SATA:
  681. case SAS_PROTOCOL_STP:
  682. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  683. rc = mvs_task_prep_ata(mvi, &tei);
  684. break;
  685. default:
  686. dev_printk(KERN_ERR, mvi->dev,
  687. "unknown sas_task proto: 0x%x\n",
  688. task->task_proto);
  689. rc = -EINVAL;
  690. break;
  691. }
  692. if (rc) {
  693. mv_dprintk("rc is %x\n", rc);
  694. goto err_out_slot_buf;
  695. }
  696. slot->task = task;
  697. slot->port = tei.port;
  698. task->lldd_task = slot;
  699. list_add_tail(&slot->entry, &tei.port->list);
  700. spin_lock(&task->task_state_lock);
  701. task->task_state_flags |= SAS_TASK_AT_INITIATOR;
  702. spin_unlock(&task->task_state_lock);
  703. mvi_dev->running_req++;
  704. ++(*pass);
  705. mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
  706. return rc;
  707. err_out_slot_buf:
  708. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  709. err_out_tag:
  710. mvs_tag_free(mvi, tag);
  711. err_out:
  712. dev_printk(KERN_ERR, mvi->dev, "mvsas prep failed[%d]!\n", rc);
  713. if (!sas_protocol_ata(task->task_proto))
  714. if (n_elem)
  715. dma_unmap_sg(mvi->dev, task->scatter, n_elem,
  716. task->data_dir);
  717. prep_out:
  718. return rc;
  719. }
  720. static int mvs_task_exec(struct sas_task *task, gfp_t gfp_flags,
  721. struct completion *completion, int is_tmf,
  722. struct mvs_tmf_task *tmf)
  723. {
  724. struct mvs_info *mvi = NULL;
  725. u32 rc = 0;
  726. u32 pass = 0;
  727. unsigned long flags = 0;
  728. mvi = ((struct mvs_device *)task->dev->lldd_dev)->mvi_info;
  729. spin_lock_irqsave(&mvi->lock, flags);
  730. rc = mvs_task_prep(task, mvi, is_tmf, tmf, &pass);
  731. if (rc)
  732. dev_printk(KERN_ERR, mvi->dev, "mvsas exec failed[%d]!\n", rc);
  733. if (likely(pass))
  734. MVS_CHIP_DISP->start_delivery(mvi, (mvi->tx_prod - 1) &
  735. (MVS_CHIP_SLOT_SZ - 1));
  736. spin_unlock_irqrestore(&mvi->lock, flags);
  737. return rc;
  738. }
  739. int mvs_queue_command(struct sas_task *task, gfp_t gfp_flags)
  740. {
  741. return mvs_task_exec(task, gfp_flags, NULL, 0, NULL);
  742. }
  743. static void mvs_slot_free(struct mvs_info *mvi, u32 rx_desc)
  744. {
  745. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  746. mvs_tag_clear(mvi, slot_idx);
  747. }
  748. static void mvs_slot_task_free(struct mvs_info *mvi, struct sas_task *task,
  749. struct mvs_slot_info *slot, u32 slot_idx)
  750. {
  751. if (!slot)
  752. return;
  753. if (!slot->task)
  754. return;
  755. if (!sas_protocol_ata(task->task_proto))
  756. if (slot->n_elem)
  757. dma_unmap_sg(mvi->dev, task->scatter,
  758. slot->n_elem, task->data_dir);
  759. switch (task->task_proto) {
  760. case SAS_PROTOCOL_SMP:
  761. dma_unmap_sg(mvi->dev, &task->smp_task.smp_resp, 1,
  762. PCI_DMA_FROMDEVICE);
  763. dma_unmap_sg(mvi->dev, &task->smp_task.smp_req, 1,
  764. PCI_DMA_TODEVICE);
  765. break;
  766. case SAS_PROTOCOL_SATA:
  767. case SAS_PROTOCOL_STP:
  768. case SAS_PROTOCOL_SSP:
  769. default:
  770. /* do nothing */
  771. break;
  772. }
  773. if (slot->buf) {
  774. pci_pool_free(mvi->dma_pool, slot->buf, slot->buf_dma);
  775. slot->buf = NULL;
  776. }
  777. list_del_init(&slot->entry);
  778. task->lldd_task = NULL;
  779. slot->task = NULL;
  780. slot->port = NULL;
  781. slot->slot_tag = 0xFFFFFFFF;
  782. mvs_slot_free(mvi, slot_idx);
  783. }
  784. static void mvs_update_wideport(struct mvs_info *mvi, int phy_no)
  785. {
  786. struct mvs_phy *phy = &mvi->phy[phy_no];
  787. struct mvs_port *port = phy->port;
  788. int j, no;
  789. for_each_phy(port->wide_port_phymap, j, no) {
  790. if (j & 1) {
  791. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  792. PHYR_WIDE_PORT);
  793. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  794. port->wide_port_phymap);
  795. } else {
  796. MVS_CHIP_DISP->write_port_cfg_addr(mvi, no,
  797. PHYR_WIDE_PORT);
  798. MVS_CHIP_DISP->write_port_cfg_data(mvi, no,
  799. 0);
  800. }
  801. }
  802. }
  803. static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
  804. {
  805. u32 tmp;
  806. struct mvs_phy *phy = &mvi->phy[i];
  807. struct mvs_port *port = phy->port;
  808. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, i);
  809. if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
  810. if (!port)
  811. phy->phy_attached = 1;
  812. return tmp;
  813. }
  814. if (port) {
  815. if (phy->phy_type & PORT_TYPE_SAS) {
  816. port->wide_port_phymap &= ~(1U << i);
  817. if (!port->wide_port_phymap)
  818. port->port_attached = 0;
  819. mvs_update_wideport(mvi, i);
  820. } else if (phy->phy_type & PORT_TYPE_SATA)
  821. port->port_attached = 0;
  822. phy->port = NULL;
  823. phy->phy_attached = 0;
  824. phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
  825. }
  826. return 0;
  827. }
  828. static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
  829. {
  830. u32 *s = (u32 *) buf;
  831. if (!s)
  832. return NULL;
  833. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
  834. s[3] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  835. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
  836. s[2] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  837. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
  838. s[1] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  839. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
  840. s[0] = cpu_to_le32(MVS_CHIP_DISP->read_port_cfg_data(mvi, i));
  841. if (((s[1] & 0x00FFFFFF) == 0x00EB1401) && (*(u8 *)&s[3] == 0x01))
  842. s[1] = 0x00EB1401 | (*((u8 *)&s[1] + 3) & 0x10);
  843. return s;
  844. }
  845. static u32 mvs_is_sig_fis_received(u32 irq_status)
  846. {
  847. return irq_status & PHYEV_SIG_FIS;
  848. }
  849. static void mvs_sig_remove_timer(struct mvs_phy *phy)
  850. {
  851. if (phy->timer.function)
  852. del_timer(&phy->timer);
  853. phy->timer.function = NULL;
  854. }
  855. void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st)
  856. {
  857. struct mvs_phy *phy = &mvi->phy[i];
  858. struct sas_identify_frame *id;
  859. id = (struct sas_identify_frame *)phy->frame_rcvd;
  860. if (get_st) {
  861. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, i);
  862. phy->phy_status = mvs_is_phy_ready(mvi, i);
  863. }
  864. if (phy->phy_status) {
  865. int oob_done = 0;
  866. struct asd_sas_phy *sas_phy = &mvi->phy[i].sas_phy;
  867. oob_done = MVS_CHIP_DISP->oob_done(mvi, i);
  868. MVS_CHIP_DISP->fix_phy_info(mvi, i, id);
  869. if (phy->phy_type & PORT_TYPE_SATA) {
  870. phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
  871. if (mvs_is_sig_fis_received(phy->irq_status)) {
  872. mvs_sig_remove_timer(phy);
  873. phy->phy_attached = 1;
  874. phy->att_dev_sas_addr =
  875. i + mvi->id * mvi->chip->n_phy;
  876. if (oob_done)
  877. sas_phy->oob_mode = SATA_OOB_MODE;
  878. phy->frame_rcvd_size =
  879. sizeof(struct dev_to_host_fis);
  880. mvs_get_d2h_reg(mvi, i, id);
  881. } else {
  882. u32 tmp;
  883. dev_printk(KERN_DEBUG, mvi->dev,
  884. "Phy%d : No sig fis\n", i);
  885. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, i);
  886. MVS_CHIP_DISP->write_port_irq_mask(mvi, i,
  887. tmp | PHYEV_SIG_FIS);
  888. phy->phy_attached = 0;
  889. phy->phy_type &= ~PORT_TYPE_SATA;
  890. goto out_done;
  891. }
  892. } else if (phy->phy_type & PORT_TYPE_SAS
  893. || phy->att_dev_info & PORT_SSP_INIT_MASK) {
  894. phy->phy_attached = 1;
  895. phy->identify.device_type =
  896. phy->att_dev_info & PORT_DEV_TYPE_MASK;
  897. if (phy->identify.device_type == SAS_END_DEVICE)
  898. phy->identify.target_port_protocols =
  899. SAS_PROTOCOL_SSP;
  900. else if (phy->identify.device_type != SAS_PHY_UNUSED)
  901. phy->identify.target_port_protocols =
  902. SAS_PROTOCOL_SMP;
  903. if (oob_done)
  904. sas_phy->oob_mode = SAS_OOB_MODE;
  905. phy->frame_rcvd_size =
  906. sizeof(struct sas_identify_frame);
  907. }
  908. memcpy(sas_phy->attached_sas_addr,
  909. &phy->att_dev_sas_addr, SAS_ADDR_SIZE);
  910. if (MVS_CHIP_DISP->phy_work_around)
  911. MVS_CHIP_DISP->phy_work_around(mvi, i);
  912. }
  913. mv_dprintk("phy %d attach dev info is %x\n",
  914. i + mvi->id * mvi->chip->n_phy, phy->att_dev_info);
  915. mv_dprintk("phy %d attach sas addr is %llx\n",
  916. i + mvi->id * mvi->chip->n_phy, phy->att_dev_sas_addr);
  917. out_done:
  918. if (get_st)
  919. MVS_CHIP_DISP->write_port_irq_stat(mvi, i, phy->irq_status);
  920. }
  921. static void mvs_port_notify_formed(struct asd_sas_phy *sas_phy, int lock)
  922. {
  923. struct sas_ha_struct *sas_ha = sas_phy->ha;
  924. struct mvs_info *mvi = NULL; int i = 0, hi;
  925. struct mvs_phy *phy = sas_phy->lldd_phy;
  926. struct asd_sas_port *sas_port = sas_phy->port;
  927. struct mvs_port *port;
  928. unsigned long flags = 0;
  929. if (!sas_port)
  930. return;
  931. while (sas_ha->sas_phy[i]) {
  932. if (sas_ha->sas_phy[i] == sas_phy)
  933. break;
  934. i++;
  935. }
  936. hi = i/((struct mvs_prv_info *)sas_ha->lldd_ha)->n_phy;
  937. mvi = ((struct mvs_prv_info *)sas_ha->lldd_ha)->mvi[hi];
  938. if (i >= mvi->chip->n_phy)
  939. port = &mvi->port[i - mvi->chip->n_phy];
  940. else
  941. port = &mvi->port[i];
  942. if (lock)
  943. spin_lock_irqsave(&mvi->lock, flags);
  944. port->port_attached = 1;
  945. phy->port = port;
  946. sas_port->lldd_port = port;
  947. if (phy->phy_type & PORT_TYPE_SAS) {
  948. port->wide_port_phymap = sas_port->phy_mask;
  949. mv_printk("set wide port phy map %x\n", sas_port->phy_mask);
  950. mvs_update_wideport(mvi, sas_phy->id);
  951. /* direct attached SAS device */
  952. if (phy->att_dev_info & PORT_SSP_TRGT_MASK) {
  953. MVS_CHIP_DISP->write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
  954. MVS_CHIP_DISP->write_port_cfg_data(mvi, i, 0x04);
  955. }
  956. }
  957. if (lock)
  958. spin_unlock_irqrestore(&mvi->lock, flags);
  959. }
  960. static void mvs_port_notify_deformed(struct asd_sas_phy *sas_phy, int lock)
  961. {
  962. struct domain_device *dev;
  963. struct mvs_phy *phy = sas_phy->lldd_phy;
  964. struct mvs_info *mvi = phy->mvi;
  965. struct asd_sas_port *port = sas_phy->port;
  966. int phy_no = 0;
  967. while (phy != &mvi->phy[phy_no]) {
  968. phy_no++;
  969. if (phy_no >= MVS_MAX_PHYS)
  970. return;
  971. }
  972. list_for_each_entry(dev, &port->dev_list, dev_list_node)
  973. mvs_do_release_task(phy->mvi, phy_no, dev);
  974. }
  975. void mvs_port_formed(struct asd_sas_phy *sas_phy)
  976. {
  977. mvs_port_notify_formed(sas_phy, 1);
  978. }
  979. void mvs_port_deformed(struct asd_sas_phy *sas_phy)
  980. {
  981. mvs_port_notify_deformed(sas_phy, 1);
  982. }
  983. struct mvs_device *mvs_alloc_dev(struct mvs_info *mvi)
  984. {
  985. u32 dev;
  986. for (dev = 0; dev < MVS_MAX_DEVICES; dev++) {
  987. if (mvi->devices[dev].dev_type == SAS_PHY_UNUSED) {
  988. mvi->devices[dev].device_id = dev;
  989. return &mvi->devices[dev];
  990. }
  991. }
  992. if (dev == MVS_MAX_DEVICES)
  993. mv_printk("max support %d devices, ignore ..\n",
  994. MVS_MAX_DEVICES);
  995. return NULL;
  996. }
  997. void mvs_free_dev(struct mvs_device *mvi_dev)
  998. {
  999. u32 id = mvi_dev->device_id;
  1000. memset(mvi_dev, 0, sizeof(*mvi_dev));
  1001. mvi_dev->device_id = id;
  1002. mvi_dev->dev_type = SAS_PHY_UNUSED;
  1003. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1004. mvi_dev->taskfileset = MVS_ID_NOT_MAPPED;
  1005. }
  1006. int mvs_dev_found_notify(struct domain_device *dev, int lock)
  1007. {
  1008. unsigned long flags = 0;
  1009. int res = 0;
  1010. struct mvs_info *mvi = NULL;
  1011. struct domain_device *parent_dev = dev->parent;
  1012. struct mvs_device *mvi_device;
  1013. mvi = mvs_find_dev_mvi(dev);
  1014. if (lock)
  1015. spin_lock_irqsave(&mvi->lock, flags);
  1016. mvi_device = mvs_alloc_dev(mvi);
  1017. if (!mvi_device) {
  1018. res = -1;
  1019. goto found_out;
  1020. }
  1021. dev->lldd_dev = mvi_device;
  1022. mvi_device->dev_status = MVS_DEV_NORMAL;
  1023. mvi_device->dev_type = dev->dev_type;
  1024. mvi_device->mvi_info = mvi;
  1025. mvi_device->sas_device = dev;
  1026. if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) {
  1027. int phy_id;
  1028. u8 phy_num = parent_dev->ex_dev.num_phys;
  1029. struct ex_phy *phy;
  1030. for (phy_id = 0; phy_id < phy_num; phy_id++) {
  1031. phy = &parent_dev->ex_dev.ex_phy[phy_id];
  1032. if (SAS_ADDR(phy->attached_sas_addr) ==
  1033. SAS_ADDR(dev->sas_addr)) {
  1034. mvi_device->attached_phy = phy_id;
  1035. break;
  1036. }
  1037. }
  1038. if (phy_id == phy_num) {
  1039. mv_printk("Error: no attached dev:%016llx"
  1040. "at ex:%016llx.\n",
  1041. SAS_ADDR(dev->sas_addr),
  1042. SAS_ADDR(parent_dev->sas_addr));
  1043. res = -1;
  1044. }
  1045. }
  1046. found_out:
  1047. if (lock)
  1048. spin_unlock_irqrestore(&mvi->lock, flags);
  1049. return res;
  1050. }
  1051. int mvs_dev_found(struct domain_device *dev)
  1052. {
  1053. return mvs_dev_found_notify(dev, 1);
  1054. }
  1055. void mvs_dev_gone_notify(struct domain_device *dev)
  1056. {
  1057. unsigned long flags = 0;
  1058. struct mvs_device *mvi_dev = dev->lldd_dev;
  1059. struct mvs_info *mvi;
  1060. if (!mvi_dev) {
  1061. mv_dprintk("found dev has gone.\n");
  1062. return;
  1063. }
  1064. mvi = mvi_dev->mvi_info;
  1065. spin_lock_irqsave(&mvi->lock, flags);
  1066. mv_dprintk("found dev[%d:%x] is gone.\n",
  1067. mvi_dev->device_id, mvi_dev->dev_type);
  1068. mvs_release_task(mvi, dev);
  1069. mvs_free_reg_set(mvi, mvi_dev);
  1070. mvs_free_dev(mvi_dev);
  1071. dev->lldd_dev = NULL;
  1072. mvi_dev->sas_device = NULL;
  1073. spin_unlock_irqrestore(&mvi->lock, flags);
  1074. }
  1075. void mvs_dev_gone(struct domain_device *dev)
  1076. {
  1077. mvs_dev_gone_notify(dev);
  1078. }
  1079. static void mvs_task_done(struct sas_task *task)
  1080. {
  1081. if (!del_timer(&task->slow_task->timer))
  1082. return;
  1083. complete(&task->slow_task->completion);
  1084. }
  1085. static void mvs_tmf_timedout(unsigned long data)
  1086. {
  1087. struct sas_task *task = (struct sas_task *)data;
  1088. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1089. complete(&task->slow_task->completion);
  1090. }
  1091. #define MVS_TASK_TIMEOUT 20
  1092. static int mvs_exec_internal_tmf_task(struct domain_device *dev,
  1093. void *parameter, u32 para_len, struct mvs_tmf_task *tmf)
  1094. {
  1095. int res, retry;
  1096. struct sas_task *task = NULL;
  1097. for (retry = 0; retry < 3; retry++) {
  1098. task = sas_alloc_slow_task(GFP_KERNEL);
  1099. if (!task)
  1100. return -ENOMEM;
  1101. task->dev = dev;
  1102. task->task_proto = dev->tproto;
  1103. memcpy(&task->ssp_task, parameter, para_len);
  1104. task->task_done = mvs_task_done;
  1105. task->slow_task->timer.data = (unsigned long) task;
  1106. task->slow_task->timer.function = mvs_tmf_timedout;
  1107. task->slow_task->timer.expires = jiffies + MVS_TASK_TIMEOUT*HZ;
  1108. add_timer(&task->slow_task->timer);
  1109. res = mvs_task_exec(task, GFP_KERNEL, NULL, 1, tmf);
  1110. if (res) {
  1111. del_timer(&task->slow_task->timer);
  1112. mv_printk("executing internal task failed:%d\n", res);
  1113. goto ex_err;
  1114. }
  1115. wait_for_completion(&task->slow_task->completion);
  1116. res = TMF_RESP_FUNC_FAILED;
  1117. /* Even TMF timed out, return direct. */
  1118. if ((task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
  1119. if (!(task->task_state_flags & SAS_TASK_STATE_DONE)) {
  1120. mv_printk("TMF task[%x] timeout.\n", tmf->tmf);
  1121. goto ex_err;
  1122. }
  1123. }
  1124. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1125. task->task_status.stat == SAM_STAT_GOOD) {
  1126. res = TMF_RESP_FUNC_COMPLETE;
  1127. break;
  1128. }
  1129. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1130. task->task_status.stat == SAS_DATA_UNDERRUN) {
  1131. /* no error, but return the number of bytes of
  1132. * underrun */
  1133. res = task->task_status.residual;
  1134. break;
  1135. }
  1136. if (task->task_status.resp == SAS_TASK_COMPLETE &&
  1137. task->task_status.stat == SAS_DATA_OVERRUN) {
  1138. mv_dprintk("blocked task error.\n");
  1139. res = -EMSGSIZE;
  1140. break;
  1141. } else {
  1142. mv_dprintk(" task to dev %016llx response: 0x%x "
  1143. "status 0x%x\n",
  1144. SAS_ADDR(dev->sas_addr),
  1145. task->task_status.resp,
  1146. task->task_status.stat);
  1147. sas_free_task(task);
  1148. task = NULL;
  1149. }
  1150. }
  1151. ex_err:
  1152. BUG_ON(retry == 3 && task != NULL);
  1153. sas_free_task(task);
  1154. return res;
  1155. }
  1156. static int mvs_debug_issue_ssp_tmf(struct domain_device *dev,
  1157. u8 *lun, struct mvs_tmf_task *tmf)
  1158. {
  1159. struct sas_ssp_task ssp_task;
  1160. if (!(dev->tproto & SAS_PROTOCOL_SSP))
  1161. return TMF_RESP_FUNC_ESUPP;
  1162. memcpy(ssp_task.LUN, lun, 8);
  1163. return mvs_exec_internal_tmf_task(dev, &ssp_task,
  1164. sizeof(ssp_task), tmf);
  1165. }
  1166. /* Standard mandates link reset for ATA (type 0)
  1167. and hard reset for SSP (type 1) , only for RECOVERY */
  1168. static int mvs_debug_I_T_nexus_reset(struct domain_device *dev)
  1169. {
  1170. int rc;
  1171. struct sas_phy *phy = sas_get_local_phy(dev);
  1172. int reset_type = (dev->dev_type == SAS_SATA_DEV ||
  1173. (dev->tproto & SAS_PROTOCOL_STP)) ? 0 : 1;
  1174. rc = sas_phy_reset(phy, reset_type);
  1175. sas_put_local_phy(phy);
  1176. msleep(2000);
  1177. return rc;
  1178. }
  1179. /* mandatory SAM-3 */
  1180. int mvs_lu_reset(struct domain_device *dev, u8 *lun)
  1181. {
  1182. unsigned long flags;
  1183. int rc = TMF_RESP_FUNC_FAILED;
  1184. struct mvs_tmf_task tmf_task;
  1185. struct mvs_device * mvi_dev = dev->lldd_dev;
  1186. struct mvs_info *mvi = mvi_dev->mvi_info;
  1187. tmf_task.tmf = TMF_LU_RESET;
  1188. mvi_dev->dev_status = MVS_DEV_EH;
  1189. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1190. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1191. spin_lock_irqsave(&mvi->lock, flags);
  1192. mvs_release_task(mvi, dev);
  1193. spin_unlock_irqrestore(&mvi->lock, flags);
  1194. }
  1195. /* If failed, fall-through I_T_Nexus reset */
  1196. mv_printk("%s for device[%x]:rc= %d\n", __func__,
  1197. mvi_dev->device_id, rc);
  1198. return rc;
  1199. }
  1200. int mvs_I_T_nexus_reset(struct domain_device *dev)
  1201. {
  1202. unsigned long flags;
  1203. int rc = TMF_RESP_FUNC_FAILED;
  1204. struct mvs_device * mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1205. struct mvs_info *mvi = mvi_dev->mvi_info;
  1206. if (mvi_dev->dev_status != MVS_DEV_EH)
  1207. return TMF_RESP_FUNC_COMPLETE;
  1208. else
  1209. mvi_dev->dev_status = MVS_DEV_NORMAL;
  1210. rc = mvs_debug_I_T_nexus_reset(dev);
  1211. mv_printk("%s for device[%x]:rc= %d\n",
  1212. __func__, mvi_dev->device_id, rc);
  1213. spin_lock_irqsave(&mvi->lock, flags);
  1214. mvs_release_task(mvi, dev);
  1215. spin_unlock_irqrestore(&mvi->lock, flags);
  1216. return rc;
  1217. }
  1218. /* optional SAM-3 */
  1219. int mvs_query_task(struct sas_task *task)
  1220. {
  1221. u32 tag;
  1222. struct scsi_lun lun;
  1223. struct mvs_tmf_task tmf_task;
  1224. int rc = TMF_RESP_FUNC_FAILED;
  1225. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1226. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1227. struct domain_device *dev = task->dev;
  1228. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1229. struct mvs_info *mvi = mvi_dev->mvi_info;
  1230. int_to_scsilun(cmnd->device->lun, &lun);
  1231. rc = mvs_find_tag(mvi, task, &tag);
  1232. if (rc == 0) {
  1233. rc = TMF_RESP_FUNC_FAILED;
  1234. return rc;
  1235. }
  1236. tmf_task.tmf = TMF_QUERY_TASK;
  1237. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1238. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1239. switch (rc) {
  1240. /* The task is still in Lun, release it then */
  1241. case TMF_RESP_FUNC_SUCC:
  1242. /* The task is not in Lun or failed, reset the phy */
  1243. case TMF_RESP_FUNC_FAILED:
  1244. case TMF_RESP_FUNC_COMPLETE:
  1245. break;
  1246. }
  1247. }
  1248. mv_printk("%s:rc= %d\n", __func__, rc);
  1249. return rc;
  1250. }
  1251. /* mandatory SAM-3, still need free task/slot info */
  1252. int mvs_abort_task(struct sas_task *task)
  1253. {
  1254. struct scsi_lun lun;
  1255. struct mvs_tmf_task tmf_task;
  1256. struct domain_device *dev = task->dev;
  1257. struct mvs_device *mvi_dev = (struct mvs_device *)dev->lldd_dev;
  1258. struct mvs_info *mvi;
  1259. int rc = TMF_RESP_FUNC_FAILED;
  1260. unsigned long flags;
  1261. u32 tag;
  1262. if (!mvi_dev) {
  1263. mv_printk("Device has removed\n");
  1264. return TMF_RESP_FUNC_FAILED;
  1265. }
  1266. mvi = mvi_dev->mvi_info;
  1267. spin_lock_irqsave(&task->task_state_lock, flags);
  1268. if (task->task_state_flags & SAS_TASK_STATE_DONE) {
  1269. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1270. rc = TMF_RESP_FUNC_COMPLETE;
  1271. goto out;
  1272. }
  1273. spin_unlock_irqrestore(&task->task_state_lock, flags);
  1274. mvi_dev->dev_status = MVS_DEV_EH;
  1275. if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
  1276. struct scsi_cmnd * cmnd = (struct scsi_cmnd *)task->uldd_task;
  1277. int_to_scsilun(cmnd->device->lun, &lun);
  1278. rc = mvs_find_tag(mvi, task, &tag);
  1279. if (rc == 0) {
  1280. mv_printk("No such tag in %s\n", __func__);
  1281. rc = TMF_RESP_FUNC_FAILED;
  1282. return rc;
  1283. }
  1284. tmf_task.tmf = TMF_ABORT_TASK;
  1285. tmf_task.tag_of_task_to_be_managed = cpu_to_le16(tag);
  1286. rc = mvs_debug_issue_ssp_tmf(dev, lun.scsi_lun, &tmf_task);
  1287. /* if successful, clear the task and callback forwards.*/
  1288. if (rc == TMF_RESP_FUNC_COMPLETE) {
  1289. u32 slot_no;
  1290. struct mvs_slot_info *slot;
  1291. if (task->lldd_task) {
  1292. slot = task->lldd_task;
  1293. slot_no = (u32) (slot - mvi->slot_info);
  1294. spin_lock_irqsave(&mvi->lock, flags);
  1295. mvs_slot_complete(mvi, slot_no, 1);
  1296. spin_unlock_irqrestore(&mvi->lock, flags);
  1297. }
  1298. }
  1299. } else if (task->task_proto & SAS_PROTOCOL_SATA ||
  1300. task->task_proto & SAS_PROTOCOL_STP) {
  1301. if (SAS_SATA_DEV == dev->dev_type) {
  1302. struct mvs_slot_info *slot = task->lldd_task;
  1303. u32 slot_idx = (u32)(slot - mvi->slot_info);
  1304. mv_dprintk("mvs_abort_task() mvi=%p task=%p "
  1305. "slot=%p slot_idx=x%x\n",
  1306. mvi, task, slot, slot_idx);
  1307. task->task_state_flags |= SAS_TASK_STATE_ABORTED;
  1308. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1309. rc = TMF_RESP_FUNC_COMPLETE;
  1310. goto out;
  1311. }
  1312. }
  1313. out:
  1314. if (rc != TMF_RESP_FUNC_COMPLETE)
  1315. mv_printk("%s:rc= %d\n", __func__, rc);
  1316. return rc;
  1317. }
  1318. int mvs_abort_task_set(struct domain_device *dev, u8 *lun)
  1319. {
  1320. int rc = TMF_RESP_FUNC_FAILED;
  1321. struct mvs_tmf_task tmf_task;
  1322. tmf_task.tmf = TMF_ABORT_TASK_SET;
  1323. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1324. return rc;
  1325. }
  1326. int mvs_clear_aca(struct domain_device *dev, u8 *lun)
  1327. {
  1328. int rc = TMF_RESP_FUNC_FAILED;
  1329. struct mvs_tmf_task tmf_task;
  1330. tmf_task.tmf = TMF_CLEAR_ACA;
  1331. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1332. return rc;
  1333. }
  1334. int mvs_clear_task_set(struct domain_device *dev, u8 *lun)
  1335. {
  1336. int rc = TMF_RESP_FUNC_FAILED;
  1337. struct mvs_tmf_task tmf_task;
  1338. tmf_task.tmf = TMF_CLEAR_TASK_SET;
  1339. rc = mvs_debug_issue_ssp_tmf(dev, lun, &tmf_task);
  1340. return rc;
  1341. }
  1342. static int mvs_sata_done(struct mvs_info *mvi, struct sas_task *task,
  1343. u32 slot_idx, int err)
  1344. {
  1345. struct mvs_device *mvi_dev = task->dev->lldd_dev;
  1346. struct task_status_struct *tstat = &task->task_status;
  1347. struct ata_task_resp *resp = (struct ata_task_resp *)tstat->buf;
  1348. int stat = SAM_STAT_GOOD;
  1349. resp->frame_len = sizeof(struct dev_to_host_fis);
  1350. memcpy(&resp->ending_fis[0],
  1351. SATA_RECEIVED_D2H_FIS(mvi_dev->taskfileset),
  1352. sizeof(struct dev_to_host_fis));
  1353. tstat->buf_valid_size = sizeof(*resp);
  1354. if (unlikely(err)) {
  1355. if (unlikely(err & CMD_ISS_STPD))
  1356. stat = SAS_OPEN_REJECT;
  1357. else
  1358. stat = SAS_PROTO_RESPONSE;
  1359. }
  1360. return stat;
  1361. }
  1362. void mvs_set_sense(u8 *buffer, int len, int d_sense,
  1363. int key, int asc, int ascq)
  1364. {
  1365. memset(buffer, 0, len);
  1366. if (d_sense) {
  1367. /* Descriptor format */
  1368. if (len < 4) {
  1369. mv_printk("Length %d of sense buffer too small to "
  1370. "fit sense %x:%x:%x", len, key, asc, ascq);
  1371. }
  1372. buffer[0] = 0x72; /* Response Code */
  1373. if (len > 1)
  1374. buffer[1] = key; /* Sense Key */
  1375. if (len > 2)
  1376. buffer[2] = asc; /* ASC */
  1377. if (len > 3)
  1378. buffer[3] = ascq; /* ASCQ */
  1379. } else {
  1380. if (len < 14) {
  1381. mv_printk("Length %d of sense buffer too small to "
  1382. "fit sense %x:%x:%x", len, key, asc, ascq);
  1383. }
  1384. buffer[0] = 0x70; /* Response Code */
  1385. if (len > 2)
  1386. buffer[2] = key; /* Sense Key */
  1387. if (len > 7)
  1388. buffer[7] = 0x0a; /* Additional Sense Length */
  1389. if (len > 12)
  1390. buffer[12] = asc; /* ASC */
  1391. if (len > 13)
  1392. buffer[13] = ascq; /* ASCQ */
  1393. }
  1394. return;
  1395. }
  1396. void mvs_fill_ssp_resp_iu(struct ssp_response_iu *iu,
  1397. u8 key, u8 asc, u8 asc_q)
  1398. {
  1399. iu->datapres = 2;
  1400. iu->response_data_len = 0;
  1401. iu->sense_data_len = 17;
  1402. iu->status = 02;
  1403. mvs_set_sense(iu->sense_data, 17, 0,
  1404. key, asc, asc_q);
  1405. }
  1406. static int mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
  1407. u32 slot_idx)
  1408. {
  1409. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1410. int stat;
  1411. u32 err_dw0 = le32_to_cpu(*(u32 *)slot->response);
  1412. u32 err_dw1 = le32_to_cpu(*((u32 *)slot->response + 1));
  1413. u32 tfs = 0;
  1414. enum mvs_port_type type = PORT_TYPE_SAS;
  1415. if (err_dw0 & CMD_ISS_STPD)
  1416. MVS_CHIP_DISP->issue_stop(mvi, type, tfs);
  1417. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1418. stat = SAM_STAT_CHECK_CONDITION;
  1419. switch (task->task_proto) {
  1420. case SAS_PROTOCOL_SSP:
  1421. {
  1422. stat = SAS_ABORTED_TASK;
  1423. if ((err_dw0 & NO_DEST) || err_dw1 & bit(31)) {
  1424. struct ssp_response_iu *iu = slot->response +
  1425. sizeof(struct mvs_err_info);
  1426. mvs_fill_ssp_resp_iu(iu, NOT_READY, 0x04, 01);
  1427. sas_ssp_task_response(mvi->dev, task, iu);
  1428. stat = SAM_STAT_CHECK_CONDITION;
  1429. }
  1430. if (err_dw1 & bit(31))
  1431. mv_printk("reuse same slot, retry command.\n");
  1432. break;
  1433. }
  1434. case SAS_PROTOCOL_SMP:
  1435. stat = SAM_STAT_CHECK_CONDITION;
  1436. break;
  1437. case SAS_PROTOCOL_SATA:
  1438. case SAS_PROTOCOL_STP:
  1439. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
  1440. {
  1441. task->ata_task.use_ncq = 0;
  1442. stat = SAS_PROTO_RESPONSE;
  1443. mvs_sata_done(mvi, task, slot_idx, err_dw0);
  1444. }
  1445. break;
  1446. default:
  1447. break;
  1448. }
  1449. return stat;
  1450. }
  1451. int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags)
  1452. {
  1453. u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
  1454. struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
  1455. struct sas_task *task = slot->task;
  1456. struct mvs_device *mvi_dev = NULL;
  1457. struct task_status_struct *tstat;
  1458. struct domain_device *dev;
  1459. u32 aborted;
  1460. void *to;
  1461. enum exec_status sts;
  1462. if (unlikely(!task || !task->lldd_task || !task->dev))
  1463. return -1;
  1464. tstat = &task->task_status;
  1465. dev = task->dev;
  1466. mvi_dev = dev->lldd_dev;
  1467. spin_lock(&task->task_state_lock);
  1468. task->task_state_flags &=
  1469. ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
  1470. task->task_state_flags |= SAS_TASK_STATE_DONE;
  1471. /* race condition*/
  1472. aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
  1473. spin_unlock(&task->task_state_lock);
  1474. memset(tstat, 0, sizeof(*tstat));
  1475. tstat->resp = SAS_TASK_COMPLETE;
  1476. if (unlikely(aborted)) {
  1477. tstat->stat = SAS_ABORTED_TASK;
  1478. if (mvi_dev && mvi_dev->running_req)
  1479. mvi_dev->running_req--;
  1480. if (sas_protocol_ata(task->task_proto))
  1481. mvs_free_reg_set(mvi, mvi_dev);
  1482. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1483. return -1;
  1484. }
  1485. /* when no device attaching, go ahead and complete by error handling*/
  1486. if (unlikely(!mvi_dev || flags)) {
  1487. if (!mvi_dev)
  1488. mv_dprintk("port has not device.\n");
  1489. tstat->stat = SAS_PHY_DOWN;
  1490. goto out;
  1491. }
  1492. /*
  1493. * error info record present; slot->response is 32 bit aligned but may
  1494. * not be 64 bit aligned, so check for zero in two 32 bit reads
  1495. */
  1496. if (unlikely((rx_desc & RXQ_ERR)
  1497. && (*((u32 *)slot->response)
  1498. || *(((u32 *)slot->response) + 1)))) {
  1499. mv_dprintk("port %d slot %d rx_desc %X has error info"
  1500. "%016llX.\n", slot->port->sas_port.id, slot_idx,
  1501. rx_desc, get_unaligned_le64(slot->response));
  1502. tstat->stat = mvs_slot_err(mvi, task, slot_idx);
  1503. tstat->resp = SAS_TASK_COMPLETE;
  1504. goto out;
  1505. }
  1506. switch (task->task_proto) {
  1507. case SAS_PROTOCOL_SSP:
  1508. /* hw says status == 0, datapres == 0 */
  1509. if (rx_desc & RXQ_GOOD) {
  1510. tstat->stat = SAM_STAT_GOOD;
  1511. tstat->resp = SAS_TASK_COMPLETE;
  1512. }
  1513. /* response frame present */
  1514. else if (rx_desc & RXQ_RSP) {
  1515. struct ssp_response_iu *iu = slot->response +
  1516. sizeof(struct mvs_err_info);
  1517. sas_ssp_task_response(mvi->dev, task, iu);
  1518. } else
  1519. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1520. break;
  1521. case SAS_PROTOCOL_SMP: {
  1522. struct scatterlist *sg_resp = &task->smp_task.smp_resp;
  1523. tstat->stat = SAM_STAT_GOOD;
  1524. to = kmap_atomic(sg_page(sg_resp));
  1525. memcpy(to + sg_resp->offset,
  1526. slot->response + sizeof(struct mvs_err_info),
  1527. sg_dma_len(sg_resp));
  1528. kunmap_atomic(to);
  1529. break;
  1530. }
  1531. case SAS_PROTOCOL_SATA:
  1532. case SAS_PROTOCOL_STP:
  1533. case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
  1534. tstat->stat = mvs_sata_done(mvi, task, slot_idx, 0);
  1535. break;
  1536. }
  1537. default:
  1538. tstat->stat = SAM_STAT_CHECK_CONDITION;
  1539. break;
  1540. }
  1541. if (!slot->port->port_attached) {
  1542. mv_dprintk("port %d has removed.\n", slot->port->sas_port.id);
  1543. tstat->stat = SAS_PHY_DOWN;
  1544. }
  1545. out:
  1546. if (mvi_dev && mvi_dev->running_req) {
  1547. mvi_dev->running_req--;
  1548. if (sas_protocol_ata(task->task_proto) && !mvi_dev->running_req)
  1549. mvs_free_reg_set(mvi, mvi_dev);
  1550. }
  1551. mvs_slot_task_free(mvi, task, slot, slot_idx);
  1552. sts = tstat->stat;
  1553. spin_unlock(&mvi->lock);
  1554. if (task->task_done)
  1555. task->task_done(task);
  1556. spin_lock(&mvi->lock);
  1557. return sts;
  1558. }
  1559. void mvs_do_release_task(struct mvs_info *mvi,
  1560. int phy_no, struct domain_device *dev)
  1561. {
  1562. u32 slot_idx;
  1563. struct mvs_phy *phy;
  1564. struct mvs_port *port;
  1565. struct mvs_slot_info *slot, *slot2;
  1566. phy = &mvi->phy[phy_no];
  1567. port = phy->port;
  1568. if (!port)
  1569. return;
  1570. /* clean cmpl queue in case request is already finished */
  1571. mvs_int_rx(mvi, false);
  1572. list_for_each_entry_safe(slot, slot2, &port->list, entry) {
  1573. struct sas_task *task;
  1574. slot_idx = (u32) (slot - mvi->slot_info);
  1575. task = slot->task;
  1576. if (dev && task->dev != dev)
  1577. continue;
  1578. mv_printk("Release slot [%x] tag[%x], task [%p]:\n",
  1579. slot_idx, slot->slot_tag, task);
  1580. MVS_CHIP_DISP->command_active(mvi, slot_idx);
  1581. mvs_slot_complete(mvi, slot_idx, 1);
  1582. }
  1583. }
  1584. void mvs_release_task(struct mvs_info *mvi,
  1585. struct domain_device *dev)
  1586. {
  1587. int i, phyno[WIDE_PORT_MAX_PHY], num;
  1588. num = mvs_find_dev_phyno(dev, phyno);
  1589. for (i = 0; i < num; i++)
  1590. mvs_do_release_task(mvi, phyno[i], dev);
  1591. }
  1592. static void mvs_phy_disconnected(struct mvs_phy *phy)
  1593. {
  1594. phy->phy_attached = 0;
  1595. phy->att_dev_info = 0;
  1596. phy->att_dev_sas_addr = 0;
  1597. }
  1598. static void mvs_work_queue(struct work_struct *work)
  1599. {
  1600. struct delayed_work *dw = container_of(work, struct delayed_work, work);
  1601. struct mvs_wq *mwq = container_of(dw, struct mvs_wq, work_q);
  1602. struct mvs_info *mvi = mwq->mvi;
  1603. unsigned long flags;
  1604. u32 phy_no = (unsigned long) mwq->data;
  1605. struct sas_ha_struct *sas_ha = mvi->sas;
  1606. struct mvs_phy *phy = &mvi->phy[phy_no];
  1607. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  1608. spin_lock_irqsave(&mvi->lock, flags);
  1609. if (mwq->handler & PHY_PLUG_EVENT) {
  1610. if (phy->phy_event & PHY_PLUG_OUT) {
  1611. u32 tmp;
  1612. struct sas_identify_frame *id;
  1613. id = (struct sas_identify_frame *)phy->frame_rcvd;
  1614. tmp = MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no);
  1615. phy->phy_event &= ~PHY_PLUG_OUT;
  1616. if (!(tmp & PHY_READY_MASK)) {
  1617. sas_phy_disconnected(sas_phy);
  1618. mvs_phy_disconnected(phy);
  1619. sas_ha->notify_phy_event(sas_phy,
  1620. PHYE_LOSS_OF_SIGNAL);
  1621. mv_dprintk("phy%d Removed Device\n", phy_no);
  1622. } else {
  1623. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1624. mvs_update_phyinfo(mvi, phy_no, 1);
  1625. mvs_bytes_dmaed(mvi, phy_no);
  1626. mvs_port_notify_formed(sas_phy, 0);
  1627. mv_dprintk("phy%d Attached Device\n", phy_no);
  1628. }
  1629. }
  1630. } else if (mwq->handler & EXP_BRCT_CHG) {
  1631. phy->phy_event &= ~EXP_BRCT_CHG;
  1632. sas_ha->notify_port_event(sas_phy,
  1633. PORTE_BROADCAST_RCVD);
  1634. mv_dprintk("phy%d Got Broadcast Change\n", phy_no);
  1635. }
  1636. list_del(&mwq->entry);
  1637. spin_unlock_irqrestore(&mvi->lock, flags);
  1638. kfree(mwq);
  1639. }
  1640. static int mvs_handle_event(struct mvs_info *mvi, void *data, int handler)
  1641. {
  1642. struct mvs_wq *mwq;
  1643. int ret = 0;
  1644. mwq = kmalloc(sizeof(struct mvs_wq), GFP_ATOMIC);
  1645. if (mwq) {
  1646. mwq->mvi = mvi;
  1647. mwq->data = data;
  1648. mwq->handler = handler;
  1649. MV_INIT_DELAYED_WORK(&mwq->work_q, mvs_work_queue, mwq);
  1650. list_add_tail(&mwq->entry, &mvi->wq_list);
  1651. schedule_delayed_work(&mwq->work_q, HZ * 2);
  1652. } else
  1653. ret = -ENOMEM;
  1654. return ret;
  1655. }
  1656. static void mvs_sig_time_out(unsigned long tphy)
  1657. {
  1658. struct mvs_phy *phy = (struct mvs_phy *)tphy;
  1659. struct mvs_info *mvi = phy->mvi;
  1660. u8 phy_no;
  1661. for (phy_no = 0; phy_no < mvi->chip->n_phy; phy_no++) {
  1662. if (&mvi->phy[phy_no] == phy) {
  1663. mv_dprintk("Get signature time out, reset phy %d\n",
  1664. phy_no+mvi->id*mvi->chip->n_phy);
  1665. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_HARD_RESET);
  1666. }
  1667. }
  1668. }
  1669. void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
  1670. {
  1671. u32 tmp;
  1672. struct mvs_phy *phy = &mvi->phy[phy_no];
  1673. phy->irq_status = MVS_CHIP_DISP->read_port_irq_stat(mvi, phy_no);
  1674. MVS_CHIP_DISP->write_port_irq_stat(mvi, phy_no, phy->irq_status);
  1675. mv_dprintk("phy %d ctrl sts=0x%08X.\n", phy_no+mvi->id*mvi->chip->n_phy,
  1676. MVS_CHIP_DISP->read_phy_ctl(mvi, phy_no));
  1677. mv_dprintk("phy %d irq sts = 0x%08X\n", phy_no+mvi->id*mvi->chip->n_phy,
  1678. phy->irq_status);
  1679. /*
  1680. * events is port event now ,
  1681. * we need check the interrupt status which belongs to per port.
  1682. */
  1683. if (phy->irq_status & PHYEV_DCDR_ERR) {
  1684. mv_dprintk("phy %d STP decoding error.\n",
  1685. phy_no + mvi->id*mvi->chip->n_phy);
  1686. }
  1687. if (phy->irq_status & PHYEV_POOF) {
  1688. mdelay(500);
  1689. if (!(phy->phy_event & PHY_PLUG_OUT)) {
  1690. int dev_sata = phy->phy_type & PORT_TYPE_SATA;
  1691. int ready;
  1692. mvs_do_release_task(mvi, phy_no, NULL);
  1693. phy->phy_event |= PHY_PLUG_OUT;
  1694. MVS_CHIP_DISP->clear_srs_irq(mvi, 0, 1);
  1695. mvs_handle_event(mvi,
  1696. (void *)(unsigned long)phy_no,
  1697. PHY_PLUG_EVENT);
  1698. ready = mvs_is_phy_ready(mvi, phy_no);
  1699. if (ready || dev_sata) {
  1700. if (MVS_CHIP_DISP->stp_reset)
  1701. MVS_CHIP_DISP->stp_reset(mvi,
  1702. phy_no);
  1703. else
  1704. MVS_CHIP_DISP->phy_reset(mvi,
  1705. phy_no, MVS_SOFT_RESET);
  1706. return;
  1707. }
  1708. }
  1709. }
  1710. if (phy->irq_status & PHYEV_COMWAKE) {
  1711. tmp = MVS_CHIP_DISP->read_port_irq_mask(mvi, phy_no);
  1712. MVS_CHIP_DISP->write_port_irq_mask(mvi, phy_no,
  1713. tmp | PHYEV_SIG_FIS);
  1714. if (phy->timer.function == NULL) {
  1715. phy->timer.data = (unsigned long)phy;
  1716. phy->timer.function = mvs_sig_time_out;
  1717. phy->timer.expires = jiffies + 5*HZ;
  1718. add_timer(&phy->timer);
  1719. }
  1720. }
  1721. if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
  1722. phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
  1723. mv_dprintk("notify plug in on phy[%d]\n", phy_no);
  1724. if (phy->phy_status) {
  1725. mdelay(10);
  1726. MVS_CHIP_DISP->detect_porttype(mvi, phy_no);
  1727. if (phy->phy_type & PORT_TYPE_SATA) {
  1728. tmp = MVS_CHIP_DISP->read_port_irq_mask(
  1729. mvi, phy_no);
  1730. tmp &= ~PHYEV_SIG_FIS;
  1731. MVS_CHIP_DISP->write_port_irq_mask(mvi,
  1732. phy_no, tmp);
  1733. }
  1734. mvs_update_phyinfo(mvi, phy_no, 0);
  1735. if (phy->phy_type & PORT_TYPE_SAS) {
  1736. MVS_CHIP_DISP->phy_reset(mvi, phy_no, MVS_PHY_TUNE);
  1737. mdelay(10);
  1738. }
  1739. mvs_bytes_dmaed(mvi, phy_no);
  1740. /* whether driver is going to handle hot plug */
  1741. if (phy->phy_event & PHY_PLUG_OUT) {
  1742. mvs_port_notify_formed(&phy->sas_phy, 0);
  1743. phy->phy_event &= ~PHY_PLUG_OUT;
  1744. }
  1745. } else {
  1746. mv_dprintk("plugin interrupt but phy%d is gone\n",
  1747. phy_no + mvi->id*mvi->chip->n_phy);
  1748. }
  1749. } else if (phy->irq_status & PHYEV_BROAD_CH) {
  1750. mv_dprintk("phy %d broadcast change.\n",
  1751. phy_no + mvi->id*mvi->chip->n_phy);
  1752. mvs_handle_event(mvi, (void *)(unsigned long)phy_no,
  1753. EXP_BRCT_CHG);
  1754. }
  1755. }
  1756. int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
  1757. {
  1758. u32 rx_prod_idx, rx_desc;
  1759. bool attn = false;
  1760. /* the first dword in the RX ring is special: it contains
  1761. * a mirror of the hardware's RX producer index, so that
  1762. * we don't have to stall the CPU reading that register.
  1763. * The actual RX ring is offset by one dword, due to this.
  1764. */
  1765. rx_prod_idx = mvi->rx_cons;
  1766. mvi->rx_cons = le32_to_cpu(mvi->rx[0]);
  1767. if (mvi->rx_cons == 0xfff) /* h/w hasn't touched RX ring yet */
  1768. return 0;
  1769. /* The CMPL_Q may come late, read from register and try again
  1770. * note: if coalescing is enabled,
  1771. * it will need to read from register every time for sure
  1772. */
  1773. if (unlikely(mvi->rx_cons == rx_prod_idx))
  1774. mvi->rx_cons = MVS_CHIP_DISP->rx_update(mvi) & RX_RING_SZ_MASK;
  1775. if (mvi->rx_cons == rx_prod_idx)
  1776. return 0;
  1777. while (mvi->rx_cons != rx_prod_idx) {
  1778. /* increment our internal RX consumer pointer */
  1779. rx_prod_idx = (rx_prod_idx + 1) & (MVS_RX_RING_SZ - 1);
  1780. rx_desc = le32_to_cpu(mvi->rx[rx_prod_idx + 1]);
  1781. if (likely(rx_desc & RXQ_DONE))
  1782. mvs_slot_complete(mvi, rx_desc, 0);
  1783. if (rx_desc & RXQ_ATTN) {
  1784. attn = true;
  1785. } else if (rx_desc & RXQ_ERR) {
  1786. if (!(rx_desc & RXQ_DONE))
  1787. mvs_slot_complete(mvi, rx_desc, 0);
  1788. } else if (rx_desc & RXQ_SLOT_RESET) {
  1789. mvs_slot_free(mvi, rx_desc);
  1790. }
  1791. }
  1792. if (attn && self_clear)
  1793. MVS_CHIP_DISP->int_full(mvi);
  1794. return 0;
  1795. }