qla_isr.c 86 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/slab.h>
  11. #include <scsi/scsi_tcq.h>
  12. #include <scsi/scsi_bsg_fc.h>
  13. #include <scsi/scsi_eh.h>
  14. static void qla2x00_mbx_completion(scsi_qla_host_t *, uint16_t);
  15. static void qla2x00_status_entry(scsi_qla_host_t *, struct rsp_que *, void *);
  16. static void qla2x00_status_cont_entry(struct rsp_que *, sts_cont_entry_t *);
  17. static void qla2x00_error_entry(scsi_qla_host_t *, struct rsp_que *,
  18. sts_entry_t *);
  19. /**
  20. * qla2100_intr_handler() - Process interrupts for the ISP2100 and ISP2200.
  21. * @irq:
  22. * @dev_id: SCSI driver HA context
  23. *
  24. * Called by system whenever the host adapter generates an interrupt.
  25. *
  26. * Returns handled flag.
  27. */
  28. irqreturn_t
  29. qla2100_intr_handler(int irq, void *dev_id)
  30. {
  31. scsi_qla_host_t *vha;
  32. struct qla_hw_data *ha;
  33. struct device_reg_2xxx __iomem *reg;
  34. int status;
  35. unsigned long iter;
  36. uint16_t hccr;
  37. uint16_t mb[4];
  38. struct rsp_que *rsp;
  39. unsigned long flags;
  40. rsp = (struct rsp_que *) dev_id;
  41. if (!rsp) {
  42. ql_log(ql_log_info, NULL, 0x505d,
  43. "%s: NULL response queue pointer.\n", __func__);
  44. return (IRQ_NONE);
  45. }
  46. ha = rsp->hw;
  47. reg = &ha->iobase->isp;
  48. status = 0;
  49. spin_lock_irqsave(&ha->hardware_lock, flags);
  50. vha = pci_get_drvdata(ha->pdev);
  51. for (iter = 50; iter--; ) {
  52. hccr = RD_REG_WORD(&reg->hccr);
  53. if (qla2x00_check_reg16_for_disconnect(vha, hccr))
  54. break;
  55. if (hccr & HCCR_RISC_PAUSE) {
  56. if (pci_channel_offline(ha->pdev))
  57. break;
  58. /*
  59. * Issue a "HARD" reset in order for the RISC interrupt
  60. * bit to be cleared. Schedule a big hammer to get
  61. * out of the RISC PAUSED state.
  62. */
  63. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  64. RD_REG_WORD(&reg->hccr);
  65. ha->isp_ops->fw_dump(vha, 1);
  66. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  67. break;
  68. } else if ((RD_REG_WORD(&reg->istatus) & ISR_RISC_INT) == 0)
  69. break;
  70. if (RD_REG_WORD(&reg->semaphore) & BIT_0) {
  71. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  72. RD_REG_WORD(&reg->hccr);
  73. /* Get mailbox data. */
  74. mb[0] = RD_MAILBOX_REG(ha, reg, 0);
  75. if (mb[0] > 0x3fff && mb[0] < 0x8000) {
  76. qla2x00_mbx_completion(vha, mb[0]);
  77. status |= MBX_INTERRUPT;
  78. } else if (mb[0] > 0x7fff && mb[0] < 0xc000) {
  79. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  80. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  81. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  82. qla2x00_async_event(vha, rsp, mb);
  83. } else {
  84. /*EMPTY*/
  85. ql_dbg(ql_dbg_async, vha, 0x5025,
  86. "Unrecognized interrupt type (%d).\n",
  87. mb[0]);
  88. }
  89. /* Release mailbox registers. */
  90. WRT_REG_WORD(&reg->semaphore, 0);
  91. RD_REG_WORD(&reg->semaphore);
  92. } else {
  93. qla2x00_process_response_queue(rsp);
  94. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  95. RD_REG_WORD(&reg->hccr);
  96. }
  97. }
  98. qla2x00_handle_mbx_completion(ha, status);
  99. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  100. return (IRQ_HANDLED);
  101. }
  102. bool
  103. qla2x00_check_reg32_for_disconnect(scsi_qla_host_t *vha, uint32_t reg)
  104. {
  105. /* Check for PCI disconnection */
  106. if (reg == 0xffffffff && !pci_channel_offline(vha->hw->pdev)) {
  107. if (!test_and_set_bit(PFLG_DISCONNECTED, &vha->pci_flags) &&
  108. !test_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags) &&
  109. !test_bit(PFLG_DRIVER_PROBING, &vha->pci_flags)) {
  110. /*
  111. * Schedule this (only once) on the default system
  112. * workqueue so that all the adapter workqueues and the
  113. * DPC thread can be shutdown cleanly.
  114. */
  115. schedule_work(&vha->hw->board_disable);
  116. }
  117. return true;
  118. } else
  119. return false;
  120. }
  121. bool
  122. qla2x00_check_reg16_for_disconnect(scsi_qla_host_t *vha, uint16_t reg)
  123. {
  124. return qla2x00_check_reg32_for_disconnect(vha, 0xffff0000 | reg);
  125. }
  126. /**
  127. * qla2300_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
  128. * @irq:
  129. * @dev_id: SCSI driver HA context
  130. *
  131. * Called by system whenever the host adapter generates an interrupt.
  132. *
  133. * Returns handled flag.
  134. */
  135. irqreturn_t
  136. qla2300_intr_handler(int irq, void *dev_id)
  137. {
  138. scsi_qla_host_t *vha;
  139. struct device_reg_2xxx __iomem *reg;
  140. int status;
  141. unsigned long iter;
  142. uint32_t stat;
  143. uint16_t hccr;
  144. uint16_t mb[4];
  145. struct rsp_que *rsp;
  146. struct qla_hw_data *ha;
  147. unsigned long flags;
  148. rsp = (struct rsp_que *) dev_id;
  149. if (!rsp) {
  150. ql_log(ql_log_info, NULL, 0x5058,
  151. "%s: NULL response queue pointer.\n", __func__);
  152. return (IRQ_NONE);
  153. }
  154. ha = rsp->hw;
  155. reg = &ha->iobase->isp;
  156. status = 0;
  157. spin_lock_irqsave(&ha->hardware_lock, flags);
  158. vha = pci_get_drvdata(ha->pdev);
  159. for (iter = 50; iter--; ) {
  160. stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
  161. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  162. break;
  163. if (stat & HSR_RISC_PAUSED) {
  164. if (unlikely(pci_channel_offline(ha->pdev)))
  165. break;
  166. hccr = RD_REG_WORD(&reg->hccr);
  167. if (hccr & (BIT_15 | BIT_13 | BIT_11 | BIT_8))
  168. ql_log(ql_log_warn, vha, 0x5026,
  169. "Parity error -- HCCR=%x, Dumping "
  170. "firmware.\n", hccr);
  171. else
  172. ql_log(ql_log_warn, vha, 0x5027,
  173. "RISC paused -- HCCR=%x, Dumping "
  174. "firmware.\n", hccr);
  175. /*
  176. * Issue a "HARD" reset in order for the RISC
  177. * interrupt bit to be cleared. Schedule a big
  178. * hammer to get out of the RISC PAUSED state.
  179. */
  180. WRT_REG_WORD(&reg->hccr, HCCR_RESET_RISC);
  181. RD_REG_WORD(&reg->hccr);
  182. ha->isp_ops->fw_dump(vha, 1);
  183. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  184. break;
  185. } else if ((stat & HSR_RISC_INT) == 0)
  186. break;
  187. switch (stat & 0xff) {
  188. case 0x1:
  189. case 0x2:
  190. case 0x10:
  191. case 0x11:
  192. qla2x00_mbx_completion(vha, MSW(stat));
  193. status |= MBX_INTERRUPT;
  194. /* Release mailbox registers. */
  195. WRT_REG_WORD(&reg->semaphore, 0);
  196. break;
  197. case 0x12:
  198. mb[0] = MSW(stat);
  199. mb[1] = RD_MAILBOX_REG(ha, reg, 1);
  200. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  201. mb[3] = RD_MAILBOX_REG(ha, reg, 3);
  202. qla2x00_async_event(vha, rsp, mb);
  203. break;
  204. case 0x13:
  205. qla2x00_process_response_queue(rsp);
  206. break;
  207. case 0x15:
  208. mb[0] = MBA_CMPLT_1_16BIT;
  209. mb[1] = MSW(stat);
  210. qla2x00_async_event(vha, rsp, mb);
  211. break;
  212. case 0x16:
  213. mb[0] = MBA_SCSI_COMPLETION;
  214. mb[1] = MSW(stat);
  215. mb[2] = RD_MAILBOX_REG(ha, reg, 2);
  216. qla2x00_async_event(vha, rsp, mb);
  217. break;
  218. default:
  219. ql_dbg(ql_dbg_async, vha, 0x5028,
  220. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  221. break;
  222. }
  223. WRT_REG_WORD(&reg->hccr, HCCR_CLR_RISC_INT);
  224. RD_REG_WORD_RELAXED(&reg->hccr);
  225. }
  226. qla2x00_handle_mbx_completion(ha, status);
  227. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  228. return (IRQ_HANDLED);
  229. }
  230. /**
  231. * qla2x00_mbx_completion() - Process mailbox command completions.
  232. * @ha: SCSI driver HA context
  233. * @mb0: Mailbox0 register
  234. */
  235. static void
  236. qla2x00_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  237. {
  238. uint16_t cnt;
  239. uint32_t mboxes;
  240. uint16_t __iomem *wptr;
  241. struct qla_hw_data *ha = vha->hw;
  242. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  243. /* Read all mbox registers? */
  244. WARN_ON_ONCE(ha->mbx_count > 32);
  245. mboxes = (1ULL << ha->mbx_count) - 1;
  246. if (!ha->mcp)
  247. ql_dbg(ql_dbg_async, vha, 0x5001, "MBX pointer ERROR.\n");
  248. else
  249. mboxes = ha->mcp->in_mb;
  250. /* Load return mailbox registers. */
  251. ha->flags.mbox_int = 1;
  252. ha->mailbox_out[0] = mb0;
  253. mboxes >>= 1;
  254. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1);
  255. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  256. if (IS_QLA2200(ha) && cnt == 8)
  257. wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8);
  258. if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0))
  259. ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr);
  260. else if (mboxes & BIT_0)
  261. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  262. wptr++;
  263. mboxes >>= 1;
  264. }
  265. }
  266. static void
  267. qla81xx_idc_event(scsi_qla_host_t *vha, uint16_t aen, uint16_t descr)
  268. {
  269. static char *event[] =
  270. { "Complete", "Request Notification", "Time Extension" };
  271. int rval;
  272. struct device_reg_24xx __iomem *reg24 = &vha->hw->iobase->isp24;
  273. struct device_reg_82xx __iomem *reg82 = &vha->hw->iobase->isp82;
  274. uint16_t __iomem *wptr;
  275. uint16_t cnt, timeout, mb[QLA_IDC_ACK_REGS];
  276. /* Seed data -- mailbox1 -> mailbox7. */
  277. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw))
  278. wptr = (uint16_t __iomem *)&reg24->mailbox1;
  279. else if (IS_QLA8044(vha->hw))
  280. wptr = (uint16_t __iomem *)&reg82->mailbox_out[1];
  281. else
  282. return;
  283. for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++)
  284. mb[cnt] = RD_REG_WORD(wptr);
  285. ql_dbg(ql_dbg_async, vha, 0x5021,
  286. "Inter-Driver Communication %s -- "
  287. "%04x %04x %04x %04x %04x %04x %04x.\n",
  288. event[aen & 0xff], mb[0], mb[1], mb[2], mb[3],
  289. mb[4], mb[5], mb[6]);
  290. switch (aen) {
  291. /* Handle IDC Error completion case. */
  292. case MBA_IDC_COMPLETE:
  293. if (mb[1] >> 15) {
  294. vha->hw->flags.idc_compl_status = 1;
  295. if (vha->hw->notify_dcbx_comp && !vha->vp_idx)
  296. complete(&vha->hw->dcbx_comp);
  297. }
  298. break;
  299. case MBA_IDC_NOTIFY:
  300. /* Acknowledgement needed? [Notify && non-zero timeout]. */
  301. timeout = (descr >> 8) & 0xf;
  302. ql_dbg(ql_dbg_async, vha, 0x5022,
  303. "%lu Inter-Driver Communication %s -- ACK timeout=%d.\n",
  304. vha->host_no, event[aen & 0xff], timeout);
  305. if (!timeout)
  306. return;
  307. rval = qla2x00_post_idc_ack_work(vha, mb);
  308. if (rval != QLA_SUCCESS)
  309. ql_log(ql_log_warn, vha, 0x5023,
  310. "IDC failed to post ACK.\n");
  311. break;
  312. case MBA_IDC_TIME_EXT:
  313. vha->hw->idc_extend_tmo = descr;
  314. ql_dbg(ql_dbg_async, vha, 0x5087,
  315. "%lu Inter-Driver Communication %s -- "
  316. "Extend timeout by=%d.\n",
  317. vha->host_no, event[aen & 0xff], vha->hw->idc_extend_tmo);
  318. break;
  319. }
  320. }
  321. #define LS_UNKNOWN 2
  322. const char *
  323. qla2x00_get_link_speed_str(struct qla_hw_data *ha, uint16_t speed)
  324. {
  325. static const char *const link_speeds[] = {
  326. "1", "2", "?", "4", "8", "16", "32", "10"
  327. };
  328. #define QLA_LAST_SPEED 7
  329. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  330. return link_speeds[0];
  331. else if (speed == 0x13)
  332. return link_speeds[QLA_LAST_SPEED];
  333. else if (speed < QLA_LAST_SPEED)
  334. return link_speeds[speed];
  335. else
  336. return link_speeds[LS_UNKNOWN];
  337. }
  338. static void
  339. qla83xx_handle_8200_aen(scsi_qla_host_t *vha, uint16_t *mb)
  340. {
  341. struct qla_hw_data *ha = vha->hw;
  342. /*
  343. * 8200 AEN Interpretation:
  344. * mb[0] = AEN code
  345. * mb[1] = AEN Reason code
  346. * mb[2] = LSW of Peg-Halt Status-1 Register
  347. * mb[6] = MSW of Peg-Halt Status-1 Register
  348. * mb[3] = LSW of Peg-Halt Status-2 register
  349. * mb[7] = MSW of Peg-Halt Status-2 register
  350. * mb[4] = IDC Device-State Register value
  351. * mb[5] = IDC Driver-Presence Register value
  352. */
  353. ql_dbg(ql_dbg_async, vha, 0x506b, "AEN Code: mb[0] = 0x%x AEN reason: "
  354. "mb[1] = 0x%x PH-status1: mb[2] = 0x%x PH-status1: mb[6] = 0x%x.\n",
  355. mb[0], mb[1], mb[2], mb[6]);
  356. ql_dbg(ql_dbg_async, vha, 0x506c, "PH-status2: mb[3] = 0x%x "
  357. "PH-status2: mb[7] = 0x%x Device-State: mb[4] = 0x%x "
  358. "Drv-Presence: mb[5] = 0x%x.\n", mb[3], mb[7], mb[4], mb[5]);
  359. if (mb[1] & (IDC_PEG_HALT_STATUS_CHANGE | IDC_NIC_FW_REPORTED_FAILURE |
  360. IDC_HEARTBEAT_FAILURE)) {
  361. ha->flags.nic_core_hung = 1;
  362. ql_log(ql_log_warn, vha, 0x5060,
  363. "83XX: F/W Error Reported: Check if reset required.\n");
  364. if (mb[1] & IDC_PEG_HALT_STATUS_CHANGE) {
  365. uint32_t protocol_engine_id, fw_err_code, err_level;
  366. /*
  367. * IDC_PEG_HALT_STATUS_CHANGE interpretation:
  368. * - PEG-Halt Status-1 Register:
  369. * (LSW = mb[2], MSW = mb[6])
  370. * Bits 0-7 = protocol-engine ID
  371. * Bits 8-28 = f/w error code
  372. * Bits 29-31 = Error-level
  373. * Error-level 0x1 = Non-Fatal error
  374. * Error-level 0x2 = Recoverable Fatal error
  375. * Error-level 0x4 = UnRecoverable Fatal error
  376. * - PEG-Halt Status-2 Register:
  377. * (LSW = mb[3], MSW = mb[7])
  378. */
  379. protocol_engine_id = (mb[2] & 0xff);
  380. fw_err_code = (((mb[2] & 0xff00) >> 8) |
  381. ((mb[6] & 0x1fff) << 8));
  382. err_level = ((mb[6] & 0xe000) >> 13);
  383. ql_log(ql_log_warn, vha, 0x5061, "PegHalt Status-1 "
  384. "Register: protocol_engine_id=0x%x "
  385. "fw_err_code=0x%x err_level=0x%x.\n",
  386. protocol_engine_id, fw_err_code, err_level);
  387. ql_log(ql_log_warn, vha, 0x5062, "PegHalt Status-2 "
  388. "Register: 0x%x%x.\n", mb[7], mb[3]);
  389. if (err_level == ERR_LEVEL_NON_FATAL) {
  390. ql_log(ql_log_warn, vha, 0x5063,
  391. "Not a fatal error, f/w has recovered "
  392. "iteself.\n");
  393. } else if (err_level == ERR_LEVEL_RECOVERABLE_FATAL) {
  394. ql_log(ql_log_fatal, vha, 0x5064,
  395. "Recoverable Fatal error: Chip reset "
  396. "required.\n");
  397. qla83xx_schedule_work(vha,
  398. QLA83XX_NIC_CORE_RESET);
  399. } else if (err_level == ERR_LEVEL_UNRECOVERABLE_FATAL) {
  400. ql_log(ql_log_fatal, vha, 0x5065,
  401. "Unrecoverable Fatal error: Set FAILED "
  402. "state, reboot required.\n");
  403. qla83xx_schedule_work(vha,
  404. QLA83XX_NIC_CORE_UNRECOVERABLE);
  405. }
  406. }
  407. if (mb[1] & IDC_NIC_FW_REPORTED_FAILURE) {
  408. uint16_t peg_fw_state, nw_interface_link_up;
  409. uint16_t nw_interface_signal_detect, sfp_status;
  410. uint16_t htbt_counter, htbt_monitor_enable;
  411. uint16_t sfp_additonal_info, sfp_multirate;
  412. uint16_t sfp_tx_fault, link_speed, dcbx_status;
  413. /*
  414. * IDC_NIC_FW_REPORTED_FAILURE interpretation:
  415. * - PEG-to-FC Status Register:
  416. * (LSW = mb[2], MSW = mb[6])
  417. * Bits 0-7 = Peg-Firmware state
  418. * Bit 8 = N/W Interface Link-up
  419. * Bit 9 = N/W Interface signal detected
  420. * Bits 10-11 = SFP Status
  421. * SFP Status 0x0 = SFP+ transceiver not expected
  422. * SFP Status 0x1 = SFP+ transceiver not present
  423. * SFP Status 0x2 = SFP+ transceiver invalid
  424. * SFP Status 0x3 = SFP+ transceiver present and
  425. * valid
  426. * Bits 12-14 = Heartbeat Counter
  427. * Bit 15 = Heartbeat Monitor Enable
  428. * Bits 16-17 = SFP Additional Info
  429. * SFP info 0x0 = Unregocnized transceiver for
  430. * Ethernet
  431. * SFP info 0x1 = SFP+ brand validation failed
  432. * SFP info 0x2 = SFP+ speed validation failed
  433. * SFP info 0x3 = SFP+ access error
  434. * Bit 18 = SFP Multirate
  435. * Bit 19 = SFP Tx Fault
  436. * Bits 20-22 = Link Speed
  437. * Bits 23-27 = Reserved
  438. * Bits 28-30 = DCBX Status
  439. * DCBX Status 0x0 = DCBX Disabled
  440. * DCBX Status 0x1 = DCBX Enabled
  441. * DCBX Status 0x2 = DCBX Exchange error
  442. * Bit 31 = Reserved
  443. */
  444. peg_fw_state = (mb[2] & 0x00ff);
  445. nw_interface_link_up = ((mb[2] & 0x0100) >> 8);
  446. nw_interface_signal_detect = ((mb[2] & 0x0200) >> 9);
  447. sfp_status = ((mb[2] & 0x0c00) >> 10);
  448. htbt_counter = ((mb[2] & 0x7000) >> 12);
  449. htbt_monitor_enable = ((mb[2] & 0x8000) >> 15);
  450. sfp_additonal_info = (mb[6] & 0x0003);
  451. sfp_multirate = ((mb[6] & 0x0004) >> 2);
  452. sfp_tx_fault = ((mb[6] & 0x0008) >> 3);
  453. link_speed = ((mb[6] & 0x0070) >> 4);
  454. dcbx_status = ((mb[6] & 0x7000) >> 12);
  455. ql_log(ql_log_warn, vha, 0x5066,
  456. "Peg-to-Fc Status Register:\n"
  457. "peg_fw_state=0x%x, nw_interface_link_up=0x%x, "
  458. "nw_interface_signal_detect=0x%x"
  459. "\nsfp_statis=0x%x.\n ", peg_fw_state,
  460. nw_interface_link_up, nw_interface_signal_detect,
  461. sfp_status);
  462. ql_log(ql_log_warn, vha, 0x5067,
  463. "htbt_counter=0x%x, htbt_monitor_enable=0x%x, "
  464. "sfp_additonal_info=0x%x, sfp_multirate=0x%x.\n ",
  465. htbt_counter, htbt_monitor_enable,
  466. sfp_additonal_info, sfp_multirate);
  467. ql_log(ql_log_warn, vha, 0x5068,
  468. "sfp_tx_fault=0x%x, link_state=0x%x, "
  469. "dcbx_status=0x%x.\n", sfp_tx_fault, link_speed,
  470. dcbx_status);
  471. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  472. }
  473. if (mb[1] & IDC_HEARTBEAT_FAILURE) {
  474. ql_log(ql_log_warn, vha, 0x5069,
  475. "Heartbeat Failure encountered, chip reset "
  476. "required.\n");
  477. qla83xx_schedule_work(vha, QLA83XX_NIC_CORE_RESET);
  478. }
  479. }
  480. if (mb[1] & IDC_DEVICE_STATE_CHANGE) {
  481. ql_log(ql_log_info, vha, 0x506a,
  482. "IDC Device-State changed = 0x%x.\n", mb[4]);
  483. if (ha->flags.nic_core_reset_owner)
  484. return;
  485. qla83xx_schedule_work(vha, MBA_IDC_AEN);
  486. }
  487. }
  488. int
  489. qla2x00_is_a_vp_did(scsi_qla_host_t *vha, uint32_t rscn_entry)
  490. {
  491. struct qla_hw_data *ha = vha->hw;
  492. scsi_qla_host_t *vp;
  493. uint32_t vp_did;
  494. unsigned long flags;
  495. int ret = 0;
  496. if (!ha->num_vhosts)
  497. return ret;
  498. spin_lock_irqsave(&ha->vport_slock, flags);
  499. list_for_each_entry(vp, &ha->vp_list, list) {
  500. vp_did = vp->d_id.b24;
  501. if (vp_did == rscn_entry) {
  502. ret = 1;
  503. break;
  504. }
  505. }
  506. spin_unlock_irqrestore(&ha->vport_slock, flags);
  507. return ret;
  508. }
  509. static inline fc_port_t *
  510. qla2x00_find_fcport_by_loopid(scsi_qla_host_t *vha, uint16_t loop_id)
  511. {
  512. fc_port_t *fcport;
  513. list_for_each_entry(fcport, &vha->vp_fcports, list)
  514. if (fcport->loop_id == loop_id)
  515. return fcport;
  516. return NULL;
  517. }
  518. /**
  519. * qla2x00_async_event() - Process aynchronous events.
  520. * @ha: SCSI driver HA context
  521. * @mb: Mailbox registers (0 - 3)
  522. */
  523. void
  524. qla2x00_async_event(scsi_qla_host_t *vha, struct rsp_que *rsp, uint16_t *mb)
  525. {
  526. uint16_t handle_cnt;
  527. uint16_t cnt, mbx;
  528. uint32_t handles[5];
  529. struct qla_hw_data *ha = vha->hw;
  530. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  531. struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
  532. struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
  533. uint32_t rscn_entry, host_pid;
  534. unsigned long flags;
  535. fc_port_t *fcport = NULL;
  536. /* Setup to process RIO completion. */
  537. handle_cnt = 0;
  538. if (IS_CNA_CAPABLE(ha))
  539. goto skip_rio;
  540. switch (mb[0]) {
  541. case MBA_SCSI_COMPLETION:
  542. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  543. handle_cnt = 1;
  544. break;
  545. case MBA_CMPLT_1_16BIT:
  546. handles[0] = mb[1];
  547. handle_cnt = 1;
  548. mb[0] = MBA_SCSI_COMPLETION;
  549. break;
  550. case MBA_CMPLT_2_16BIT:
  551. handles[0] = mb[1];
  552. handles[1] = mb[2];
  553. handle_cnt = 2;
  554. mb[0] = MBA_SCSI_COMPLETION;
  555. break;
  556. case MBA_CMPLT_3_16BIT:
  557. handles[0] = mb[1];
  558. handles[1] = mb[2];
  559. handles[2] = mb[3];
  560. handle_cnt = 3;
  561. mb[0] = MBA_SCSI_COMPLETION;
  562. break;
  563. case MBA_CMPLT_4_16BIT:
  564. handles[0] = mb[1];
  565. handles[1] = mb[2];
  566. handles[2] = mb[3];
  567. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  568. handle_cnt = 4;
  569. mb[0] = MBA_SCSI_COMPLETION;
  570. break;
  571. case MBA_CMPLT_5_16BIT:
  572. handles[0] = mb[1];
  573. handles[1] = mb[2];
  574. handles[2] = mb[3];
  575. handles[3] = (uint32_t)RD_MAILBOX_REG(ha, reg, 6);
  576. handles[4] = (uint32_t)RD_MAILBOX_REG(ha, reg, 7);
  577. handle_cnt = 5;
  578. mb[0] = MBA_SCSI_COMPLETION;
  579. break;
  580. case MBA_CMPLT_2_32BIT:
  581. handles[0] = le32_to_cpu((uint32_t)((mb[2] << 16) | mb[1]));
  582. handles[1] = le32_to_cpu(
  583. ((uint32_t)(RD_MAILBOX_REG(ha, reg, 7) << 16)) |
  584. RD_MAILBOX_REG(ha, reg, 6));
  585. handle_cnt = 2;
  586. mb[0] = MBA_SCSI_COMPLETION;
  587. break;
  588. default:
  589. break;
  590. }
  591. skip_rio:
  592. switch (mb[0]) {
  593. case MBA_SCSI_COMPLETION: /* Fast Post */
  594. if (!vha->flags.online)
  595. break;
  596. for (cnt = 0; cnt < handle_cnt; cnt++)
  597. qla2x00_process_completed_request(vha, rsp->req,
  598. handles[cnt]);
  599. break;
  600. case MBA_RESET: /* Reset */
  601. ql_dbg(ql_dbg_async, vha, 0x5002,
  602. "Asynchronous RESET.\n");
  603. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  604. break;
  605. case MBA_SYSTEM_ERR: /* System Error */
  606. mbx = (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha)) ?
  607. RD_REG_WORD(&reg24->mailbox7) : 0;
  608. ql_log(ql_log_warn, vha, 0x5003,
  609. "ISP System Error - mbx1=%xh mbx2=%xh mbx3=%xh "
  610. "mbx7=%xh.\n", mb[1], mb[2], mb[3], mbx);
  611. ha->isp_ops->fw_dump(vha, 1);
  612. if (IS_FWI2_CAPABLE(ha)) {
  613. if (mb[1] == 0 && mb[2] == 0) {
  614. ql_log(ql_log_fatal, vha, 0x5004,
  615. "Unrecoverable Hardware Error: adapter "
  616. "marked OFFLINE!\n");
  617. vha->flags.online = 0;
  618. vha->device_flags |= DFLG_DEV_FAILED;
  619. } else {
  620. /* Check to see if MPI timeout occurred */
  621. if ((mbx & MBX_3) && (ha->port_no == 0))
  622. set_bit(MPI_RESET_NEEDED,
  623. &vha->dpc_flags);
  624. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  625. }
  626. } else if (mb[1] == 0) {
  627. ql_log(ql_log_fatal, vha, 0x5005,
  628. "Unrecoverable Hardware Error: adapter marked "
  629. "OFFLINE!\n");
  630. vha->flags.online = 0;
  631. vha->device_flags |= DFLG_DEV_FAILED;
  632. } else
  633. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  634. break;
  635. case MBA_REQ_TRANSFER_ERR: /* Request Transfer Error */
  636. ql_log(ql_log_warn, vha, 0x5006,
  637. "ISP Request Transfer Error (%x).\n", mb[1]);
  638. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  639. break;
  640. case MBA_RSP_TRANSFER_ERR: /* Response Transfer Error */
  641. ql_log(ql_log_warn, vha, 0x5007,
  642. "ISP Response Transfer Error.\n");
  643. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  644. break;
  645. case MBA_WAKEUP_THRES: /* Request Queue Wake-up */
  646. ql_dbg(ql_dbg_async, vha, 0x5008,
  647. "Asynchronous WAKEUP_THRES.\n");
  648. break;
  649. case MBA_LIP_OCCURRED: /* Loop Initialization Procedure */
  650. ql_dbg(ql_dbg_async, vha, 0x5009,
  651. "LIP occurred (%x).\n", mb[1]);
  652. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  653. atomic_set(&vha->loop_state, LOOP_DOWN);
  654. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  655. qla2x00_mark_all_devices_lost(vha, 1);
  656. }
  657. if (vha->vp_idx) {
  658. atomic_set(&vha->vp_state, VP_FAILED);
  659. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  660. }
  661. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  662. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  663. vha->flags.management_server_logged_in = 0;
  664. qla2x00_post_aen_work(vha, FCH_EVT_LIP, mb[1]);
  665. break;
  666. case MBA_LOOP_UP: /* Loop Up Event */
  667. if (IS_QLA2100(ha) || IS_QLA2200(ha))
  668. ha->link_data_rate = PORT_SPEED_1GB;
  669. else
  670. ha->link_data_rate = mb[1];
  671. ql_log(ql_log_info, vha, 0x500a,
  672. "LOOP UP detected (%s Gbps).\n",
  673. qla2x00_get_link_speed_str(ha, ha->link_data_rate));
  674. vha->flags.management_server_logged_in = 0;
  675. qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, ha->link_data_rate);
  676. break;
  677. case MBA_LOOP_DOWN: /* Loop Down Event */
  678. mbx = (IS_QLA81XX(ha) || IS_QLA8031(ha))
  679. ? RD_REG_WORD(&reg24->mailbox4) : 0;
  680. mbx = (IS_P3P_TYPE(ha)) ? RD_REG_WORD(&reg82->mailbox_out[4])
  681. : mbx;
  682. ql_log(ql_log_info, vha, 0x500b,
  683. "LOOP DOWN detected (%x %x %x %x).\n",
  684. mb[1], mb[2], mb[3], mbx);
  685. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  686. atomic_set(&vha->loop_state, LOOP_DOWN);
  687. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  688. /*
  689. * In case of loop down, restore WWPN from
  690. * NVRAM in case of FA-WWPN capable ISP
  691. * Restore for Physical Port only
  692. */
  693. if (!vha->vp_idx) {
  694. if (ha->flags.fawwpn_enabled) {
  695. void *wwpn = ha->init_cb->port_name;
  696. memcpy(vha->port_name, wwpn, WWN_SIZE);
  697. fc_host_port_name(vha->host) =
  698. wwn_to_u64(vha->port_name);
  699. ql_dbg(ql_dbg_init + ql_dbg_verbose,
  700. vha, 0x0144, "LOOP DOWN detected,"
  701. "restore WWPN %016llx\n",
  702. wwn_to_u64(vha->port_name));
  703. }
  704. clear_bit(VP_CONFIG_OK, &vha->vp_flags);
  705. }
  706. vha->device_flags |= DFLG_NO_CABLE;
  707. qla2x00_mark_all_devices_lost(vha, 1);
  708. }
  709. if (vha->vp_idx) {
  710. atomic_set(&vha->vp_state, VP_FAILED);
  711. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  712. }
  713. vha->flags.management_server_logged_in = 0;
  714. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  715. qla2x00_post_aen_work(vha, FCH_EVT_LINKDOWN, 0);
  716. break;
  717. case MBA_LIP_RESET: /* LIP reset occurred */
  718. ql_dbg(ql_dbg_async, vha, 0x500c,
  719. "LIP reset occurred (%x).\n", mb[1]);
  720. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  721. atomic_set(&vha->loop_state, LOOP_DOWN);
  722. atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
  723. qla2x00_mark_all_devices_lost(vha, 1);
  724. }
  725. if (vha->vp_idx) {
  726. atomic_set(&vha->vp_state, VP_FAILED);
  727. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  728. }
  729. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  730. ha->operating_mode = LOOP;
  731. vha->flags.management_server_logged_in = 0;
  732. qla2x00_post_aen_work(vha, FCH_EVT_LIPRESET, mb[1]);
  733. break;
  734. /* case MBA_DCBX_COMPLETE: */
  735. case MBA_POINT_TO_POINT: /* Point-to-Point */
  736. if (IS_QLA2100(ha))
  737. break;
  738. if (IS_CNA_CAPABLE(ha)) {
  739. ql_dbg(ql_dbg_async, vha, 0x500d,
  740. "DCBX Completed -- %04x %04x %04x.\n",
  741. mb[1], mb[2], mb[3]);
  742. if (ha->notify_dcbx_comp && !vha->vp_idx)
  743. complete(&ha->dcbx_comp);
  744. } else
  745. ql_dbg(ql_dbg_async, vha, 0x500e,
  746. "Asynchronous P2P MODE received.\n");
  747. /*
  748. * Until there's a transition from loop down to loop up, treat
  749. * this as loop down only.
  750. */
  751. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  752. atomic_set(&vha->loop_state, LOOP_DOWN);
  753. if (!atomic_read(&vha->loop_down_timer))
  754. atomic_set(&vha->loop_down_timer,
  755. LOOP_DOWN_TIME);
  756. qla2x00_mark_all_devices_lost(vha, 1);
  757. }
  758. if (vha->vp_idx) {
  759. atomic_set(&vha->vp_state, VP_FAILED);
  760. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  761. }
  762. if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)))
  763. set_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
  764. set_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags);
  765. set_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags);
  766. ha->flags.gpsc_supported = 1;
  767. vha->flags.management_server_logged_in = 0;
  768. break;
  769. case MBA_CHG_IN_CONNECTION: /* Change in connection mode */
  770. if (IS_QLA2100(ha))
  771. break;
  772. ql_dbg(ql_dbg_async, vha, 0x500f,
  773. "Configuration change detected: value=%x.\n", mb[1]);
  774. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  775. atomic_set(&vha->loop_state, LOOP_DOWN);
  776. if (!atomic_read(&vha->loop_down_timer))
  777. atomic_set(&vha->loop_down_timer,
  778. LOOP_DOWN_TIME);
  779. qla2x00_mark_all_devices_lost(vha, 1);
  780. }
  781. if (vha->vp_idx) {
  782. atomic_set(&vha->vp_state, VP_FAILED);
  783. fc_vport_set_state(vha->fc_vport, FC_VPORT_FAILED);
  784. }
  785. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  786. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  787. break;
  788. case MBA_PORT_UPDATE: /* Port database update */
  789. /*
  790. * Handle only global and vn-port update events
  791. *
  792. * Relevant inputs:
  793. * mb[1] = N_Port handle of changed port
  794. * OR 0xffff for global event
  795. * mb[2] = New login state
  796. * 7 = Port logged out
  797. * mb[3] = LSB is vp_idx, 0xff = all vps
  798. *
  799. * Skip processing if:
  800. * Event is global, vp_idx is NOT all vps,
  801. * vp_idx does not match
  802. * Event is not global, vp_idx does not match
  803. */
  804. if (IS_QLA2XXX_MIDTYPE(ha) &&
  805. ((mb[1] == 0xffff && (mb[3] & 0xff) != 0xff) ||
  806. (mb[1] != 0xffff)) && vha->vp_idx != (mb[3] & 0xff))
  807. break;
  808. if (mb[2] == 0x7) {
  809. ql_dbg(ql_dbg_async, vha, 0x5010,
  810. "Port %s %04x %04x %04x.\n",
  811. mb[1] == 0xffff ? "unavailable" : "logout",
  812. mb[1], mb[2], mb[3]);
  813. if (mb[1] == 0xffff)
  814. goto global_port_update;
  815. /* Port logout */
  816. fcport = qla2x00_find_fcport_by_loopid(vha, mb[1]);
  817. if (!fcport)
  818. break;
  819. if (atomic_read(&fcport->state) != FCS_ONLINE)
  820. break;
  821. ql_dbg(ql_dbg_async, vha, 0x508a,
  822. "Marking port lost loopid=%04x portid=%06x.\n",
  823. fcport->loop_id, fcport->d_id.b24);
  824. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  825. break;
  826. global_port_update:
  827. /* Port unavailable. */
  828. ql_log(ql_log_warn, vha, 0x505e,
  829. "Link is offline.\n");
  830. if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
  831. atomic_set(&vha->loop_state, LOOP_DOWN);
  832. atomic_set(&vha->loop_down_timer,
  833. LOOP_DOWN_TIME);
  834. vha->device_flags |= DFLG_NO_CABLE;
  835. qla2x00_mark_all_devices_lost(vha, 1);
  836. }
  837. if (vha->vp_idx) {
  838. atomic_set(&vha->vp_state, VP_FAILED);
  839. fc_vport_set_state(vha->fc_vport,
  840. FC_VPORT_FAILED);
  841. qla2x00_mark_all_devices_lost(vha, 1);
  842. }
  843. vha->flags.management_server_logged_in = 0;
  844. ha->link_data_rate = PORT_SPEED_UNKNOWN;
  845. break;
  846. }
  847. /*
  848. * If PORT UPDATE is global (received LIP_OCCURRED/LIP_RESET
  849. * event etc. earlier indicating loop is down) then process
  850. * it. Otherwise ignore it and Wait for RSCN to come in.
  851. */
  852. atomic_set(&vha->loop_down_timer, 0);
  853. if (atomic_read(&vha->loop_state) != LOOP_DOWN &&
  854. atomic_read(&vha->loop_state) != LOOP_DEAD) {
  855. ql_dbg(ql_dbg_async, vha, 0x5011,
  856. "Asynchronous PORT UPDATE ignored %04x/%04x/%04x.\n",
  857. mb[1], mb[2], mb[3]);
  858. qlt_async_event(mb[0], vha, mb);
  859. break;
  860. }
  861. ql_dbg(ql_dbg_async, vha, 0x5012,
  862. "Port database changed %04x %04x %04x.\n",
  863. mb[1], mb[2], mb[3]);
  864. /*
  865. * Mark all devices as missing so we will login again.
  866. */
  867. atomic_set(&vha->loop_state, LOOP_UP);
  868. qla2x00_mark_all_devices_lost(vha, 1);
  869. if (vha->vp_idx == 0 && !qla_ini_mode_enabled(vha))
  870. set_bit(SCR_PENDING, &vha->dpc_flags);
  871. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  872. set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
  873. set_bit(VP_CONFIG_OK, &vha->vp_flags);
  874. qlt_async_event(mb[0], vha, mb);
  875. break;
  876. case MBA_RSCN_UPDATE: /* State Change Registration */
  877. /* Check if the Vport has issued a SCR */
  878. if (vha->vp_idx && test_bit(VP_SCR_NEEDED, &vha->vp_flags))
  879. break;
  880. /* Only handle SCNs for our Vport index. */
  881. if (ha->flags.npiv_supported && vha->vp_idx != (mb[3] & 0xff))
  882. break;
  883. ql_dbg(ql_dbg_async, vha, 0x5013,
  884. "RSCN database changed -- %04x %04x %04x.\n",
  885. mb[1], mb[2], mb[3]);
  886. rscn_entry = ((mb[1] & 0xff) << 16) | mb[2];
  887. host_pid = (vha->d_id.b.domain << 16) | (vha->d_id.b.area << 8)
  888. | vha->d_id.b.al_pa;
  889. if (rscn_entry == host_pid) {
  890. ql_dbg(ql_dbg_async, vha, 0x5014,
  891. "Ignoring RSCN update to local host "
  892. "port ID (%06x).\n", host_pid);
  893. break;
  894. }
  895. /* Ignore reserved bits from RSCN-payload. */
  896. rscn_entry = ((mb[1] & 0x3ff) << 16) | mb[2];
  897. /* Skip RSCNs for virtual ports on the same physical port */
  898. if (qla2x00_is_a_vp_did(vha, rscn_entry))
  899. break;
  900. /*
  901. * Search for the rport related to this RSCN entry and mark it
  902. * as lost.
  903. */
  904. list_for_each_entry(fcport, &vha->vp_fcports, list) {
  905. if (atomic_read(&fcport->state) != FCS_ONLINE)
  906. continue;
  907. if (fcport->d_id.b24 == rscn_entry) {
  908. qla2x00_mark_device_lost(vha, fcport, 0, 0);
  909. break;
  910. }
  911. }
  912. atomic_set(&vha->loop_down_timer, 0);
  913. vha->flags.management_server_logged_in = 0;
  914. set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
  915. set_bit(RSCN_UPDATE, &vha->dpc_flags);
  916. qla2x00_post_aen_work(vha, FCH_EVT_RSCN, rscn_entry);
  917. break;
  918. /* case MBA_RIO_RESPONSE: */
  919. case MBA_ZIO_RESPONSE:
  920. ql_dbg(ql_dbg_async, vha, 0x5015,
  921. "[R|Z]IO update completion.\n");
  922. if (IS_FWI2_CAPABLE(ha))
  923. qla24xx_process_response_queue(vha, rsp);
  924. else
  925. qla2x00_process_response_queue(rsp);
  926. break;
  927. case MBA_DISCARD_RND_FRAME:
  928. ql_dbg(ql_dbg_async, vha, 0x5016,
  929. "Discard RND Frame -- %04x %04x %04x.\n",
  930. mb[1], mb[2], mb[3]);
  931. break;
  932. case MBA_TRACE_NOTIFICATION:
  933. ql_dbg(ql_dbg_async, vha, 0x5017,
  934. "Trace Notification -- %04x %04x.\n", mb[1], mb[2]);
  935. break;
  936. case MBA_ISP84XX_ALERT:
  937. ql_dbg(ql_dbg_async, vha, 0x5018,
  938. "ISP84XX Alert Notification -- %04x %04x %04x.\n",
  939. mb[1], mb[2], mb[3]);
  940. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  941. switch (mb[1]) {
  942. case A84_PANIC_RECOVERY:
  943. ql_log(ql_log_info, vha, 0x5019,
  944. "Alert 84XX: panic recovery %04x %04x.\n",
  945. mb[2], mb[3]);
  946. break;
  947. case A84_OP_LOGIN_COMPLETE:
  948. ha->cs84xx->op_fw_version = mb[3] << 16 | mb[2];
  949. ql_log(ql_log_info, vha, 0x501a,
  950. "Alert 84XX: firmware version %x.\n",
  951. ha->cs84xx->op_fw_version);
  952. break;
  953. case A84_DIAG_LOGIN_COMPLETE:
  954. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  955. ql_log(ql_log_info, vha, 0x501b,
  956. "Alert 84XX: diagnostic firmware version %x.\n",
  957. ha->cs84xx->diag_fw_version);
  958. break;
  959. case A84_GOLD_LOGIN_COMPLETE:
  960. ha->cs84xx->diag_fw_version = mb[3] << 16 | mb[2];
  961. ha->cs84xx->fw_update = 1;
  962. ql_log(ql_log_info, vha, 0x501c,
  963. "Alert 84XX: gold firmware version %x.\n",
  964. ha->cs84xx->gold_fw_version);
  965. break;
  966. default:
  967. ql_log(ql_log_warn, vha, 0x501d,
  968. "Alert 84xx: Invalid Alert %04x %04x %04x.\n",
  969. mb[1], mb[2], mb[3]);
  970. }
  971. spin_unlock_irqrestore(&ha->cs84xx->access_lock, flags);
  972. break;
  973. case MBA_DCBX_START:
  974. ql_dbg(ql_dbg_async, vha, 0x501e,
  975. "DCBX Started -- %04x %04x %04x.\n",
  976. mb[1], mb[2], mb[3]);
  977. break;
  978. case MBA_DCBX_PARAM_UPDATE:
  979. ql_dbg(ql_dbg_async, vha, 0x501f,
  980. "DCBX Parameters Updated -- %04x %04x %04x.\n",
  981. mb[1], mb[2], mb[3]);
  982. break;
  983. case MBA_FCF_CONF_ERR:
  984. ql_dbg(ql_dbg_async, vha, 0x5020,
  985. "FCF Configuration Error -- %04x %04x %04x.\n",
  986. mb[1], mb[2], mb[3]);
  987. break;
  988. case MBA_IDC_NOTIFY:
  989. if (IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  990. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  991. if (((mb[2] & 0x7fff) == MBC_PORT_RESET ||
  992. (mb[2] & 0x7fff) == MBC_SET_PORT_CONFIG) &&
  993. (mb[4] & INTERNAL_LOOPBACK_MASK) != 0) {
  994. set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
  995. /*
  996. * Extend loop down timer since port is active.
  997. */
  998. if (atomic_read(&vha->loop_state) == LOOP_DOWN)
  999. atomic_set(&vha->loop_down_timer,
  1000. LOOP_DOWN_TIME);
  1001. qla2xxx_wake_dpc(vha);
  1002. }
  1003. }
  1004. case MBA_IDC_COMPLETE:
  1005. if (ha->notify_lb_portup_comp && !vha->vp_idx)
  1006. complete(&ha->lb_portup_comp);
  1007. /* Fallthru */
  1008. case MBA_IDC_TIME_EXT:
  1009. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) ||
  1010. IS_QLA8044(ha))
  1011. qla81xx_idc_event(vha, mb[0], mb[1]);
  1012. break;
  1013. case MBA_IDC_AEN:
  1014. mb[4] = RD_REG_WORD(&reg24->mailbox4);
  1015. mb[5] = RD_REG_WORD(&reg24->mailbox5);
  1016. mb[6] = RD_REG_WORD(&reg24->mailbox6);
  1017. mb[7] = RD_REG_WORD(&reg24->mailbox7);
  1018. qla83xx_handle_8200_aen(vha, mb);
  1019. break;
  1020. case MBA_DPORT_DIAGNOSTICS:
  1021. ql_dbg(ql_dbg_async, vha, 0x5052,
  1022. "D-Port Diagnostics: %04x %04x=%s\n", mb[0], mb[1],
  1023. mb[1] == 0 ? "start" :
  1024. mb[1] == 1 ? "done (ok)" :
  1025. mb[1] == 2 ? "done (error)" : "other");
  1026. break;
  1027. default:
  1028. ql_dbg(ql_dbg_async, vha, 0x5057,
  1029. "Unknown AEN:%04x %04x %04x %04x\n",
  1030. mb[0], mb[1], mb[2], mb[3]);
  1031. }
  1032. qlt_async_event(mb[0], vha, mb);
  1033. if (!vha->vp_idx && ha->num_vhosts)
  1034. qla2x00_alert_all_vps(rsp, mb);
  1035. }
  1036. /**
  1037. * qla2x00_process_completed_request() - Process a Fast Post response.
  1038. * @ha: SCSI driver HA context
  1039. * @index: SRB index
  1040. */
  1041. void
  1042. qla2x00_process_completed_request(struct scsi_qla_host *vha,
  1043. struct req_que *req, uint32_t index)
  1044. {
  1045. srb_t *sp;
  1046. struct qla_hw_data *ha = vha->hw;
  1047. /* Validate handle. */
  1048. if (index >= req->num_outstanding_cmds) {
  1049. ql_log(ql_log_warn, vha, 0x3014,
  1050. "Invalid SCSI command index (%x).\n", index);
  1051. if (IS_P3P_TYPE(ha))
  1052. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1053. else
  1054. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1055. return;
  1056. }
  1057. sp = req->outstanding_cmds[index];
  1058. if (sp) {
  1059. /* Free outstanding command slot. */
  1060. req->outstanding_cmds[index] = NULL;
  1061. /* Save ISP completion status */
  1062. sp->done(ha, sp, DID_OK << 16);
  1063. } else {
  1064. ql_log(ql_log_warn, vha, 0x3016, "Invalid SCSI SRB.\n");
  1065. if (IS_P3P_TYPE(ha))
  1066. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1067. else
  1068. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1069. }
  1070. }
  1071. srb_t *
  1072. qla2x00_get_sp_from_handle(scsi_qla_host_t *vha, const char *func,
  1073. struct req_que *req, void *iocb)
  1074. {
  1075. struct qla_hw_data *ha = vha->hw;
  1076. sts_entry_t *pkt = iocb;
  1077. srb_t *sp = NULL;
  1078. uint16_t index;
  1079. index = LSW(pkt->handle);
  1080. if (index >= req->num_outstanding_cmds) {
  1081. ql_log(ql_log_warn, vha, 0x5031,
  1082. "Invalid command index (%x).\n", index);
  1083. if (IS_P3P_TYPE(ha))
  1084. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1085. else
  1086. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1087. goto done;
  1088. }
  1089. sp = req->outstanding_cmds[index];
  1090. if (!sp) {
  1091. ql_log(ql_log_warn, vha, 0x5032,
  1092. "Invalid completion handle (%x) -- timed-out.\n", index);
  1093. return sp;
  1094. }
  1095. if (sp->handle != index) {
  1096. ql_log(ql_log_warn, vha, 0x5033,
  1097. "SRB handle (%x) mismatch %x.\n", sp->handle, index);
  1098. return NULL;
  1099. }
  1100. req->outstanding_cmds[index] = NULL;
  1101. done:
  1102. return sp;
  1103. }
  1104. static void
  1105. qla2x00_mbx_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  1106. struct mbx_entry *mbx)
  1107. {
  1108. const char func[] = "MBX-IOCB";
  1109. const char *type;
  1110. fc_port_t *fcport;
  1111. srb_t *sp;
  1112. struct srb_iocb *lio;
  1113. uint16_t *data;
  1114. uint16_t status;
  1115. sp = qla2x00_get_sp_from_handle(vha, func, req, mbx);
  1116. if (!sp)
  1117. return;
  1118. lio = &sp->u.iocb_cmd;
  1119. type = sp->name;
  1120. fcport = sp->fcport;
  1121. data = lio->u.logio.data;
  1122. data[0] = MBS_COMMAND_ERROR;
  1123. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1124. QLA_LOGIO_LOGIN_RETRIED : 0;
  1125. if (mbx->entry_status) {
  1126. ql_dbg(ql_dbg_async, vha, 0x5043,
  1127. "Async-%s error entry - hdl=%x portid=%02x%02x%02x "
  1128. "entry-status=%x status=%x state-flag=%x "
  1129. "status-flags=%x.\n", type, sp->handle,
  1130. fcport->d_id.b.domain, fcport->d_id.b.area,
  1131. fcport->d_id.b.al_pa, mbx->entry_status,
  1132. le16_to_cpu(mbx->status), le16_to_cpu(mbx->state_flags),
  1133. le16_to_cpu(mbx->status_flags));
  1134. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5029,
  1135. (uint8_t *)mbx, sizeof(*mbx));
  1136. goto logio_done;
  1137. }
  1138. status = le16_to_cpu(mbx->status);
  1139. if (status == 0x30 && sp->type == SRB_LOGIN_CMD &&
  1140. le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE)
  1141. status = 0;
  1142. if (!status && le16_to_cpu(mbx->mb0) == MBS_COMMAND_COMPLETE) {
  1143. ql_dbg(ql_dbg_async, vha, 0x5045,
  1144. "Async-%s complete - hdl=%x portid=%02x%02x%02x mbx1=%x.\n",
  1145. type, sp->handle, fcport->d_id.b.domain,
  1146. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1147. le16_to_cpu(mbx->mb1));
  1148. data[0] = MBS_COMMAND_COMPLETE;
  1149. if (sp->type == SRB_LOGIN_CMD) {
  1150. fcport->port_type = FCT_TARGET;
  1151. if (le16_to_cpu(mbx->mb1) & BIT_0)
  1152. fcport->port_type = FCT_INITIATOR;
  1153. else if (le16_to_cpu(mbx->mb1) & BIT_1)
  1154. fcport->flags |= FCF_FCP2_DEVICE;
  1155. }
  1156. goto logio_done;
  1157. }
  1158. data[0] = le16_to_cpu(mbx->mb0);
  1159. switch (data[0]) {
  1160. case MBS_PORT_ID_USED:
  1161. data[1] = le16_to_cpu(mbx->mb1);
  1162. break;
  1163. case MBS_LOOP_ID_USED:
  1164. break;
  1165. default:
  1166. data[0] = MBS_COMMAND_ERROR;
  1167. break;
  1168. }
  1169. ql_log(ql_log_warn, vha, 0x5046,
  1170. "Async-%s failed - hdl=%x portid=%02x%02x%02x status=%x "
  1171. "mb0=%x mb1=%x mb2=%x mb6=%x mb7=%x.\n", type, sp->handle,
  1172. fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1173. status, le16_to_cpu(mbx->mb0), le16_to_cpu(mbx->mb1),
  1174. le16_to_cpu(mbx->mb2), le16_to_cpu(mbx->mb6),
  1175. le16_to_cpu(mbx->mb7));
  1176. logio_done:
  1177. sp->done(vha, sp, 0);
  1178. }
  1179. static void
  1180. qla2x00_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1181. sts_entry_t *pkt, int iocb_type)
  1182. {
  1183. const char func[] = "CT_IOCB";
  1184. const char *type;
  1185. srb_t *sp;
  1186. struct fc_bsg_job *bsg_job;
  1187. uint16_t comp_status;
  1188. int res;
  1189. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1190. if (!sp)
  1191. return;
  1192. bsg_job = sp->u.bsg_job;
  1193. type = "ct pass-through";
  1194. comp_status = le16_to_cpu(pkt->comp_status);
  1195. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1196. * fc payload to the caller
  1197. */
  1198. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1199. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1200. if (comp_status != CS_COMPLETE) {
  1201. if (comp_status == CS_DATA_UNDERRUN) {
  1202. res = DID_OK << 16;
  1203. bsg_job->reply->reply_payload_rcv_len =
  1204. le16_to_cpu(((sts_entry_t *)pkt)->rsp_info_len);
  1205. ql_log(ql_log_warn, vha, 0x5048,
  1206. "CT pass-through-%s error "
  1207. "comp_status-status=0x%x total_byte = 0x%x.\n",
  1208. type, comp_status,
  1209. bsg_job->reply->reply_payload_rcv_len);
  1210. } else {
  1211. ql_log(ql_log_warn, vha, 0x5049,
  1212. "CT pass-through-%s error "
  1213. "comp_status-status=0x%x.\n", type, comp_status);
  1214. res = DID_ERROR << 16;
  1215. bsg_job->reply->reply_payload_rcv_len = 0;
  1216. }
  1217. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5035,
  1218. (uint8_t *)pkt, sizeof(*pkt));
  1219. } else {
  1220. res = DID_OK << 16;
  1221. bsg_job->reply->reply_payload_rcv_len =
  1222. bsg_job->reply_payload.payload_len;
  1223. bsg_job->reply_len = 0;
  1224. }
  1225. sp->done(vha, sp, res);
  1226. }
  1227. static void
  1228. qla24xx_els_ct_entry(scsi_qla_host_t *vha, struct req_que *req,
  1229. struct sts_entry_24xx *pkt, int iocb_type)
  1230. {
  1231. const char func[] = "ELS_CT_IOCB";
  1232. const char *type;
  1233. srb_t *sp;
  1234. struct fc_bsg_job *bsg_job;
  1235. uint16_t comp_status;
  1236. uint32_t fw_status[3];
  1237. uint8_t* fw_sts_ptr;
  1238. int res;
  1239. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  1240. if (!sp)
  1241. return;
  1242. bsg_job = sp->u.bsg_job;
  1243. type = NULL;
  1244. switch (sp->type) {
  1245. case SRB_ELS_CMD_RPT:
  1246. case SRB_ELS_CMD_HST:
  1247. type = "els";
  1248. break;
  1249. case SRB_CT_CMD:
  1250. type = "ct pass-through";
  1251. break;
  1252. default:
  1253. ql_dbg(ql_dbg_user, vha, 0x503e,
  1254. "Unrecognized SRB: (%p) type=%d.\n", sp, sp->type);
  1255. return;
  1256. }
  1257. comp_status = fw_status[0] = le16_to_cpu(pkt->comp_status);
  1258. fw_status[1] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_1);
  1259. fw_status[2] = le16_to_cpu(((struct els_sts_entry_24xx*)pkt)->error_subcode_2);
  1260. /* return FC_CTELS_STATUS_OK and leave the decoding of the ELS/CT
  1261. * fc payload to the caller
  1262. */
  1263. bsg_job->reply->reply_data.ctels_reply.status = FC_CTELS_STATUS_OK;
  1264. bsg_job->reply_len = sizeof(struct fc_bsg_reply) + sizeof(fw_status);
  1265. if (comp_status != CS_COMPLETE) {
  1266. if (comp_status == CS_DATA_UNDERRUN) {
  1267. res = DID_OK << 16;
  1268. bsg_job->reply->reply_payload_rcv_len =
  1269. le16_to_cpu(((struct els_sts_entry_24xx *)pkt)->total_byte_count);
  1270. ql_dbg(ql_dbg_user, vha, 0x503f,
  1271. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1272. "error subcode 1=0x%x error subcode 2=0x%x total_byte = 0x%x.\n",
  1273. type, sp->handle, comp_status, fw_status[1], fw_status[2],
  1274. le16_to_cpu(((struct els_sts_entry_24xx *)
  1275. pkt)->total_byte_count));
  1276. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1277. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1278. }
  1279. else {
  1280. ql_dbg(ql_dbg_user, vha, 0x5040,
  1281. "ELS-CT pass-through-%s error hdl=%x comp_status-status=0x%x "
  1282. "error subcode 1=0x%x error subcode 2=0x%x.\n",
  1283. type, sp->handle, comp_status,
  1284. le16_to_cpu(((struct els_sts_entry_24xx *)
  1285. pkt)->error_subcode_1),
  1286. le16_to_cpu(((struct els_sts_entry_24xx *)
  1287. pkt)->error_subcode_2));
  1288. res = DID_ERROR << 16;
  1289. bsg_job->reply->reply_payload_rcv_len = 0;
  1290. fw_sts_ptr = ((uint8_t*)bsg_job->req->sense) + sizeof(struct fc_bsg_reply);
  1291. memcpy( fw_sts_ptr, fw_status, sizeof(fw_status));
  1292. }
  1293. ql_dump_buffer(ql_dbg_user + ql_dbg_buffer, vha, 0x5056,
  1294. (uint8_t *)pkt, sizeof(*pkt));
  1295. }
  1296. else {
  1297. res = DID_OK << 16;
  1298. bsg_job->reply->reply_payload_rcv_len = bsg_job->reply_payload.payload_len;
  1299. bsg_job->reply_len = 0;
  1300. }
  1301. sp->done(vha, sp, res);
  1302. }
  1303. static void
  1304. qla24xx_logio_entry(scsi_qla_host_t *vha, struct req_que *req,
  1305. struct logio_entry_24xx *logio)
  1306. {
  1307. const char func[] = "LOGIO-IOCB";
  1308. const char *type;
  1309. fc_port_t *fcport;
  1310. srb_t *sp;
  1311. struct srb_iocb *lio;
  1312. uint16_t *data;
  1313. uint32_t iop[2];
  1314. sp = qla2x00_get_sp_from_handle(vha, func, req, logio);
  1315. if (!sp)
  1316. return;
  1317. lio = &sp->u.iocb_cmd;
  1318. type = sp->name;
  1319. fcport = sp->fcport;
  1320. data = lio->u.logio.data;
  1321. data[0] = MBS_COMMAND_ERROR;
  1322. data[1] = lio->u.logio.flags & SRB_LOGIN_RETRIED ?
  1323. QLA_LOGIO_LOGIN_RETRIED : 0;
  1324. if (logio->entry_status) {
  1325. ql_log(ql_log_warn, fcport->vha, 0x5034,
  1326. "Async-%s error entry - hdl=%x"
  1327. "portid=%02x%02x%02x entry-status=%x.\n",
  1328. type, sp->handle, fcport->d_id.b.domain,
  1329. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1330. logio->entry_status);
  1331. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x504d,
  1332. (uint8_t *)logio, sizeof(*logio));
  1333. goto logio_done;
  1334. }
  1335. if (le16_to_cpu(logio->comp_status) == CS_COMPLETE) {
  1336. ql_dbg(ql_dbg_async, fcport->vha, 0x5036,
  1337. "Async-%s complete - hdl=%x portid=%02x%02x%02x "
  1338. "iop0=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1339. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1340. le32_to_cpu(logio->io_parameter[0]));
  1341. data[0] = MBS_COMMAND_COMPLETE;
  1342. if (sp->type != SRB_LOGIN_CMD)
  1343. goto logio_done;
  1344. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1345. if (iop[0] & BIT_4) {
  1346. fcport->port_type = FCT_TARGET;
  1347. if (iop[0] & BIT_8)
  1348. fcport->flags |= FCF_FCP2_DEVICE;
  1349. } else if (iop[0] & BIT_5)
  1350. fcport->port_type = FCT_INITIATOR;
  1351. if (iop[0] & BIT_7)
  1352. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1353. if (logio->io_parameter[7] || logio->io_parameter[8])
  1354. fcport->supported_classes |= FC_COS_CLASS2;
  1355. if (logio->io_parameter[9] || logio->io_parameter[10])
  1356. fcport->supported_classes |= FC_COS_CLASS3;
  1357. goto logio_done;
  1358. }
  1359. iop[0] = le32_to_cpu(logio->io_parameter[0]);
  1360. iop[1] = le32_to_cpu(logio->io_parameter[1]);
  1361. switch (iop[0]) {
  1362. case LSC_SCODE_PORTID_USED:
  1363. data[0] = MBS_PORT_ID_USED;
  1364. data[1] = LSW(iop[1]);
  1365. break;
  1366. case LSC_SCODE_NPORT_USED:
  1367. data[0] = MBS_LOOP_ID_USED;
  1368. break;
  1369. default:
  1370. data[0] = MBS_COMMAND_ERROR;
  1371. break;
  1372. }
  1373. ql_dbg(ql_dbg_async, fcport->vha, 0x5037,
  1374. "Async-%s failed - hdl=%x portid=%02x%02x%02x comp=%x "
  1375. "iop0=%x iop1=%x.\n", type, sp->handle, fcport->d_id.b.domain,
  1376. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  1377. le16_to_cpu(logio->comp_status),
  1378. le32_to_cpu(logio->io_parameter[0]),
  1379. le32_to_cpu(logio->io_parameter[1]));
  1380. logio_done:
  1381. sp->done(vha, sp, 0);
  1382. }
  1383. static void
  1384. qla24xx_tm_iocb_entry(scsi_qla_host_t *vha, struct req_que *req, void *tsk)
  1385. {
  1386. const char func[] = "TMF-IOCB";
  1387. const char *type;
  1388. fc_port_t *fcport;
  1389. srb_t *sp;
  1390. struct srb_iocb *iocb;
  1391. struct sts_entry_24xx *sts = (struct sts_entry_24xx *)tsk;
  1392. sp = qla2x00_get_sp_from_handle(vha, func, req, tsk);
  1393. if (!sp)
  1394. return;
  1395. iocb = &sp->u.iocb_cmd;
  1396. type = sp->name;
  1397. fcport = sp->fcport;
  1398. iocb->u.tmf.data = QLA_SUCCESS;
  1399. if (sts->entry_status) {
  1400. ql_log(ql_log_warn, fcport->vha, 0x5038,
  1401. "Async-%s error - hdl=%x entry-status(%x).\n",
  1402. type, sp->handle, sts->entry_status);
  1403. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1404. } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
  1405. ql_log(ql_log_warn, fcport->vha, 0x5039,
  1406. "Async-%s error - hdl=%x completion status(%x).\n",
  1407. type, sp->handle, sts->comp_status);
  1408. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1409. } else if ((le16_to_cpu(sts->scsi_status) &
  1410. SS_RESPONSE_INFO_LEN_VALID)) {
  1411. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  1412. ql_log(ql_log_warn, fcport->vha, 0x503b,
  1413. "Async-%s error - hdl=%x not enough response(%d).\n",
  1414. type, sp->handle, sts->rsp_data_len);
  1415. } else if (sts->data[3]) {
  1416. ql_log(ql_log_warn, fcport->vha, 0x503c,
  1417. "Async-%s error - hdl=%x response(%x).\n",
  1418. type, sp->handle, sts->data[3]);
  1419. iocb->u.tmf.data = QLA_FUNCTION_FAILED;
  1420. }
  1421. }
  1422. if (iocb->u.tmf.data != QLA_SUCCESS)
  1423. ql_dump_buffer(ql_dbg_async + ql_dbg_buffer, vha, 0x5055,
  1424. (uint8_t *)sts, sizeof(*sts));
  1425. sp->done(vha, sp, 0);
  1426. }
  1427. /**
  1428. * qla2x00_process_response_queue() - Process response queue entries.
  1429. * @ha: SCSI driver HA context
  1430. */
  1431. void
  1432. qla2x00_process_response_queue(struct rsp_que *rsp)
  1433. {
  1434. struct scsi_qla_host *vha;
  1435. struct qla_hw_data *ha = rsp->hw;
  1436. struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  1437. sts_entry_t *pkt;
  1438. uint16_t handle_cnt;
  1439. uint16_t cnt;
  1440. vha = pci_get_drvdata(ha->pdev);
  1441. if (!vha->flags.online)
  1442. return;
  1443. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  1444. pkt = (sts_entry_t *)rsp->ring_ptr;
  1445. rsp->ring_index++;
  1446. if (rsp->ring_index == rsp->length) {
  1447. rsp->ring_index = 0;
  1448. rsp->ring_ptr = rsp->ring;
  1449. } else {
  1450. rsp->ring_ptr++;
  1451. }
  1452. if (pkt->entry_status != 0) {
  1453. qla2x00_error_entry(vha, rsp, pkt);
  1454. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1455. wmb();
  1456. continue;
  1457. }
  1458. switch (pkt->entry_type) {
  1459. case STATUS_TYPE:
  1460. qla2x00_status_entry(vha, rsp, pkt);
  1461. break;
  1462. case STATUS_TYPE_21:
  1463. handle_cnt = ((sts21_entry_t *)pkt)->handle_count;
  1464. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1465. qla2x00_process_completed_request(vha, rsp->req,
  1466. ((sts21_entry_t *)pkt)->handle[cnt]);
  1467. }
  1468. break;
  1469. case STATUS_TYPE_22:
  1470. handle_cnt = ((sts22_entry_t *)pkt)->handle_count;
  1471. for (cnt = 0; cnt < handle_cnt; cnt++) {
  1472. qla2x00_process_completed_request(vha, rsp->req,
  1473. ((sts22_entry_t *)pkt)->handle[cnt]);
  1474. }
  1475. break;
  1476. case STATUS_CONT_TYPE:
  1477. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  1478. break;
  1479. case MBX_IOCB_TYPE:
  1480. qla2x00_mbx_iocb_entry(vha, rsp->req,
  1481. (struct mbx_entry *)pkt);
  1482. break;
  1483. case CT_IOCB_TYPE:
  1484. qla2x00_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  1485. break;
  1486. default:
  1487. /* Type Not Supported. */
  1488. ql_log(ql_log_warn, vha, 0x504a,
  1489. "Received unknown response pkt type %x "
  1490. "entry status=%x.\n",
  1491. pkt->entry_type, pkt->entry_status);
  1492. break;
  1493. }
  1494. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  1495. wmb();
  1496. }
  1497. /* Adjust ring index */
  1498. WRT_REG_WORD(ISP_RSP_Q_OUT(ha, reg), rsp->ring_index);
  1499. }
  1500. static inline void
  1501. qla2x00_handle_sense(srb_t *sp, uint8_t *sense_data, uint32_t par_sense_len,
  1502. uint32_t sense_len, struct rsp_que *rsp, int res)
  1503. {
  1504. struct scsi_qla_host *vha = sp->fcport->vha;
  1505. struct scsi_cmnd *cp = GET_CMD_SP(sp);
  1506. uint32_t track_sense_len;
  1507. if (sense_len >= SCSI_SENSE_BUFFERSIZE)
  1508. sense_len = SCSI_SENSE_BUFFERSIZE;
  1509. SET_CMD_SENSE_LEN(sp, sense_len);
  1510. SET_CMD_SENSE_PTR(sp, cp->sense_buffer);
  1511. track_sense_len = sense_len;
  1512. if (sense_len > par_sense_len)
  1513. sense_len = par_sense_len;
  1514. memcpy(cp->sense_buffer, sense_data, sense_len);
  1515. SET_CMD_SENSE_PTR(sp, cp->sense_buffer + sense_len);
  1516. track_sense_len -= sense_len;
  1517. SET_CMD_SENSE_LEN(sp, track_sense_len);
  1518. if (track_sense_len != 0) {
  1519. rsp->status_srb = sp;
  1520. cp->result = res;
  1521. }
  1522. if (sense_len) {
  1523. ql_dbg(ql_dbg_io + ql_dbg_buffer, vha, 0x301c,
  1524. "Check condition Sense data, nexus%ld:%d:%llu cmd=%p.\n",
  1525. sp->fcport->vha->host_no, cp->device->id, cp->device->lun,
  1526. cp);
  1527. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302b,
  1528. cp->sense_buffer, sense_len);
  1529. }
  1530. }
  1531. struct scsi_dif_tuple {
  1532. __be16 guard; /* Checksum */
  1533. __be16 app_tag; /* APPL identifier */
  1534. __be32 ref_tag; /* Target LBA or indirect LBA */
  1535. };
  1536. /*
  1537. * Checks the guard or meta-data for the type of error
  1538. * detected by the HBA. In case of errors, we set the
  1539. * ASC/ASCQ fields in the sense buffer with ILLEGAL_REQUEST
  1540. * to indicate to the kernel that the HBA detected error.
  1541. */
  1542. static inline int
  1543. qla2x00_handle_dif_error(srb_t *sp, struct sts_entry_24xx *sts24)
  1544. {
  1545. struct scsi_qla_host *vha = sp->fcport->vha;
  1546. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  1547. uint8_t *ap = &sts24->data[12];
  1548. uint8_t *ep = &sts24->data[20];
  1549. uint32_t e_ref_tag, a_ref_tag;
  1550. uint16_t e_app_tag, a_app_tag;
  1551. uint16_t e_guard, a_guard;
  1552. /*
  1553. * swab32 of the "data" field in the beginning of qla2x00_status_entry()
  1554. * would make guard field appear at offset 2
  1555. */
  1556. a_guard = le16_to_cpu(*(uint16_t *)(ap + 2));
  1557. a_app_tag = le16_to_cpu(*(uint16_t *)(ap + 0));
  1558. a_ref_tag = le32_to_cpu(*(uint32_t *)(ap + 4));
  1559. e_guard = le16_to_cpu(*(uint16_t *)(ep + 2));
  1560. e_app_tag = le16_to_cpu(*(uint16_t *)(ep + 0));
  1561. e_ref_tag = le32_to_cpu(*(uint32_t *)(ep + 4));
  1562. ql_dbg(ql_dbg_io, vha, 0x3023,
  1563. "iocb(s) %p Returned STATUS.\n", sts24);
  1564. ql_dbg(ql_dbg_io, vha, 0x3024,
  1565. "DIF ERROR in cmd 0x%x lba 0x%llx act ref"
  1566. " tag=0x%x, exp ref_tag=0x%x, act app tag=0x%x, exp app"
  1567. " tag=0x%x, act guard=0x%x, exp guard=0x%x.\n",
  1568. cmd->cmnd[0], (u64)scsi_get_lba(cmd), a_ref_tag, e_ref_tag,
  1569. a_app_tag, e_app_tag, a_guard, e_guard);
  1570. /*
  1571. * Ignore sector if:
  1572. * For type 3: ref & app tag is all 'f's
  1573. * For type 0,1,2: app tag is all 'f's
  1574. */
  1575. if ((a_app_tag == 0xffff) &&
  1576. ((scsi_get_prot_type(cmd) != SCSI_PROT_DIF_TYPE3) ||
  1577. (a_ref_tag == 0xffffffff))) {
  1578. uint32_t blocks_done, resid;
  1579. sector_t lba_s = scsi_get_lba(cmd);
  1580. /* 2TB boundary case covered automatically with this */
  1581. blocks_done = e_ref_tag - (uint32_t)lba_s + 1;
  1582. resid = scsi_bufflen(cmd) - (blocks_done *
  1583. cmd->device->sector_size);
  1584. scsi_set_resid(cmd, resid);
  1585. cmd->result = DID_OK << 16;
  1586. /* Update protection tag */
  1587. if (scsi_prot_sg_count(cmd)) {
  1588. uint32_t i, j = 0, k = 0, num_ent;
  1589. struct scatterlist *sg;
  1590. struct sd_dif_tuple *spt;
  1591. /* Patch the corresponding protection tags */
  1592. scsi_for_each_prot_sg(cmd, sg,
  1593. scsi_prot_sg_count(cmd), i) {
  1594. num_ent = sg_dma_len(sg) / 8;
  1595. if (k + num_ent < blocks_done) {
  1596. k += num_ent;
  1597. continue;
  1598. }
  1599. j = blocks_done - k - 1;
  1600. k = blocks_done;
  1601. break;
  1602. }
  1603. if (k != blocks_done) {
  1604. ql_log(ql_log_warn, vha, 0x302f,
  1605. "unexpected tag values tag:lba=%x:%llx)\n",
  1606. e_ref_tag, (unsigned long long)lba_s);
  1607. return 1;
  1608. }
  1609. spt = page_address(sg_page(sg)) + sg->offset;
  1610. spt += j;
  1611. spt->app_tag = 0xffff;
  1612. if (scsi_get_prot_type(cmd) == SCSI_PROT_DIF_TYPE3)
  1613. spt->ref_tag = 0xffffffff;
  1614. }
  1615. return 0;
  1616. }
  1617. /* check guard */
  1618. if (e_guard != a_guard) {
  1619. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1620. 0x10, 0x1);
  1621. set_driver_byte(cmd, DRIVER_SENSE);
  1622. set_host_byte(cmd, DID_ABORT);
  1623. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1624. return 1;
  1625. }
  1626. /* check ref tag */
  1627. if (e_ref_tag != a_ref_tag) {
  1628. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1629. 0x10, 0x3);
  1630. set_driver_byte(cmd, DRIVER_SENSE);
  1631. set_host_byte(cmd, DID_ABORT);
  1632. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1633. return 1;
  1634. }
  1635. /* check appl tag */
  1636. if (e_app_tag != a_app_tag) {
  1637. scsi_build_sense_buffer(1, cmd->sense_buffer, ILLEGAL_REQUEST,
  1638. 0x10, 0x2);
  1639. set_driver_byte(cmd, DRIVER_SENSE);
  1640. set_host_byte(cmd, DID_ABORT);
  1641. cmd->result |= SAM_STAT_CHECK_CONDITION << 1;
  1642. return 1;
  1643. }
  1644. return 1;
  1645. }
  1646. static void
  1647. qla25xx_process_bidir_status_iocb(scsi_qla_host_t *vha, void *pkt,
  1648. struct req_que *req, uint32_t index)
  1649. {
  1650. struct qla_hw_data *ha = vha->hw;
  1651. srb_t *sp;
  1652. uint16_t comp_status;
  1653. uint16_t scsi_status;
  1654. uint16_t thread_id;
  1655. uint32_t rval = EXT_STATUS_OK;
  1656. struct fc_bsg_job *bsg_job = NULL;
  1657. sts_entry_t *sts;
  1658. struct sts_entry_24xx *sts24;
  1659. sts = (sts_entry_t *) pkt;
  1660. sts24 = (struct sts_entry_24xx *) pkt;
  1661. /* Validate handle. */
  1662. if (index >= req->num_outstanding_cmds) {
  1663. ql_log(ql_log_warn, vha, 0x70af,
  1664. "Invalid SCSI completion handle 0x%x.\n", index);
  1665. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1666. return;
  1667. }
  1668. sp = req->outstanding_cmds[index];
  1669. if (sp) {
  1670. /* Free outstanding command slot. */
  1671. req->outstanding_cmds[index] = NULL;
  1672. bsg_job = sp->u.bsg_job;
  1673. } else {
  1674. ql_log(ql_log_warn, vha, 0x70b0,
  1675. "Req:%d: Invalid ISP SCSI completion handle(0x%x)\n",
  1676. req->id, index);
  1677. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1678. return;
  1679. }
  1680. if (IS_FWI2_CAPABLE(ha)) {
  1681. comp_status = le16_to_cpu(sts24->comp_status);
  1682. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1683. } else {
  1684. comp_status = le16_to_cpu(sts->comp_status);
  1685. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1686. }
  1687. thread_id = bsg_job->request->rqst_data.h_vendor.vendor_cmd[1];
  1688. switch (comp_status) {
  1689. case CS_COMPLETE:
  1690. if (scsi_status == 0) {
  1691. bsg_job->reply->reply_payload_rcv_len =
  1692. bsg_job->reply_payload.payload_len;
  1693. vha->qla_stats.input_bytes +=
  1694. bsg_job->reply->reply_payload_rcv_len;
  1695. vha->qla_stats.input_requests++;
  1696. rval = EXT_STATUS_OK;
  1697. }
  1698. goto done;
  1699. case CS_DATA_OVERRUN:
  1700. ql_dbg(ql_dbg_user, vha, 0x70b1,
  1701. "Command completed with date overrun thread_id=%d\n",
  1702. thread_id);
  1703. rval = EXT_STATUS_DATA_OVERRUN;
  1704. break;
  1705. case CS_DATA_UNDERRUN:
  1706. ql_dbg(ql_dbg_user, vha, 0x70b2,
  1707. "Command completed with date underrun thread_id=%d\n",
  1708. thread_id);
  1709. rval = EXT_STATUS_DATA_UNDERRUN;
  1710. break;
  1711. case CS_BIDIR_RD_OVERRUN:
  1712. ql_dbg(ql_dbg_user, vha, 0x70b3,
  1713. "Command completed with read data overrun thread_id=%d\n",
  1714. thread_id);
  1715. rval = EXT_STATUS_DATA_OVERRUN;
  1716. break;
  1717. case CS_BIDIR_RD_WR_OVERRUN:
  1718. ql_dbg(ql_dbg_user, vha, 0x70b4,
  1719. "Command completed with read and write data overrun "
  1720. "thread_id=%d\n", thread_id);
  1721. rval = EXT_STATUS_DATA_OVERRUN;
  1722. break;
  1723. case CS_BIDIR_RD_OVERRUN_WR_UNDERRUN:
  1724. ql_dbg(ql_dbg_user, vha, 0x70b5,
  1725. "Command completed with read data over and write data "
  1726. "underrun thread_id=%d\n", thread_id);
  1727. rval = EXT_STATUS_DATA_OVERRUN;
  1728. break;
  1729. case CS_BIDIR_RD_UNDERRUN:
  1730. ql_dbg(ql_dbg_user, vha, 0x70b6,
  1731. "Command completed with read data data underrun "
  1732. "thread_id=%d\n", thread_id);
  1733. rval = EXT_STATUS_DATA_UNDERRUN;
  1734. break;
  1735. case CS_BIDIR_RD_UNDERRUN_WR_OVERRUN:
  1736. ql_dbg(ql_dbg_user, vha, 0x70b7,
  1737. "Command completed with read data under and write data "
  1738. "overrun thread_id=%d\n", thread_id);
  1739. rval = EXT_STATUS_DATA_UNDERRUN;
  1740. break;
  1741. case CS_BIDIR_RD_WR_UNDERRUN:
  1742. ql_dbg(ql_dbg_user, vha, 0x70b8,
  1743. "Command completed with read and write data underrun "
  1744. "thread_id=%d\n", thread_id);
  1745. rval = EXT_STATUS_DATA_UNDERRUN;
  1746. break;
  1747. case CS_BIDIR_DMA:
  1748. ql_dbg(ql_dbg_user, vha, 0x70b9,
  1749. "Command completed with data DMA error thread_id=%d\n",
  1750. thread_id);
  1751. rval = EXT_STATUS_DMA_ERR;
  1752. break;
  1753. case CS_TIMEOUT:
  1754. ql_dbg(ql_dbg_user, vha, 0x70ba,
  1755. "Command completed with timeout thread_id=%d\n",
  1756. thread_id);
  1757. rval = EXT_STATUS_TIMEOUT;
  1758. break;
  1759. default:
  1760. ql_dbg(ql_dbg_user, vha, 0x70bb,
  1761. "Command completed with completion status=0x%x "
  1762. "thread_id=%d\n", comp_status, thread_id);
  1763. rval = EXT_STATUS_ERR;
  1764. break;
  1765. }
  1766. bsg_job->reply->reply_payload_rcv_len = 0;
  1767. done:
  1768. /* Return the vendor specific reply to API */
  1769. bsg_job->reply->reply_data.vendor_reply.vendor_rsp[0] = rval;
  1770. bsg_job->reply_len = sizeof(struct fc_bsg_reply);
  1771. /* Always return DID_OK, bsg will send the vendor specific response
  1772. * in this case only */
  1773. sp->done(vha, sp, (DID_OK << 6));
  1774. }
  1775. /**
  1776. * qla2x00_status_entry() - Process a Status IOCB entry.
  1777. * @ha: SCSI driver HA context
  1778. * @pkt: Entry pointer
  1779. */
  1780. static void
  1781. qla2x00_status_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, void *pkt)
  1782. {
  1783. srb_t *sp;
  1784. fc_port_t *fcport;
  1785. struct scsi_cmnd *cp;
  1786. sts_entry_t *sts;
  1787. struct sts_entry_24xx *sts24;
  1788. uint16_t comp_status;
  1789. uint16_t scsi_status;
  1790. uint16_t ox_id;
  1791. uint8_t lscsi_status;
  1792. int32_t resid;
  1793. uint32_t sense_len, par_sense_len, rsp_info_len, resid_len,
  1794. fw_resid_len;
  1795. uint8_t *rsp_info, *sense_data;
  1796. struct qla_hw_data *ha = vha->hw;
  1797. uint32_t handle;
  1798. uint16_t que;
  1799. struct req_que *req;
  1800. int logit = 1;
  1801. int res = 0;
  1802. uint16_t state_flags = 0;
  1803. uint16_t retry_delay = 0;
  1804. sts = (sts_entry_t *) pkt;
  1805. sts24 = (struct sts_entry_24xx *) pkt;
  1806. if (IS_FWI2_CAPABLE(ha)) {
  1807. comp_status = le16_to_cpu(sts24->comp_status);
  1808. scsi_status = le16_to_cpu(sts24->scsi_status) & SS_MASK;
  1809. state_flags = le16_to_cpu(sts24->state_flags);
  1810. } else {
  1811. comp_status = le16_to_cpu(sts->comp_status);
  1812. scsi_status = le16_to_cpu(sts->scsi_status) & SS_MASK;
  1813. }
  1814. handle = (uint32_t) LSW(sts->handle);
  1815. que = MSW(sts->handle);
  1816. req = ha->req_q_map[que];
  1817. /* Check for invalid queue pointer */
  1818. if (req == NULL ||
  1819. que >= find_first_zero_bit(ha->req_qid_map, ha->max_req_queues)) {
  1820. ql_dbg(ql_dbg_io, vha, 0x3059,
  1821. "Invalid status handle (0x%x): Bad req pointer. req=%p, "
  1822. "que=%u.\n", sts->handle, req, que);
  1823. return;
  1824. }
  1825. /* Validate handle. */
  1826. if (handle < req->num_outstanding_cmds) {
  1827. sp = req->outstanding_cmds[handle];
  1828. if (!sp) {
  1829. ql_dbg(ql_dbg_io, vha, 0x3075,
  1830. "%s(%ld): Already returned command for status handle (0x%x).\n",
  1831. __func__, vha->host_no, sts->handle);
  1832. return;
  1833. }
  1834. } else {
  1835. ql_dbg(ql_dbg_io, vha, 0x3017,
  1836. "Invalid status handle, out of range (0x%x).\n",
  1837. sts->handle);
  1838. if (!test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
  1839. if (IS_P3P_TYPE(ha))
  1840. set_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags);
  1841. else
  1842. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  1843. qla2xxx_wake_dpc(vha);
  1844. }
  1845. return;
  1846. }
  1847. if (unlikely((state_flags & BIT_1) && (sp->type == SRB_BIDI_CMD))) {
  1848. qla25xx_process_bidir_status_iocb(vha, pkt, req, handle);
  1849. return;
  1850. }
  1851. /* Task Management completion. */
  1852. if (sp->type == SRB_TM_CMD) {
  1853. qla24xx_tm_iocb_entry(vha, req, pkt);
  1854. return;
  1855. }
  1856. /* Fast path completion. */
  1857. if (comp_status == CS_COMPLETE && scsi_status == 0) {
  1858. qla2x00_process_completed_request(vha, req, handle);
  1859. return;
  1860. }
  1861. req->outstanding_cmds[handle] = NULL;
  1862. cp = GET_CMD_SP(sp);
  1863. if (cp == NULL) {
  1864. ql_dbg(ql_dbg_io, vha, 0x3018,
  1865. "Command already returned (0x%x/%p).\n",
  1866. sts->handle, sp);
  1867. return;
  1868. }
  1869. lscsi_status = scsi_status & STATUS_MASK;
  1870. fcport = sp->fcport;
  1871. ox_id = 0;
  1872. sense_len = par_sense_len = rsp_info_len = resid_len =
  1873. fw_resid_len = 0;
  1874. if (IS_FWI2_CAPABLE(ha)) {
  1875. if (scsi_status & SS_SENSE_LEN_VALID)
  1876. sense_len = le32_to_cpu(sts24->sense_len);
  1877. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1878. rsp_info_len = le32_to_cpu(sts24->rsp_data_len);
  1879. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER))
  1880. resid_len = le32_to_cpu(sts24->rsp_residual_count);
  1881. if (comp_status == CS_DATA_UNDERRUN)
  1882. fw_resid_len = le32_to_cpu(sts24->residual_len);
  1883. rsp_info = sts24->data;
  1884. sense_data = sts24->data;
  1885. host_to_fcp_swap(sts24->data, sizeof(sts24->data));
  1886. ox_id = le16_to_cpu(sts24->ox_id);
  1887. par_sense_len = sizeof(sts24->data);
  1888. /* Valid values of the retry delay timer are 0x1-0xffef */
  1889. if (sts24->retry_delay > 0 && sts24->retry_delay < 0xfff1)
  1890. retry_delay = sts24->retry_delay;
  1891. } else {
  1892. if (scsi_status & SS_SENSE_LEN_VALID)
  1893. sense_len = le16_to_cpu(sts->req_sense_length);
  1894. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID)
  1895. rsp_info_len = le16_to_cpu(sts->rsp_info_len);
  1896. resid_len = le32_to_cpu(sts->residual_length);
  1897. rsp_info = sts->rsp_info;
  1898. sense_data = sts->req_sense_data;
  1899. par_sense_len = sizeof(sts->req_sense_data);
  1900. }
  1901. /* Check for any FCP transport errors. */
  1902. if (scsi_status & SS_RESPONSE_INFO_LEN_VALID) {
  1903. /* Sense data lies beyond any FCP RESPONSE data. */
  1904. if (IS_FWI2_CAPABLE(ha)) {
  1905. sense_data += rsp_info_len;
  1906. par_sense_len -= rsp_info_len;
  1907. }
  1908. if (rsp_info_len > 3 && rsp_info[3]) {
  1909. ql_dbg(ql_dbg_io, fcport->vha, 0x3019,
  1910. "FCP I/O protocol failure (0x%x/0x%x).\n",
  1911. rsp_info_len, rsp_info[3]);
  1912. res = DID_BUS_BUSY << 16;
  1913. goto out;
  1914. }
  1915. }
  1916. /* Check for overrun. */
  1917. if (IS_FWI2_CAPABLE(ha) && comp_status == CS_COMPLETE &&
  1918. scsi_status & SS_RESIDUAL_OVER)
  1919. comp_status = CS_DATA_OVERRUN;
  1920. /*
  1921. * Check retry_delay_timer value if we receive a busy or
  1922. * queue full.
  1923. */
  1924. if (lscsi_status == SAM_STAT_TASK_SET_FULL ||
  1925. lscsi_status == SAM_STAT_BUSY)
  1926. qla2x00_set_retry_delay_timestamp(fcport, retry_delay);
  1927. /*
  1928. * Based on Host and scsi status generate status code for Linux
  1929. */
  1930. switch (comp_status) {
  1931. case CS_COMPLETE:
  1932. case CS_QUEUE_FULL:
  1933. if (scsi_status == 0) {
  1934. res = DID_OK << 16;
  1935. break;
  1936. }
  1937. if (scsi_status & (SS_RESIDUAL_UNDER | SS_RESIDUAL_OVER)) {
  1938. resid = resid_len;
  1939. scsi_set_resid(cp, resid);
  1940. if (!lscsi_status &&
  1941. ((unsigned)(scsi_bufflen(cp) - resid) <
  1942. cp->underflow)) {
  1943. ql_dbg(ql_dbg_io, fcport->vha, 0x301a,
  1944. "Mid-layer underflow "
  1945. "detected (0x%x of 0x%x bytes).\n",
  1946. resid, scsi_bufflen(cp));
  1947. res = DID_ERROR << 16;
  1948. break;
  1949. }
  1950. }
  1951. res = DID_OK << 16 | lscsi_status;
  1952. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  1953. ql_dbg(ql_dbg_io, fcport->vha, 0x301b,
  1954. "QUEUE FULL detected.\n");
  1955. break;
  1956. }
  1957. logit = 0;
  1958. if (lscsi_status != SS_CHECK_CONDITION)
  1959. break;
  1960. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  1961. if (!(scsi_status & SS_SENSE_LEN_VALID))
  1962. break;
  1963. qla2x00_handle_sense(sp, sense_data, par_sense_len, sense_len,
  1964. rsp, res);
  1965. break;
  1966. case CS_DATA_UNDERRUN:
  1967. /* Use F/W calculated residual length. */
  1968. resid = IS_FWI2_CAPABLE(ha) ? fw_resid_len : resid_len;
  1969. scsi_set_resid(cp, resid);
  1970. if (scsi_status & SS_RESIDUAL_UNDER) {
  1971. if (IS_FWI2_CAPABLE(ha) && fw_resid_len != resid_len) {
  1972. ql_dbg(ql_dbg_io, fcport->vha, 0x301d,
  1973. "Dropped frame(s) detected "
  1974. "(0x%x of 0x%x bytes).\n",
  1975. resid, scsi_bufflen(cp));
  1976. res = DID_ERROR << 16 | lscsi_status;
  1977. goto check_scsi_status;
  1978. }
  1979. if (!lscsi_status &&
  1980. ((unsigned)(scsi_bufflen(cp) - resid) <
  1981. cp->underflow)) {
  1982. ql_dbg(ql_dbg_io, fcport->vha, 0x301e,
  1983. "Mid-layer underflow "
  1984. "detected (0x%x of 0x%x bytes).\n",
  1985. resid, scsi_bufflen(cp));
  1986. res = DID_ERROR << 16;
  1987. break;
  1988. }
  1989. } else if (lscsi_status != SAM_STAT_TASK_SET_FULL &&
  1990. lscsi_status != SAM_STAT_BUSY) {
  1991. /*
  1992. * scsi status of task set and busy are considered to be
  1993. * task not completed.
  1994. */
  1995. ql_dbg(ql_dbg_io, fcport->vha, 0x301f,
  1996. "Dropped frame(s) detected (0x%x "
  1997. "of 0x%x bytes).\n", resid,
  1998. scsi_bufflen(cp));
  1999. res = DID_ERROR << 16 | lscsi_status;
  2000. goto check_scsi_status;
  2001. } else {
  2002. ql_dbg(ql_dbg_io, fcport->vha, 0x3030,
  2003. "scsi_status: 0x%x, lscsi_status: 0x%x\n",
  2004. scsi_status, lscsi_status);
  2005. }
  2006. res = DID_OK << 16 | lscsi_status;
  2007. logit = 0;
  2008. check_scsi_status:
  2009. /*
  2010. * Check to see if SCSI Status is non zero. If so report SCSI
  2011. * Status.
  2012. */
  2013. if (lscsi_status != 0) {
  2014. if (lscsi_status == SAM_STAT_TASK_SET_FULL) {
  2015. ql_dbg(ql_dbg_io, fcport->vha, 0x3020,
  2016. "QUEUE FULL detected.\n");
  2017. logit = 1;
  2018. break;
  2019. }
  2020. if (lscsi_status != SS_CHECK_CONDITION)
  2021. break;
  2022. memset(cp->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
  2023. if (!(scsi_status & SS_SENSE_LEN_VALID))
  2024. break;
  2025. qla2x00_handle_sense(sp, sense_data, par_sense_len,
  2026. sense_len, rsp, res);
  2027. }
  2028. break;
  2029. case CS_PORT_LOGGED_OUT:
  2030. case CS_PORT_CONFIG_CHG:
  2031. case CS_PORT_BUSY:
  2032. case CS_INCOMPLETE:
  2033. case CS_PORT_UNAVAILABLE:
  2034. case CS_TIMEOUT:
  2035. case CS_RESET:
  2036. /*
  2037. * We are going to have the fc class block the rport
  2038. * while we try to recover so instruct the mid layer
  2039. * to requeue until the class decides how to handle this.
  2040. */
  2041. res = DID_TRANSPORT_DISRUPTED << 16;
  2042. if (comp_status == CS_TIMEOUT) {
  2043. if (IS_FWI2_CAPABLE(ha))
  2044. break;
  2045. else if ((le16_to_cpu(sts->status_flags) &
  2046. SF_LOGOUT_SENT) == 0)
  2047. break;
  2048. }
  2049. ql_dbg(ql_dbg_io, fcport->vha, 0x3021,
  2050. "Port to be marked lost on fcport=%02x%02x%02x, current "
  2051. "port state= %s.\n", fcport->d_id.b.domain,
  2052. fcport->d_id.b.area, fcport->d_id.b.al_pa,
  2053. port_state_str[atomic_read(&fcport->state)]);
  2054. if (atomic_read(&fcport->state) == FCS_ONLINE)
  2055. qla2x00_mark_device_lost(fcport->vha, fcport, 1, 1);
  2056. break;
  2057. case CS_ABORTED:
  2058. res = DID_RESET << 16;
  2059. break;
  2060. case CS_DIF_ERROR:
  2061. logit = qla2x00_handle_dif_error(sp, sts24);
  2062. res = cp->result;
  2063. break;
  2064. case CS_TRANSPORT:
  2065. res = DID_ERROR << 16;
  2066. if (!IS_PI_SPLIT_DET_CAPABLE(ha))
  2067. break;
  2068. if (state_flags & BIT_4)
  2069. scmd_printk(KERN_WARNING, cp,
  2070. "Unsupported device '%s' found.\n",
  2071. cp->device->vendor);
  2072. break;
  2073. default:
  2074. res = DID_ERROR << 16;
  2075. break;
  2076. }
  2077. out:
  2078. if (logit)
  2079. ql_dbg(ql_dbg_io, fcport->vha, 0x3022,
  2080. "FCP command status: 0x%x-0x%x (0x%x) nexus=%ld:%d:%llu "
  2081. "portid=%02x%02x%02x oxid=0x%x cdb=%10phN len=0x%x "
  2082. "rsp_info=0x%x resid=0x%x fw_resid=0x%x sp=%p cp=%p.\n",
  2083. comp_status, scsi_status, res, vha->host_no,
  2084. cp->device->id, cp->device->lun, fcport->d_id.b.domain,
  2085. fcport->d_id.b.area, fcport->d_id.b.al_pa, ox_id,
  2086. cp->cmnd, scsi_bufflen(cp), rsp_info_len,
  2087. resid_len, fw_resid_len, sp, cp);
  2088. if (rsp->status_srb == NULL)
  2089. sp->done(ha, sp, res);
  2090. }
  2091. /**
  2092. * qla2x00_status_cont_entry() - Process a Status Continuations entry.
  2093. * @ha: SCSI driver HA context
  2094. * @pkt: Entry pointer
  2095. *
  2096. * Extended sense data.
  2097. */
  2098. static void
  2099. qla2x00_status_cont_entry(struct rsp_que *rsp, sts_cont_entry_t *pkt)
  2100. {
  2101. uint8_t sense_sz = 0;
  2102. struct qla_hw_data *ha = rsp->hw;
  2103. struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
  2104. srb_t *sp = rsp->status_srb;
  2105. struct scsi_cmnd *cp;
  2106. uint32_t sense_len;
  2107. uint8_t *sense_ptr;
  2108. if (!sp || !GET_CMD_SENSE_LEN(sp))
  2109. return;
  2110. sense_len = GET_CMD_SENSE_LEN(sp);
  2111. sense_ptr = GET_CMD_SENSE_PTR(sp);
  2112. cp = GET_CMD_SP(sp);
  2113. if (cp == NULL) {
  2114. ql_log(ql_log_warn, vha, 0x3025,
  2115. "cmd is NULL: already returned to OS (sp=%p).\n", sp);
  2116. rsp->status_srb = NULL;
  2117. return;
  2118. }
  2119. if (sense_len > sizeof(pkt->data))
  2120. sense_sz = sizeof(pkt->data);
  2121. else
  2122. sense_sz = sense_len;
  2123. /* Move sense data. */
  2124. if (IS_FWI2_CAPABLE(ha))
  2125. host_to_fcp_swap(pkt->data, sizeof(pkt->data));
  2126. memcpy(sense_ptr, pkt->data, sense_sz);
  2127. ql_dump_buffer(ql_dbg_io + ql_dbg_buffer, vha, 0x302c,
  2128. sense_ptr, sense_sz);
  2129. sense_len -= sense_sz;
  2130. sense_ptr += sense_sz;
  2131. SET_CMD_SENSE_PTR(sp, sense_ptr);
  2132. SET_CMD_SENSE_LEN(sp, sense_len);
  2133. /* Place command on done queue. */
  2134. if (sense_len == 0) {
  2135. rsp->status_srb = NULL;
  2136. sp->done(ha, sp, cp->result);
  2137. }
  2138. }
  2139. /**
  2140. * qla2x00_error_entry() - Process an error entry.
  2141. * @ha: SCSI driver HA context
  2142. * @pkt: Entry pointer
  2143. */
  2144. static void
  2145. qla2x00_error_entry(scsi_qla_host_t *vha, struct rsp_que *rsp, sts_entry_t *pkt)
  2146. {
  2147. srb_t *sp;
  2148. struct qla_hw_data *ha = vha->hw;
  2149. const char func[] = "ERROR-IOCB";
  2150. uint16_t que = MSW(pkt->handle);
  2151. struct req_que *req = NULL;
  2152. int res = DID_ERROR << 16;
  2153. ql_dbg(ql_dbg_async, vha, 0x502a,
  2154. "type of error status in response: 0x%x\n", pkt->entry_status);
  2155. if (que >= ha->max_req_queues || !ha->req_q_map[que])
  2156. goto fatal;
  2157. req = ha->req_q_map[que];
  2158. if (pkt->entry_status & RF_BUSY)
  2159. res = DID_BUS_BUSY << 16;
  2160. if (pkt->entry_type == NOTIFY_ACK_TYPE &&
  2161. pkt->handle == QLA_TGT_SKIP_HANDLE)
  2162. return;
  2163. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2164. if (sp) {
  2165. sp->done(ha, sp, res);
  2166. return;
  2167. }
  2168. fatal:
  2169. ql_log(ql_log_warn, vha, 0x5030,
  2170. "Error entry - invalid handle/queue (%04x).\n", que);
  2171. }
  2172. /**
  2173. * qla24xx_mbx_completion() - Process mailbox command completions.
  2174. * @ha: SCSI driver HA context
  2175. * @mb0: Mailbox0 register
  2176. */
  2177. static void
  2178. qla24xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
  2179. {
  2180. uint16_t cnt;
  2181. uint32_t mboxes;
  2182. uint16_t __iomem *wptr;
  2183. struct qla_hw_data *ha = vha->hw;
  2184. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2185. /* Read all mbox registers? */
  2186. WARN_ON_ONCE(ha->mbx_count > 32);
  2187. mboxes = (1ULL << ha->mbx_count) - 1;
  2188. if (!ha->mcp)
  2189. ql_dbg(ql_dbg_async, vha, 0x504e, "MBX pointer ERROR.\n");
  2190. else
  2191. mboxes = ha->mcp->in_mb;
  2192. /* Load return mailbox registers. */
  2193. ha->flags.mbox_int = 1;
  2194. ha->mailbox_out[0] = mb0;
  2195. mboxes >>= 1;
  2196. wptr = (uint16_t __iomem *)&reg->mailbox1;
  2197. for (cnt = 1; cnt < ha->mbx_count; cnt++) {
  2198. if (mboxes & BIT_0)
  2199. ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
  2200. mboxes >>= 1;
  2201. wptr++;
  2202. }
  2203. }
  2204. static void
  2205. qla24xx_abort_iocb_entry(scsi_qla_host_t *vha, struct req_que *req,
  2206. struct abort_entry_24xx *pkt)
  2207. {
  2208. const char func[] = "ABT_IOCB";
  2209. srb_t *sp;
  2210. struct srb_iocb *abt;
  2211. sp = qla2x00_get_sp_from_handle(vha, func, req, pkt);
  2212. if (!sp)
  2213. return;
  2214. abt = &sp->u.iocb_cmd;
  2215. abt->u.abt.comp_status = le32_to_cpu(pkt->nport_handle);
  2216. sp->done(vha, sp, 0);
  2217. }
  2218. /**
  2219. * qla24xx_process_response_queue() - Process response queue entries.
  2220. * @ha: SCSI driver HA context
  2221. */
  2222. void qla24xx_process_response_queue(struct scsi_qla_host *vha,
  2223. struct rsp_que *rsp)
  2224. {
  2225. struct sts_entry_24xx *pkt;
  2226. struct qla_hw_data *ha = vha->hw;
  2227. if (!vha->flags.online)
  2228. return;
  2229. while (rsp->ring_ptr->signature != RESPONSE_PROCESSED) {
  2230. pkt = (struct sts_entry_24xx *)rsp->ring_ptr;
  2231. rsp->ring_index++;
  2232. if (rsp->ring_index == rsp->length) {
  2233. rsp->ring_index = 0;
  2234. rsp->ring_ptr = rsp->ring;
  2235. } else {
  2236. rsp->ring_ptr++;
  2237. }
  2238. if (pkt->entry_status != 0) {
  2239. qla2x00_error_entry(vha, rsp, (sts_entry_t *) pkt);
  2240. if (qlt_24xx_process_response_error(vha, pkt))
  2241. goto process_err;
  2242. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2243. wmb();
  2244. continue;
  2245. }
  2246. process_err:
  2247. switch (pkt->entry_type) {
  2248. case STATUS_TYPE:
  2249. qla2x00_status_entry(vha, rsp, pkt);
  2250. break;
  2251. case STATUS_CONT_TYPE:
  2252. qla2x00_status_cont_entry(rsp, (sts_cont_entry_t *)pkt);
  2253. break;
  2254. case VP_RPT_ID_IOCB_TYPE:
  2255. qla24xx_report_id_acquisition(vha,
  2256. (struct vp_rpt_id_entry_24xx *)pkt);
  2257. break;
  2258. case LOGINOUT_PORT_IOCB_TYPE:
  2259. qla24xx_logio_entry(vha, rsp->req,
  2260. (struct logio_entry_24xx *)pkt);
  2261. break;
  2262. case CT_IOCB_TYPE:
  2263. qla24xx_els_ct_entry(vha, rsp->req, pkt, CT_IOCB_TYPE);
  2264. break;
  2265. case ELS_IOCB_TYPE:
  2266. qla24xx_els_ct_entry(vha, rsp->req, pkt, ELS_IOCB_TYPE);
  2267. break;
  2268. case ABTS_RECV_24XX:
  2269. /* ensure that the ATIO queue is empty */
  2270. qlt_24xx_process_atio_queue(vha);
  2271. case ABTS_RESP_24XX:
  2272. case CTIO_TYPE7:
  2273. case NOTIFY_ACK_TYPE:
  2274. case CTIO_CRC2:
  2275. qlt_response_pkt_all_vps(vha, (response_t *)pkt);
  2276. break;
  2277. case MARKER_TYPE:
  2278. /* Do nothing in this case, this check is to prevent it
  2279. * from falling into default case
  2280. */
  2281. break;
  2282. case ABORT_IOCB_TYPE:
  2283. qla24xx_abort_iocb_entry(vha, rsp->req,
  2284. (struct abort_entry_24xx *)pkt);
  2285. break;
  2286. default:
  2287. /* Type Not Supported. */
  2288. ql_dbg(ql_dbg_async, vha, 0x5042,
  2289. "Received unknown response pkt type %x "
  2290. "entry status=%x.\n",
  2291. pkt->entry_type, pkt->entry_status);
  2292. break;
  2293. }
  2294. ((response_t *)pkt)->signature = RESPONSE_PROCESSED;
  2295. wmb();
  2296. }
  2297. /* Adjust ring index */
  2298. if (IS_P3P_TYPE(ha)) {
  2299. struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
  2300. WRT_REG_DWORD(&reg->rsp_q_out[0], rsp->ring_index);
  2301. } else
  2302. WRT_REG_DWORD(rsp->rsp_q_out, rsp->ring_index);
  2303. }
  2304. static void
  2305. qla2xxx_check_risc_status(scsi_qla_host_t *vha)
  2306. {
  2307. int rval;
  2308. uint32_t cnt;
  2309. struct qla_hw_data *ha = vha->hw;
  2310. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  2311. if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
  2312. !IS_QLA27XX(ha))
  2313. return;
  2314. rval = QLA_SUCCESS;
  2315. WRT_REG_DWORD(&reg->iobase_addr, 0x7C00);
  2316. RD_REG_DWORD(&reg->iobase_addr);
  2317. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2318. for (cnt = 10000; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2319. rval == QLA_SUCCESS; cnt--) {
  2320. if (cnt) {
  2321. WRT_REG_DWORD(&reg->iobase_window, 0x0001);
  2322. udelay(10);
  2323. } else
  2324. rval = QLA_FUNCTION_TIMEOUT;
  2325. }
  2326. if (rval == QLA_SUCCESS)
  2327. goto next_test;
  2328. rval = QLA_SUCCESS;
  2329. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2330. for (cnt = 100; (RD_REG_DWORD(&reg->iobase_window) & BIT_0) == 0 &&
  2331. rval == QLA_SUCCESS; cnt--) {
  2332. if (cnt) {
  2333. WRT_REG_DWORD(&reg->iobase_window, 0x0003);
  2334. udelay(10);
  2335. } else
  2336. rval = QLA_FUNCTION_TIMEOUT;
  2337. }
  2338. if (rval != QLA_SUCCESS)
  2339. goto done;
  2340. next_test:
  2341. if (RD_REG_DWORD(&reg->iobase_c8) & BIT_3)
  2342. ql_log(ql_log_info, vha, 0x504c,
  2343. "Additional code -- 0x55AA.\n");
  2344. done:
  2345. WRT_REG_DWORD(&reg->iobase_window, 0x0000);
  2346. RD_REG_DWORD(&reg->iobase_window);
  2347. }
  2348. /**
  2349. * qla24xx_intr_handler() - Process interrupts for the ISP23xx and ISP24xx.
  2350. * @irq:
  2351. * @dev_id: SCSI driver HA context
  2352. *
  2353. * Called by system whenever the host adapter generates an interrupt.
  2354. *
  2355. * Returns handled flag.
  2356. */
  2357. irqreturn_t
  2358. qla24xx_intr_handler(int irq, void *dev_id)
  2359. {
  2360. scsi_qla_host_t *vha;
  2361. struct qla_hw_data *ha;
  2362. struct device_reg_24xx __iomem *reg;
  2363. int status;
  2364. unsigned long iter;
  2365. uint32_t stat;
  2366. uint32_t hccr;
  2367. uint16_t mb[8];
  2368. struct rsp_que *rsp;
  2369. unsigned long flags;
  2370. rsp = (struct rsp_que *) dev_id;
  2371. if (!rsp) {
  2372. ql_log(ql_log_info, NULL, 0x5059,
  2373. "%s: NULL response queue pointer.\n", __func__);
  2374. return IRQ_NONE;
  2375. }
  2376. ha = rsp->hw;
  2377. reg = &ha->iobase->isp24;
  2378. status = 0;
  2379. if (unlikely(pci_channel_offline(ha->pdev)))
  2380. return IRQ_HANDLED;
  2381. spin_lock_irqsave(&ha->hardware_lock, flags);
  2382. vha = pci_get_drvdata(ha->pdev);
  2383. for (iter = 50; iter--; ) {
  2384. stat = RD_REG_DWORD(&reg->host_status);
  2385. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2386. break;
  2387. if (stat & HSRX_RISC_PAUSED) {
  2388. if (unlikely(pci_channel_offline(ha->pdev)))
  2389. break;
  2390. hccr = RD_REG_DWORD(&reg->hccr);
  2391. ql_log(ql_log_warn, vha, 0x504b,
  2392. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2393. hccr);
  2394. qla2xxx_check_risc_status(vha);
  2395. ha->isp_ops->fw_dump(vha, 1);
  2396. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2397. break;
  2398. } else if ((stat & HSRX_RISC_INT) == 0)
  2399. break;
  2400. switch (stat & 0xff) {
  2401. case INTR_ROM_MB_SUCCESS:
  2402. case INTR_ROM_MB_FAILED:
  2403. case INTR_MB_SUCCESS:
  2404. case INTR_MB_FAILED:
  2405. qla24xx_mbx_completion(vha, MSW(stat));
  2406. status |= MBX_INTERRUPT;
  2407. break;
  2408. case INTR_ASYNC_EVENT:
  2409. mb[0] = MSW(stat);
  2410. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2411. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2412. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2413. qla2x00_async_event(vha, rsp, mb);
  2414. break;
  2415. case INTR_RSP_QUE_UPDATE:
  2416. case INTR_RSP_QUE_UPDATE_83XX:
  2417. qla24xx_process_response_queue(vha, rsp);
  2418. break;
  2419. case INTR_ATIO_QUE_UPDATE:
  2420. qlt_24xx_process_atio_queue(vha);
  2421. break;
  2422. case INTR_ATIO_RSP_QUE_UPDATE:
  2423. qlt_24xx_process_atio_queue(vha);
  2424. qla24xx_process_response_queue(vha, rsp);
  2425. break;
  2426. default:
  2427. ql_dbg(ql_dbg_async, vha, 0x504f,
  2428. "Unrecognized interrupt type (%d).\n", stat * 0xff);
  2429. break;
  2430. }
  2431. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2432. RD_REG_DWORD_RELAXED(&reg->hccr);
  2433. if (unlikely(IS_QLA83XX(ha) && (ha->pdev->revision == 1)))
  2434. ndelay(3500);
  2435. }
  2436. qla2x00_handle_mbx_completion(ha, status);
  2437. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2438. return IRQ_HANDLED;
  2439. }
  2440. static irqreturn_t
  2441. qla24xx_msix_rsp_q(int irq, void *dev_id)
  2442. {
  2443. struct qla_hw_data *ha;
  2444. struct rsp_que *rsp;
  2445. struct device_reg_24xx __iomem *reg;
  2446. struct scsi_qla_host *vha;
  2447. unsigned long flags;
  2448. uint32_t stat = 0;
  2449. rsp = (struct rsp_que *) dev_id;
  2450. if (!rsp) {
  2451. ql_log(ql_log_info, NULL, 0x505a,
  2452. "%s: NULL response queue pointer.\n", __func__);
  2453. return IRQ_NONE;
  2454. }
  2455. ha = rsp->hw;
  2456. reg = &ha->iobase->isp24;
  2457. spin_lock_irqsave(&ha->hardware_lock, flags);
  2458. vha = pci_get_drvdata(ha->pdev);
  2459. /*
  2460. * Use host_status register to check to PCI disconnection before we
  2461. * we process the response queue.
  2462. */
  2463. stat = RD_REG_DWORD(&reg->host_status);
  2464. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2465. goto out;
  2466. qla24xx_process_response_queue(vha, rsp);
  2467. if (!ha->flags.disable_msix_handshake) {
  2468. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2469. RD_REG_DWORD_RELAXED(&reg->hccr);
  2470. }
  2471. out:
  2472. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2473. return IRQ_HANDLED;
  2474. }
  2475. static irqreturn_t
  2476. qla25xx_msix_rsp_q(int irq, void *dev_id)
  2477. {
  2478. struct qla_hw_data *ha;
  2479. scsi_qla_host_t *vha;
  2480. struct rsp_que *rsp;
  2481. struct device_reg_24xx __iomem *reg;
  2482. unsigned long flags;
  2483. uint32_t hccr = 0;
  2484. rsp = (struct rsp_que *) dev_id;
  2485. if (!rsp) {
  2486. ql_log(ql_log_info, NULL, 0x505b,
  2487. "%s: NULL response queue pointer.\n", __func__);
  2488. return IRQ_NONE;
  2489. }
  2490. ha = rsp->hw;
  2491. vha = pci_get_drvdata(ha->pdev);
  2492. /* Clear the interrupt, if enabled, for this response queue */
  2493. if (!ha->flags.disable_msix_handshake) {
  2494. reg = &ha->iobase->isp24;
  2495. spin_lock_irqsave(&ha->hardware_lock, flags);
  2496. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2497. hccr = RD_REG_DWORD_RELAXED(&reg->hccr);
  2498. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2499. }
  2500. if (qla2x00_check_reg32_for_disconnect(vha, hccr))
  2501. goto out;
  2502. queue_work_on((int) (rsp->id - 1), ha->wq, &rsp->q_work);
  2503. out:
  2504. return IRQ_HANDLED;
  2505. }
  2506. static irqreturn_t
  2507. qla24xx_msix_default(int irq, void *dev_id)
  2508. {
  2509. scsi_qla_host_t *vha;
  2510. struct qla_hw_data *ha;
  2511. struct rsp_que *rsp;
  2512. struct device_reg_24xx __iomem *reg;
  2513. int status;
  2514. uint32_t stat;
  2515. uint32_t hccr;
  2516. uint16_t mb[8];
  2517. unsigned long flags;
  2518. rsp = (struct rsp_que *) dev_id;
  2519. if (!rsp) {
  2520. ql_log(ql_log_info, NULL, 0x505c,
  2521. "%s: NULL response queue pointer.\n", __func__);
  2522. return IRQ_NONE;
  2523. }
  2524. ha = rsp->hw;
  2525. reg = &ha->iobase->isp24;
  2526. status = 0;
  2527. spin_lock_irqsave(&ha->hardware_lock, flags);
  2528. vha = pci_get_drvdata(ha->pdev);
  2529. do {
  2530. stat = RD_REG_DWORD(&reg->host_status);
  2531. if (qla2x00_check_reg32_for_disconnect(vha, stat))
  2532. break;
  2533. if (stat & HSRX_RISC_PAUSED) {
  2534. if (unlikely(pci_channel_offline(ha->pdev)))
  2535. break;
  2536. hccr = RD_REG_DWORD(&reg->hccr);
  2537. ql_log(ql_log_info, vha, 0x5050,
  2538. "RISC paused -- HCCR=%x, Dumping firmware.\n",
  2539. hccr);
  2540. qla2xxx_check_risc_status(vha);
  2541. ha->isp_ops->fw_dump(vha, 1);
  2542. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  2543. break;
  2544. } else if ((stat & HSRX_RISC_INT) == 0)
  2545. break;
  2546. switch (stat & 0xff) {
  2547. case INTR_ROM_MB_SUCCESS:
  2548. case INTR_ROM_MB_FAILED:
  2549. case INTR_MB_SUCCESS:
  2550. case INTR_MB_FAILED:
  2551. qla24xx_mbx_completion(vha, MSW(stat));
  2552. status |= MBX_INTERRUPT;
  2553. break;
  2554. case INTR_ASYNC_EVENT:
  2555. mb[0] = MSW(stat);
  2556. mb[1] = RD_REG_WORD(&reg->mailbox1);
  2557. mb[2] = RD_REG_WORD(&reg->mailbox2);
  2558. mb[3] = RD_REG_WORD(&reg->mailbox3);
  2559. qla2x00_async_event(vha, rsp, mb);
  2560. break;
  2561. case INTR_RSP_QUE_UPDATE:
  2562. case INTR_RSP_QUE_UPDATE_83XX:
  2563. qla24xx_process_response_queue(vha, rsp);
  2564. break;
  2565. case INTR_ATIO_QUE_UPDATE:
  2566. qlt_24xx_process_atio_queue(vha);
  2567. break;
  2568. case INTR_ATIO_RSP_QUE_UPDATE:
  2569. qlt_24xx_process_atio_queue(vha);
  2570. qla24xx_process_response_queue(vha, rsp);
  2571. break;
  2572. default:
  2573. ql_dbg(ql_dbg_async, vha, 0x5051,
  2574. "Unrecognized interrupt type (%d).\n", stat & 0xff);
  2575. break;
  2576. }
  2577. WRT_REG_DWORD(&reg->hccr, HCCRX_CLR_RISC_INT);
  2578. } while (0);
  2579. qla2x00_handle_mbx_completion(ha, status);
  2580. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2581. return IRQ_HANDLED;
  2582. }
  2583. /* Interrupt handling helpers. */
  2584. struct qla_init_msix_entry {
  2585. const char *name;
  2586. irq_handler_t handler;
  2587. };
  2588. static struct qla_init_msix_entry msix_entries[3] = {
  2589. { "qla2xxx (default)", qla24xx_msix_default },
  2590. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2591. { "qla2xxx (multiq)", qla25xx_msix_rsp_q },
  2592. };
  2593. static struct qla_init_msix_entry qla82xx_msix_entries[2] = {
  2594. { "qla2xxx (default)", qla82xx_msix_default },
  2595. { "qla2xxx (rsp_q)", qla82xx_msix_rsp_q },
  2596. };
  2597. static struct qla_init_msix_entry qla83xx_msix_entries[3] = {
  2598. { "qla2xxx (default)", qla24xx_msix_default },
  2599. { "qla2xxx (rsp_q)", qla24xx_msix_rsp_q },
  2600. { "qla2xxx (atio_q)", qla83xx_msix_atio_q },
  2601. };
  2602. static void
  2603. qla24xx_disable_msix(struct qla_hw_data *ha)
  2604. {
  2605. int i;
  2606. struct qla_msix_entry *qentry;
  2607. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2608. for (i = 0; i < ha->msix_count; i++) {
  2609. qentry = &ha->msix_entries[i];
  2610. if (qentry->have_irq)
  2611. free_irq(qentry->vector, qentry->rsp);
  2612. }
  2613. pci_disable_msix(ha->pdev);
  2614. kfree(ha->msix_entries);
  2615. ha->msix_entries = NULL;
  2616. ha->flags.msix_enabled = 0;
  2617. ql_dbg(ql_dbg_init, vha, 0x0042,
  2618. "Disabled the MSI.\n");
  2619. }
  2620. static int
  2621. qla24xx_enable_msix(struct qla_hw_data *ha, struct rsp_que *rsp)
  2622. {
  2623. #define MIN_MSIX_COUNT 2
  2624. #define ATIO_VECTOR 2
  2625. int i, ret;
  2626. struct msix_entry *entries;
  2627. struct qla_msix_entry *qentry;
  2628. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2629. entries = kzalloc(sizeof(struct msix_entry) * ha->msix_count,
  2630. GFP_KERNEL);
  2631. if (!entries) {
  2632. ql_log(ql_log_warn, vha, 0x00bc,
  2633. "Failed to allocate memory for msix_entry.\n");
  2634. return -ENOMEM;
  2635. }
  2636. for (i = 0; i < ha->msix_count; i++)
  2637. entries[i].entry = i;
  2638. ret = pci_enable_msix_range(ha->pdev,
  2639. entries, MIN_MSIX_COUNT, ha->msix_count);
  2640. if (ret < 0) {
  2641. ql_log(ql_log_fatal, vha, 0x00c7,
  2642. "MSI-X: Failed to enable support, "
  2643. "giving up -- %d/%d.\n",
  2644. ha->msix_count, ret);
  2645. goto msix_out;
  2646. } else if (ret < ha->msix_count) {
  2647. ql_log(ql_log_warn, vha, 0x00c6,
  2648. "MSI-X: Failed to enable support "
  2649. "-- %d/%d\n Retry with %d vectors.\n",
  2650. ha->msix_count, ret, ret);
  2651. ha->msix_count = ret;
  2652. ha->max_rsp_queues = ha->msix_count - 1;
  2653. }
  2654. ha->msix_entries = kzalloc(sizeof(struct qla_msix_entry) *
  2655. ha->msix_count, GFP_KERNEL);
  2656. if (!ha->msix_entries) {
  2657. ql_log(ql_log_fatal, vha, 0x00c8,
  2658. "Failed to allocate memory for ha->msix_entries.\n");
  2659. ret = -ENOMEM;
  2660. goto msix_out;
  2661. }
  2662. ha->flags.msix_enabled = 1;
  2663. for (i = 0; i < ha->msix_count; i++) {
  2664. qentry = &ha->msix_entries[i];
  2665. qentry->vector = entries[i].vector;
  2666. qentry->entry = entries[i].entry;
  2667. qentry->have_irq = 0;
  2668. qentry->rsp = NULL;
  2669. }
  2670. /* Enable MSI-X vectors for the base queue */
  2671. for (i = 0; i < 2; i++) {
  2672. qentry = &ha->msix_entries[i];
  2673. if (IS_P3P_TYPE(ha))
  2674. ret = request_irq(qentry->vector,
  2675. qla82xx_msix_entries[i].handler,
  2676. 0, qla82xx_msix_entries[i].name, rsp);
  2677. else
  2678. ret = request_irq(qentry->vector,
  2679. msix_entries[i].handler,
  2680. 0, msix_entries[i].name, rsp);
  2681. if (ret)
  2682. goto msix_register_fail;
  2683. qentry->have_irq = 1;
  2684. qentry->rsp = rsp;
  2685. rsp->msix = qentry;
  2686. }
  2687. /*
  2688. * If target mode is enable, also request the vector for the ATIO
  2689. * queue.
  2690. */
  2691. if (QLA_TGT_MODE_ENABLED() && IS_ATIO_MSIX_CAPABLE(ha)) {
  2692. qentry = &ha->msix_entries[ATIO_VECTOR];
  2693. ret = request_irq(qentry->vector,
  2694. qla83xx_msix_entries[ATIO_VECTOR].handler,
  2695. 0, qla83xx_msix_entries[ATIO_VECTOR].name, rsp);
  2696. qentry->have_irq = 1;
  2697. qentry->rsp = rsp;
  2698. rsp->msix = qentry;
  2699. }
  2700. msix_register_fail:
  2701. if (ret) {
  2702. ql_log(ql_log_fatal, vha, 0x00cb,
  2703. "MSI-X: unable to register handler -- %x/%d.\n",
  2704. qentry->vector, ret);
  2705. qla24xx_disable_msix(ha);
  2706. ha->mqenable = 0;
  2707. goto msix_out;
  2708. }
  2709. /* Enable MSI-X vector for response queue update for queue 0 */
  2710. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  2711. if (ha->msixbase && ha->mqiobase &&
  2712. (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2713. ha->mqenable = 1;
  2714. } else
  2715. if (ha->mqiobase
  2716. && (ha->max_rsp_queues > 1 || ha->max_req_queues > 1))
  2717. ha->mqenable = 1;
  2718. ql_dbg(ql_dbg_multiq, vha, 0xc005,
  2719. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2720. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2721. ql_dbg(ql_dbg_init, vha, 0x0055,
  2722. "mqiobase=%p, max_rsp_queues=%d, max_req_queues=%d.\n",
  2723. ha->mqiobase, ha->max_rsp_queues, ha->max_req_queues);
  2724. msix_out:
  2725. kfree(entries);
  2726. return ret;
  2727. }
  2728. int
  2729. qla2x00_request_irqs(struct qla_hw_data *ha, struct rsp_que *rsp)
  2730. {
  2731. int ret = QLA_FUNCTION_FAILED;
  2732. device_reg_t *reg = ha->iobase;
  2733. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2734. /* If possible, enable MSI-X. */
  2735. if (!IS_QLA2432(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2736. !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && !IS_QLAFX00(ha) &&
  2737. !IS_QLA27XX(ha))
  2738. goto skip_msi;
  2739. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  2740. (ha->pdev->subsystem_device == 0x7040 ||
  2741. ha->pdev->subsystem_device == 0x7041 ||
  2742. ha->pdev->subsystem_device == 0x1705)) {
  2743. ql_log(ql_log_warn, vha, 0x0034,
  2744. "MSI-X: Unsupported ISP 2432 SSVID/SSDID (0x%X,0x%X).\n",
  2745. ha->pdev->subsystem_vendor,
  2746. ha->pdev->subsystem_device);
  2747. goto skip_msi;
  2748. }
  2749. if (IS_QLA2432(ha) && (ha->pdev->revision < QLA_MSIX_CHIP_REV_24XX)) {
  2750. ql_log(ql_log_warn, vha, 0x0035,
  2751. "MSI-X; Unsupported ISP2432 (0x%X, 0x%X).\n",
  2752. ha->pdev->revision, QLA_MSIX_CHIP_REV_24XX);
  2753. goto skip_msix;
  2754. }
  2755. ret = qla24xx_enable_msix(ha, rsp);
  2756. if (!ret) {
  2757. ql_dbg(ql_dbg_init, vha, 0x0036,
  2758. "MSI-X: Enabled (0x%X, 0x%X).\n",
  2759. ha->chip_revision, ha->fw_attributes);
  2760. goto clear_risc_ints;
  2761. }
  2762. skip_msix:
  2763. ql_log(ql_log_info, vha, 0x0037,
  2764. "Falling back-to MSI mode -%d.\n", ret);
  2765. if (!IS_QLA24XX(ha) && !IS_QLA2532(ha) && !IS_QLA8432(ha) &&
  2766. !IS_QLA8001(ha) && !IS_P3P_TYPE(ha) && !IS_QLAFX00(ha) &&
  2767. !IS_QLA27XX(ha))
  2768. goto skip_msi;
  2769. ret = pci_enable_msi(ha->pdev);
  2770. if (!ret) {
  2771. ql_dbg(ql_dbg_init, vha, 0x0038,
  2772. "MSI: Enabled.\n");
  2773. ha->flags.msi_enabled = 1;
  2774. } else
  2775. ql_log(ql_log_warn, vha, 0x0039,
  2776. "Falling back-to INTa mode -- %d.\n", ret);
  2777. skip_msi:
  2778. /* Skip INTx on ISP82xx. */
  2779. if (!ha->flags.msi_enabled && IS_QLA82XX(ha))
  2780. return QLA_FUNCTION_FAILED;
  2781. ret = request_irq(ha->pdev->irq, ha->isp_ops->intr_handler,
  2782. ha->flags.msi_enabled ? 0 : IRQF_SHARED,
  2783. QLA2XXX_DRIVER_NAME, rsp);
  2784. if (ret) {
  2785. ql_log(ql_log_warn, vha, 0x003a,
  2786. "Failed to reserve interrupt %d already in use.\n",
  2787. ha->pdev->irq);
  2788. goto fail;
  2789. } else if (!ha->flags.msi_enabled) {
  2790. ql_dbg(ql_dbg_init, vha, 0x0125,
  2791. "INTa mode: Enabled.\n");
  2792. ha->flags.mr_intr_valid = 1;
  2793. }
  2794. clear_risc_ints:
  2795. if (IS_FWI2_CAPABLE(ha) || IS_QLAFX00(ha))
  2796. goto fail;
  2797. spin_lock_irq(&ha->hardware_lock);
  2798. WRT_REG_WORD(&reg->isp.semaphore, 0);
  2799. spin_unlock_irq(&ha->hardware_lock);
  2800. fail:
  2801. return ret;
  2802. }
  2803. void
  2804. qla2x00_free_irqs(scsi_qla_host_t *vha)
  2805. {
  2806. struct qla_hw_data *ha = vha->hw;
  2807. struct rsp_que *rsp;
  2808. /*
  2809. * We need to check that ha->rsp_q_map is valid in case we are called
  2810. * from a probe failure context.
  2811. */
  2812. if (!ha->rsp_q_map || !ha->rsp_q_map[0])
  2813. return;
  2814. rsp = ha->rsp_q_map[0];
  2815. if (ha->flags.msix_enabled)
  2816. qla24xx_disable_msix(ha);
  2817. else if (ha->flags.msi_enabled) {
  2818. free_irq(ha->pdev->irq, rsp);
  2819. pci_disable_msi(ha->pdev);
  2820. } else
  2821. free_irq(ha->pdev->irq, rsp);
  2822. }
  2823. int qla25xx_request_irq(struct rsp_que *rsp)
  2824. {
  2825. struct qla_hw_data *ha = rsp->hw;
  2826. struct qla_init_msix_entry *intr = &msix_entries[2];
  2827. struct qla_msix_entry *msix = rsp->msix;
  2828. scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
  2829. int ret;
  2830. ret = request_irq(msix->vector, intr->handler, 0, intr->name, rsp);
  2831. if (ret) {
  2832. ql_log(ql_log_fatal, vha, 0x00e6,
  2833. "MSI-X: Unable to register handler -- %x/%d.\n",
  2834. msix->vector, ret);
  2835. return ret;
  2836. }
  2837. msix->have_irq = 1;
  2838. msix->rsp = rsp;
  2839. return ret;
  2840. }