qla_mbx.c 135 KB

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  1. /*
  2. * QLogic Fibre Channel HBA Driver
  3. * Copyright (c) 2003-2014 QLogic Corporation
  4. *
  5. * See LICENSE.qla2xxx for copyright and licensing details.
  6. */
  7. #include "qla_def.h"
  8. #include "qla_target.h"
  9. #include <linux/delay.h>
  10. #include <linux/gfp.h>
  11. /*
  12. * qla2x00_mailbox_command
  13. * Issue mailbox command and waits for completion.
  14. *
  15. * Input:
  16. * ha = adapter block pointer.
  17. * mcp = driver internal mbx struct pointer.
  18. *
  19. * Output:
  20. * mb[MAX_MAILBOX_REGISTER_COUNT] = returned mailbox data.
  21. *
  22. * Returns:
  23. * 0 : QLA_SUCCESS = cmd performed success
  24. * 1 : QLA_FUNCTION_FAILED (error encountered)
  25. * 6 : QLA_FUNCTION_TIMEOUT (timeout condition encountered)
  26. *
  27. * Context:
  28. * Kernel context.
  29. */
  30. static int
  31. qla2x00_mailbox_command(scsi_qla_host_t *vha, mbx_cmd_t *mcp)
  32. {
  33. int rval, i;
  34. unsigned long flags = 0;
  35. device_reg_t *reg;
  36. uint8_t abort_active;
  37. uint8_t io_lock_on;
  38. uint16_t command = 0;
  39. uint16_t *iptr;
  40. uint16_t __iomem *optr;
  41. uint32_t cnt;
  42. uint32_t mboxes;
  43. uint16_t __iomem *mbx_reg;
  44. unsigned long wait_time;
  45. struct qla_hw_data *ha = vha->hw;
  46. scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
  47. ql_dbg(ql_dbg_mbx, vha, 0x1000, "Entered %s.\n", __func__);
  48. if (ha->pdev->error_state > pci_channel_io_frozen) {
  49. ql_log(ql_log_warn, vha, 0x1001,
  50. "error_state is greater than pci_channel_io_frozen, "
  51. "exiting.\n");
  52. return QLA_FUNCTION_TIMEOUT;
  53. }
  54. if (vha->device_flags & DFLG_DEV_FAILED) {
  55. ql_log(ql_log_warn, vha, 0x1002,
  56. "Device in failed state, exiting.\n");
  57. return QLA_FUNCTION_TIMEOUT;
  58. }
  59. reg = ha->iobase;
  60. io_lock_on = base_vha->flags.init_done;
  61. rval = QLA_SUCCESS;
  62. abort_active = test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
  63. if (ha->flags.pci_channel_io_perm_failure) {
  64. ql_log(ql_log_warn, vha, 0x1003,
  65. "Perm failure on EEH timeout MBX, exiting.\n");
  66. return QLA_FUNCTION_TIMEOUT;
  67. }
  68. if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
  69. /* Setting Link-Down error */
  70. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  71. ql_log(ql_log_warn, vha, 0x1004,
  72. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  73. return QLA_FUNCTION_TIMEOUT;
  74. }
  75. /*
  76. * Wait for active mailbox commands to finish by waiting at most tov
  77. * seconds. This is to serialize actual issuing of mailbox cmds during
  78. * non ISP abort time.
  79. */
  80. if (!wait_for_completion_timeout(&ha->mbx_cmd_comp, mcp->tov * HZ)) {
  81. /* Timeout occurred. Return error. */
  82. ql_log(ql_log_warn, vha, 0x1005,
  83. "Cmd access timeout, cmd=0x%x, Exiting.\n",
  84. mcp->mb[0]);
  85. return QLA_FUNCTION_TIMEOUT;
  86. }
  87. ha->flags.mbox_busy = 1;
  88. /* Save mailbox command for debug */
  89. ha->mcp = mcp;
  90. ql_dbg(ql_dbg_mbx, vha, 0x1006,
  91. "Prepare to issue mbox cmd=0x%x.\n", mcp->mb[0]);
  92. spin_lock_irqsave(&ha->hardware_lock, flags);
  93. /* Load mailbox registers. */
  94. if (IS_P3P_TYPE(ha))
  95. optr = (uint16_t __iomem *)&reg->isp82.mailbox_in[0];
  96. else if (IS_FWI2_CAPABLE(ha) && !(IS_P3P_TYPE(ha)))
  97. optr = (uint16_t __iomem *)&reg->isp24.mailbox0;
  98. else
  99. optr = (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 0);
  100. iptr = mcp->mb;
  101. command = mcp->mb[0];
  102. mboxes = mcp->out_mb;
  103. ql_dbg(ql_dbg_mbx, vha, 0x1111,
  104. "Mailbox registers (OUT):\n");
  105. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  106. if (IS_QLA2200(ha) && cnt == 8)
  107. optr =
  108. (uint16_t __iomem *)MAILBOX_REG(ha, &reg->isp, 8);
  109. if (mboxes & BIT_0) {
  110. ql_dbg(ql_dbg_mbx, vha, 0x1112,
  111. "mbox[%d]<-0x%04x\n", cnt, *iptr);
  112. WRT_REG_WORD(optr, *iptr);
  113. }
  114. mboxes >>= 1;
  115. optr++;
  116. iptr++;
  117. }
  118. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1117,
  119. "I/O Address = %p.\n", optr);
  120. /* Issue set host interrupt command to send cmd out. */
  121. ha->flags.mbox_int = 0;
  122. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  123. /* Unlock mbx registers and wait for interrupt */
  124. ql_dbg(ql_dbg_mbx, vha, 0x100f,
  125. "Going to unlock irq & waiting for interrupts. "
  126. "jiffies=%lx.\n", jiffies);
  127. /* Wait for mbx cmd completion until timeout */
  128. if ((!abort_active && io_lock_on) || IS_NOPOLLING_TYPE(ha)) {
  129. set_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  130. if (IS_P3P_TYPE(ha)) {
  131. if (RD_REG_DWORD(&reg->isp82.hint) &
  132. HINT_MBX_INT_PENDING) {
  133. spin_unlock_irqrestore(&ha->hardware_lock,
  134. flags);
  135. ha->flags.mbox_busy = 0;
  136. ql_dbg(ql_dbg_mbx, vha, 0x1010,
  137. "Pending mailbox timeout, exiting.\n");
  138. rval = QLA_FUNCTION_TIMEOUT;
  139. goto premature_exit;
  140. }
  141. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  142. } else if (IS_FWI2_CAPABLE(ha))
  143. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  144. else
  145. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  146. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  147. if (!wait_for_completion_timeout(&ha->mbx_intr_comp,
  148. mcp->tov * HZ)) {
  149. ql_dbg(ql_dbg_mbx, vha, 0x117a,
  150. "cmd=%x Timeout.\n", command);
  151. spin_lock_irqsave(&ha->hardware_lock, flags);
  152. clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
  153. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  154. }
  155. } else {
  156. ql_dbg(ql_dbg_mbx, vha, 0x1011,
  157. "Cmd=%x Polling Mode.\n", command);
  158. if (IS_P3P_TYPE(ha)) {
  159. if (RD_REG_DWORD(&reg->isp82.hint) &
  160. HINT_MBX_INT_PENDING) {
  161. spin_unlock_irqrestore(&ha->hardware_lock,
  162. flags);
  163. ha->flags.mbox_busy = 0;
  164. ql_dbg(ql_dbg_mbx, vha, 0x1012,
  165. "Pending mailbox timeout, exiting.\n");
  166. rval = QLA_FUNCTION_TIMEOUT;
  167. goto premature_exit;
  168. }
  169. WRT_REG_DWORD(&reg->isp82.hint, HINT_MBX_INT_PENDING);
  170. } else if (IS_FWI2_CAPABLE(ha))
  171. WRT_REG_DWORD(&reg->isp24.hccr, HCCRX_SET_HOST_INT);
  172. else
  173. WRT_REG_WORD(&reg->isp.hccr, HCCR_SET_HOST_INT);
  174. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  175. wait_time = jiffies + mcp->tov * HZ; /* wait at most tov secs */
  176. while (!ha->flags.mbox_int) {
  177. if (time_after(jiffies, wait_time))
  178. break;
  179. /* Check for pending interrupts. */
  180. qla2x00_poll(ha->rsp_q_map[0]);
  181. if (!ha->flags.mbox_int &&
  182. !(IS_QLA2200(ha) &&
  183. command == MBC_LOAD_RISC_RAM_EXTENDED))
  184. msleep(10);
  185. } /* while */
  186. ql_dbg(ql_dbg_mbx, vha, 0x1013,
  187. "Waited %d sec.\n",
  188. (uint)((jiffies - (wait_time - (mcp->tov * HZ)))/HZ));
  189. }
  190. /* Check whether we timed out */
  191. if (ha->flags.mbox_int) {
  192. uint16_t *iptr2;
  193. ql_dbg(ql_dbg_mbx, vha, 0x1014,
  194. "Cmd=%x completed.\n", command);
  195. /* Got interrupt. Clear the flag. */
  196. ha->flags.mbox_int = 0;
  197. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  198. if (IS_P3P_TYPE(ha) && ha->flags.isp82xx_fw_hung) {
  199. ha->flags.mbox_busy = 0;
  200. /* Setting Link-Down error */
  201. mcp->mb[0] = MBS_LINK_DOWN_ERROR;
  202. ha->mcp = NULL;
  203. rval = QLA_FUNCTION_FAILED;
  204. ql_log(ql_log_warn, vha, 0x1015,
  205. "FW hung = %d.\n", ha->flags.isp82xx_fw_hung);
  206. goto premature_exit;
  207. }
  208. if (ha->mailbox_out[0] != MBS_COMMAND_COMPLETE)
  209. rval = QLA_FUNCTION_FAILED;
  210. /* Load return mailbox registers. */
  211. iptr2 = mcp->mb;
  212. iptr = (uint16_t *)&ha->mailbox_out[0];
  213. mboxes = mcp->in_mb;
  214. ql_dbg(ql_dbg_mbx, vha, 0x1113,
  215. "Mailbox registers (IN):\n");
  216. for (cnt = 0; cnt < ha->mbx_count; cnt++) {
  217. if (mboxes & BIT_0) {
  218. *iptr2 = *iptr;
  219. ql_dbg(ql_dbg_mbx, vha, 0x1114,
  220. "mbox[%d]->0x%04x\n", cnt, *iptr2);
  221. }
  222. mboxes >>= 1;
  223. iptr2++;
  224. iptr++;
  225. }
  226. } else {
  227. uint16_t mb0;
  228. uint32_t ictrl;
  229. if (IS_FWI2_CAPABLE(ha)) {
  230. mb0 = RD_REG_WORD(&reg->isp24.mailbox0);
  231. ictrl = RD_REG_DWORD(&reg->isp24.ictrl);
  232. } else {
  233. mb0 = RD_MAILBOX_REG(ha, &reg->isp, 0);
  234. ictrl = RD_REG_WORD(&reg->isp.ictrl);
  235. }
  236. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1119,
  237. "MBX Command timeout for cmd %x, iocontrol=%x jiffies=%lx "
  238. "mb[0]=0x%x\n", command, ictrl, jiffies, mb0);
  239. ql_dump_regs(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1019);
  240. /*
  241. * Attempt to capture a firmware dump for further analysis
  242. * of the current firmware state. We do not need to do this
  243. * if we are intentionally generating a dump.
  244. */
  245. if (mcp->mb[0] != MBC_GEN_SYSTEM_ERROR)
  246. ha->isp_ops->fw_dump(vha, 0);
  247. rval = QLA_FUNCTION_TIMEOUT;
  248. }
  249. ha->flags.mbox_busy = 0;
  250. /* Clean up */
  251. ha->mcp = NULL;
  252. if ((abort_active || !io_lock_on) && !IS_NOPOLLING_TYPE(ha)) {
  253. ql_dbg(ql_dbg_mbx, vha, 0x101a,
  254. "Checking for additional resp interrupt.\n");
  255. /* polling mode for non isp_abort commands. */
  256. qla2x00_poll(ha->rsp_q_map[0]);
  257. }
  258. if (rval == QLA_FUNCTION_TIMEOUT &&
  259. mcp->mb[0] != MBC_GEN_SYSTEM_ERROR) {
  260. if (!io_lock_on || (mcp->flags & IOCTL_CMD) ||
  261. ha->flags.eeh_busy) {
  262. /* not in dpc. schedule it for dpc to take over. */
  263. ql_dbg(ql_dbg_mbx, vha, 0x101b,
  264. "Timeout, schedule isp_abort_needed.\n");
  265. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  266. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  267. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  268. if (IS_QLA82XX(ha)) {
  269. ql_dbg(ql_dbg_mbx, vha, 0x112a,
  270. "disabling pause transmit on port "
  271. "0 & 1.\n");
  272. qla82xx_wr_32(ha,
  273. QLA82XX_CRB_NIU + 0x98,
  274. CRB_NIU_XG_PAUSE_CTL_P0|
  275. CRB_NIU_XG_PAUSE_CTL_P1);
  276. }
  277. ql_log(ql_log_info, base_vha, 0x101c,
  278. "Mailbox cmd timeout occurred, cmd=0x%x, "
  279. "mb[0]=0x%x, eeh_busy=0x%x. Scheduling ISP "
  280. "abort.\n", command, mcp->mb[0],
  281. ha->flags.eeh_busy);
  282. set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  283. qla2xxx_wake_dpc(vha);
  284. }
  285. } else if (!abort_active) {
  286. /* call abort directly since we are in the DPC thread */
  287. ql_dbg(ql_dbg_mbx, vha, 0x101d,
  288. "Timeout, calling abort_isp.\n");
  289. if (!test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) &&
  290. !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
  291. !test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
  292. if (IS_QLA82XX(ha)) {
  293. ql_dbg(ql_dbg_mbx, vha, 0x112b,
  294. "disabling pause transmit on port "
  295. "0 & 1.\n");
  296. qla82xx_wr_32(ha,
  297. QLA82XX_CRB_NIU + 0x98,
  298. CRB_NIU_XG_PAUSE_CTL_P0|
  299. CRB_NIU_XG_PAUSE_CTL_P1);
  300. }
  301. ql_log(ql_log_info, base_vha, 0x101e,
  302. "Mailbox cmd timeout occurred, cmd=0x%x, "
  303. "mb[0]=0x%x. Scheduling ISP abort ",
  304. command, mcp->mb[0]);
  305. set_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  306. clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
  307. /* Allow next mbx cmd to come in. */
  308. complete(&ha->mbx_cmd_comp);
  309. if (ha->isp_ops->abort_isp(vha)) {
  310. /* Failed. retry later. */
  311. set_bit(ISP_ABORT_NEEDED,
  312. &vha->dpc_flags);
  313. }
  314. clear_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags);
  315. ql_dbg(ql_dbg_mbx, vha, 0x101f,
  316. "Finished abort_isp.\n");
  317. goto mbx_done;
  318. }
  319. }
  320. }
  321. premature_exit:
  322. /* Allow next mbx cmd to come in. */
  323. complete(&ha->mbx_cmd_comp);
  324. mbx_done:
  325. if (rval) {
  326. ql_dbg(ql_dbg_disc, base_vha, 0x1020,
  327. "**** Failed mbx[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x, cmd=%x ****.\n",
  328. mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3], command);
  329. ql_dbg(ql_dbg_disc, vha, 0x1115,
  330. "host status: 0x%x, flags:0x%lx, intr ctrl reg:0x%x, intr status:0x%x\n",
  331. RD_REG_DWORD(&reg->isp24.host_status),
  332. ha->fw_dump_cap_flags,
  333. RD_REG_DWORD(&reg->isp24.ictrl),
  334. RD_REG_DWORD(&reg->isp24.istatus));
  335. mbx_reg = &reg->isp24.mailbox0;
  336. for (i = 0; i < 6; i++)
  337. ql_dbg(ql_dbg_disc + ql_dbg_verbose, vha, 0x1116,
  338. "mbox[%d] 0x%04x\n", i, RD_REG_WORD(mbx_reg++));
  339. } else {
  340. ql_dbg(ql_dbg_mbx, base_vha, 0x1021, "Done %s.\n", __func__);
  341. }
  342. return rval;
  343. }
  344. int
  345. qla2x00_load_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t risc_addr,
  346. uint32_t risc_code_size)
  347. {
  348. int rval;
  349. struct qla_hw_data *ha = vha->hw;
  350. mbx_cmd_t mc;
  351. mbx_cmd_t *mcp = &mc;
  352. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1022,
  353. "Entered %s.\n", __func__);
  354. if (MSW(risc_addr) || IS_FWI2_CAPABLE(ha)) {
  355. mcp->mb[0] = MBC_LOAD_RISC_RAM_EXTENDED;
  356. mcp->mb[8] = MSW(risc_addr);
  357. mcp->out_mb = MBX_8|MBX_0;
  358. } else {
  359. mcp->mb[0] = MBC_LOAD_RISC_RAM;
  360. mcp->out_mb = MBX_0;
  361. }
  362. mcp->mb[1] = LSW(risc_addr);
  363. mcp->mb[2] = MSW(req_dma);
  364. mcp->mb[3] = LSW(req_dma);
  365. mcp->mb[6] = MSW(MSD(req_dma));
  366. mcp->mb[7] = LSW(MSD(req_dma));
  367. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  368. if (IS_FWI2_CAPABLE(ha)) {
  369. mcp->mb[4] = MSW(risc_code_size);
  370. mcp->mb[5] = LSW(risc_code_size);
  371. mcp->out_mb |= MBX_5|MBX_4;
  372. } else {
  373. mcp->mb[4] = LSW(risc_code_size);
  374. mcp->out_mb |= MBX_4;
  375. }
  376. mcp->in_mb = MBX_0;
  377. mcp->tov = MBX_TOV_SECONDS;
  378. mcp->flags = 0;
  379. rval = qla2x00_mailbox_command(vha, mcp);
  380. if (rval != QLA_SUCCESS) {
  381. ql_dbg(ql_dbg_mbx, vha, 0x1023,
  382. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  383. } else {
  384. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1024,
  385. "Done %s.\n", __func__);
  386. }
  387. return rval;
  388. }
  389. #define EXTENDED_BB_CREDITS BIT_0
  390. /*
  391. * qla2x00_execute_fw
  392. * Start adapter firmware.
  393. *
  394. * Input:
  395. * ha = adapter block pointer.
  396. * TARGET_QUEUE_LOCK must be released.
  397. * ADAPTER_STATE_LOCK must be released.
  398. *
  399. * Returns:
  400. * qla2x00 local function return status code.
  401. *
  402. * Context:
  403. * Kernel context.
  404. */
  405. int
  406. qla2x00_execute_fw(scsi_qla_host_t *vha, uint32_t risc_addr)
  407. {
  408. int rval;
  409. struct qla_hw_data *ha = vha->hw;
  410. mbx_cmd_t mc;
  411. mbx_cmd_t *mcp = &mc;
  412. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1025,
  413. "Entered %s.\n", __func__);
  414. mcp->mb[0] = MBC_EXECUTE_FIRMWARE;
  415. mcp->out_mb = MBX_0;
  416. mcp->in_mb = MBX_0;
  417. if (IS_FWI2_CAPABLE(ha)) {
  418. mcp->mb[1] = MSW(risc_addr);
  419. mcp->mb[2] = LSW(risc_addr);
  420. mcp->mb[3] = 0;
  421. if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) ||
  422. IS_QLA27XX(ha)) {
  423. struct nvram_81xx *nv = ha->nvram;
  424. mcp->mb[4] = (nv->enhanced_features &
  425. EXTENDED_BB_CREDITS);
  426. } else
  427. mcp->mb[4] = 0;
  428. mcp->out_mb |= MBX_4|MBX_3|MBX_2|MBX_1;
  429. mcp->in_mb |= MBX_1;
  430. } else {
  431. mcp->mb[1] = LSW(risc_addr);
  432. mcp->out_mb |= MBX_1;
  433. if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
  434. mcp->mb[2] = 0;
  435. mcp->out_mb |= MBX_2;
  436. }
  437. }
  438. mcp->tov = MBX_TOV_SECONDS;
  439. mcp->flags = 0;
  440. rval = qla2x00_mailbox_command(vha, mcp);
  441. if (rval != QLA_SUCCESS) {
  442. ql_dbg(ql_dbg_mbx, vha, 0x1026,
  443. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  444. } else {
  445. if (IS_FWI2_CAPABLE(ha)) {
  446. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1027,
  447. "Done exchanges=%x.\n", mcp->mb[1]);
  448. } else {
  449. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1028,
  450. "Done %s.\n", __func__);
  451. }
  452. }
  453. return rval;
  454. }
  455. /*
  456. * qla2x00_get_fw_version
  457. * Get firmware version.
  458. *
  459. * Input:
  460. * ha: adapter state pointer.
  461. * major: pointer for major number.
  462. * minor: pointer for minor number.
  463. * subminor: pointer for subminor number.
  464. *
  465. * Returns:
  466. * qla2x00 local function return status code.
  467. *
  468. * Context:
  469. * Kernel context.
  470. */
  471. int
  472. qla2x00_get_fw_version(scsi_qla_host_t *vha)
  473. {
  474. int rval;
  475. mbx_cmd_t mc;
  476. mbx_cmd_t *mcp = &mc;
  477. struct qla_hw_data *ha = vha->hw;
  478. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1029,
  479. "Entered %s.\n", __func__);
  480. mcp->mb[0] = MBC_GET_FIRMWARE_VERSION;
  481. mcp->out_mb = MBX_0;
  482. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  483. if (IS_QLA81XX(vha->hw) || IS_QLA8031(ha) || IS_QLA8044(ha))
  484. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8;
  485. if (IS_FWI2_CAPABLE(ha))
  486. mcp->in_mb |= MBX_17|MBX_16|MBX_15;
  487. if (IS_QLA27XX(ha))
  488. mcp->in_mb |= MBX_23 | MBX_22 | MBX_21 | MBX_20 | MBX_19 |
  489. MBX_18 | MBX_14 | MBX_13 | MBX_11 | MBX_10 | MBX_9 | MBX_8;
  490. mcp->flags = 0;
  491. mcp->tov = MBX_TOV_SECONDS;
  492. rval = qla2x00_mailbox_command(vha, mcp);
  493. if (rval != QLA_SUCCESS)
  494. goto failed;
  495. /* Return mailbox data. */
  496. ha->fw_major_version = mcp->mb[1];
  497. ha->fw_minor_version = mcp->mb[2];
  498. ha->fw_subminor_version = mcp->mb[3];
  499. ha->fw_attributes = mcp->mb[6];
  500. if (IS_QLA2100(vha->hw) || IS_QLA2200(vha->hw))
  501. ha->fw_memory_size = 0x1FFFF; /* Defaults to 128KB. */
  502. else
  503. ha->fw_memory_size = (mcp->mb[5] << 16) | mcp->mb[4];
  504. if (IS_QLA81XX(vha->hw) || IS_QLA8031(vha->hw) || IS_QLA8044(ha)) {
  505. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  506. ha->mpi_version[1] = mcp->mb[11] >> 8;
  507. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  508. ha->mpi_capabilities = (mcp->mb[12] << 16) | mcp->mb[13];
  509. ha->phy_version[0] = mcp->mb[8] & 0xff;
  510. ha->phy_version[1] = mcp->mb[9] >> 8;
  511. ha->phy_version[2] = mcp->mb[9] & 0xff;
  512. }
  513. if (IS_FWI2_CAPABLE(ha)) {
  514. ha->fw_attributes_h = mcp->mb[15];
  515. ha->fw_attributes_ext[0] = mcp->mb[16];
  516. ha->fw_attributes_ext[1] = mcp->mb[17];
  517. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1139,
  518. "%s: FW_attributes Upper: 0x%x, Lower: 0x%x.\n",
  519. __func__, mcp->mb[15], mcp->mb[6]);
  520. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x112f,
  521. "%s: Ext_FwAttributes Upper: 0x%x, Lower: 0x%x.\n",
  522. __func__, mcp->mb[17], mcp->mb[16]);
  523. }
  524. if (IS_QLA27XX(ha)) {
  525. ha->mpi_version[0] = mcp->mb[10] & 0xff;
  526. ha->mpi_version[1] = mcp->mb[11] >> 8;
  527. ha->mpi_version[2] = mcp->mb[11] & 0xff;
  528. ha->pep_version[0] = mcp->mb[13] & 0xff;
  529. ha->pep_version[1] = mcp->mb[14] >> 8;
  530. ha->pep_version[2] = mcp->mb[14] & 0xff;
  531. ha->fw_shared_ram_start = (mcp->mb[19] << 16) | mcp->mb[18];
  532. ha->fw_shared_ram_end = (mcp->mb[21] << 16) | mcp->mb[20];
  533. }
  534. failed:
  535. if (rval != QLA_SUCCESS) {
  536. /*EMPTY*/
  537. ql_dbg(ql_dbg_mbx, vha, 0x102a, "Failed=%x.\n", rval);
  538. } else {
  539. /*EMPTY*/
  540. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102b,
  541. "Done %s.\n", __func__);
  542. }
  543. return rval;
  544. }
  545. /*
  546. * qla2x00_get_fw_options
  547. * Set firmware options.
  548. *
  549. * Input:
  550. * ha = adapter block pointer.
  551. * fwopt = pointer for firmware options.
  552. *
  553. * Returns:
  554. * qla2x00 local function return status code.
  555. *
  556. * Context:
  557. * Kernel context.
  558. */
  559. int
  560. qla2x00_get_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  561. {
  562. int rval;
  563. mbx_cmd_t mc;
  564. mbx_cmd_t *mcp = &mc;
  565. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102c,
  566. "Entered %s.\n", __func__);
  567. mcp->mb[0] = MBC_GET_FIRMWARE_OPTION;
  568. mcp->out_mb = MBX_0;
  569. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  570. mcp->tov = MBX_TOV_SECONDS;
  571. mcp->flags = 0;
  572. rval = qla2x00_mailbox_command(vha, mcp);
  573. if (rval != QLA_SUCCESS) {
  574. /*EMPTY*/
  575. ql_dbg(ql_dbg_mbx, vha, 0x102d, "Failed=%x.\n", rval);
  576. } else {
  577. fwopts[0] = mcp->mb[0];
  578. fwopts[1] = mcp->mb[1];
  579. fwopts[2] = mcp->mb[2];
  580. fwopts[3] = mcp->mb[3];
  581. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102e,
  582. "Done %s.\n", __func__);
  583. }
  584. return rval;
  585. }
  586. /*
  587. * qla2x00_set_fw_options
  588. * Set firmware options.
  589. *
  590. * Input:
  591. * ha = adapter block pointer.
  592. * fwopt = pointer for firmware options.
  593. *
  594. * Returns:
  595. * qla2x00 local function return status code.
  596. *
  597. * Context:
  598. * Kernel context.
  599. */
  600. int
  601. qla2x00_set_fw_options(scsi_qla_host_t *vha, uint16_t *fwopts)
  602. {
  603. int rval;
  604. mbx_cmd_t mc;
  605. mbx_cmd_t *mcp = &mc;
  606. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x102f,
  607. "Entered %s.\n", __func__);
  608. mcp->mb[0] = MBC_SET_FIRMWARE_OPTION;
  609. mcp->mb[1] = fwopts[1];
  610. mcp->mb[2] = fwopts[2];
  611. mcp->mb[3] = fwopts[3];
  612. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  613. mcp->in_mb = MBX_0;
  614. if (IS_FWI2_CAPABLE(vha->hw)) {
  615. mcp->in_mb |= MBX_1;
  616. } else {
  617. mcp->mb[10] = fwopts[10];
  618. mcp->mb[11] = fwopts[11];
  619. mcp->mb[12] = 0; /* Undocumented, but used */
  620. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  621. }
  622. mcp->tov = MBX_TOV_SECONDS;
  623. mcp->flags = 0;
  624. rval = qla2x00_mailbox_command(vha, mcp);
  625. fwopts[0] = mcp->mb[0];
  626. if (rval != QLA_SUCCESS) {
  627. /*EMPTY*/
  628. ql_dbg(ql_dbg_mbx, vha, 0x1030,
  629. "Failed=%x (%x/%x).\n", rval, mcp->mb[0], mcp->mb[1]);
  630. } else {
  631. /*EMPTY*/
  632. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1031,
  633. "Done %s.\n", __func__);
  634. }
  635. return rval;
  636. }
  637. /*
  638. * qla2x00_mbx_reg_test
  639. * Mailbox register wrap test.
  640. *
  641. * Input:
  642. * ha = adapter block pointer.
  643. * TARGET_QUEUE_LOCK must be released.
  644. * ADAPTER_STATE_LOCK must be released.
  645. *
  646. * Returns:
  647. * qla2x00 local function return status code.
  648. *
  649. * Context:
  650. * Kernel context.
  651. */
  652. int
  653. qla2x00_mbx_reg_test(scsi_qla_host_t *vha)
  654. {
  655. int rval;
  656. mbx_cmd_t mc;
  657. mbx_cmd_t *mcp = &mc;
  658. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1032,
  659. "Entered %s.\n", __func__);
  660. mcp->mb[0] = MBC_MAILBOX_REGISTER_TEST;
  661. mcp->mb[1] = 0xAAAA;
  662. mcp->mb[2] = 0x5555;
  663. mcp->mb[3] = 0xAA55;
  664. mcp->mb[4] = 0x55AA;
  665. mcp->mb[5] = 0xA5A5;
  666. mcp->mb[6] = 0x5A5A;
  667. mcp->mb[7] = 0x2525;
  668. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  669. mcp->in_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  670. mcp->tov = MBX_TOV_SECONDS;
  671. mcp->flags = 0;
  672. rval = qla2x00_mailbox_command(vha, mcp);
  673. if (rval == QLA_SUCCESS) {
  674. if (mcp->mb[1] != 0xAAAA || mcp->mb[2] != 0x5555 ||
  675. mcp->mb[3] != 0xAA55 || mcp->mb[4] != 0x55AA)
  676. rval = QLA_FUNCTION_FAILED;
  677. if (mcp->mb[5] != 0xA5A5 || mcp->mb[6] != 0x5A5A ||
  678. mcp->mb[7] != 0x2525)
  679. rval = QLA_FUNCTION_FAILED;
  680. }
  681. if (rval != QLA_SUCCESS) {
  682. /*EMPTY*/
  683. ql_dbg(ql_dbg_mbx, vha, 0x1033, "Failed=%x.\n", rval);
  684. } else {
  685. /*EMPTY*/
  686. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1034,
  687. "Done %s.\n", __func__);
  688. }
  689. return rval;
  690. }
  691. /*
  692. * qla2x00_verify_checksum
  693. * Verify firmware checksum.
  694. *
  695. * Input:
  696. * ha = adapter block pointer.
  697. * TARGET_QUEUE_LOCK must be released.
  698. * ADAPTER_STATE_LOCK must be released.
  699. *
  700. * Returns:
  701. * qla2x00 local function return status code.
  702. *
  703. * Context:
  704. * Kernel context.
  705. */
  706. int
  707. qla2x00_verify_checksum(scsi_qla_host_t *vha, uint32_t risc_addr)
  708. {
  709. int rval;
  710. mbx_cmd_t mc;
  711. mbx_cmd_t *mcp = &mc;
  712. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1035,
  713. "Entered %s.\n", __func__);
  714. mcp->mb[0] = MBC_VERIFY_CHECKSUM;
  715. mcp->out_mb = MBX_0;
  716. mcp->in_mb = MBX_0;
  717. if (IS_FWI2_CAPABLE(vha->hw)) {
  718. mcp->mb[1] = MSW(risc_addr);
  719. mcp->mb[2] = LSW(risc_addr);
  720. mcp->out_mb |= MBX_2|MBX_1;
  721. mcp->in_mb |= MBX_2|MBX_1;
  722. } else {
  723. mcp->mb[1] = LSW(risc_addr);
  724. mcp->out_mb |= MBX_1;
  725. mcp->in_mb |= MBX_1;
  726. }
  727. mcp->tov = MBX_TOV_SECONDS;
  728. mcp->flags = 0;
  729. rval = qla2x00_mailbox_command(vha, mcp);
  730. if (rval != QLA_SUCCESS) {
  731. ql_dbg(ql_dbg_mbx, vha, 0x1036,
  732. "Failed=%x chm sum=%x.\n", rval, IS_FWI2_CAPABLE(vha->hw) ?
  733. (mcp->mb[2] << 16) | mcp->mb[1] : mcp->mb[1]);
  734. } else {
  735. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1037,
  736. "Done %s.\n", __func__);
  737. }
  738. return rval;
  739. }
  740. /*
  741. * qla2x00_issue_iocb
  742. * Issue IOCB using mailbox command
  743. *
  744. * Input:
  745. * ha = adapter state pointer.
  746. * buffer = buffer pointer.
  747. * phys_addr = physical address of buffer.
  748. * size = size of buffer.
  749. * TARGET_QUEUE_LOCK must be released.
  750. * ADAPTER_STATE_LOCK must be released.
  751. *
  752. * Returns:
  753. * qla2x00 local function return status code.
  754. *
  755. * Context:
  756. * Kernel context.
  757. */
  758. int
  759. qla2x00_issue_iocb_timeout(scsi_qla_host_t *vha, void *buffer,
  760. dma_addr_t phys_addr, size_t size, uint32_t tov)
  761. {
  762. int rval;
  763. mbx_cmd_t mc;
  764. mbx_cmd_t *mcp = &mc;
  765. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1038,
  766. "Entered %s.\n", __func__);
  767. mcp->mb[0] = MBC_IOCB_COMMAND_A64;
  768. mcp->mb[1] = 0;
  769. mcp->mb[2] = MSW(phys_addr);
  770. mcp->mb[3] = LSW(phys_addr);
  771. mcp->mb[6] = MSW(MSD(phys_addr));
  772. mcp->mb[7] = LSW(MSD(phys_addr));
  773. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  774. mcp->in_mb = MBX_2|MBX_0;
  775. mcp->tov = tov;
  776. mcp->flags = 0;
  777. rval = qla2x00_mailbox_command(vha, mcp);
  778. if (rval != QLA_SUCCESS) {
  779. /*EMPTY*/
  780. ql_dbg(ql_dbg_mbx, vha, 0x1039, "Failed=%x.\n", rval);
  781. } else {
  782. sts_entry_t *sts_entry = (sts_entry_t *) buffer;
  783. /* Mask reserved bits. */
  784. sts_entry->entry_status &=
  785. IS_FWI2_CAPABLE(vha->hw) ? RF_MASK_24XX : RF_MASK;
  786. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103a,
  787. "Done %s.\n", __func__);
  788. }
  789. return rval;
  790. }
  791. int
  792. qla2x00_issue_iocb(scsi_qla_host_t *vha, void *buffer, dma_addr_t phys_addr,
  793. size_t size)
  794. {
  795. return qla2x00_issue_iocb_timeout(vha, buffer, phys_addr, size,
  796. MBX_TOV_SECONDS);
  797. }
  798. /*
  799. * qla2x00_abort_command
  800. * Abort command aborts a specified IOCB.
  801. *
  802. * Input:
  803. * ha = adapter block pointer.
  804. * sp = SB structure pointer.
  805. *
  806. * Returns:
  807. * qla2x00 local function return status code.
  808. *
  809. * Context:
  810. * Kernel context.
  811. */
  812. int
  813. qla2x00_abort_command(srb_t *sp)
  814. {
  815. unsigned long flags = 0;
  816. int rval;
  817. uint32_t handle = 0;
  818. mbx_cmd_t mc;
  819. mbx_cmd_t *mcp = &mc;
  820. fc_port_t *fcport = sp->fcport;
  821. scsi_qla_host_t *vha = fcport->vha;
  822. struct qla_hw_data *ha = vha->hw;
  823. struct req_que *req = vha->req;
  824. struct scsi_cmnd *cmd = GET_CMD_SP(sp);
  825. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103b,
  826. "Entered %s.\n", __func__);
  827. spin_lock_irqsave(&ha->hardware_lock, flags);
  828. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  829. if (req->outstanding_cmds[handle] == sp)
  830. break;
  831. }
  832. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  833. if (handle == req->num_outstanding_cmds) {
  834. /* command not found */
  835. return QLA_FUNCTION_FAILED;
  836. }
  837. mcp->mb[0] = MBC_ABORT_COMMAND;
  838. if (HAS_EXTENDED_IDS(ha))
  839. mcp->mb[1] = fcport->loop_id;
  840. else
  841. mcp->mb[1] = fcport->loop_id << 8;
  842. mcp->mb[2] = (uint16_t)handle;
  843. mcp->mb[3] = (uint16_t)(handle >> 16);
  844. mcp->mb[6] = (uint16_t)cmd->device->lun;
  845. mcp->out_mb = MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  846. mcp->in_mb = MBX_0;
  847. mcp->tov = MBX_TOV_SECONDS;
  848. mcp->flags = 0;
  849. rval = qla2x00_mailbox_command(vha, mcp);
  850. if (rval != QLA_SUCCESS) {
  851. ql_dbg(ql_dbg_mbx, vha, 0x103c, "Failed=%x.\n", rval);
  852. } else {
  853. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103d,
  854. "Done %s.\n", __func__);
  855. }
  856. return rval;
  857. }
  858. int
  859. qla2x00_abort_target(struct fc_port *fcport, uint64_t l, int tag)
  860. {
  861. int rval, rval2;
  862. mbx_cmd_t mc;
  863. mbx_cmd_t *mcp = &mc;
  864. scsi_qla_host_t *vha;
  865. struct req_que *req;
  866. struct rsp_que *rsp;
  867. l = l;
  868. vha = fcport->vha;
  869. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103e,
  870. "Entered %s.\n", __func__);
  871. req = vha->hw->req_q_map[0];
  872. rsp = req->rsp;
  873. mcp->mb[0] = MBC_ABORT_TARGET;
  874. mcp->out_mb = MBX_9|MBX_2|MBX_1|MBX_0;
  875. if (HAS_EXTENDED_IDS(vha->hw)) {
  876. mcp->mb[1] = fcport->loop_id;
  877. mcp->mb[10] = 0;
  878. mcp->out_mb |= MBX_10;
  879. } else {
  880. mcp->mb[1] = fcport->loop_id << 8;
  881. }
  882. mcp->mb[2] = vha->hw->loop_reset_delay;
  883. mcp->mb[9] = vha->vp_idx;
  884. mcp->in_mb = MBX_0;
  885. mcp->tov = MBX_TOV_SECONDS;
  886. mcp->flags = 0;
  887. rval = qla2x00_mailbox_command(vha, mcp);
  888. if (rval != QLA_SUCCESS) {
  889. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x103f,
  890. "Failed=%x.\n", rval);
  891. }
  892. /* Issue marker IOCB. */
  893. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, 0,
  894. MK_SYNC_ID);
  895. if (rval2 != QLA_SUCCESS) {
  896. ql_dbg(ql_dbg_mbx, vha, 0x1040,
  897. "Failed to issue marker IOCB (%x).\n", rval2);
  898. } else {
  899. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1041,
  900. "Done %s.\n", __func__);
  901. }
  902. return rval;
  903. }
  904. int
  905. qla2x00_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
  906. {
  907. int rval, rval2;
  908. mbx_cmd_t mc;
  909. mbx_cmd_t *mcp = &mc;
  910. scsi_qla_host_t *vha;
  911. struct req_que *req;
  912. struct rsp_que *rsp;
  913. vha = fcport->vha;
  914. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1042,
  915. "Entered %s.\n", __func__);
  916. req = vha->hw->req_q_map[0];
  917. rsp = req->rsp;
  918. mcp->mb[0] = MBC_LUN_RESET;
  919. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  920. if (HAS_EXTENDED_IDS(vha->hw))
  921. mcp->mb[1] = fcport->loop_id;
  922. else
  923. mcp->mb[1] = fcport->loop_id << 8;
  924. mcp->mb[2] = (u32)l;
  925. mcp->mb[3] = 0;
  926. mcp->mb[9] = vha->vp_idx;
  927. mcp->in_mb = MBX_0;
  928. mcp->tov = MBX_TOV_SECONDS;
  929. mcp->flags = 0;
  930. rval = qla2x00_mailbox_command(vha, mcp);
  931. if (rval != QLA_SUCCESS) {
  932. ql_dbg(ql_dbg_mbx, vha, 0x1043, "Failed=%x.\n", rval);
  933. }
  934. /* Issue marker IOCB. */
  935. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  936. MK_SYNC_ID_LUN);
  937. if (rval2 != QLA_SUCCESS) {
  938. ql_dbg(ql_dbg_mbx, vha, 0x1044,
  939. "Failed to issue marker IOCB (%x).\n", rval2);
  940. } else {
  941. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1045,
  942. "Done %s.\n", __func__);
  943. }
  944. return rval;
  945. }
  946. /*
  947. * qla2x00_get_adapter_id
  948. * Get adapter ID and topology.
  949. *
  950. * Input:
  951. * ha = adapter block pointer.
  952. * id = pointer for loop ID.
  953. * al_pa = pointer for AL_PA.
  954. * area = pointer for area.
  955. * domain = pointer for domain.
  956. * top = pointer for topology.
  957. * TARGET_QUEUE_LOCK must be released.
  958. * ADAPTER_STATE_LOCK must be released.
  959. *
  960. * Returns:
  961. * qla2x00 local function return status code.
  962. *
  963. * Context:
  964. * Kernel context.
  965. */
  966. int
  967. qla2x00_get_adapter_id(scsi_qla_host_t *vha, uint16_t *id, uint8_t *al_pa,
  968. uint8_t *area, uint8_t *domain, uint16_t *top, uint16_t *sw_cap)
  969. {
  970. int rval;
  971. mbx_cmd_t mc;
  972. mbx_cmd_t *mcp = &mc;
  973. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1046,
  974. "Entered %s.\n", __func__);
  975. mcp->mb[0] = MBC_GET_ADAPTER_LOOP_ID;
  976. mcp->mb[9] = vha->vp_idx;
  977. mcp->out_mb = MBX_9|MBX_0;
  978. mcp->in_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  979. if (IS_CNA_CAPABLE(vha->hw))
  980. mcp->in_mb |= MBX_13|MBX_12|MBX_11|MBX_10;
  981. if (IS_FWI2_CAPABLE(vha->hw))
  982. mcp->in_mb |= MBX_19|MBX_18|MBX_17|MBX_16;
  983. mcp->tov = MBX_TOV_SECONDS;
  984. mcp->flags = 0;
  985. rval = qla2x00_mailbox_command(vha, mcp);
  986. if (mcp->mb[0] == MBS_COMMAND_ERROR)
  987. rval = QLA_COMMAND_ERROR;
  988. else if (mcp->mb[0] == MBS_INVALID_COMMAND)
  989. rval = QLA_INVALID_COMMAND;
  990. /* Return data. */
  991. *id = mcp->mb[1];
  992. *al_pa = LSB(mcp->mb[2]);
  993. *area = MSB(mcp->mb[2]);
  994. *domain = LSB(mcp->mb[3]);
  995. *top = mcp->mb[6];
  996. *sw_cap = mcp->mb[7];
  997. if (rval != QLA_SUCCESS) {
  998. /*EMPTY*/
  999. ql_dbg(ql_dbg_mbx, vha, 0x1047, "Failed=%x.\n", rval);
  1000. } else {
  1001. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1048,
  1002. "Done %s.\n", __func__);
  1003. if (IS_CNA_CAPABLE(vha->hw)) {
  1004. vha->fcoe_vlan_id = mcp->mb[9] & 0xfff;
  1005. vha->fcoe_fcf_idx = mcp->mb[10];
  1006. vha->fcoe_vn_port_mac[5] = mcp->mb[11] >> 8;
  1007. vha->fcoe_vn_port_mac[4] = mcp->mb[11] & 0xff;
  1008. vha->fcoe_vn_port_mac[3] = mcp->mb[12] >> 8;
  1009. vha->fcoe_vn_port_mac[2] = mcp->mb[12] & 0xff;
  1010. vha->fcoe_vn_port_mac[1] = mcp->mb[13] >> 8;
  1011. vha->fcoe_vn_port_mac[0] = mcp->mb[13] & 0xff;
  1012. }
  1013. /* If FA-WWN supported */
  1014. if (IS_FAWWN_CAPABLE(vha->hw)) {
  1015. if (mcp->mb[7] & BIT_14) {
  1016. vha->port_name[0] = MSB(mcp->mb[16]);
  1017. vha->port_name[1] = LSB(mcp->mb[16]);
  1018. vha->port_name[2] = MSB(mcp->mb[17]);
  1019. vha->port_name[3] = LSB(mcp->mb[17]);
  1020. vha->port_name[4] = MSB(mcp->mb[18]);
  1021. vha->port_name[5] = LSB(mcp->mb[18]);
  1022. vha->port_name[6] = MSB(mcp->mb[19]);
  1023. vha->port_name[7] = LSB(mcp->mb[19]);
  1024. fc_host_port_name(vha->host) =
  1025. wwn_to_u64(vha->port_name);
  1026. ql_dbg(ql_dbg_mbx, vha, 0x10ca,
  1027. "FA-WWN acquired %016llx\n",
  1028. wwn_to_u64(vha->port_name));
  1029. }
  1030. }
  1031. }
  1032. return rval;
  1033. }
  1034. /*
  1035. * qla2x00_get_retry_cnt
  1036. * Get current firmware login retry count and delay.
  1037. *
  1038. * Input:
  1039. * ha = adapter block pointer.
  1040. * retry_cnt = pointer to login retry count.
  1041. * tov = pointer to login timeout value.
  1042. *
  1043. * Returns:
  1044. * qla2x00 local function return status code.
  1045. *
  1046. * Context:
  1047. * Kernel context.
  1048. */
  1049. int
  1050. qla2x00_get_retry_cnt(scsi_qla_host_t *vha, uint8_t *retry_cnt, uint8_t *tov,
  1051. uint16_t *r_a_tov)
  1052. {
  1053. int rval;
  1054. uint16_t ratov;
  1055. mbx_cmd_t mc;
  1056. mbx_cmd_t *mcp = &mc;
  1057. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1049,
  1058. "Entered %s.\n", __func__);
  1059. mcp->mb[0] = MBC_GET_RETRY_COUNT;
  1060. mcp->out_mb = MBX_0;
  1061. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1062. mcp->tov = MBX_TOV_SECONDS;
  1063. mcp->flags = 0;
  1064. rval = qla2x00_mailbox_command(vha, mcp);
  1065. if (rval != QLA_SUCCESS) {
  1066. /*EMPTY*/
  1067. ql_dbg(ql_dbg_mbx, vha, 0x104a,
  1068. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  1069. } else {
  1070. /* Convert returned data and check our values. */
  1071. *r_a_tov = mcp->mb[3] / 2;
  1072. ratov = (mcp->mb[3]/2) / 10; /* mb[3] value is in 100ms */
  1073. if (mcp->mb[1] * ratov > (*retry_cnt) * (*tov)) {
  1074. /* Update to the larger values */
  1075. *retry_cnt = (uint8_t)mcp->mb[1];
  1076. *tov = ratov;
  1077. }
  1078. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104b,
  1079. "Done %s mb3=%d ratov=%d.\n", __func__, mcp->mb[3], ratov);
  1080. }
  1081. return rval;
  1082. }
  1083. /*
  1084. * qla2x00_init_firmware
  1085. * Initialize adapter firmware.
  1086. *
  1087. * Input:
  1088. * ha = adapter block pointer.
  1089. * dptr = Initialization control block pointer.
  1090. * size = size of initialization control block.
  1091. * TARGET_QUEUE_LOCK must be released.
  1092. * ADAPTER_STATE_LOCK must be released.
  1093. *
  1094. * Returns:
  1095. * qla2x00 local function return status code.
  1096. *
  1097. * Context:
  1098. * Kernel context.
  1099. */
  1100. int
  1101. qla2x00_init_firmware(scsi_qla_host_t *vha, uint16_t size)
  1102. {
  1103. int rval;
  1104. mbx_cmd_t mc;
  1105. mbx_cmd_t *mcp = &mc;
  1106. struct qla_hw_data *ha = vha->hw;
  1107. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104c,
  1108. "Entered %s.\n", __func__);
  1109. if (IS_P3P_TYPE(ha) && ql2xdbwr)
  1110. qla82xx_wr_32(ha, (uintptr_t __force)ha->nxdb_wr_ptr,
  1111. (0x04 | (ha->portnum << 5) | (0 << 8) | (0 << 16)));
  1112. if (ha->flags.npiv_supported)
  1113. mcp->mb[0] = MBC_MID_INITIALIZE_FIRMWARE;
  1114. else
  1115. mcp->mb[0] = MBC_INITIALIZE_FIRMWARE;
  1116. mcp->mb[1] = 0;
  1117. mcp->mb[2] = MSW(ha->init_cb_dma);
  1118. mcp->mb[3] = LSW(ha->init_cb_dma);
  1119. mcp->mb[6] = MSW(MSD(ha->init_cb_dma));
  1120. mcp->mb[7] = LSW(MSD(ha->init_cb_dma));
  1121. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1122. if (ha->ex_init_cb && ha->ex_init_cb->ex_version) {
  1123. mcp->mb[1] = BIT_0;
  1124. mcp->mb[10] = MSW(ha->ex_init_cb_dma);
  1125. mcp->mb[11] = LSW(ha->ex_init_cb_dma);
  1126. mcp->mb[12] = MSW(MSD(ha->ex_init_cb_dma));
  1127. mcp->mb[13] = LSW(MSD(ha->ex_init_cb_dma));
  1128. mcp->mb[14] = sizeof(*ha->ex_init_cb);
  1129. mcp->out_mb |= MBX_14|MBX_13|MBX_12|MBX_11|MBX_10;
  1130. }
  1131. /* 1 and 2 should normally be captured. */
  1132. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  1133. if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
  1134. /* mb3 is additional info about the installed SFP. */
  1135. mcp->in_mb |= MBX_3;
  1136. mcp->buf_size = size;
  1137. mcp->flags = MBX_DMA_OUT;
  1138. mcp->tov = MBX_TOV_SECONDS;
  1139. rval = qla2x00_mailbox_command(vha, mcp);
  1140. if (rval != QLA_SUCCESS) {
  1141. /*EMPTY*/
  1142. ql_dbg(ql_dbg_mbx, vha, 0x104d,
  1143. "Failed=%x mb[0]=%x, mb[1]=%x, mb[2]=%x, mb[3]=%x,.\n",
  1144. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3]);
  1145. } else {
  1146. /*EMPTY*/
  1147. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104e,
  1148. "Done %s.\n", __func__);
  1149. }
  1150. return rval;
  1151. }
  1152. /*
  1153. * qla2x00_get_node_name_list
  1154. * Issue get node name list mailbox command, kmalloc()
  1155. * and return the resulting list. Caller must kfree() it!
  1156. *
  1157. * Input:
  1158. * ha = adapter state pointer.
  1159. * out_data = resulting list
  1160. * out_len = length of the resulting list
  1161. *
  1162. * Returns:
  1163. * qla2x00 local function return status code.
  1164. *
  1165. * Context:
  1166. * Kernel context.
  1167. */
  1168. int
  1169. qla2x00_get_node_name_list(scsi_qla_host_t *vha, void **out_data, int *out_len)
  1170. {
  1171. struct qla_hw_data *ha = vha->hw;
  1172. struct qla_port_24xx_data *list = NULL;
  1173. void *pmap;
  1174. mbx_cmd_t mc;
  1175. dma_addr_t pmap_dma;
  1176. ulong dma_size;
  1177. int rval, left;
  1178. left = 1;
  1179. while (left > 0) {
  1180. dma_size = left * sizeof(*list);
  1181. pmap = dma_alloc_coherent(&ha->pdev->dev, dma_size,
  1182. &pmap_dma, GFP_KERNEL);
  1183. if (!pmap) {
  1184. ql_log(ql_log_warn, vha, 0x113f,
  1185. "%s(%ld): DMA Alloc failed of %ld\n",
  1186. __func__, vha->host_no, dma_size);
  1187. rval = QLA_MEMORY_ALLOC_FAILED;
  1188. goto out;
  1189. }
  1190. mc.mb[0] = MBC_PORT_NODE_NAME_LIST;
  1191. mc.mb[1] = BIT_1 | BIT_3;
  1192. mc.mb[2] = MSW(pmap_dma);
  1193. mc.mb[3] = LSW(pmap_dma);
  1194. mc.mb[6] = MSW(MSD(pmap_dma));
  1195. mc.mb[7] = LSW(MSD(pmap_dma));
  1196. mc.mb[8] = dma_size;
  1197. mc.out_mb = MBX_0|MBX_1|MBX_2|MBX_3|MBX_6|MBX_7|MBX_8;
  1198. mc.in_mb = MBX_0|MBX_1;
  1199. mc.tov = 30;
  1200. mc.flags = MBX_DMA_IN;
  1201. rval = qla2x00_mailbox_command(vha, &mc);
  1202. if (rval != QLA_SUCCESS) {
  1203. if ((mc.mb[0] == MBS_COMMAND_ERROR) &&
  1204. (mc.mb[1] == 0xA)) {
  1205. left += le16_to_cpu(mc.mb[2]) /
  1206. sizeof(struct qla_port_24xx_data);
  1207. goto restart;
  1208. }
  1209. goto out_free;
  1210. }
  1211. left = 0;
  1212. list = kmemdup(pmap, dma_size, GFP_KERNEL);
  1213. if (!list) {
  1214. ql_log(ql_log_warn, vha, 0x1140,
  1215. "%s(%ld): failed to allocate node names list "
  1216. "structure.\n", __func__, vha->host_no);
  1217. rval = QLA_MEMORY_ALLOC_FAILED;
  1218. goto out_free;
  1219. }
  1220. restart:
  1221. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1222. }
  1223. *out_data = list;
  1224. *out_len = dma_size;
  1225. out:
  1226. return rval;
  1227. out_free:
  1228. dma_free_coherent(&ha->pdev->dev, dma_size, pmap, pmap_dma);
  1229. return rval;
  1230. }
  1231. /*
  1232. * qla2x00_get_port_database
  1233. * Issue normal/enhanced get port database mailbox command
  1234. * and copy device name as necessary.
  1235. *
  1236. * Input:
  1237. * ha = adapter state pointer.
  1238. * dev = structure pointer.
  1239. * opt = enhanced cmd option byte.
  1240. *
  1241. * Returns:
  1242. * qla2x00 local function return status code.
  1243. *
  1244. * Context:
  1245. * Kernel context.
  1246. */
  1247. int
  1248. qla2x00_get_port_database(scsi_qla_host_t *vha, fc_port_t *fcport, uint8_t opt)
  1249. {
  1250. int rval;
  1251. mbx_cmd_t mc;
  1252. mbx_cmd_t *mcp = &mc;
  1253. port_database_t *pd;
  1254. struct port_database_24xx *pd24;
  1255. dma_addr_t pd_dma;
  1256. struct qla_hw_data *ha = vha->hw;
  1257. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x104f,
  1258. "Entered %s.\n", __func__);
  1259. pd24 = NULL;
  1260. pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
  1261. if (pd == NULL) {
  1262. ql_log(ql_log_warn, vha, 0x1050,
  1263. "Failed to allocate port database structure.\n");
  1264. return QLA_MEMORY_ALLOC_FAILED;
  1265. }
  1266. memset(pd, 0, max(PORT_DATABASE_SIZE, PORT_DATABASE_24XX_SIZE));
  1267. mcp->mb[0] = MBC_GET_PORT_DATABASE;
  1268. if (opt != 0 && !IS_FWI2_CAPABLE(ha))
  1269. mcp->mb[0] = MBC_ENHANCED_GET_PORT_DATABASE;
  1270. mcp->mb[2] = MSW(pd_dma);
  1271. mcp->mb[3] = LSW(pd_dma);
  1272. mcp->mb[6] = MSW(MSD(pd_dma));
  1273. mcp->mb[7] = LSW(MSD(pd_dma));
  1274. mcp->mb[9] = vha->vp_idx;
  1275. mcp->out_mb = MBX_9|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  1276. mcp->in_mb = MBX_0;
  1277. if (IS_FWI2_CAPABLE(ha)) {
  1278. mcp->mb[1] = fcport->loop_id;
  1279. mcp->mb[10] = opt;
  1280. mcp->out_mb |= MBX_10|MBX_1;
  1281. mcp->in_mb |= MBX_1;
  1282. } else if (HAS_EXTENDED_IDS(ha)) {
  1283. mcp->mb[1] = fcport->loop_id;
  1284. mcp->mb[10] = opt;
  1285. mcp->out_mb |= MBX_10|MBX_1;
  1286. } else {
  1287. mcp->mb[1] = fcport->loop_id << 8 | opt;
  1288. mcp->out_mb |= MBX_1;
  1289. }
  1290. mcp->buf_size = IS_FWI2_CAPABLE(ha) ?
  1291. PORT_DATABASE_24XX_SIZE : PORT_DATABASE_SIZE;
  1292. mcp->flags = MBX_DMA_IN;
  1293. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1294. rval = qla2x00_mailbox_command(vha, mcp);
  1295. if (rval != QLA_SUCCESS)
  1296. goto gpd_error_out;
  1297. if (IS_FWI2_CAPABLE(ha)) {
  1298. uint64_t zero = 0;
  1299. pd24 = (struct port_database_24xx *) pd;
  1300. /* Check for logged in state. */
  1301. if (pd24->current_login_state != PDS_PRLI_COMPLETE &&
  1302. pd24->last_login_state != PDS_PRLI_COMPLETE) {
  1303. ql_dbg(ql_dbg_mbx, vha, 0x1051,
  1304. "Unable to verify login-state (%x/%x) for "
  1305. "loop_id %x.\n", pd24->current_login_state,
  1306. pd24->last_login_state, fcport->loop_id);
  1307. rval = QLA_FUNCTION_FAILED;
  1308. goto gpd_error_out;
  1309. }
  1310. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1311. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1312. memcmp(fcport->port_name, pd24->port_name, 8))) {
  1313. /* We lost the device mid way. */
  1314. rval = QLA_NOT_LOGGED_IN;
  1315. goto gpd_error_out;
  1316. }
  1317. /* Names are little-endian. */
  1318. memcpy(fcport->node_name, pd24->node_name, WWN_SIZE);
  1319. memcpy(fcport->port_name, pd24->port_name, WWN_SIZE);
  1320. /* Get port_id of device. */
  1321. fcport->d_id.b.domain = pd24->port_id[0];
  1322. fcport->d_id.b.area = pd24->port_id[1];
  1323. fcport->d_id.b.al_pa = pd24->port_id[2];
  1324. fcport->d_id.b.rsvd_1 = 0;
  1325. /* If not target must be initiator or unknown type. */
  1326. if ((pd24->prli_svc_param_word_3[0] & BIT_4) == 0)
  1327. fcport->port_type = FCT_INITIATOR;
  1328. else
  1329. fcport->port_type = FCT_TARGET;
  1330. /* Passback COS information. */
  1331. fcport->supported_classes = (pd24->flags & PDF_CLASS_2) ?
  1332. FC_COS_CLASS2 : FC_COS_CLASS3;
  1333. if (pd24->prli_svc_param_word_3[0] & BIT_7)
  1334. fcport->flags |= FCF_CONF_COMP_SUPPORTED;
  1335. } else {
  1336. uint64_t zero = 0;
  1337. /* Check for logged in state. */
  1338. if (pd->master_state != PD_STATE_PORT_LOGGED_IN &&
  1339. pd->slave_state != PD_STATE_PORT_LOGGED_IN) {
  1340. ql_dbg(ql_dbg_mbx, vha, 0x100a,
  1341. "Unable to verify login-state (%x/%x) - "
  1342. "portid=%02x%02x%02x.\n", pd->master_state,
  1343. pd->slave_state, fcport->d_id.b.domain,
  1344. fcport->d_id.b.area, fcport->d_id.b.al_pa);
  1345. rval = QLA_FUNCTION_FAILED;
  1346. goto gpd_error_out;
  1347. }
  1348. if (fcport->loop_id == FC_NO_LOOP_ID ||
  1349. (memcmp(fcport->port_name, (uint8_t *)&zero, 8) &&
  1350. memcmp(fcport->port_name, pd->port_name, 8))) {
  1351. /* We lost the device mid way. */
  1352. rval = QLA_NOT_LOGGED_IN;
  1353. goto gpd_error_out;
  1354. }
  1355. /* Names are little-endian. */
  1356. memcpy(fcport->node_name, pd->node_name, WWN_SIZE);
  1357. memcpy(fcport->port_name, pd->port_name, WWN_SIZE);
  1358. /* Get port_id of device. */
  1359. fcport->d_id.b.domain = pd->port_id[0];
  1360. fcport->d_id.b.area = pd->port_id[3];
  1361. fcport->d_id.b.al_pa = pd->port_id[2];
  1362. fcport->d_id.b.rsvd_1 = 0;
  1363. /* If not target must be initiator or unknown type. */
  1364. if ((pd->prli_svc_param_word_3[0] & BIT_4) == 0)
  1365. fcport->port_type = FCT_INITIATOR;
  1366. else
  1367. fcport->port_type = FCT_TARGET;
  1368. /* Passback COS information. */
  1369. fcport->supported_classes = (pd->options & BIT_4) ?
  1370. FC_COS_CLASS2: FC_COS_CLASS3;
  1371. }
  1372. gpd_error_out:
  1373. dma_pool_free(ha->s_dma_pool, pd, pd_dma);
  1374. if (rval != QLA_SUCCESS) {
  1375. ql_dbg(ql_dbg_mbx, vha, 0x1052,
  1376. "Failed=%x mb[0]=%x mb[1]=%x.\n", rval,
  1377. mcp->mb[0], mcp->mb[1]);
  1378. } else {
  1379. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1053,
  1380. "Done %s.\n", __func__);
  1381. }
  1382. return rval;
  1383. }
  1384. /*
  1385. * qla2x00_get_firmware_state
  1386. * Get adapter firmware state.
  1387. *
  1388. * Input:
  1389. * ha = adapter block pointer.
  1390. * dptr = pointer for firmware state.
  1391. * TARGET_QUEUE_LOCK must be released.
  1392. * ADAPTER_STATE_LOCK must be released.
  1393. *
  1394. * Returns:
  1395. * qla2x00 local function return status code.
  1396. *
  1397. * Context:
  1398. * Kernel context.
  1399. */
  1400. int
  1401. qla2x00_get_firmware_state(scsi_qla_host_t *vha, uint16_t *states)
  1402. {
  1403. int rval;
  1404. mbx_cmd_t mc;
  1405. mbx_cmd_t *mcp = &mc;
  1406. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1054,
  1407. "Entered %s.\n", __func__);
  1408. mcp->mb[0] = MBC_GET_FIRMWARE_STATE;
  1409. mcp->out_mb = MBX_0;
  1410. if (IS_FWI2_CAPABLE(vha->hw))
  1411. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  1412. else
  1413. mcp->in_mb = MBX_1|MBX_0;
  1414. mcp->tov = MBX_TOV_SECONDS;
  1415. mcp->flags = 0;
  1416. rval = qla2x00_mailbox_command(vha, mcp);
  1417. /* Return firmware states. */
  1418. states[0] = mcp->mb[1];
  1419. if (IS_FWI2_CAPABLE(vha->hw)) {
  1420. states[1] = mcp->mb[2];
  1421. states[2] = mcp->mb[3];
  1422. states[3] = mcp->mb[4];
  1423. states[4] = mcp->mb[5];
  1424. states[5] = mcp->mb[6]; /* DPORT status */
  1425. }
  1426. if (rval != QLA_SUCCESS) {
  1427. /*EMPTY*/
  1428. ql_dbg(ql_dbg_mbx, vha, 0x1055, "Failed=%x.\n", rval);
  1429. } else {
  1430. /*EMPTY*/
  1431. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1056,
  1432. "Done %s.\n", __func__);
  1433. }
  1434. return rval;
  1435. }
  1436. /*
  1437. * qla2x00_get_port_name
  1438. * Issue get port name mailbox command.
  1439. * Returned name is in big endian format.
  1440. *
  1441. * Input:
  1442. * ha = adapter block pointer.
  1443. * loop_id = loop ID of device.
  1444. * name = pointer for name.
  1445. * TARGET_QUEUE_LOCK must be released.
  1446. * ADAPTER_STATE_LOCK must be released.
  1447. *
  1448. * Returns:
  1449. * qla2x00 local function return status code.
  1450. *
  1451. * Context:
  1452. * Kernel context.
  1453. */
  1454. int
  1455. qla2x00_get_port_name(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t *name,
  1456. uint8_t opt)
  1457. {
  1458. int rval;
  1459. mbx_cmd_t mc;
  1460. mbx_cmd_t *mcp = &mc;
  1461. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1057,
  1462. "Entered %s.\n", __func__);
  1463. mcp->mb[0] = MBC_GET_PORT_NAME;
  1464. mcp->mb[9] = vha->vp_idx;
  1465. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  1466. if (HAS_EXTENDED_IDS(vha->hw)) {
  1467. mcp->mb[1] = loop_id;
  1468. mcp->mb[10] = opt;
  1469. mcp->out_mb |= MBX_10;
  1470. } else {
  1471. mcp->mb[1] = loop_id << 8 | opt;
  1472. }
  1473. mcp->in_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1474. mcp->tov = MBX_TOV_SECONDS;
  1475. mcp->flags = 0;
  1476. rval = qla2x00_mailbox_command(vha, mcp);
  1477. if (rval != QLA_SUCCESS) {
  1478. /*EMPTY*/
  1479. ql_dbg(ql_dbg_mbx, vha, 0x1058, "Failed=%x.\n", rval);
  1480. } else {
  1481. if (name != NULL) {
  1482. /* This function returns name in big endian. */
  1483. name[0] = MSB(mcp->mb[2]);
  1484. name[1] = LSB(mcp->mb[2]);
  1485. name[2] = MSB(mcp->mb[3]);
  1486. name[3] = LSB(mcp->mb[3]);
  1487. name[4] = MSB(mcp->mb[6]);
  1488. name[5] = LSB(mcp->mb[6]);
  1489. name[6] = MSB(mcp->mb[7]);
  1490. name[7] = LSB(mcp->mb[7]);
  1491. }
  1492. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1059,
  1493. "Done %s.\n", __func__);
  1494. }
  1495. return rval;
  1496. }
  1497. /*
  1498. * qla24xx_link_initialization
  1499. * Issue link initialization mailbox command.
  1500. *
  1501. * Input:
  1502. * ha = adapter block pointer.
  1503. * TARGET_QUEUE_LOCK must be released.
  1504. * ADAPTER_STATE_LOCK must be released.
  1505. *
  1506. * Returns:
  1507. * qla2x00 local function return status code.
  1508. *
  1509. * Context:
  1510. * Kernel context.
  1511. */
  1512. int
  1513. qla24xx_link_initialize(scsi_qla_host_t *vha)
  1514. {
  1515. int rval;
  1516. mbx_cmd_t mc;
  1517. mbx_cmd_t *mcp = &mc;
  1518. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1152,
  1519. "Entered %s.\n", __func__);
  1520. if (!IS_FWI2_CAPABLE(vha->hw) || IS_CNA_CAPABLE(vha->hw))
  1521. return QLA_FUNCTION_FAILED;
  1522. mcp->mb[0] = MBC_LINK_INITIALIZATION;
  1523. mcp->mb[1] = BIT_4;
  1524. if (vha->hw->operating_mode == LOOP)
  1525. mcp->mb[1] |= BIT_6;
  1526. else
  1527. mcp->mb[1] |= BIT_5;
  1528. mcp->mb[2] = 0;
  1529. mcp->mb[3] = 0;
  1530. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1531. mcp->in_mb = MBX_0;
  1532. mcp->tov = MBX_TOV_SECONDS;
  1533. mcp->flags = 0;
  1534. rval = qla2x00_mailbox_command(vha, mcp);
  1535. if (rval != QLA_SUCCESS) {
  1536. ql_dbg(ql_dbg_mbx, vha, 0x1153, "Failed=%x.\n", rval);
  1537. } else {
  1538. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1154,
  1539. "Done %s.\n", __func__);
  1540. }
  1541. return rval;
  1542. }
  1543. /*
  1544. * qla2x00_lip_reset
  1545. * Issue LIP reset mailbox command.
  1546. *
  1547. * Input:
  1548. * ha = adapter block pointer.
  1549. * TARGET_QUEUE_LOCK must be released.
  1550. * ADAPTER_STATE_LOCK must be released.
  1551. *
  1552. * Returns:
  1553. * qla2x00 local function return status code.
  1554. *
  1555. * Context:
  1556. * Kernel context.
  1557. */
  1558. int
  1559. qla2x00_lip_reset(scsi_qla_host_t *vha)
  1560. {
  1561. int rval;
  1562. mbx_cmd_t mc;
  1563. mbx_cmd_t *mcp = &mc;
  1564. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105a,
  1565. "Entered %s.\n", __func__);
  1566. if (IS_CNA_CAPABLE(vha->hw)) {
  1567. /* Logout across all FCFs. */
  1568. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1569. mcp->mb[1] = BIT_1;
  1570. mcp->mb[2] = 0;
  1571. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1572. } else if (IS_FWI2_CAPABLE(vha->hw)) {
  1573. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  1574. mcp->mb[1] = BIT_6;
  1575. mcp->mb[2] = 0;
  1576. mcp->mb[3] = vha->hw->loop_reset_delay;
  1577. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1578. } else {
  1579. mcp->mb[0] = MBC_LIP_RESET;
  1580. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1581. if (HAS_EXTENDED_IDS(vha->hw)) {
  1582. mcp->mb[1] = 0x00ff;
  1583. mcp->mb[10] = 0;
  1584. mcp->out_mb |= MBX_10;
  1585. } else {
  1586. mcp->mb[1] = 0xff00;
  1587. }
  1588. mcp->mb[2] = vha->hw->loop_reset_delay;
  1589. mcp->mb[3] = 0;
  1590. }
  1591. mcp->in_mb = MBX_0;
  1592. mcp->tov = MBX_TOV_SECONDS;
  1593. mcp->flags = 0;
  1594. rval = qla2x00_mailbox_command(vha, mcp);
  1595. if (rval != QLA_SUCCESS) {
  1596. /*EMPTY*/
  1597. ql_dbg(ql_dbg_mbx, vha, 0x105b, "Failed=%x.\n", rval);
  1598. } else {
  1599. /*EMPTY*/
  1600. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105c,
  1601. "Done %s.\n", __func__);
  1602. }
  1603. return rval;
  1604. }
  1605. /*
  1606. * qla2x00_send_sns
  1607. * Send SNS command.
  1608. *
  1609. * Input:
  1610. * ha = adapter block pointer.
  1611. * sns = pointer for command.
  1612. * cmd_size = command size.
  1613. * buf_size = response/command size.
  1614. * TARGET_QUEUE_LOCK must be released.
  1615. * ADAPTER_STATE_LOCK must be released.
  1616. *
  1617. * Returns:
  1618. * qla2x00 local function return status code.
  1619. *
  1620. * Context:
  1621. * Kernel context.
  1622. */
  1623. int
  1624. qla2x00_send_sns(scsi_qla_host_t *vha, dma_addr_t sns_phys_address,
  1625. uint16_t cmd_size, size_t buf_size)
  1626. {
  1627. int rval;
  1628. mbx_cmd_t mc;
  1629. mbx_cmd_t *mcp = &mc;
  1630. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105d,
  1631. "Entered %s.\n", __func__);
  1632. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x105e,
  1633. "Retry cnt=%d ratov=%d total tov=%d.\n",
  1634. vha->hw->retry_count, vha->hw->login_timeout, mcp->tov);
  1635. mcp->mb[0] = MBC_SEND_SNS_COMMAND;
  1636. mcp->mb[1] = cmd_size;
  1637. mcp->mb[2] = MSW(sns_phys_address);
  1638. mcp->mb[3] = LSW(sns_phys_address);
  1639. mcp->mb[6] = MSW(MSD(sns_phys_address));
  1640. mcp->mb[7] = LSW(MSD(sns_phys_address));
  1641. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  1642. mcp->in_mb = MBX_0|MBX_1;
  1643. mcp->buf_size = buf_size;
  1644. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN;
  1645. mcp->tov = (vha->hw->login_timeout * 2) + (vha->hw->login_timeout / 2);
  1646. rval = qla2x00_mailbox_command(vha, mcp);
  1647. if (rval != QLA_SUCCESS) {
  1648. /*EMPTY*/
  1649. ql_dbg(ql_dbg_mbx, vha, 0x105f,
  1650. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  1651. rval, mcp->mb[0], mcp->mb[1]);
  1652. } else {
  1653. /*EMPTY*/
  1654. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1060,
  1655. "Done %s.\n", __func__);
  1656. }
  1657. return rval;
  1658. }
  1659. int
  1660. qla24xx_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1661. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1662. {
  1663. int rval;
  1664. struct logio_entry_24xx *lg;
  1665. dma_addr_t lg_dma;
  1666. uint32_t iop[2];
  1667. struct qla_hw_data *ha = vha->hw;
  1668. struct req_que *req;
  1669. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1061,
  1670. "Entered %s.\n", __func__);
  1671. if (ha->flags.cpu_affinity_enabled)
  1672. req = ha->req_q_map[0];
  1673. else
  1674. req = vha->req;
  1675. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1676. if (lg == NULL) {
  1677. ql_log(ql_log_warn, vha, 0x1062,
  1678. "Failed to allocate login IOCB.\n");
  1679. return QLA_MEMORY_ALLOC_FAILED;
  1680. }
  1681. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1682. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1683. lg->entry_count = 1;
  1684. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1685. lg->nport_handle = cpu_to_le16(loop_id);
  1686. lg->control_flags = cpu_to_le16(LCF_COMMAND_PLOGI);
  1687. if (opt & BIT_0)
  1688. lg->control_flags |= cpu_to_le16(LCF_COND_PLOGI);
  1689. if (opt & BIT_1)
  1690. lg->control_flags |= cpu_to_le16(LCF_SKIP_PRLI);
  1691. lg->port_id[0] = al_pa;
  1692. lg->port_id[1] = area;
  1693. lg->port_id[2] = domain;
  1694. lg->vp_index = vha->vp_idx;
  1695. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1696. (ha->r_a_tov / 10 * 2) + 2);
  1697. if (rval != QLA_SUCCESS) {
  1698. ql_dbg(ql_dbg_mbx, vha, 0x1063,
  1699. "Failed to issue login IOCB (%x).\n", rval);
  1700. } else if (lg->entry_status != 0) {
  1701. ql_dbg(ql_dbg_mbx, vha, 0x1064,
  1702. "Failed to complete IOCB -- error status (%x).\n",
  1703. lg->entry_status);
  1704. rval = QLA_FUNCTION_FAILED;
  1705. } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
  1706. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1707. iop[1] = le32_to_cpu(lg->io_parameter[1]);
  1708. ql_dbg(ql_dbg_mbx, vha, 0x1065,
  1709. "Failed to complete IOCB -- completion status (%x) "
  1710. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1711. iop[0], iop[1]);
  1712. switch (iop[0]) {
  1713. case LSC_SCODE_PORTID_USED:
  1714. mb[0] = MBS_PORT_ID_USED;
  1715. mb[1] = LSW(iop[1]);
  1716. break;
  1717. case LSC_SCODE_NPORT_USED:
  1718. mb[0] = MBS_LOOP_ID_USED;
  1719. break;
  1720. case LSC_SCODE_NOLINK:
  1721. case LSC_SCODE_NOIOCB:
  1722. case LSC_SCODE_NOXCB:
  1723. case LSC_SCODE_CMD_FAILED:
  1724. case LSC_SCODE_NOFABRIC:
  1725. case LSC_SCODE_FW_NOT_READY:
  1726. case LSC_SCODE_NOT_LOGGED_IN:
  1727. case LSC_SCODE_NOPCB:
  1728. case LSC_SCODE_ELS_REJECT:
  1729. case LSC_SCODE_CMD_PARAM_ERR:
  1730. case LSC_SCODE_NONPORT:
  1731. case LSC_SCODE_LOGGED_IN:
  1732. case LSC_SCODE_NOFLOGI_ACC:
  1733. default:
  1734. mb[0] = MBS_COMMAND_ERROR;
  1735. break;
  1736. }
  1737. } else {
  1738. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1066,
  1739. "Done %s.\n", __func__);
  1740. iop[0] = le32_to_cpu(lg->io_parameter[0]);
  1741. mb[0] = MBS_COMMAND_COMPLETE;
  1742. mb[1] = 0;
  1743. if (iop[0] & BIT_4) {
  1744. if (iop[0] & BIT_8)
  1745. mb[1] |= BIT_1;
  1746. } else
  1747. mb[1] = BIT_0;
  1748. /* Passback COS information. */
  1749. mb[10] = 0;
  1750. if (lg->io_parameter[7] || lg->io_parameter[8])
  1751. mb[10] |= BIT_0; /* Class 2. */
  1752. if (lg->io_parameter[9] || lg->io_parameter[10])
  1753. mb[10] |= BIT_1; /* Class 3. */
  1754. if (lg->io_parameter[0] & cpu_to_le32(BIT_7))
  1755. mb[10] |= BIT_7; /* Confirmed Completion
  1756. * Allowed
  1757. */
  1758. }
  1759. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1760. return rval;
  1761. }
  1762. /*
  1763. * qla2x00_login_fabric
  1764. * Issue login fabric port mailbox command.
  1765. *
  1766. * Input:
  1767. * ha = adapter block pointer.
  1768. * loop_id = device loop ID.
  1769. * domain = device domain.
  1770. * area = device area.
  1771. * al_pa = device AL_PA.
  1772. * status = pointer for return status.
  1773. * opt = command options.
  1774. * TARGET_QUEUE_LOCK must be released.
  1775. * ADAPTER_STATE_LOCK must be released.
  1776. *
  1777. * Returns:
  1778. * qla2x00 local function return status code.
  1779. *
  1780. * Context:
  1781. * Kernel context.
  1782. */
  1783. int
  1784. qla2x00_login_fabric(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1785. uint8_t area, uint8_t al_pa, uint16_t *mb, uint8_t opt)
  1786. {
  1787. int rval;
  1788. mbx_cmd_t mc;
  1789. mbx_cmd_t *mcp = &mc;
  1790. struct qla_hw_data *ha = vha->hw;
  1791. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1067,
  1792. "Entered %s.\n", __func__);
  1793. mcp->mb[0] = MBC_LOGIN_FABRIC_PORT;
  1794. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  1795. if (HAS_EXTENDED_IDS(ha)) {
  1796. mcp->mb[1] = loop_id;
  1797. mcp->mb[10] = opt;
  1798. mcp->out_mb |= MBX_10;
  1799. } else {
  1800. mcp->mb[1] = (loop_id << 8) | opt;
  1801. }
  1802. mcp->mb[2] = domain;
  1803. mcp->mb[3] = area << 8 | al_pa;
  1804. mcp->in_mb = MBX_7|MBX_6|MBX_2|MBX_1|MBX_0;
  1805. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1806. mcp->flags = 0;
  1807. rval = qla2x00_mailbox_command(vha, mcp);
  1808. /* Return mailbox statuses. */
  1809. if (mb != NULL) {
  1810. mb[0] = mcp->mb[0];
  1811. mb[1] = mcp->mb[1];
  1812. mb[2] = mcp->mb[2];
  1813. mb[6] = mcp->mb[6];
  1814. mb[7] = mcp->mb[7];
  1815. /* COS retrieved from Get-Port-Database mailbox command. */
  1816. mb[10] = 0;
  1817. }
  1818. if (rval != QLA_SUCCESS) {
  1819. /* RLU tmp code: need to change main mailbox_command function to
  1820. * return ok even when the mailbox completion value is not
  1821. * SUCCESS. The caller needs to be responsible to interpret
  1822. * the return values of this mailbox command if we're not
  1823. * to change too much of the existing code.
  1824. */
  1825. if (mcp->mb[0] == 0x4001 || mcp->mb[0] == 0x4002 ||
  1826. mcp->mb[0] == 0x4003 || mcp->mb[0] == 0x4005 ||
  1827. mcp->mb[0] == 0x4006)
  1828. rval = QLA_SUCCESS;
  1829. /*EMPTY*/
  1830. ql_dbg(ql_dbg_mbx, vha, 0x1068,
  1831. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  1832. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  1833. } else {
  1834. /*EMPTY*/
  1835. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1069,
  1836. "Done %s.\n", __func__);
  1837. }
  1838. return rval;
  1839. }
  1840. /*
  1841. * qla2x00_login_local_device
  1842. * Issue login loop port mailbox command.
  1843. *
  1844. * Input:
  1845. * ha = adapter block pointer.
  1846. * loop_id = device loop ID.
  1847. * opt = command options.
  1848. *
  1849. * Returns:
  1850. * Return status code.
  1851. *
  1852. * Context:
  1853. * Kernel context.
  1854. *
  1855. */
  1856. int
  1857. qla2x00_login_local_device(scsi_qla_host_t *vha, fc_port_t *fcport,
  1858. uint16_t *mb_ret, uint8_t opt)
  1859. {
  1860. int rval;
  1861. mbx_cmd_t mc;
  1862. mbx_cmd_t *mcp = &mc;
  1863. struct qla_hw_data *ha = vha->hw;
  1864. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106a,
  1865. "Entered %s.\n", __func__);
  1866. if (IS_FWI2_CAPABLE(ha))
  1867. return qla24xx_login_fabric(vha, fcport->loop_id,
  1868. fcport->d_id.b.domain, fcport->d_id.b.area,
  1869. fcport->d_id.b.al_pa, mb_ret, opt);
  1870. mcp->mb[0] = MBC_LOGIN_LOOP_PORT;
  1871. if (HAS_EXTENDED_IDS(ha))
  1872. mcp->mb[1] = fcport->loop_id;
  1873. else
  1874. mcp->mb[1] = fcport->loop_id << 8;
  1875. mcp->mb[2] = opt;
  1876. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  1877. mcp->in_mb = MBX_7|MBX_6|MBX_1|MBX_0;
  1878. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  1879. mcp->flags = 0;
  1880. rval = qla2x00_mailbox_command(vha, mcp);
  1881. /* Return mailbox statuses. */
  1882. if (mb_ret != NULL) {
  1883. mb_ret[0] = mcp->mb[0];
  1884. mb_ret[1] = mcp->mb[1];
  1885. mb_ret[6] = mcp->mb[6];
  1886. mb_ret[7] = mcp->mb[7];
  1887. }
  1888. if (rval != QLA_SUCCESS) {
  1889. /* AV tmp code: need to change main mailbox_command function to
  1890. * return ok even when the mailbox completion value is not
  1891. * SUCCESS. The caller needs to be responsible to interpret
  1892. * the return values of this mailbox command if we're not
  1893. * to change too much of the existing code.
  1894. */
  1895. if (mcp->mb[0] == 0x4005 || mcp->mb[0] == 0x4006)
  1896. rval = QLA_SUCCESS;
  1897. ql_dbg(ql_dbg_mbx, vha, 0x106b,
  1898. "Failed=%x mb[0]=%x mb[1]=%x mb[6]=%x mb[7]=%x.\n",
  1899. rval, mcp->mb[0], mcp->mb[1], mcp->mb[6], mcp->mb[7]);
  1900. } else {
  1901. /*EMPTY*/
  1902. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106c,
  1903. "Done %s.\n", __func__);
  1904. }
  1905. return (rval);
  1906. }
  1907. int
  1908. qla24xx_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1909. uint8_t area, uint8_t al_pa)
  1910. {
  1911. int rval;
  1912. struct logio_entry_24xx *lg;
  1913. dma_addr_t lg_dma;
  1914. struct qla_hw_data *ha = vha->hw;
  1915. struct req_que *req;
  1916. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x106d,
  1917. "Entered %s.\n", __func__);
  1918. lg = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &lg_dma);
  1919. if (lg == NULL) {
  1920. ql_log(ql_log_warn, vha, 0x106e,
  1921. "Failed to allocate logout IOCB.\n");
  1922. return QLA_MEMORY_ALLOC_FAILED;
  1923. }
  1924. memset(lg, 0, sizeof(struct logio_entry_24xx));
  1925. if (ql2xmaxqueues > 1)
  1926. req = ha->req_q_map[0];
  1927. else
  1928. req = vha->req;
  1929. lg->entry_type = LOGINOUT_PORT_IOCB_TYPE;
  1930. lg->entry_count = 1;
  1931. lg->handle = MAKE_HANDLE(req->id, lg->handle);
  1932. lg->nport_handle = cpu_to_le16(loop_id);
  1933. lg->control_flags =
  1934. cpu_to_le16(LCF_COMMAND_LOGO|LCF_IMPL_LOGO|
  1935. LCF_FREE_NPORT);
  1936. lg->port_id[0] = al_pa;
  1937. lg->port_id[1] = area;
  1938. lg->port_id[2] = domain;
  1939. lg->vp_index = vha->vp_idx;
  1940. rval = qla2x00_issue_iocb_timeout(vha, lg, lg_dma, 0,
  1941. (ha->r_a_tov / 10 * 2) + 2);
  1942. if (rval != QLA_SUCCESS) {
  1943. ql_dbg(ql_dbg_mbx, vha, 0x106f,
  1944. "Failed to issue logout IOCB (%x).\n", rval);
  1945. } else if (lg->entry_status != 0) {
  1946. ql_dbg(ql_dbg_mbx, vha, 0x1070,
  1947. "Failed to complete IOCB -- error status (%x).\n",
  1948. lg->entry_status);
  1949. rval = QLA_FUNCTION_FAILED;
  1950. } else if (lg->comp_status != cpu_to_le16(CS_COMPLETE)) {
  1951. ql_dbg(ql_dbg_mbx, vha, 0x1071,
  1952. "Failed to complete IOCB -- completion status (%x) "
  1953. "ioparam=%x/%x.\n", le16_to_cpu(lg->comp_status),
  1954. le32_to_cpu(lg->io_parameter[0]),
  1955. le32_to_cpu(lg->io_parameter[1]));
  1956. } else {
  1957. /*EMPTY*/
  1958. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1072,
  1959. "Done %s.\n", __func__);
  1960. }
  1961. dma_pool_free(ha->s_dma_pool, lg, lg_dma);
  1962. return rval;
  1963. }
  1964. /*
  1965. * qla2x00_fabric_logout
  1966. * Issue logout fabric port mailbox command.
  1967. *
  1968. * Input:
  1969. * ha = adapter block pointer.
  1970. * loop_id = device loop ID.
  1971. * TARGET_QUEUE_LOCK must be released.
  1972. * ADAPTER_STATE_LOCK must be released.
  1973. *
  1974. * Returns:
  1975. * qla2x00 local function return status code.
  1976. *
  1977. * Context:
  1978. * Kernel context.
  1979. */
  1980. int
  1981. qla2x00_fabric_logout(scsi_qla_host_t *vha, uint16_t loop_id, uint8_t domain,
  1982. uint8_t area, uint8_t al_pa)
  1983. {
  1984. int rval;
  1985. mbx_cmd_t mc;
  1986. mbx_cmd_t *mcp = &mc;
  1987. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1073,
  1988. "Entered %s.\n", __func__);
  1989. mcp->mb[0] = MBC_LOGOUT_FABRIC_PORT;
  1990. mcp->out_mb = MBX_1|MBX_0;
  1991. if (HAS_EXTENDED_IDS(vha->hw)) {
  1992. mcp->mb[1] = loop_id;
  1993. mcp->mb[10] = 0;
  1994. mcp->out_mb |= MBX_10;
  1995. } else {
  1996. mcp->mb[1] = loop_id << 8;
  1997. }
  1998. mcp->in_mb = MBX_1|MBX_0;
  1999. mcp->tov = MBX_TOV_SECONDS;
  2000. mcp->flags = 0;
  2001. rval = qla2x00_mailbox_command(vha, mcp);
  2002. if (rval != QLA_SUCCESS) {
  2003. /*EMPTY*/
  2004. ql_dbg(ql_dbg_mbx, vha, 0x1074,
  2005. "Failed=%x mb[1]=%x.\n", rval, mcp->mb[1]);
  2006. } else {
  2007. /*EMPTY*/
  2008. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1075,
  2009. "Done %s.\n", __func__);
  2010. }
  2011. return rval;
  2012. }
  2013. /*
  2014. * qla2x00_full_login_lip
  2015. * Issue full login LIP mailbox command.
  2016. *
  2017. * Input:
  2018. * ha = adapter block pointer.
  2019. * TARGET_QUEUE_LOCK must be released.
  2020. * ADAPTER_STATE_LOCK must be released.
  2021. *
  2022. * Returns:
  2023. * qla2x00 local function return status code.
  2024. *
  2025. * Context:
  2026. * Kernel context.
  2027. */
  2028. int
  2029. qla2x00_full_login_lip(scsi_qla_host_t *vha)
  2030. {
  2031. int rval;
  2032. mbx_cmd_t mc;
  2033. mbx_cmd_t *mcp = &mc;
  2034. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1076,
  2035. "Entered %s.\n", __func__);
  2036. mcp->mb[0] = MBC_LIP_FULL_LOGIN;
  2037. mcp->mb[1] = IS_FWI2_CAPABLE(vha->hw) ? BIT_3 : 0;
  2038. mcp->mb[2] = 0;
  2039. mcp->mb[3] = 0;
  2040. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  2041. mcp->in_mb = MBX_0;
  2042. mcp->tov = MBX_TOV_SECONDS;
  2043. mcp->flags = 0;
  2044. rval = qla2x00_mailbox_command(vha, mcp);
  2045. if (rval != QLA_SUCCESS) {
  2046. /*EMPTY*/
  2047. ql_dbg(ql_dbg_mbx, vha, 0x1077, "Failed=%x.\n", rval);
  2048. } else {
  2049. /*EMPTY*/
  2050. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1078,
  2051. "Done %s.\n", __func__);
  2052. }
  2053. return rval;
  2054. }
  2055. /*
  2056. * qla2x00_get_id_list
  2057. *
  2058. * Input:
  2059. * ha = adapter block pointer.
  2060. *
  2061. * Returns:
  2062. * qla2x00 local function return status code.
  2063. *
  2064. * Context:
  2065. * Kernel context.
  2066. */
  2067. int
  2068. qla2x00_get_id_list(scsi_qla_host_t *vha, void *id_list, dma_addr_t id_list_dma,
  2069. uint16_t *entries)
  2070. {
  2071. int rval;
  2072. mbx_cmd_t mc;
  2073. mbx_cmd_t *mcp = &mc;
  2074. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1079,
  2075. "Entered %s.\n", __func__);
  2076. if (id_list == NULL)
  2077. return QLA_FUNCTION_FAILED;
  2078. mcp->mb[0] = MBC_GET_ID_LIST;
  2079. mcp->out_mb = MBX_0;
  2080. if (IS_FWI2_CAPABLE(vha->hw)) {
  2081. mcp->mb[2] = MSW(id_list_dma);
  2082. mcp->mb[3] = LSW(id_list_dma);
  2083. mcp->mb[6] = MSW(MSD(id_list_dma));
  2084. mcp->mb[7] = LSW(MSD(id_list_dma));
  2085. mcp->mb[8] = 0;
  2086. mcp->mb[9] = vha->vp_idx;
  2087. mcp->out_mb |= MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2;
  2088. } else {
  2089. mcp->mb[1] = MSW(id_list_dma);
  2090. mcp->mb[2] = LSW(id_list_dma);
  2091. mcp->mb[3] = MSW(MSD(id_list_dma));
  2092. mcp->mb[6] = LSW(MSD(id_list_dma));
  2093. mcp->out_mb |= MBX_6|MBX_3|MBX_2|MBX_1;
  2094. }
  2095. mcp->in_mb = MBX_1|MBX_0;
  2096. mcp->tov = MBX_TOV_SECONDS;
  2097. mcp->flags = 0;
  2098. rval = qla2x00_mailbox_command(vha, mcp);
  2099. if (rval != QLA_SUCCESS) {
  2100. /*EMPTY*/
  2101. ql_dbg(ql_dbg_mbx, vha, 0x107a, "Failed=%x.\n", rval);
  2102. } else {
  2103. *entries = mcp->mb[1];
  2104. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107b,
  2105. "Done %s.\n", __func__);
  2106. }
  2107. return rval;
  2108. }
  2109. /*
  2110. * qla2x00_get_resource_cnts
  2111. * Get current firmware resource counts.
  2112. *
  2113. * Input:
  2114. * ha = adapter block pointer.
  2115. *
  2116. * Returns:
  2117. * qla2x00 local function return status code.
  2118. *
  2119. * Context:
  2120. * Kernel context.
  2121. */
  2122. int
  2123. qla2x00_get_resource_cnts(scsi_qla_host_t *vha, uint16_t *cur_xchg_cnt,
  2124. uint16_t *orig_xchg_cnt, uint16_t *cur_iocb_cnt,
  2125. uint16_t *orig_iocb_cnt, uint16_t *max_npiv_vports, uint16_t *max_fcfs)
  2126. {
  2127. int rval;
  2128. mbx_cmd_t mc;
  2129. mbx_cmd_t *mcp = &mc;
  2130. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107c,
  2131. "Entered %s.\n", __func__);
  2132. mcp->mb[0] = MBC_GET_RESOURCE_COUNTS;
  2133. mcp->out_mb = MBX_0;
  2134. mcp->in_mb = MBX_11|MBX_10|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  2135. if (IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) || IS_QLA27XX(vha->hw))
  2136. mcp->in_mb |= MBX_12;
  2137. mcp->tov = MBX_TOV_SECONDS;
  2138. mcp->flags = 0;
  2139. rval = qla2x00_mailbox_command(vha, mcp);
  2140. if (rval != QLA_SUCCESS) {
  2141. /*EMPTY*/
  2142. ql_dbg(ql_dbg_mbx, vha, 0x107d,
  2143. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2144. } else {
  2145. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107e,
  2146. "Done %s mb1=%x mb2=%x mb3=%x mb6=%x mb7=%x mb10=%x "
  2147. "mb11=%x mb12=%x.\n", __func__, mcp->mb[1], mcp->mb[2],
  2148. mcp->mb[3], mcp->mb[6], mcp->mb[7], mcp->mb[10],
  2149. mcp->mb[11], mcp->mb[12]);
  2150. if (cur_xchg_cnt)
  2151. *cur_xchg_cnt = mcp->mb[3];
  2152. if (orig_xchg_cnt)
  2153. *orig_xchg_cnt = mcp->mb[6];
  2154. if (cur_iocb_cnt)
  2155. *cur_iocb_cnt = mcp->mb[7];
  2156. if (orig_iocb_cnt)
  2157. *orig_iocb_cnt = mcp->mb[10];
  2158. if (vha->hw->flags.npiv_supported && max_npiv_vports)
  2159. *max_npiv_vports = mcp->mb[11];
  2160. if ((IS_QLA81XX(vha->hw) || IS_QLA83XX(vha->hw) ||
  2161. IS_QLA27XX(vha->hw)) && max_fcfs)
  2162. *max_fcfs = mcp->mb[12];
  2163. }
  2164. return (rval);
  2165. }
  2166. /*
  2167. * qla2x00_get_fcal_position_map
  2168. * Get FCAL (LILP) position map using mailbox command
  2169. *
  2170. * Input:
  2171. * ha = adapter state pointer.
  2172. * pos_map = buffer pointer (can be NULL).
  2173. *
  2174. * Returns:
  2175. * qla2x00 local function return status code.
  2176. *
  2177. * Context:
  2178. * Kernel context.
  2179. */
  2180. int
  2181. qla2x00_get_fcal_position_map(scsi_qla_host_t *vha, char *pos_map)
  2182. {
  2183. int rval;
  2184. mbx_cmd_t mc;
  2185. mbx_cmd_t *mcp = &mc;
  2186. char *pmap;
  2187. dma_addr_t pmap_dma;
  2188. struct qla_hw_data *ha = vha->hw;
  2189. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x107f,
  2190. "Entered %s.\n", __func__);
  2191. pmap = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &pmap_dma);
  2192. if (pmap == NULL) {
  2193. ql_log(ql_log_warn, vha, 0x1080,
  2194. "Memory alloc failed.\n");
  2195. return QLA_MEMORY_ALLOC_FAILED;
  2196. }
  2197. memset(pmap, 0, FCAL_MAP_SIZE);
  2198. mcp->mb[0] = MBC_GET_FC_AL_POSITION_MAP;
  2199. mcp->mb[2] = MSW(pmap_dma);
  2200. mcp->mb[3] = LSW(pmap_dma);
  2201. mcp->mb[6] = MSW(MSD(pmap_dma));
  2202. mcp->mb[7] = LSW(MSD(pmap_dma));
  2203. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2204. mcp->in_mb = MBX_1|MBX_0;
  2205. mcp->buf_size = FCAL_MAP_SIZE;
  2206. mcp->flags = MBX_DMA_IN;
  2207. mcp->tov = (ha->login_timeout * 2) + (ha->login_timeout / 2);
  2208. rval = qla2x00_mailbox_command(vha, mcp);
  2209. if (rval == QLA_SUCCESS) {
  2210. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1081,
  2211. "mb0/mb1=%x/%X FC/AL position map size (%x).\n",
  2212. mcp->mb[0], mcp->mb[1], (unsigned)pmap[0]);
  2213. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111d,
  2214. pmap, pmap[0] + 1);
  2215. if (pos_map)
  2216. memcpy(pos_map, pmap, FCAL_MAP_SIZE);
  2217. }
  2218. dma_pool_free(ha->s_dma_pool, pmap, pmap_dma);
  2219. if (rval != QLA_SUCCESS) {
  2220. ql_dbg(ql_dbg_mbx, vha, 0x1082, "Failed=%x.\n", rval);
  2221. } else {
  2222. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1083,
  2223. "Done %s.\n", __func__);
  2224. }
  2225. return rval;
  2226. }
  2227. /*
  2228. * qla2x00_get_link_status
  2229. *
  2230. * Input:
  2231. * ha = adapter block pointer.
  2232. * loop_id = device loop ID.
  2233. * ret_buf = pointer to link status return buffer.
  2234. *
  2235. * Returns:
  2236. * 0 = success.
  2237. * BIT_0 = mem alloc error.
  2238. * BIT_1 = mailbox error.
  2239. */
  2240. int
  2241. qla2x00_get_link_status(scsi_qla_host_t *vha, uint16_t loop_id,
  2242. struct link_statistics *stats, dma_addr_t stats_dma)
  2243. {
  2244. int rval;
  2245. mbx_cmd_t mc;
  2246. mbx_cmd_t *mcp = &mc;
  2247. uint32_t *siter, *diter, dwords;
  2248. struct qla_hw_data *ha = vha->hw;
  2249. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1084,
  2250. "Entered %s.\n", __func__);
  2251. mcp->mb[0] = MBC_GET_LINK_STATUS;
  2252. mcp->mb[2] = MSW(stats_dma);
  2253. mcp->mb[3] = LSW(stats_dma);
  2254. mcp->mb[6] = MSW(MSD(stats_dma));
  2255. mcp->mb[7] = LSW(MSD(stats_dma));
  2256. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2257. mcp->in_mb = MBX_0;
  2258. if (IS_FWI2_CAPABLE(ha)) {
  2259. mcp->mb[1] = loop_id;
  2260. mcp->mb[4] = 0;
  2261. mcp->mb[10] = 0;
  2262. mcp->out_mb |= MBX_10|MBX_4|MBX_1;
  2263. mcp->in_mb |= MBX_1;
  2264. } else if (HAS_EXTENDED_IDS(ha)) {
  2265. mcp->mb[1] = loop_id;
  2266. mcp->mb[10] = 0;
  2267. mcp->out_mb |= MBX_10|MBX_1;
  2268. } else {
  2269. mcp->mb[1] = loop_id << 8;
  2270. mcp->out_mb |= MBX_1;
  2271. }
  2272. mcp->tov = MBX_TOV_SECONDS;
  2273. mcp->flags = IOCTL_CMD;
  2274. rval = qla2x00_mailbox_command(vha, mcp);
  2275. if (rval == QLA_SUCCESS) {
  2276. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2277. ql_dbg(ql_dbg_mbx, vha, 0x1085,
  2278. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2279. rval = QLA_FUNCTION_FAILED;
  2280. } else {
  2281. /* Copy over data -- firmware data is LE. */
  2282. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1086,
  2283. "Done %s.\n", __func__);
  2284. dwords = offsetof(struct link_statistics, unused1) / 4;
  2285. siter = diter = &stats->link_fail_cnt;
  2286. while (dwords--)
  2287. *diter++ = le32_to_cpu(*siter++);
  2288. }
  2289. } else {
  2290. /* Failed. */
  2291. ql_dbg(ql_dbg_mbx, vha, 0x1087, "Failed=%x.\n", rval);
  2292. }
  2293. return rval;
  2294. }
  2295. int
  2296. qla24xx_get_isp_stats(scsi_qla_host_t *vha, struct link_statistics *stats,
  2297. dma_addr_t stats_dma)
  2298. {
  2299. int rval;
  2300. mbx_cmd_t mc;
  2301. mbx_cmd_t *mcp = &mc;
  2302. uint32_t *siter, *diter, dwords;
  2303. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1088,
  2304. "Entered %s.\n", __func__);
  2305. mcp->mb[0] = MBC_GET_LINK_PRIV_STATS;
  2306. mcp->mb[2] = MSW(stats_dma);
  2307. mcp->mb[3] = LSW(stats_dma);
  2308. mcp->mb[6] = MSW(MSD(stats_dma));
  2309. mcp->mb[7] = LSW(MSD(stats_dma));
  2310. mcp->mb[8] = sizeof(struct link_statistics) / 4;
  2311. mcp->mb[9] = vha->vp_idx;
  2312. mcp->mb[10] = 0;
  2313. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  2314. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2315. mcp->tov = MBX_TOV_SECONDS;
  2316. mcp->flags = IOCTL_CMD;
  2317. rval = qla2x00_mailbox_command(vha, mcp);
  2318. if (rval == QLA_SUCCESS) {
  2319. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  2320. ql_dbg(ql_dbg_mbx, vha, 0x1089,
  2321. "Failed mb[0]=%x.\n", mcp->mb[0]);
  2322. rval = QLA_FUNCTION_FAILED;
  2323. } else {
  2324. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108a,
  2325. "Done %s.\n", __func__);
  2326. /* Copy over data -- firmware data is LE. */
  2327. dwords = sizeof(struct link_statistics) / 4;
  2328. siter = diter = &stats->link_fail_cnt;
  2329. while (dwords--)
  2330. *diter++ = le32_to_cpu(*siter++);
  2331. }
  2332. } else {
  2333. /* Failed. */
  2334. ql_dbg(ql_dbg_mbx, vha, 0x108b, "Failed=%x.\n", rval);
  2335. }
  2336. return rval;
  2337. }
  2338. int
  2339. qla24xx_abort_command(srb_t *sp)
  2340. {
  2341. int rval;
  2342. unsigned long flags = 0;
  2343. struct abort_entry_24xx *abt;
  2344. dma_addr_t abt_dma;
  2345. uint32_t handle;
  2346. fc_port_t *fcport = sp->fcport;
  2347. struct scsi_qla_host *vha = fcport->vha;
  2348. struct qla_hw_data *ha = vha->hw;
  2349. struct req_que *req = vha->req;
  2350. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x108c,
  2351. "Entered %s.\n", __func__);
  2352. if (ql2xasynctmfenable)
  2353. return qla24xx_async_abort_command(sp);
  2354. spin_lock_irqsave(&ha->hardware_lock, flags);
  2355. for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
  2356. if (req->outstanding_cmds[handle] == sp)
  2357. break;
  2358. }
  2359. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  2360. if (handle == req->num_outstanding_cmds) {
  2361. /* Command not found. */
  2362. return QLA_FUNCTION_FAILED;
  2363. }
  2364. abt = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &abt_dma);
  2365. if (abt == NULL) {
  2366. ql_log(ql_log_warn, vha, 0x108d,
  2367. "Failed to allocate abort IOCB.\n");
  2368. return QLA_MEMORY_ALLOC_FAILED;
  2369. }
  2370. memset(abt, 0, sizeof(struct abort_entry_24xx));
  2371. abt->entry_type = ABORT_IOCB_TYPE;
  2372. abt->entry_count = 1;
  2373. abt->handle = MAKE_HANDLE(req->id, abt->handle);
  2374. abt->nport_handle = cpu_to_le16(fcport->loop_id);
  2375. abt->handle_to_abort = MAKE_HANDLE(req->id, handle);
  2376. abt->port_id[0] = fcport->d_id.b.al_pa;
  2377. abt->port_id[1] = fcport->d_id.b.area;
  2378. abt->port_id[2] = fcport->d_id.b.domain;
  2379. abt->vp_index = fcport->vha->vp_idx;
  2380. abt->req_que_no = cpu_to_le16(req->id);
  2381. rval = qla2x00_issue_iocb(vha, abt, abt_dma, 0);
  2382. if (rval != QLA_SUCCESS) {
  2383. ql_dbg(ql_dbg_mbx, vha, 0x108e,
  2384. "Failed to issue IOCB (%x).\n", rval);
  2385. } else if (abt->entry_status != 0) {
  2386. ql_dbg(ql_dbg_mbx, vha, 0x108f,
  2387. "Failed to complete IOCB -- error status (%x).\n",
  2388. abt->entry_status);
  2389. rval = QLA_FUNCTION_FAILED;
  2390. } else if (abt->nport_handle != cpu_to_le16(0)) {
  2391. ql_dbg(ql_dbg_mbx, vha, 0x1090,
  2392. "Failed to complete IOCB -- completion status (%x).\n",
  2393. le16_to_cpu(abt->nport_handle));
  2394. if (abt->nport_handle == CS_IOCB_ERROR)
  2395. rval = QLA_FUNCTION_PARAMETER_ERROR;
  2396. else
  2397. rval = QLA_FUNCTION_FAILED;
  2398. } else {
  2399. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1091,
  2400. "Done %s.\n", __func__);
  2401. }
  2402. dma_pool_free(ha->s_dma_pool, abt, abt_dma);
  2403. return rval;
  2404. }
  2405. struct tsk_mgmt_cmd {
  2406. union {
  2407. struct tsk_mgmt_entry tsk;
  2408. struct sts_entry_24xx sts;
  2409. } p;
  2410. };
  2411. static int
  2412. __qla24xx_issue_tmf(char *name, uint32_t type, struct fc_port *fcport,
  2413. uint64_t l, int tag)
  2414. {
  2415. int rval, rval2;
  2416. struct tsk_mgmt_cmd *tsk;
  2417. struct sts_entry_24xx *sts;
  2418. dma_addr_t tsk_dma;
  2419. scsi_qla_host_t *vha;
  2420. struct qla_hw_data *ha;
  2421. struct req_que *req;
  2422. struct rsp_que *rsp;
  2423. vha = fcport->vha;
  2424. ha = vha->hw;
  2425. req = vha->req;
  2426. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1092,
  2427. "Entered %s.\n", __func__);
  2428. if (ha->flags.cpu_affinity_enabled)
  2429. rsp = ha->rsp_q_map[tag + 1];
  2430. else
  2431. rsp = req->rsp;
  2432. tsk = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &tsk_dma);
  2433. if (tsk == NULL) {
  2434. ql_log(ql_log_warn, vha, 0x1093,
  2435. "Failed to allocate task management IOCB.\n");
  2436. return QLA_MEMORY_ALLOC_FAILED;
  2437. }
  2438. memset(tsk, 0, sizeof(struct tsk_mgmt_cmd));
  2439. tsk->p.tsk.entry_type = TSK_MGMT_IOCB_TYPE;
  2440. tsk->p.tsk.entry_count = 1;
  2441. tsk->p.tsk.handle = MAKE_HANDLE(req->id, tsk->p.tsk.handle);
  2442. tsk->p.tsk.nport_handle = cpu_to_le16(fcport->loop_id);
  2443. tsk->p.tsk.timeout = cpu_to_le16(ha->r_a_tov / 10 * 2);
  2444. tsk->p.tsk.control_flags = cpu_to_le32(type);
  2445. tsk->p.tsk.port_id[0] = fcport->d_id.b.al_pa;
  2446. tsk->p.tsk.port_id[1] = fcport->d_id.b.area;
  2447. tsk->p.tsk.port_id[2] = fcport->d_id.b.domain;
  2448. tsk->p.tsk.vp_index = fcport->vha->vp_idx;
  2449. if (type == TCF_LUN_RESET) {
  2450. int_to_scsilun(l, &tsk->p.tsk.lun);
  2451. host_to_fcp_swap((uint8_t *)&tsk->p.tsk.lun,
  2452. sizeof(tsk->p.tsk.lun));
  2453. }
  2454. sts = &tsk->p.sts;
  2455. rval = qla2x00_issue_iocb(vha, tsk, tsk_dma, 0);
  2456. if (rval != QLA_SUCCESS) {
  2457. ql_dbg(ql_dbg_mbx, vha, 0x1094,
  2458. "Failed to issue %s reset IOCB (%x).\n", name, rval);
  2459. } else if (sts->entry_status != 0) {
  2460. ql_dbg(ql_dbg_mbx, vha, 0x1095,
  2461. "Failed to complete IOCB -- error status (%x).\n",
  2462. sts->entry_status);
  2463. rval = QLA_FUNCTION_FAILED;
  2464. } else if (sts->comp_status != cpu_to_le16(CS_COMPLETE)) {
  2465. ql_dbg(ql_dbg_mbx, vha, 0x1096,
  2466. "Failed to complete IOCB -- completion status (%x).\n",
  2467. le16_to_cpu(sts->comp_status));
  2468. rval = QLA_FUNCTION_FAILED;
  2469. } else if (le16_to_cpu(sts->scsi_status) &
  2470. SS_RESPONSE_INFO_LEN_VALID) {
  2471. if (le32_to_cpu(sts->rsp_data_len) < 4) {
  2472. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1097,
  2473. "Ignoring inconsistent data length -- not enough "
  2474. "response info (%d).\n",
  2475. le32_to_cpu(sts->rsp_data_len));
  2476. } else if (sts->data[3]) {
  2477. ql_dbg(ql_dbg_mbx, vha, 0x1098,
  2478. "Failed to complete IOCB -- response (%x).\n",
  2479. sts->data[3]);
  2480. rval = QLA_FUNCTION_FAILED;
  2481. }
  2482. }
  2483. /* Issue marker IOCB. */
  2484. rval2 = qla2x00_marker(vha, req, rsp, fcport->loop_id, l,
  2485. type == TCF_LUN_RESET ? MK_SYNC_ID_LUN: MK_SYNC_ID);
  2486. if (rval2 != QLA_SUCCESS) {
  2487. ql_dbg(ql_dbg_mbx, vha, 0x1099,
  2488. "Failed to issue marker IOCB (%x).\n", rval2);
  2489. } else {
  2490. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109a,
  2491. "Done %s.\n", __func__);
  2492. }
  2493. dma_pool_free(ha->s_dma_pool, tsk, tsk_dma);
  2494. return rval;
  2495. }
  2496. int
  2497. qla24xx_abort_target(struct fc_port *fcport, uint64_t l, int tag)
  2498. {
  2499. struct qla_hw_data *ha = fcport->vha->hw;
  2500. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2501. return qla2x00_async_tm_cmd(fcport, TCF_TARGET_RESET, l, tag);
  2502. return __qla24xx_issue_tmf("Target", TCF_TARGET_RESET, fcport, l, tag);
  2503. }
  2504. int
  2505. qla24xx_lun_reset(struct fc_port *fcport, uint64_t l, int tag)
  2506. {
  2507. struct qla_hw_data *ha = fcport->vha->hw;
  2508. if ((ql2xasynctmfenable) && IS_FWI2_CAPABLE(ha))
  2509. return qla2x00_async_tm_cmd(fcport, TCF_LUN_RESET, l, tag);
  2510. return __qla24xx_issue_tmf("Lun", TCF_LUN_RESET, fcport, l, tag);
  2511. }
  2512. int
  2513. qla2x00_system_error(scsi_qla_host_t *vha)
  2514. {
  2515. int rval;
  2516. mbx_cmd_t mc;
  2517. mbx_cmd_t *mcp = &mc;
  2518. struct qla_hw_data *ha = vha->hw;
  2519. if (!IS_QLA23XX(ha) && !IS_FWI2_CAPABLE(ha))
  2520. return QLA_FUNCTION_FAILED;
  2521. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109b,
  2522. "Entered %s.\n", __func__);
  2523. mcp->mb[0] = MBC_GEN_SYSTEM_ERROR;
  2524. mcp->out_mb = MBX_0;
  2525. mcp->in_mb = MBX_0;
  2526. mcp->tov = 5;
  2527. mcp->flags = 0;
  2528. rval = qla2x00_mailbox_command(vha, mcp);
  2529. if (rval != QLA_SUCCESS) {
  2530. ql_dbg(ql_dbg_mbx, vha, 0x109c, "Failed=%x.\n", rval);
  2531. } else {
  2532. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109d,
  2533. "Done %s.\n", __func__);
  2534. }
  2535. return rval;
  2536. }
  2537. int
  2538. qla2x00_write_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t data)
  2539. {
  2540. int rval;
  2541. mbx_cmd_t mc;
  2542. mbx_cmd_t *mcp = &mc;
  2543. if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
  2544. !IS_QLA27XX(vha->hw))
  2545. return QLA_FUNCTION_FAILED;
  2546. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1182,
  2547. "Entered %s.\n", __func__);
  2548. mcp->mb[0] = MBC_WRITE_SERDES;
  2549. mcp->mb[1] = addr;
  2550. if (IS_QLA2031(vha->hw))
  2551. mcp->mb[2] = data & 0xff;
  2552. else
  2553. mcp->mb[2] = data;
  2554. mcp->mb[3] = 0;
  2555. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  2556. mcp->in_mb = MBX_0;
  2557. mcp->tov = MBX_TOV_SECONDS;
  2558. mcp->flags = 0;
  2559. rval = qla2x00_mailbox_command(vha, mcp);
  2560. if (rval != QLA_SUCCESS) {
  2561. ql_dbg(ql_dbg_mbx, vha, 0x1183,
  2562. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2563. } else {
  2564. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1184,
  2565. "Done %s.\n", __func__);
  2566. }
  2567. return rval;
  2568. }
  2569. int
  2570. qla2x00_read_serdes_word(scsi_qla_host_t *vha, uint16_t addr, uint16_t *data)
  2571. {
  2572. int rval;
  2573. mbx_cmd_t mc;
  2574. mbx_cmd_t *mcp = &mc;
  2575. if (!IS_QLA25XX(vha->hw) && !IS_QLA2031(vha->hw) &&
  2576. !IS_QLA27XX(vha->hw))
  2577. return QLA_FUNCTION_FAILED;
  2578. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1185,
  2579. "Entered %s.\n", __func__);
  2580. mcp->mb[0] = MBC_READ_SERDES;
  2581. mcp->mb[1] = addr;
  2582. mcp->mb[3] = 0;
  2583. mcp->out_mb = MBX_3|MBX_1|MBX_0;
  2584. mcp->in_mb = MBX_1|MBX_0;
  2585. mcp->tov = MBX_TOV_SECONDS;
  2586. mcp->flags = 0;
  2587. rval = qla2x00_mailbox_command(vha, mcp);
  2588. if (IS_QLA2031(vha->hw))
  2589. *data = mcp->mb[1] & 0xff;
  2590. else
  2591. *data = mcp->mb[1];
  2592. if (rval != QLA_SUCCESS) {
  2593. ql_dbg(ql_dbg_mbx, vha, 0x1186,
  2594. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2595. } else {
  2596. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1187,
  2597. "Done %s.\n", __func__);
  2598. }
  2599. return rval;
  2600. }
  2601. int
  2602. qla8044_write_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
  2603. {
  2604. int rval;
  2605. mbx_cmd_t mc;
  2606. mbx_cmd_t *mcp = &mc;
  2607. if (!IS_QLA8044(vha->hw))
  2608. return QLA_FUNCTION_FAILED;
  2609. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1186,
  2610. "Entered %s.\n", __func__);
  2611. mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
  2612. mcp->mb[1] = HCS_WRITE_SERDES;
  2613. mcp->mb[3] = LSW(addr);
  2614. mcp->mb[4] = MSW(addr);
  2615. mcp->mb[5] = LSW(data);
  2616. mcp->mb[6] = MSW(data);
  2617. mcp->out_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_1|MBX_0;
  2618. mcp->in_mb = MBX_0;
  2619. mcp->tov = MBX_TOV_SECONDS;
  2620. mcp->flags = 0;
  2621. rval = qla2x00_mailbox_command(vha, mcp);
  2622. if (rval != QLA_SUCCESS) {
  2623. ql_dbg(ql_dbg_mbx, vha, 0x1187,
  2624. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2625. } else {
  2626. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1188,
  2627. "Done %s.\n", __func__);
  2628. }
  2629. return rval;
  2630. }
  2631. int
  2632. qla8044_read_serdes_word(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
  2633. {
  2634. int rval;
  2635. mbx_cmd_t mc;
  2636. mbx_cmd_t *mcp = &mc;
  2637. if (!IS_QLA8044(vha->hw))
  2638. return QLA_FUNCTION_FAILED;
  2639. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1189,
  2640. "Entered %s.\n", __func__);
  2641. mcp->mb[0] = MBC_SET_GET_ETH_SERDES_REG;
  2642. mcp->mb[1] = HCS_READ_SERDES;
  2643. mcp->mb[3] = LSW(addr);
  2644. mcp->mb[4] = MSW(addr);
  2645. mcp->out_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  2646. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  2647. mcp->tov = MBX_TOV_SECONDS;
  2648. mcp->flags = 0;
  2649. rval = qla2x00_mailbox_command(vha, mcp);
  2650. *data = mcp->mb[2] << 16 | mcp->mb[1];
  2651. if (rval != QLA_SUCCESS) {
  2652. ql_dbg(ql_dbg_mbx, vha, 0x118a,
  2653. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2654. } else {
  2655. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x118b,
  2656. "Done %s.\n", __func__);
  2657. }
  2658. return rval;
  2659. }
  2660. /**
  2661. * qla2x00_set_serdes_params() -
  2662. * @ha: HA context
  2663. *
  2664. * Returns
  2665. */
  2666. int
  2667. qla2x00_set_serdes_params(scsi_qla_host_t *vha, uint16_t sw_em_1g,
  2668. uint16_t sw_em_2g, uint16_t sw_em_4g)
  2669. {
  2670. int rval;
  2671. mbx_cmd_t mc;
  2672. mbx_cmd_t *mcp = &mc;
  2673. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x109e,
  2674. "Entered %s.\n", __func__);
  2675. mcp->mb[0] = MBC_SERDES_PARAMS;
  2676. mcp->mb[1] = BIT_0;
  2677. mcp->mb[2] = sw_em_1g | BIT_15;
  2678. mcp->mb[3] = sw_em_2g | BIT_15;
  2679. mcp->mb[4] = sw_em_4g | BIT_15;
  2680. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2681. mcp->in_mb = MBX_0;
  2682. mcp->tov = MBX_TOV_SECONDS;
  2683. mcp->flags = 0;
  2684. rval = qla2x00_mailbox_command(vha, mcp);
  2685. if (rval != QLA_SUCCESS) {
  2686. /*EMPTY*/
  2687. ql_dbg(ql_dbg_mbx, vha, 0x109f,
  2688. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  2689. } else {
  2690. /*EMPTY*/
  2691. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a0,
  2692. "Done %s.\n", __func__);
  2693. }
  2694. return rval;
  2695. }
  2696. int
  2697. qla2x00_stop_firmware(scsi_qla_host_t *vha)
  2698. {
  2699. int rval;
  2700. mbx_cmd_t mc;
  2701. mbx_cmd_t *mcp = &mc;
  2702. if (!IS_FWI2_CAPABLE(vha->hw))
  2703. return QLA_FUNCTION_FAILED;
  2704. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a1,
  2705. "Entered %s.\n", __func__);
  2706. mcp->mb[0] = MBC_STOP_FIRMWARE;
  2707. mcp->mb[1] = 0;
  2708. mcp->out_mb = MBX_1|MBX_0;
  2709. mcp->in_mb = MBX_0;
  2710. mcp->tov = 5;
  2711. mcp->flags = 0;
  2712. rval = qla2x00_mailbox_command(vha, mcp);
  2713. if (rval != QLA_SUCCESS) {
  2714. ql_dbg(ql_dbg_mbx, vha, 0x10a2, "Failed=%x.\n", rval);
  2715. if (mcp->mb[0] == MBS_INVALID_COMMAND)
  2716. rval = QLA_INVALID_COMMAND;
  2717. } else {
  2718. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a3,
  2719. "Done %s.\n", __func__);
  2720. }
  2721. return rval;
  2722. }
  2723. int
  2724. qla2x00_enable_eft_trace(scsi_qla_host_t *vha, dma_addr_t eft_dma,
  2725. uint16_t buffers)
  2726. {
  2727. int rval;
  2728. mbx_cmd_t mc;
  2729. mbx_cmd_t *mcp = &mc;
  2730. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a4,
  2731. "Entered %s.\n", __func__);
  2732. if (!IS_FWI2_CAPABLE(vha->hw))
  2733. return QLA_FUNCTION_FAILED;
  2734. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2735. return QLA_FUNCTION_FAILED;
  2736. mcp->mb[0] = MBC_TRACE_CONTROL;
  2737. mcp->mb[1] = TC_EFT_ENABLE;
  2738. mcp->mb[2] = LSW(eft_dma);
  2739. mcp->mb[3] = MSW(eft_dma);
  2740. mcp->mb[4] = LSW(MSD(eft_dma));
  2741. mcp->mb[5] = MSW(MSD(eft_dma));
  2742. mcp->mb[6] = buffers;
  2743. mcp->mb[7] = TC_AEN_DISABLE;
  2744. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2745. mcp->in_mb = MBX_1|MBX_0;
  2746. mcp->tov = MBX_TOV_SECONDS;
  2747. mcp->flags = 0;
  2748. rval = qla2x00_mailbox_command(vha, mcp);
  2749. if (rval != QLA_SUCCESS) {
  2750. ql_dbg(ql_dbg_mbx, vha, 0x10a5,
  2751. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2752. rval, mcp->mb[0], mcp->mb[1]);
  2753. } else {
  2754. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a6,
  2755. "Done %s.\n", __func__);
  2756. }
  2757. return rval;
  2758. }
  2759. int
  2760. qla2x00_disable_eft_trace(scsi_qla_host_t *vha)
  2761. {
  2762. int rval;
  2763. mbx_cmd_t mc;
  2764. mbx_cmd_t *mcp = &mc;
  2765. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a7,
  2766. "Entered %s.\n", __func__);
  2767. if (!IS_FWI2_CAPABLE(vha->hw))
  2768. return QLA_FUNCTION_FAILED;
  2769. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2770. return QLA_FUNCTION_FAILED;
  2771. mcp->mb[0] = MBC_TRACE_CONTROL;
  2772. mcp->mb[1] = TC_EFT_DISABLE;
  2773. mcp->out_mb = MBX_1|MBX_0;
  2774. mcp->in_mb = MBX_1|MBX_0;
  2775. mcp->tov = MBX_TOV_SECONDS;
  2776. mcp->flags = 0;
  2777. rval = qla2x00_mailbox_command(vha, mcp);
  2778. if (rval != QLA_SUCCESS) {
  2779. ql_dbg(ql_dbg_mbx, vha, 0x10a8,
  2780. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2781. rval, mcp->mb[0], mcp->mb[1]);
  2782. } else {
  2783. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10a9,
  2784. "Done %s.\n", __func__);
  2785. }
  2786. return rval;
  2787. }
  2788. int
  2789. qla2x00_enable_fce_trace(scsi_qla_host_t *vha, dma_addr_t fce_dma,
  2790. uint16_t buffers, uint16_t *mb, uint32_t *dwords)
  2791. {
  2792. int rval;
  2793. mbx_cmd_t mc;
  2794. mbx_cmd_t *mcp = &mc;
  2795. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10aa,
  2796. "Entered %s.\n", __func__);
  2797. if (!IS_QLA25XX(vha->hw) && !IS_QLA81XX(vha->hw) &&
  2798. !IS_QLA83XX(vha->hw) && !IS_QLA27XX(vha->hw))
  2799. return QLA_FUNCTION_FAILED;
  2800. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2801. return QLA_FUNCTION_FAILED;
  2802. mcp->mb[0] = MBC_TRACE_CONTROL;
  2803. mcp->mb[1] = TC_FCE_ENABLE;
  2804. mcp->mb[2] = LSW(fce_dma);
  2805. mcp->mb[3] = MSW(fce_dma);
  2806. mcp->mb[4] = LSW(MSD(fce_dma));
  2807. mcp->mb[5] = MSW(MSD(fce_dma));
  2808. mcp->mb[6] = buffers;
  2809. mcp->mb[7] = TC_AEN_DISABLE;
  2810. mcp->mb[8] = 0;
  2811. mcp->mb[9] = TC_FCE_DEFAULT_RX_SIZE;
  2812. mcp->mb[10] = TC_FCE_DEFAULT_TX_SIZE;
  2813. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2814. MBX_1|MBX_0;
  2815. mcp->in_mb = MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  2816. mcp->tov = MBX_TOV_SECONDS;
  2817. mcp->flags = 0;
  2818. rval = qla2x00_mailbox_command(vha, mcp);
  2819. if (rval != QLA_SUCCESS) {
  2820. ql_dbg(ql_dbg_mbx, vha, 0x10ab,
  2821. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2822. rval, mcp->mb[0], mcp->mb[1]);
  2823. } else {
  2824. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ac,
  2825. "Done %s.\n", __func__);
  2826. if (mb)
  2827. memcpy(mb, mcp->mb, 8 * sizeof(*mb));
  2828. if (dwords)
  2829. *dwords = buffers;
  2830. }
  2831. return rval;
  2832. }
  2833. int
  2834. qla2x00_disable_fce_trace(scsi_qla_host_t *vha, uint64_t *wr, uint64_t *rd)
  2835. {
  2836. int rval;
  2837. mbx_cmd_t mc;
  2838. mbx_cmd_t *mcp = &mc;
  2839. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ad,
  2840. "Entered %s.\n", __func__);
  2841. if (!IS_FWI2_CAPABLE(vha->hw))
  2842. return QLA_FUNCTION_FAILED;
  2843. if (unlikely(pci_channel_offline(vha->hw->pdev)))
  2844. return QLA_FUNCTION_FAILED;
  2845. mcp->mb[0] = MBC_TRACE_CONTROL;
  2846. mcp->mb[1] = TC_FCE_DISABLE;
  2847. mcp->mb[2] = TC_FCE_DISABLE_TRACE;
  2848. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  2849. mcp->in_mb = MBX_9|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|
  2850. MBX_1|MBX_0;
  2851. mcp->tov = MBX_TOV_SECONDS;
  2852. mcp->flags = 0;
  2853. rval = qla2x00_mailbox_command(vha, mcp);
  2854. if (rval != QLA_SUCCESS) {
  2855. ql_dbg(ql_dbg_mbx, vha, 0x10ae,
  2856. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  2857. rval, mcp->mb[0], mcp->mb[1]);
  2858. } else {
  2859. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10af,
  2860. "Done %s.\n", __func__);
  2861. if (wr)
  2862. *wr = (uint64_t) mcp->mb[5] << 48 |
  2863. (uint64_t) mcp->mb[4] << 32 |
  2864. (uint64_t) mcp->mb[3] << 16 |
  2865. (uint64_t) mcp->mb[2];
  2866. if (rd)
  2867. *rd = (uint64_t) mcp->mb[9] << 48 |
  2868. (uint64_t) mcp->mb[8] << 32 |
  2869. (uint64_t) mcp->mb[7] << 16 |
  2870. (uint64_t) mcp->mb[6];
  2871. }
  2872. return rval;
  2873. }
  2874. int
  2875. qla2x00_get_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2876. uint16_t *port_speed, uint16_t *mb)
  2877. {
  2878. int rval;
  2879. mbx_cmd_t mc;
  2880. mbx_cmd_t *mcp = &mc;
  2881. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b0,
  2882. "Entered %s.\n", __func__);
  2883. if (!IS_IIDMA_CAPABLE(vha->hw))
  2884. return QLA_FUNCTION_FAILED;
  2885. mcp->mb[0] = MBC_PORT_PARAMS;
  2886. mcp->mb[1] = loop_id;
  2887. mcp->mb[2] = mcp->mb[3] = 0;
  2888. mcp->mb[9] = vha->vp_idx;
  2889. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2890. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2891. mcp->tov = MBX_TOV_SECONDS;
  2892. mcp->flags = 0;
  2893. rval = qla2x00_mailbox_command(vha, mcp);
  2894. /* Return mailbox statuses. */
  2895. if (mb != NULL) {
  2896. mb[0] = mcp->mb[0];
  2897. mb[1] = mcp->mb[1];
  2898. mb[3] = mcp->mb[3];
  2899. }
  2900. if (rval != QLA_SUCCESS) {
  2901. ql_dbg(ql_dbg_mbx, vha, 0x10b1, "Failed=%x.\n", rval);
  2902. } else {
  2903. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b2,
  2904. "Done %s.\n", __func__);
  2905. if (port_speed)
  2906. *port_speed = mcp->mb[3];
  2907. }
  2908. return rval;
  2909. }
  2910. int
  2911. qla2x00_set_idma_speed(scsi_qla_host_t *vha, uint16_t loop_id,
  2912. uint16_t port_speed, uint16_t *mb)
  2913. {
  2914. int rval;
  2915. mbx_cmd_t mc;
  2916. mbx_cmd_t *mcp = &mc;
  2917. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b3,
  2918. "Entered %s.\n", __func__);
  2919. if (!IS_IIDMA_CAPABLE(vha->hw))
  2920. return QLA_FUNCTION_FAILED;
  2921. mcp->mb[0] = MBC_PORT_PARAMS;
  2922. mcp->mb[1] = loop_id;
  2923. mcp->mb[2] = BIT_0;
  2924. mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
  2925. mcp->mb[9] = vha->vp_idx;
  2926. mcp->out_mb = MBX_9|MBX_3|MBX_2|MBX_1|MBX_0;
  2927. mcp->in_mb = MBX_3|MBX_1|MBX_0;
  2928. mcp->tov = MBX_TOV_SECONDS;
  2929. mcp->flags = 0;
  2930. rval = qla2x00_mailbox_command(vha, mcp);
  2931. /* Return mailbox statuses. */
  2932. if (mb != NULL) {
  2933. mb[0] = mcp->mb[0];
  2934. mb[1] = mcp->mb[1];
  2935. mb[3] = mcp->mb[3];
  2936. }
  2937. if (rval != QLA_SUCCESS) {
  2938. ql_dbg(ql_dbg_mbx, vha, 0x10b4,
  2939. "Failed=%x.\n", rval);
  2940. } else {
  2941. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b5,
  2942. "Done %s.\n", __func__);
  2943. }
  2944. return rval;
  2945. }
  2946. void
  2947. qla24xx_report_id_acquisition(scsi_qla_host_t *vha,
  2948. struct vp_rpt_id_entry_24xx *rptid_entry)
  2949. {
  2950. uint8_t vp_idx;
  2951. uint16_t stat = le16_to_cpu(rptid_entry->vp_idx);
  2952. struct qla_hw_data *ha = vha->hw;
  2953. scsi_qla_host_t *vp;
  2954. unsigned long flags;
  2955. int found;
  2956. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b6,
  2957. "Entered %s.\n", __func__);
  2958. if (rptid_entry->entry_status != 0)
  2959. return;
  2960. if (rptid_entry->format == 0) {
  2961. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b7,
  2962. "Format 0 : Number of VPs setup %d, number of "
  2963. "VPs acquired %d.\n",
  2964. MSB(le16_to_cpu(rptid_entry->vp_count)),
  2965. LSB(le16_to_cpu(rptid_entry->vp_count)));
  2966. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b8,
  2967. "Primary port id %02x%02x%02x.\n",
  2968. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2969. rptid_entry->port_id[0]);
  2970. } else if (rptid_entry->format == 1) {
  2971. vp_idx = LSB(stat);
  2972. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10b9,
  2973. "Format 1: VP[%d] enabled - status %d - with "
  2974. "port id %02x%02x%02x.\n", vp_idx, MSB(stat),
  2975. rptid_entry->port_id[2], rptid_entry->port_id[1],
  2976. rptid_entry->port_id[0]);
  2977. /* FA-WWN is only for physical port */
  2978. if (!vp_idx) {
  2979. void *wwpn = ha->init_cb->port_name;
  2980. if (!MSB(stat)) {
  2981. if (rptid_entry->vp_idx_map[1] & BIT_6)
  2982. wwpn = rptid_entry->reserved_4 + 8;
  2983. }
  2984. memcpy(vha->port_name, wwpn, WWN_SIZE);
  2985. fc_host_port_name(vha->host) =
  2986. wwn_to_u64(vha->port_name);
  2987. ql_dbg(ql_dbg_mbx, vha, 0x1018,
  2988. "FA-WWN portname %016llx (%x)\n",
  2989. fc_host_port_name(vha->host), MSB(stat));
  2990. }
  2991. vp = vha;
  2992. if (vp_idx == 0)
  2993. goto reg_needed;
  2994. if (MSB(stat) != 0 && MSB(stat) != 2) {
  2995. ql_dbg(ql_dbg_mbx, vha, 0x10ba,
  2996. "Could not acquire ID for VP[%d].\n", vp_idx);
  2997. return;
  2998. }
  2999. found = 0;
  3000. spin_lock_irqsave(&ha->vport_slock, flags);
  3001. list_for_each_entry(vp, &ha->vp_list, list) {
  3002. if (vp_idx == vp->vp_idx) {
  3003. found = 1;
  3004. break;
  3005. }
  3006. }
  3007. spin_unlock_irqrestore(&ha->vport_slock, flags);
  3008. if (!found)
  3009. return;
  3010. vp->d_id.b.domain = rptid_entry->port_id[2];
  3011. vp->d_id.b.area = rptid_entry->port_id[1];
  3012. vp->d_id.b.al_pa = rptid_entry->port_id[0];
  3013. /*
  3014. * Cannot configure here as we are still sitting on the
  3015. * response queue. Handle it in dpc context.
  3016. */
  3017. set_bit(VP_IDX_ACQUIRED, &vp->vp_flags);
  3018. reg_needed:
  3019. set_bit(REGISTER_FC4_NEEDED, &vp->dpc_flags);
  3020. set_bit(REGISTER_FDMI_NEEDED, &vp->dpc_flags);
  3021. set_bit(VP_DPC_NEEDED, &vha->dpc_flags);
  3022. qla2xxx_wake_dpc(vha);
  3023. }
  3024. }
  3025. /*
  3026. * qla24xx_modify_vp_config
  3027. * Change VP configuration for vha
  3028. *
  3029. * Input:
  3030. * vha = adapter block pointer.
  3031. *
  3032. * Returns:
  3033. * qla2xxx local function return status code.
  3034. *
  3035. * Context:
  3036. * Kernel context.
  3037. */
  3038. int
  3039. qla24xx_modify_vp_config(scsi_qla_host_t *vha)
  3040. {
  3041. int rval;
  3042. struct vp_config_entry_24xx *vpmod;
  3043. dma_addr_t vpmod_dma;
  3044. struct qla_hw_data *ha = vha->hw;
  3045. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3046. /* This can be called by the parent */
  3047. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10bb,
  3048. "Entered %s.\n", __func__);
  3049. vpmod = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vpmod_dma);
  3050. if (!vpmod) {
  3051. ql_log(ql_log_warn, vha, 0x10bc,
  3052. "Failed to allocate modify VP IOCB.\n");
  3053. return QLA_MEMORY_ALLOC_FAILED;
  3054. }
  3055. memset(vpmod, 0, sizeof(struct vp_config_entry_24xx));
  3056. vpmod->entry_type = VP_CONFIG_IOCB_TYPE;
  3057. vpmod->entry_count = 1;
  3058. vpmod->command = VCT_COMMAND_MOD_ENABLE_VPS;
  3059. vpmod->vp_count = 1;
  3060. vpmod->vp_index1 = vha->vp_idx;
  3061. vpmod->options_idx1 = BIT_3|BIT_4|BIT_5;
  3062. qlt_modify_vp_config(vha, vpmod);
  3063. memcpy(vpmod->node_name_idx1, vha->node_name, WWN_SIZE);
  3064. memcpy(vpmod->port_name_idx1, vha->port_name, WWN_SIZE);
  3065. vpmod->entry_count = 1;
  3066. rval = qla2x00_issue_iocb(base_vha, vpmod, vpmod_dma, 0);
  3067. if (rval != QLA_SUCCESS) {
  3068. ql_dbg(ql_dbg_mbx, vha, 0x10bd,
  3069. "Failed to issue VP config IOCB (%x).\n", rval);
  3070. } else if (vpmod->comp_status != 0) {
  3071. ql_dbg(ql_dbg_mbx, vha, 0x10be,
  3072. "Failed to complete IOCB -- error status (%x).\n",
  3073. vpmod->comp_status);
  3074. rval = QLA_FUNCTION_FAILED;
  3075. } else if (vpmod->comp_status != cpu_to_le16(CS_COMPLETE)) {
  3076. ql_dbg(ql_dbg_mbx, vha, 0x10bf,
  3077. "Failed to complete IOCB -- completion status (%x).\n",
  3078. le16_to_cpu(vpmod->comp_status));
  3079. rval = QLA_FUNCTION_FAILED;
  3080. } else {
  3081. /* EMPTY */
  3082. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c0,
  3083. "Done %s.\n", __func__);
  3084. fc_vport_set_state(vha->fc_vport, FC_VPORT_INITIALIZING);
  3085. }
  3086. dma_pool_free(ha->s_dma_pool, vpmod, vpmod_dma);
  3087. return rval;
  3088. }
  3089. /*
  3090. * qla24xx_control_vp
  3091. * Enable a virtual port for given host
  3092. *
  3093. * Input:
  3094. * ha = adapter block pointer.
  3095. * vhba = virtual adapter (unused)
  3096. * index = index number for enabled VP
  3097. *
  3098. * Returns:
  3099. * qla2xxx local function return status code.
  3100. *
  3101. * Context:
  3102. * Kernel context.
  3103. */
  3104. int
  3105. qla24xx_control_vp(scsi_qla_host_t *vha, int cmd)
  3106. {
  3107. int rval;
  3108. int map, pos;
  3109. struct vp_ctrl_entry_24xx *vce;
  3110. dma_addr_t vce_dma;
  3111. struct qla_hw_data *ha = vha->hw;
  3112. int vp_index = vha->vp_idx;
  3113. struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
  3114. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c1,
  3115. "Entered %s enabling index %d.\n", __func__, vp_index);
  3116. if (vp_index == 0 || vp_index >= ha->max_npiv_vports)
  3117. return QLA_PARAMETER_ERROR;
  3118. vce = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &vce_dma);
  3119. if (!vce) {
  3120. ql_log(ql_log_warn, vha, 0x10c2,
  3121. "Failed to allocate VP control IOCB.\n");
  3122. return QLA_MEMORY_ALLOC_FAILED;
  3123. }
  3124. memset(vce, 0, sizeof(struct vp_ctrl_entry_24xx));
  3125. vce->entry_type = VP_CTRL_IOCB_TYPE;
  3126. vce->entry_count = 1;
  3127. vce->command = cpu_to_le16(cmd);
  3128. vce->vp_count = cpu_to_le16(1);
  3129. /* index map in firmware starts with 1; decrement index
  3130. * this is ok as we never use index 0
  3131. */
  3132. map = (vp_index - 1) / 8;
  3133. pos = (vp_index - 1) & 7;
  3134. mutex_lock(&ha->vport_lock);
  3135. vce->vp_idx_map[map] |= 1 << pos;
  3136. mutex_unlock(&ha->vport_lock);
  3137. rval = qla2x00_issue_iocb(base_vha, vce, vce_dma, 0);
  3138. if (rval != QLA_SUCCESS) {
  3139. ql_dbg(ql_dbg_mbx, vha, 0x10c3,
  3140. "Failed to issue VP control IOCB (%x).\n", rval);
  3141. } else if (vce->entry_status != 0) {
  3142. ql_dbg(ql_dbg_mbx, vha, 0x10c4,
  3143. "Failed to complete IOCB -- error status (%x).\n",
  3144. vce->entry_status);
  3145. rval = QLA_FUNCTION_FAILED;
  3146. } else if (vce->comp_status != cpu_to_le16(CS_COMPLETE)) {
  3147. ql_dbg(ql_dbg_mbx, vha, 0x10c5,
  3148. "Failed to complet IOCB -- completion status (%x).\n",
  3149. le16_to_cpu(vce->comp_status));
  3150. rval = QLA_FUNCTION_FAILED;
  3151. } else {
  3152. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c6,
  3153. "Done %s.\n", __func__);
  3154. }
  3155. dma_pool_free(ha->s_dma_pool, vce, vce_dma);
  3156. return rval;
  3157. }
  3158. /*
  3159. * qla2x00_send_change_request
  3160. * Receive or disable RSCN request from fabric controller
  3161. *
  3162. * Input:
  3163. * ha = adapter block pointer
  3164. * format = registration format:
  3165. * 0 - Reserved
  3166. * 1 - Fabric detected registration
  3167. * 2 - N_port detected registration
  3168. * 3 - Full registration
  3169. * FF - clear registration
  3170. * vp_idx = Virtual port index
  3171. *
  3172. * Returns:
  3173. * qla2x00 local function return status code.
  3174. *
  3175. * Context:
  3176. * Kernel Context
  3177. */
  3178. int
  3179. qla2x00_send_change_request(scsi_qla_host_t *vha, uint16_t format,
  3180. uint16_t vp_idx)
  3181. {
  3182. int rval;
  3183. mbx_cmd_t mc;
  3184. mbx_cmd_t *mcp = &mc;
  3185. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c7,
  3186. "Entered %s.\n", __func__);
  3187. mcp->mb[0] = MBC_SEND_CHANGE_REQUEST;
  3188. mcp->mb[1] = format;
  3189. mcp->mb[9] = vp_idx;
  3190. mcp->out_mb = MBX_9|MBX_1|MBX_0;
  3191. mcp->in_mb = MBX_0|MBX_1;
  3192. mcp->tov = MBX_TOV_SECONDS;
  3193. mcp->flags = 0;
  3194. rval = qla2x00_mailbox_command(vha, mcp);
  3195. if (rval == QLA_SUCCESS) {
  3196. if (mcp->mb[0] != MBS_COMMAND_COMPLETE) {
  3197. rval = BIT_1;
  3198. }
  3199. } else
  3200. rval = BIT_1;
  3201. return rval;
  3202. }
  3203. int
  3204. qla2x00_dump_ram(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  3205. uint32_t size)
  3206. {
  3207. int rval;
  3208. mbx_cmd_t mc;
  3209. mbx_cmd_t *mcp = &mc;
  3210. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1009,
  3211. "Entered %s.\n", __func__);
  3212. if (MSW(addr) || IS_FWI2_CAPABLE(vha->hw)) {
  3213. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  3214. mcp->mb[8] = MSW(addr);
  3215. mcp->out_mb = MBX_8|MBX_0;
  3216. } else {
  3217. mcp->mb[0] = MBC_DUMP_RISC_RAM;
  3218. mcp->out_mb = MBX_0;
  3219. }
  3220. mcp->mb[1] = LSW(addr);
  3221. mcp->mb[2] = MSW(req_dma);
  3222. mcp->mb[3] = LSW(req_dma);
  3223. mcp->mb[6] = MSW(MSD(req_dma));
  3224. mcp->mb[7] = LSW(MSD(req_dma));
  3225. mcp->out_mb |= MBX_7|MBX_6|MBX_3|MBX_2|MBX_1;
  3226. if (IS_FWI2_CAPABLE(vha->hw)) {
  3227. mcp->mb[4] = MSW(size);
  3228. mcp->mb[5] = LSW(size);
  3229. mcp->out_mb |= MBX_5|MBX_4;
  3230. } else {
  3231. mcp->mb[4] = LSW(size);
  3232. mcp->out_mb |= MBX_4;
  3233. }
  3234. mcp->in_mb = MBX_0;
  3235. mcp->tov = MBX_TOV_SECONDS;
  3236. mcp->flags = 0;
  3237. rval = qla2x00_mailbox_command(vha, mcp);
  3238. if (rval != QLA_SUCCESS) {
  3239. ql_dbg(ql_dbg_mbx, vha, 0x1008,
  3240. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3241. } else {
  3242. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1007,
  3243. "Done %s.\n", __func__);
  3244. }
  3245. return rval;
  3246. }
  3247. /* 84XX Support **************************************************************/
  3248. struct cs84xx_mgmt_cmd {
  3249. union {
  3250. struct verify_chip_entry_84xx req;
  3251. struct verify_chip_rsp_84xx rsp;
  3252. } p;
  3253. };
  3254. int
  3255. qla84xx_verify_chip(struct scsi_qla_host *vha, uint16_t *status)
  3256. {
  3257. int rval, retry;
  3258. struct cs84xx_mgmt_cmd *mn;
  3259. dma_addr_t mn_dma;
  3260. uint16_t options;
  3261. unsigned long flags;
  3262. struct qla_hw_data *ha = vha->hw;
  3263. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10c8,
  3264. "Entered %s.\n", __func__);
  3265. mn = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &mn_dma);
  3266. if (mn == NULL) {
  3267. return QLA_MEMORY_ALLOC_FAILED;
  3268. }
  3269. /* Force Update? */
  3270. options = ha->cs84xx->fw_update ? VCO_FORCE_UPDATE : 0;
  3271. /* Diagnostic firmware? */
  3272. /* options |= MENLO_DIAG_FW; */
  3273. /* We update the firmware with only one data sequence. */
  3274. options |= VCO_END_OF_DATA;
  3275. do {
  3276. retry = 0;
  3277. memset(mn, 0, sizeof(*mn));
  3278. mn->p.req.entry_type = VERIFY_CHIP_IOCB_TYPE;
  3279. mn->p.req.entry_count = 1;
  3280. mn->p.req.options = cpu_to_le16(options);
  3281. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111c,
  3282. "Dump of Verify Request.\n");
  3283. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x111e,
  3284. (uint8_t *)mn, sizeof(*mn));
  3285. rval = qla2x00_issue_iocb_timeout(vha, mn, mn_dma, 0, 120);
  3286. if (rval != QLA_SUCCESS) {
  3287. ql_dbg(ql_dbg_mbx, vha, 0x10cb,
  3288. "Failed to issue verify IOCB (%x).\n", rval);
  3289. goto verify_done;
  3290. }
  3291. ql_dbg(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1110,
  3292. "Dump of Verify Response.\n");
  3293. ql_dump_buffer(ql_dbg_mbx + ql_dbg_buffer, vha, 0x1118,
  3294. (uint8_t *)mn, sizeof(*mn));
  3295. status[0] = le16_to_cpu(mn->p.rsp.comp_status);
  3296. status[1] = status[0] == CS_VCS_CHIP_FAILURE ?
  3297. le16_to_cpu(mn->p.rsp.failure_code) : 0;
  3298. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ce,
  3299. "cs=%x fc=%x.\n", status[0], status[1]);
  3300. if (status[0] != CS_COMPLETE) {
  3301. rval = QLA_FUNCTION_FAILED;
  3302. if (!(options & VCO_DONT_UPDATE_FW)) {
  3303. ql_dbg(ql_dbg_mbx, vha, 0x10cf,
  3304. "Firmware update failed. Retrying "
  3305. "without update firmware.\n");
  3306. options |= VCO_DONT_UPDATE_FW;
  3307. options &= ~VCO_FORCE_UPDATE;
  3308. retry = 1;
  3309. }
  3310. } else {
  3311. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d0,
  3312. "Firmware updated to %x.\n",
  3313. le32_to_cpu(mn->p.rsp.fw_ver));
  3314. /* NOTE: we only update OP firmware. */
  3315. spin_lock_irqsave(&ha->cs84xx->access_lock, flags);
  3316. ha->cs84xx->op_fw_version =
  3317. le32_to_cpu(mn->p.rsp.fw_ver);
  3318. spin_unlock_irqrestore(&ha->cs84xx->access_lock,
  3319. flags);
  3320. }
  3321. } while (retry);
  3322. verify_done:
  3323. dma_pool_free(ha->s_dma_pool, mn, mn_dma);
  3324. if (rval != QLA_SUCCESS) {
  3325. ql_dbg(ql_dbg_mbx, vha, 0x10d1,
  3326. "Failed=%x.\n", rval);
  3327. } else {
  3328. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d2,
  3329. "Done %s.\n", __func__);
  3330. }
  3331. return rval;
  3332. }
  3333. int
  3334. qla25xx_init_req_que(struct scsi_qla_host *vha, struct req_que *req)
  3335. {
  3336. int rval;
  3337. unsigned long flags;
  3338. mbx_cmd_t mc;
  3339. mbx_cmd_t *mcp = &mc;
  3340. struct qla_hw_data *ha = vha->hw;
  3341. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d3,
  3342. "Entered %s.\n", __func__);
  3343. if (IS_SHADOW_REG_CAPABLE(ha))
  3344. req->options |= BIT_13;
  3345. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3346. mcp->mb[1] = req->options;
  3347. mcp->mb[2] = MSW(LSD(req->dma));
  3348. mcp->mb[3] = LSW(LSD(req->dma));
  3349. mcp->mb[6] = MSW(MSD(req->dma));
  3350. mcp->mb[7] = LSW(MSD(req->dma));
  3351. mcp->mb[5] = req->length;
  3352. if (req->rsp)
  3353. mcp->mb[10] = req->rsp->id;
  3354. mcp->mb[12] = req->qos;
  3355. mcp->mb[11] = req->vp_idx;
  3356. mcp->mb[13] = req->rid;
  3357. if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
  3358. mcp->mb[15] = 0;
  3359. mcp->mb[4] = req->id;
  3360. /* que in ptr index */
  3361. mcp->mb[8] = 0;
  3362. /* que out ptr index */
  3363. mcp->mb[9] = *req->out_ptr = 0;
  3364. mcp->out_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|MBX_7|
  3365. MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3366. mcp->in_mb = MBX_0;
  3367. mcp->flags = MBX_DMA_OUT;
  3368. mcp->tov = MBX_TOV_SECONDS * 2;
  3369. if (IS_QLA81XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha))
  3370. mcp->in_mb |= MBX_1;
  3371. if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  3372. mcp->out_mb |= MBX_15;
  3373. /* debug q create issue in SR-IOV */
  3374. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3375. }
  3376. spin_lock_irqsave(&ha->hardware_lock, flags);
  3377. if (!(req->options & BIT_0)) {
  3378. WRT_REG_DWORD(req->req_q_in, 0);
  3379. if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
  3380. WRT_REG_DWORD(req->req_q_out, 0);
  3381. }
  3382. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3383. rval = qla2x00_mailbox_command(vha, mcp);
  3384. if (rval != QLA_SUCCESS) {
  3385. ql_dbg(ql_dbg_mbx, vha, 0x10d4,
  3386. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3387. } else {
  3388. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d5,
  3389. "Done %s.\n", __func__);
  3390. }
  3391. return rval;
  3392. }
  3393. int
  3394. qla25xx_init_rsp_que(struct scsi_qla_host *vha, struct rsp_que *rsp)
  3395. {
  3396. int rval;
  3397. unsigned long flags;
  3398. mbx_cmd_t mc;
  3399. mbx_cmd_t *mcp = &mc;
  3400. struct qla_hw_data *ha = vha->hw;
  3401. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d6,
  3402. "Entered %s.\n", __func__);
  3403. if (IS_SHADOW_REG_CAPABLE(ha))
  3404. rsp->options |= BIT_13;
  3405. mcp->mb[0] = MBC_INITIALIZE_MULTIQ;
  3406. mcp->mb[1] = rsp->options;
  3407. mcp->mb[2] = MSW(LSD(rsp->dma));
  3408. mcp->mb[3] = LSW(LSD(rsp->dma));
  3409. mcp->mb[6] = MSW(MSD(rsp->dma));
  3410. mcp->mb[7] = LSW(MSD(rsp->dma));
  3411. mcp->mb[5] = rsp->length;
  3412. mcp->mb[14] = rsp->msix->entry;
  3413. mcp->mb[13] = rsp->rid;
  3414. if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
  3415. mcp->mb[15] = 0;
  3416. mcp->mb[4] = rsp->id;
  3417. /* que in ptr index */
  3418. mcp->mb[8] = *rsp->in_ptr = 0;
  3419. /* que out ptr index */
  3420. mcp->mb[9] = 0;
  3421. mcp->out_mb = MBX_14|MBX_13|MBX_9|MBX_8|MBX_7
  3422. |MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3423. mcp->in_mb = MBX_0;
  3424. mcp->flags = MBX_DMA_OUT;
  3425. mcp->tov = MBX_TOV_SECONDS * 2;
  3426. if (IS_QLA81XX(ha)) {
  3427. mcp->out_mb |= MBX_12|MBX_11|MBX_10;
  3428. mcp->in_mb |= MBX_1;
  3429. } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
  3430. mcp->out_mb |= MBX_15|MBX_12|MBX_11|MBX_10;
  3431. mcp->in_mb |= MBX_1;
  3432. /* debug q create issue in SR-IOV */
  3433. mcp->in_mb |= MBX_9 | MBX_8 | MBX_7;
  3434. }
  3435. spin_lock_irqsave(&ha->hardware_lock, flags);
  3436. if (!(rsp->options & BIT_0)) {
  3437. WRT_REG_DWORD(rsp->rsp_q_out, 0);
  3438. if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
  3439. WRT_REG_DWORD(rsp->rsp_q_in, 0);
  3440. }
  3441. spin_unlock_irqrestore(&ha->hardware_lock, flags);
  3442. rval = qla2x00_mailbox_command(vha, mcp);
  3443. if (rval != QLA_SUCCESS) {
  3444. ql_dbg(ql_dbg_mbx, vha, 0x10d7,
  3445. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3446. } else {
  3447. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d8,
  3448. "Done %s.\n", __func__);
  3449. }
  3450. return rval;
  3451. }
  3452. int
  3453. qla81xx_idc_ack(scsi_qla_host_t *vha, uint16_t *mb)
  3454. {
  3455. int rval;
  3456. mbx_cmd_t mc;
  3457. mbx_cmd_t *mcp = &mc;
  3458. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10d9,
  3459. "Entered %s.\n", __func__);
  3460. mcp->mb[0] = MBC_IDC_ACK;
  3461. memcpy(&mcp->mb[1], mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
  3462. mcp->out_mb = MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3463. mcp->in_mb = MBX_0;
  3464. mcp->tov = MBX_TOV_SECONDS;
  3465. mcp->flags = 0;
  3466. rval = qla2x00_mailbox_command(vha, mcp);
  3467. if (rval != QLA_SUCCESS) {
  3468. ql_dbg(ql_dbg_mbx, vha, 0x10da,
  3469. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3470. } else {
  3471. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10db,
  3472. "Done %s.\n", __func__);
  3473. }
  3474. return rval;
  3475. }
  3476. int
  3477. qla81xx_fac_get_sector_size(scsi_qla_host_t *vha, uint32_t *sector_size)
  3478. {
  3479. int rval;
  3480. mbx_cmd_t mc;
  3481. mbx_cmd_t *mcp = &mc;
  3482. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10dc,
  3483. "Entered %s.\n", __func__);
  3484. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
  3485. !IS_QLA27XX(vha->hw))
  3486. return QLA_FUNCTION_FAILED;
  3487. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3488. mcp->mb[1] = FAC_OPT_CMD_GET_SECTOR_SIZE;
  3489. mcp->out_mb = MBX_1|MBX_0;
  3490. mcp->in_mb = MBX_1|MBX_0;
  3491. mcp->tov = MBX_TOV_SECONDS;
  3492. mcp->flags = 0;
  3493. rval = qla2x00_mailbox_command(vha, mcp);
  3494. if (rval != QLA_SUCCESS) {
  3495. ql_dbg(ql_dbg_mbx, vha, 0x10dd,
  3496. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3497. rval, mcp->mb[0], mcp->mb[1]);
  3498. } else {
  3499. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10de,
  3500. "Done %s.\n", __func__);
  3501. *sector_size = mcp->mb[1];
  3502. }
  3503. return rval;
  3504. }
  3505. int
  3506. qla81xx_fac_do_write_enable(scsi_qla_host_t *vha, int enable)
  3507. {
  3508. int rval;
  3509. mbx_cmd_t mc;
  3510. mbx_cmd_t *mcp = &mc;
  3511. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
  3512. !IS_QLA27XX(vha->hw))
  3513. return QLA_FUNCTION_FAILED;
  3514. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10df,
  3515. "Entered %s.\n", __func__);
  3516. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3517. mcp->mb[1] = enable ? FAC_OPT_CMD_WRITE_ENABLE :
  3518. FAC_OPT_CMD_WRITE_PROTECT;
  3519. mcp->out_mb = MBX_1|MBX_0;
  3520. mcp->in_mb = MBX_1|MBX_0;
  3521. mcp->tov = MBX_TOV_SECONDS;
  3522. mcp->flags = 0;
  3523. rval = qla2x00_mailbox_command(vha, mcp);
  3524. if (rval != QLA_SUCCESS) {
  3525. ql_dbg(ql_dbg_mbx, vha, 0x10e0,
  3526. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3527. rval, mcp->mb[0], mcp->mb[1]);
  3528. } else {
  3529. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e1,
  3530. "Done %s.\n", __func__);
  3531. }
  3532. return rval;
  3533. }
  3534. int
  3535. qla81xx_fac_erase_sector(scsi_qla_host_t *vha, uint32_t start, uint32_t finish)
  3536. {
  3537. int rval;
  3538. mbx_cmd_t mc;
  3539. mbx_cmd_t *mcp = &mc;
  3540. if (!IS_QLA81XX(vha->hw) && !IS_QLA83XX(vha->hw) &&
  3541. !IS_QLA27XX(vha->hw))
  3542. return QLA_FUNCTION_FAILED;
  3543. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e2,
  3544. "Entered %s.\n", __func__);
  3545. mcp->mb[0] = MBC_FLASH_ACCESS_CTRL;
  3546. mcp->mb[1] = FAC_OPT_CMD_ERASE_SECTOR;
  3547. mcp->mb[2] = LSW(start);
  3548. mcp->mb[3] = MSW(start);
  3549. mcp->mb[4] = LSW(finish);
  3550. mcp->mb[5] = MSW(finish);
  3551. mcp->out_mb = MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  3552. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3553. mcp->tov = MBX_TOV_SECONDS;
  3554. mcp->flags = 0;
  3555. rval = qla2x00_mailbox_command(vha, mcp);
  3556. if (rval != QLA_SUCCESS) {
  3557. ql_dbg(ql_dbg_mbx, vha, 0x10e3,
  3558. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3559. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3560. } else {
  3561. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e4,
  3562. "Done %s.\n", __func__);
  3563. }
  3564. return rval;
  3565. }
  3566. int
  3567. qla81xx_restart_mpi_firmware(scsi_qla_host_t *vha)
  3568. {
  3569. int rval = 0;
  3570. mbx_cmd_t mc;
  3571. mbx_cmd_t *mcp = &mc;
  3572. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e5,
  3573. "Entered %s.\n", __func__);
  3574. mcp->mb[0] = MBC_RESTART_MPI_FW;
  3575. mcp->out_mb = MBX_0;
  3576. mcp->in_mb = MBX_0|MBX_1;
  3577. mcp->tov = MBX_TOV_SECONDS;
  3578. mcp->flags = 0;
  3579. rval = qla2x00_mailbox_command(vha, mcp);
  3580. if (rval != QLA_SUCCESS) {
  3581. ql_dbg(ql_dbg_mbx, vha, 0x10e6,
  3582. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3583. rval, mcp->mb[0], mcp->mb[1]);
  3584. } else {
  3585. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e7,
  3586. "Done %s.\n", __func__);
  3587. }
  3588. return rval;
  3589. }
  3590. int
  3591. qla82xx_set_driver_version(scsi_qla_host_t *vha, char *version)
  3592. {
  3593. int rval;
  3594. mbx_cmd_t mc;
  3595. mbx_cmd_t *mcp = &mc;
  3596. int i;
  3597. int len;
  3598. uint16_t *str;
  3599. struct qla_hw_data *ha = vha->hw;
  3600. if (!IS_P3P_TYPE(ha))
  3601. return QLA_FUNCTION_FAILED;
  3602. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117b,
  3603. "Entered %s.\n", __func__);
  3604. str = (void *)version;
  3605. len = strlen(version);
  3606. mcp->mb[0] = MBC_SET_RNID_PARAMS;
  3607. mcp->mb[1] = RNID_TYPE_SET_VERSION << 8;
  3608. mcp->out_mb = MBX_1|MBX_0;
  3609. for (i = 4; i < 16 && len; i++, str++, len -= 2) {
  3610. mcp->mb[i] = cpu_to_le16p(str);
  3611. mcp->out_mb |= 1<<i;
  3612. }
  3613. for (; i < 16; i++) {
  3614. mcp->mb[i] = 0;
  3615. mcp->out_mb |= 1<<i;
  3616. }
  3617. mcp->in_mb = MBX_1|MBX_0;
  3618. mcp->tov = MBX_TOV_SECONDS;
  3619. mcp->flags = 0;
  3620. rval = qla2x00_mailbox_command(vha, mcp);
  3621. if (rval != QLA_SUCCESS) {
  3622. ql_dbg(ql_dbg_mbx, vha, 0x117c,
  3623. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3624. } else {
  3625. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117d,
  3626. "Done %s.\n", __func__);
  3627. }
  3628. return rval;
  3629. }
  3630. int
  3631. qla25xx_set_driver_version(scsi_qla_host_t *vha, char *version)
  3632. {
  3633. int rval;
  3634. mbx_cmd_t mc;
  3635. mbx_cmd_t *mcp = &mc;
  3636. int len;
  3637. uint16_t dwlen;
  3638. uint8_t *str;
  3639. dma_addr_t str_dma;
  3640. struct qla_hw_data *ha = vha->hw;
  3641. if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha) ||
  3642. IS_P3P_TYPE(ha))
  3643. return QLA_FUNCTION_FAILED;
  3644. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x117e,
  3645. "Entered %s.\n", __func__);
  3646. str = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, &str_dma);
  3647. if (!str) {
  3648. ql_log(ql_log_warn, vha, 0x117f,
  3649. "Failed to allocate driver version param.\n");
  3650. return QLA_MEMORY_ALLOC_FAILED;
  3651. }
  3652. memcpy(str, "\x7\x3\x11\x0", 4);
  3653. dwlen = str[0];
  3654. len = dwlen * 4 - 4;
  3655. memset(str + 4, 0, len);
  3656. if (len > strlen(version))
  3657. len = strlen(version);
  3658. memcpy(str + 4, version, len);
  3659. mcp->mb[0] = MBC_SET_RNID_PARAMS;
  3660. mcp->mb[1] = RNID_TYPE_SET_VERSION << 8 | dwlen;
  3661. mcp->mb[2] = MSW(LSD(str_dma));
  3662. mcp->mb[3] = LSW(LSD(str_dma));
  3663. mcp->mb[6] = MSW(MSD(str_dma));
  3664. mcp->mb[7] = LSW(MSD(str_dma));
  3665. mcp->out_mb = MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3666. mcp->in_mb = MBX_1|MBX_0;
  3667. mcp->tov = MBX_TOV_SECONDS;
  3668. mcp->flags = 0;
  3669. rval = qla2x00_mailbox_command(vha, mcp);
  3670. if (rval != QLA_SUCCESS) {
  3671. ql_dbg(ql_dbg_mbx, vha, 0x1180,
  3672. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3673. } else {
  3674. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1181,
  3675. "Done %s.\n", __func__);
  3676. }
  3677. dma_pool_free(ha->s_dma_pool, str, str_dma);
  3678. return rval;
  3679. }
  3680. static int
  3681. qla2x00_read_asic_temperature(scsi_qla_host_t *vha, uint16_t *temp)
  3682. {
  3683. int rval;
  3684. mbx_cmd_t mc;
  3685. mbx_cmd_t *mcp = &mc;
  3686. if (!IS_FWI2_CAPABLE(vha->hw))
  3687. return QLA_FUNCTION_FAILED;
  3688. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1159,
  3689. "Entered %s.\n", __func__);
  3690. mcp->mb[0] = MBC_GET_RNID_PARAMS;
  3691. mcp->mb[1] = RNID_TYPE_ASIC_TEMP << 8;
  3692. mcp->out_mb = MBX_1|MBX_0;
  3693. mcp->in_mb = MBX_1|MBX_0;
  3694. mcp->tov = MBX_TOV_SECONDS;
  3695. mcp->flags = 0;
  3696. rval = qla2x00_mailbox_command(vha, mcp);
  3697. *temp = mcp->mb[1];
  3698. if (rval != QLA_SUCCESS) {
  3699. ql_dbg(ql_dbg_mbx, vha, 0x115a,
  3700. "Failed=%x mb[0]=%x,%x.\n", rval, mcp->mb[0], mcp->mb[1]);
  3701. } else {
  3702. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x115b,
  3703. "Done %s.\n", __func__);
  3704. }
  3705. return rval;
  3706. }
  3707. int
  3708. qla2x00_read_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3709. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3710. {
  3711. int rval;
  3712. mbx_cmd_t mc;
  3713. mbx_cmd_t *mcp = &mc;
  3714. struct qla_hw_data *ha = vha->hw;
  3715. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10e8,
  3716. "Entered %s.\n", __func__);
  3717. if (!IS_FWI2_CAPABLE(ha))
  3718. return QLA_FUNCTION_FAILED;
  3719. if (len == 1)
  3720. opt |= BIT_0;
  3721. mcp->mb[0] = MBC_READ_SFP;
  3722. mcp->mb[1] = dev;
  3723. mcp->mb[2] = MSW(sfp_dma);
  3724. mcp->mb[3] = LSW(sfp_dma);
  3725. mcp->mb[6] = MSW(MSD(sfp_dma));
  3726. mcp->mb[7] = LSW(MSD(sfp_dma));
  3727. mcp->mb[8] = len;
  3728. mcp->mb[9] = off;
  3729. mcp->mb[10] = opt;
  3730. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3731. mcp->in_mb = MBX_1|MBX_0;
  3732. mcp->tov = MBX_TOV_SECONDS;
  3733. mcp->flags = 0;
  3734. rval = qla2x00_mailbox_command(vha, mcp);
  3735. if (opt & BIT_0)
  3736. *sfp = mcp->mb[1];
  3737. if (rval != QLA_SUCCESS) {
  3738. ql_dbg(ql_dbg_mbx, vha, 0x10e9,
  3739. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3740. } else {
  3741. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ea,
  3742. "Done %s.\n", __func__);
  3743. }
  3744. return rval;
  3745. }
  3746. int
  3747. qla2x00_write_sfp(scsi_qla_host_t *vha, dma_addr_t sfp_dma, uint8_t *sfp,
  3748. uint16_t dev, uint16_t off, uint16_t len, uint16_t opt)
  3749. {
  3750. int rval;
  3751. mbx_cmd_t mc;
  3752. mbx_cmd_t *mcp = &mc;
  3753. struct qla_hw_data *ha = vha->hw;
  3754. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10eb,
  3755. "Entered %s.\n", __func__);
  3756. if (!IS_FWI2_CAPABLE(ha))
  3757. return QLA_FUNCTION_FAILED;
  3758. if (len == 1)
  3759. opt |= BIT_0;
  3760. if (opt & BIT_0)
  3761. len = *sfp;
  3762. mcp->mb[0] = MBC_WRITE_SFP;
  3763. mcp->mb[1] = dev;
  3764. mcp->mb[2] = MSW(sfp_dma);
  3765. mcp->mb[3] = LSW(sfp_dma);
  3766. mcp->mb[6] = MSW(MSD(sfp_dma));
  3767. mcp->mb[7] = LSW(MSD(sfp_dma));
  3768. mcp->mb[8] = len;
  3769. mcp->mb[9] = off;
  3770. mcp->mb[10] = opt;
  3771. mcp->out_mb = MBX_10|MBX_9|MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3772. mcp->in_mb = MBX_1|MBX_0;
  3773. mcp->tov = MBX_TOV_SECONDS;
  3774. mcp->flags = 0;
  3775. rval = qla2x00_mailbox_command(vha, mcp);
  3776. if (rval != QLA_SUCCESS) {
  3777. ql_dbg(ql_dbg_mbx, vha, 0x10ec,
  3778. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3779. } else {
  3780. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ed,
  3781. "Done %s.\n", __func__);
  3782. }
  3783. return rval;
  3784. }
  3785. int
  3786. qla2x00_get_xgmac_stats(scsi_qla_host_t *vha, dma_addr_t stats_dma,
  3787. uint16_t size_in_bytes, uint16_t *actual_size)
  3788. {
  3789. int rval;
  3790. mbx_cmd_t mc;
  3791. mbx_cmd_t *mcp = &mc;
  3792. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ee,
  3793. "Entered %s.\n", __func__);
  3794. if (!IS_CNA_CAPABLE(vha->hw))
  3795. return QLA_FUNCTION_FAILED;
  3796. mcp->mb[0] = MBC_GET_XGMAC_STATS;
  3797. mcp->mb[2] = MSW(stats_dma);
  3798. mcp->mb[3] = LSW(stats_dma);
  3799. mcp->mb[6] = MSW(MSD(stats_dma));
  3800. mcp->mb[7] = LSW(MSD(stats_dma));
  3801. mcp->mb[8] = size_in_bytes >> 2;
  3802. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_0;
  3803. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3804. mcp->tov = MBX_TOV_SECONDS;
  3805. mcp->flags = 0;
  3806. rval = qla2x00_mailbox_command(vha, mcp);
  3807. if (rval != QLA_SUCCESS) {
  3808. ql_dbg(ql_dbg_mbx, vha, 0x10ef,
  3809. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3810. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3811. } else {
  3812. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f0,
  3813. "Done %s.\n", __func__);
  3814. *actual_size = mcp->mb[2] << 2;
  3815. }
  3816. return rval;
  3817. }
  3818. int
  3819. qla2x00_get_dcbx_params(scsi_qla_host_t *vha, dma_addr_t tlv_dma,
  3820. uint16_t size)
  3821. {
  3822. int rval;
  3823. mbx_cmd_t mc;
  3824. mbx_cmd_t *mcp = &mc;
  3825. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f1,
  3826. "Entered %s.\n", __func__);
  3827. if (!IS_CNA_CAPABLE(vha->hw))
  3828. return QLA_FUNCTION_FAILED;
  3829. mcp->mb[0] = MBC_GET_DCBX_PARAMS;
  3830. mcp->mb[1] = 0;
  3831. mcp->mb[2] = MSW(tlv_dma);
  3832. mcp->mb[3] = LSW(tlv_dma);
  3833. mcp->mb[6] = MSW(MSD(tlv_dma));
  3834. mcp->mb[7] = LSW(MSD(tlv_dma));
  3835. mcp->mb[8] = size;
  3836. mcp->out_mb = MBX_8|MBX_7|MBX_6|MBX_3|MBX_2|MBX_1|MBX_0;
  3837. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  3838. mcp->tov = MBX_TOV_SECONDS;
  3839. mcp->flags = 0;
  3840. rval = qla2x00_mailbox_command(vha, mcp);
  3841. if (rval != QLA_SUCCESS) {
  3842. ql_dbg(ql_dbg_mbx, vha, 0x10f2,
  3843. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x.\n",
  3844. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2]);
  3845. } else {
  3846. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f3,
  3847. "Done %s.\n", __func__);
  3848. }
  3849. return rval;
  3850. }
  3851. int
  3852. qla2x00_read_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t *data)
  3853. {
  3854. int rval;
  3855. mbx_cmd_t mc;
  3856. mbx_cmd_t *mcp = &mc;
  3857. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f4,
  3858. "Entered %s.\n", __func__);
  3859. if (!IS_FWI2_CAPABLE(vha->hw))
  3860. return QLA_FUNCTION_FAILED;
  3861. mcp->mb[0] = MBC_READ_RAM_EXTENDED;
  3862. mcp->mb[1] = LSW(risc_addr);
  3863. mcp->mb[8] = MSW(risc_addr);
  3864. mcp->out_mb = MBX_8|MBX_1|MBX_0;
  3865. mcp->in_mb = MBX_3|MBX_2|MBX_0;
  3866. mcp->tov = 30;
  3867. mcp->flags = 0;
  3868. rval = qla2x00_mailbox_command(vha, mcp);
  3869. if (rval != QLA_SUCCESS) {
  3870. ql_dbg(ql_dbg_mbx, vha, 0x10f5,
  3871. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  3872. } else {
  3873. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f6,
  3874. "Done %s.\n", __func__);
  3875. *data = mcp->mb[3] << 16 | mcp->mb[2];
  3876. }
  3877. return rval;
  3878. }
  3879. int
  3880. qla2x00_loopback_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3881. uint16_t *mresp)
  3882. {
  3883. int rval;
  3884. mbx_cmd_t mc;
  3885. mbx_cmd_t *mcp = &mc;
  3886. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f7,
  3887. "Entered %s.\n", __func__);
  3888. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3889. mcp->mb[0] = MBC_DIAGNOSTIC_LOOP_BACK;
  3890. mcp->mb[1] = mreq->options | BIT_6; // BIT_6 specifies 64 bit addressing
  3891. /* transfer count */
  3892. mcp->mb[10] = LSW(mreq->transfer_size);
  3893. mcp->mb[11] = MSW(mreq->transfer_size);
  3894. /* send data address */
  3895. mcp->mb[14] = LSW(mreq->send_dma);
  3896. mcp->mb[15] = MSW(mreq->send_dma);
  3897. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3898. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3899. /* receive data address */
  3900. mcp->mb[16] = LSW(mreq->rcv_dma);
  3901. mcp->mb[17] = MSW(mreq->rcv_dma);
  3902. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3903. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3904. /* Iteration count */
  3905. mcp->mb[18] = LSW(mreq->iteration_count);
  3906. mcp->mb[19] = MSW(mreq->iteration_count);
  3907. mcp->out_mb = MBX_21|MBX_20|MBX_19|MBX_18|MBX_17|MBX_16|MBX_15|
  3908. MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3909. if (IS_CNA_CAPABLE(vha->hw))
  3910. mcp->out_mb |= MBX_2;
  3911. mcp->in_mb = MBX_19|MBX_18|MBX_3|MBX_2|MBX_1|MBX_0;
  3912. mcp->buf_size = mreq->transfer_size;
  3913. mcp->tov = MBX_TOV_SECONDS;
  3914. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3915. rval = qla2x00_mailbox_command(vha, mcp);
  3916. if (rval != QLA_SUCCESS) {
  3917. ql_dbg(ql_dbg_mbx, vha, 0x10f8,
  3918. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[18]=%x "
  3919. "mb[19]=%x.\n", rval, mcp->mb[0], mcp->mb[1], mcp->mb[2],
  3920. mcp->mb[3], mcp->mb[18], mcp->mb[19]);
  3921. } else {
  3922. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10f9,
  3923. "Done %s.\n", __func__);
  3924. }
  3925. /* Copy mailbox information */
  3926. memcpy( mresp, mcp->mb, 64);
  3927. return rval;
  3928. }
  3929. int
  3930. qla2x00_echo_test(scsi_qla_host_t *vha, struct msg_echo_lb *mreq,
  3931. uint16_t *mresp)
  3932. {
  3933. int rval;
  3934. mbx_cmd_t mc;
  3935. mbx_cmd_t *mcp = &mc;
  3936. struct qla_hw_data *ha = vha->hw;
  3937. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fa,
  3938. "Entered %s.\n", __func__);
  3939. memset(mcp->mb, 0 , sizeof(mcp->mb));
  3940. mcp->mb[0] = MBC_DIAGNOSTIC_ECHO;
  3941. mcp->mb[1] = mreq->options | BIT_6; /* BIT_6 specifies 64bit address */
  3942. if (IS_CNA_CAPABLE(ha)) {
  3943. mcp->mb[1] |= BIT_15;
  3944. mcp->mb[2] = vha->fcoe_fcf_idx;
  3945. }
  3946. mcp->mb[16] = LSW(mreq->rcv_dma);
  3947. mcp->mb[17] = MSW(mreq->rcv_dma);
  3948. mcp->mb[6] = LSW(MSD(mreq->rcv_dma));
  3949. mcp->mb[7] = MSW(MSD(mreq->rcv_dma));
  3950. mcp->mb[10] = LSW(mreq->transfer_size);
  3951. mcp->mb[14] = LSW(mreq->send_dma);
  3952. mcp->mb[15] = MSW(mreq->send_dma);
  3953. mcp->mb[20] = LSW(MSD(mreq->send_dma));
  3954. mcp->mb[21] = MSW(MSD(mreq->send_dma));
  3955. mcp->out_mb = MBX_21|MBX_20|MBX_17|MBX_16|MBX_15|
  3956. MBX_14|MBX_10|MBX_7|MBX_6|MBX_1|MBX_0;
  3957. if (IS_CNA_CAPABLE(ha))
  3958. mcp->out_mb |= MBX_2;
  3959. mcp->in_mb = MBX_0;
  3960. if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha) ||
  3961. IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3962. mcp->in_mb |= MBX_1;
  3963. if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha))
  3964. mcp->in_mb |= MBX_3;
  3965. mcp->tov = MBX_TOV_SECONDS;
  3966. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3967. mcp->buf_size = mreq->transfer_size;
  3968. rval = qla2x00_mailbox_command(vha, mcp);
  3969. if (rval != QLA_SUCCESS) {
  3970. ql_dbg(ql_dbg_mbx, vha, 0x10fb,
  3971. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  3972. rval, mcp->mb[0], mcp->mb[1]);
  3973. } else {
  3974. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fc,
  3975. "Done %s.\n", __func__);
  3976. }
  3977. /* Copy mailbox information */
  3978. memcpy(mresp, mcp->mb, 64);
  3979. return rval;
  3980. }
  3981. int
  3982. qla84xx_reset_chip(scsi_qla_host_t *vha, uint16_t enable_diagnostic)
  3983. {
  3984. int rval;
  3985. mbx_cmd_t mc;
  3986. mbx_cmd_t *mcp = &mc;
  3987. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10fd,
  3988. "Entered %s enable_diag=%d.\n", __func__, enable_diagnostic);
  3989. mcp->mb[0] = MBC_ISP84XX_RESET;
  3990. mcp->mb[1] = enable_diagnostic;
  3991. mcp->out_mb = MBX_1|MBX_0;
  3992. mcp->in_mb = MBX_1|MBX_0;
  3993. mcp->tov = MBX_TOV_SECONDS;
  3994. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  3995. rval = qla2x00_mailbox_command(vha, mcp);
  3996. if (rval != QLA_SUCCESS)
  3997. ql_dbg(ql_dbg_mbx, vha, 0x10fe, "Failed=%x.\n", rval);
  3998. else
  3999. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10ff,
  4000. "Done %s.\n", __func__);
  4001. return rval;
  4002. }
  4003. int
  4004. qla2x00_write_ram_word(scsi_qla_host_t *vha, uint32_t risc_addr, uint32_t data)
  4005. {
  4006. int rval;
  4007. mbx_cmd_t mc;
  4008. mbx_cmd_t *mcp = &mc;
  4009. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1100,
  4010. "Entered %s.\n", __func__);
  4011. if (!IS_FWI2_CAPABLE(vha->hw))
  4012. return QLA_FUNCTION_FAILED;
  4013. mcp->mb[0] = MBC_WRITE_RAM_WORD_EXTENDED;
  4014. mcp->mb[1] = LSW(risc_addr);
  4015. mcp->mb[2] = LSW(data);
  4016. mcp->mb[3] = MSW(data);
  4017. mcp->mb[8] = MSW(risc_addr);
  4018. mcp->out_mb = MBX_8|MBX_3|MBX_2|MBX_1|MBX_0;
  4019. mcp->in_mb = MBX_0;
  4020. mcp->tov = 30;
  4021. mcp->flags = 0;
  4022. rval = qla2x00_mailbox_command(vha, mcp);
  4023. if (rval != QLA_SUCCESS) {
  4024. ql_dbg(ql_dbg_mbx, vha, 0x1101,
  4025. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4026. } else {
  4027. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1102,
  4028. "Done %s.\n", __func__);
  4029. }
  4030. return rval;
  4031. }
  4032. int
  4033. qla81xx_write_mpi_register(scsi_qla_host_t *vha, uint16_t *mb)
  4034. {
  4035. int rval;
  4036. uint32_t stat, timer;
  4037. uint16_t mb0 = 0;
  4038. struct qla_hw_data *ha = vha->hw;
  4039. struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
  4040. rval = QLA_SUCCESS;
  4041. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1103,
  4042. "Entered %s.\n", __func__);
  4043. clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags);
  4044. /* Write the MBC data to the registers */
  4045. WRT_REG_WORD(&reg->mailbox0, MBC_WRITE_MPI_REGISTER);
  4046. WRT_REG_WORD(&reg->mailbox1, mb[0]);
  4047. WRT_REG_WORD(&reg->mailbox2, mb[1]);
  4048. WRT_REG_WORD(&reg->mailbox3, mb[2]);
  4049. WRT_REG_WORD(&reg->mailbox4, mb[3]);
  4050. WRT_REG_DWORD(&reg->hccr, HCCRX_SET_HOST_INT);
  4051. /* Poll for MBC interrupt */
  4052. for (timer = 6000000; timer; timer--) {
  4053. /* Check for pending interrupts. */
  4054. stat = RD_REG_DWORD(&reg->host_status);
  4055. if (stat & HSRX_RISC_INT) {
  4056. stat &= 0xff;
  4057. if (stat == 0x1 || stat == 0x2 ||
  4058. stat == 0x10 || stat == 0x11) {
  4059. set_bit(MBX_INTERRUPT,
  4060. &ha->mbx_cmd_flags);
  4061. mb0 = RD_REG_WORD(&reg->mailbox0);
  4062. WRT_REG_DWORD(&reg->hccr,
  4063. HCCRX_CLR_RISC_INT);
  4064. RD_REG_DWORD(&reg->hccr);
  4065. break;
  4066. }
  4067. }
  4068. udelay(5);
  4069. }
  4070. if (test_and_clear_bit(MBX_INTERRUPT, &ha->mbx_cmd_flags))
  4071. rval = mb0 & MBS_MASK;
  4072. else
  4073. rval = QLA_FUNCTION_FAILED;
  4074. if (rval != QLA_SUCCESS) {
  4075. ql_dbg(ql_dbg_mbx, vha, 0x1104,
  4076. "Failed=%x mb[0]=%x.\n", rval, mb[0]);
  4077. } else {
  4078. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1105,
  4079. "Done %s.\n", __func__);
  4080. }
  4081. return rval;
  4082. }
  4083. int
  4084. qla2x00_get_data_rate(scsi_qla_host_t *vha)
  4085. {
  4086. int rval;
  4087. mbx_cmd_t mc;
  4088. mbx_cmd_t *mcp = &mc;
  4089. struct qla_hw_data *ha = vha->hw;
  4090. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1106,
  4091. "Entered %s.\n", __func__);
  4092. if (!IS_FWI2_CAPABLE(ha))
  4093. return QLA_FUNCTION_FAILED;
  4094. mcp->mb[0] = MBC_DATA_RATE;
  4095. mcp->mb[1] = 0;
  4096. mcp->out_mb = MBX_1|MBX_0;
  4097. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4098. if (IS_QLA83XX(ha) || IS_QLA27XX(ha))
  4099. mcp->in_mb |= MBX_3;
  4100. mcp->tov = MBX_TOV_SECONDS;
  4101. mcp->flags = 0;
  4102. rval = qla2x00_mailbox_command(vha, mcp);
  4103. if (rval != QLA_SUCCESS) {
  4104. ql_dbg(ql_dbg_mbx, vha, 0x1107,
  4105. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4106. } else {
  4107. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1108,
  4108. "Done %s.\n", __func__);
  4109. if (mcp->mb[1] != 0x7)
  4110. ha->link_data_rate = mcp->mb[1];
  4111. }
  4112. return rval;
  4113. }
  4114. int
  4115. qla81xx_get_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  4116. {
  4117. int rval;
  4118. mbx_cmd_t mc;
  4119. mbx_cmd_t *mcp = &mc;
  4120. struct qla_hw_data *ha = vha->hw;
  4121. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1109,
  4122. "Entered %s.\n", __func__);
  4123. if (!IS_QLA81XX(ha) && !IS_QLA83XX(ha) && !IS_QLA8044(ha) &&
  4124. !IS_QLA27XX(ha))
  4125. return QLA_FUNCTION_FAILED;
  4126. mcp->mb[0] = MBC_GET_PORT_CONFIG;
  4127. mcp->out_mb = MBX_0;
  4128. mcp->in_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4129. mcp->tov = MBX_TOV_SECONDS;
  4130. mcp->flags = 0;
  4131. rval = qla2x00_mailbox_command(vha, mcp);
  4132. if (rval != QLA_SUCCESS) {
  4133. ql_dbg(ql_dbg_mbx, vha, 0x110a,
  4134. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4135. } else {
  4136. /* Copy all bits to preserve original value */
  4137. memcpy(mb, &mcp->mb[1], sizeof(uint16_t) * 4);
  4138. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110b,
  4139. "Done %s.\n", __func__);
  4140. }
  4141. return rval;
  4142. }
  4143. int
  4144. qla81xx_set_port_config(scsi_qla_host_t *vha, uint16_t *mb)
  4145. {
  4146. int rval;
  4147. mbx_cmd_t mc;
  4148. mbx_cmd_t *mcp = &mc;
  4149. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110c,
  4150. "Entered %s.\n", __func__);
  4151. mcp->mb[0] = MBC_SET_PORT_CONFIG;
  4152. /* Copy all bits to preserve original setting */
  4153. memcpy(&mcp->mb[1], mb, sizeof(uint16_t) * 4);
  4154. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4155. mcp->in_mb = MBX_0;
  4156. mcp->tov = MBX_TOV_SECONDS;
  4157. mcp->flags = 0;
  4158. rval = qla2x00_mailbox_command(vha, mcp);
  4159. if (rval != QLA_SUCCESS) {
  4160. ql_dbg(ql_dbg_mbx, vha, 0x110d,
  4161. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4162. } else
  4163. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110e,
  4164. "Done %s.\n", __func__);
  4165. return rval;
  4166. }
  4167. int
  4168. qla24xx_set_fcp_prio(scsi_qla_host_t *vha, uint16_t loop_id, uint16_t priority,
  4169. uint16_t *mb)
  4170. {
  4171. int rval;
  4172. mbx_cmd_t mc;
  4173. mbx_cmd_t *mcp = &mc;
  4174. struct qla_hw_data *ha = vha->hw;
  4175. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x110f,
  4176. "Entered %s.\n", __func__);
  4177. if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha))
  4178. return QLA_FUNCTION_FAILED;
  4179. mcp->mb[0] = MBC_PORT_PARAMS;
  4180. mcp->mb[1] = loop_id;
  4181. if (ha->flags.fcp_prio_enabled)
  4182. mcp->mb[2] = BIT_1;
  4183. else
  4184. mcp->mb[2] = BIT_2;
  4185. mcp->mb[4] = priority & 0xf;
  4186. mcp->mb[9] = vha->vp_idx;
  4187. mcp->out_mb = MBX_9|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4188. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  4189. mcp->tov = 30;
  4190. mcp->flags = 0;
  4191. rval = qla2x00_mailbox_command(vha, mcp);
  4192. if (mb != NULL) {
  4193. mb[0] = mcp->mb[0];
  4194. mb[1] = mcp->mb[1];
  4195. mb[3] = mcp->mb[3];
  4196. mb[4] = mcp->mb[4];
  4197. }
  4198. if (rval != QLA_SUCCESS) {
  4199. ql_dbg(ql_dbg_mbx, vha, 0x10cd, "Failed=%x.\n", rval);
  4200. } else {
  4201. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x10cc,
  4202. "Done %s.\n", __func__);
  4203. }
  4204. return rval;
  4205. }
  4206. int
  4207. qla2x00_get_thermal_temp(scsi_qla_host_t *vha, uint16_t *temp)
  4208. {
  4209. int rval = QLA_FUNCTION_FAILED;
  4210. struct qla_hw_data *ha = vha->hw;
  4211. uint8_t byte;
  4212. if (!IS_FWI2_CAPABLE(ha) || IS_QLA24XX_TYPE(ha) || IS_QLA81XX(ha)) {
  4213. ql_dbg(ql_dbg_mbx, vha, 0x1150,
  4214. "Thermal not supported by this card.\n");
  4215. return rval;
  4216. }
  4217. if (IS_QLA25XX(ha)) {
  4218. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
  4219. ha->pdev->subsystem_device == 0x0175) {
  4220. rval = qla2x00_read_sfp(vha, 0, &byte,
  4221. 0x98, 0x1, 1, BIT_13|BIT_0);
  4222. *temp = byte;
  4223. return rval;
  4224. }
  4225. if (ha->pdev->subsystem_vendor == PCI_VENDOR_ID_HP &&
  4226. ha->pdev->subsystem_device == 0x338e) {
  4227. rval = qla2x00_read_sfp(vha, 0, &byte,
  4228. 0x98, 0x1, 1, BIT_15|BIT_14|BIT_0);
  4229. *temp = byte;
  4230. return rval;
  4231. }
  4232. ql_dbg(ql_dbg_mbx, vha, 0x10c9,
  4233. "Thermal not supported by this card.\n");
  4234. return rval;
  4235. }
  4236. if (IS_QLA82XX(ha)) {
  4237. *temp = qla82xx_read_temperature(vha);
  4238. rval = QLA_SUCCESS;
  4239. return rval;
  4240. } else if (IS_QLA8044(ha)) {
  4241. *temp = qla8044_read_temperature(vha);
  4242. rval = QLA_SUCCESS;
  4243. return rval;
  4244. }
  4245. rval = qla2x00_read_asic_temperature(vha, temp);
  4246. return rval;
  4247. }
  4248. int
  4249. qla82xx_mbx_intr_enable(scsi_qla_host_t *vha)
  4250. {
  4251. int rval;
  4252. struct qla_hw_data *ha = vha->hw;
  4253. mbx_cmd_t mc;
  4254. mbx_cmd_t *mcp = &mc;
  4255. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1017,
  4256. "Entered %s.\n", __func__);
  4257. if (!IS_FWI2_CAPABLE(ha))
  4258. return QLA_FUNCTION_FAILED;
  4259. memset(mcp, 0, sizeof(mbx_cmd_t));
  4260. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4261. mcp->mb[1] = 1;
  4262. mcp->out_mb = MBX_1|MBX_0;
  4263. mcp->in_mb = MBX_0;
  4264. mcp->tov = 30;
  4265. mcp->flags = 0;
  4266. rval = qla2x00_mailbox_command(vha, mcp);
  4267. if (rval != QLA_SUCCESS) {
  4268. ql_dbg(ql_dbg_mbx, vha, 0x1016,
  4269. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4270. } else {
  4271. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100e,
  4272. "Done %s.\n", __func__);
  4273. }
  4274. return rval;
  4275. }
  4276. int
  4277. qla82xx_mbx_intr_disable(scsi_qla_host_t *vha)
  4278. {
  4279. int rval;
  4280. struct qla_hw_data *ha = vha->hw;
  4281. mbx_cmd_t mc;
  4282. mbx_cmd_t *mcp = &mc;
  4283. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100d,
  4284. "Entered %s.\n", __func__);
  4285. if (!IS_P3P_TYPE(ha))
  4286. return QLA_FUNCTION_FAILED;
  4287. memset(mcp, 0, sizeof(mbx_cmd_t));
  4288. mcp->mb[0] = MBC_TOGGLE_INTERRUPT;
  4289. mcp->mb[1] = 0;
  4290. mcp->out_mb = MBX_1|MBX_0;
  4291. mcp->in_mb = MBX_0;
  4292. mcp->tov = 30;
  4293. mcp->flags = 0;
  4294. rval = qla2x00_mailbox_command(vha, mcp);
  4295. if (rval != QLA_SUCCESS) {
  4296. ql_dbg(ql_dbg_mbx, vha, 0x100c,
  4297. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4298. } else {
  4299. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x100b,
  4300. "Done %s.\n", __func__);
  4301. }
  4302. return rval;
  4303. }
  4304. int
  4305. qla82xx_md_get_template_size(scsi_qla_host_t *vha)
  4306. {
  4307. struct qla_hw_data *ha = vha->hw;
  4308. mbx_cmd_t mc;
  4309. mbx_cmd_t *mcp = &mc;
  4310. int rval = QLA_FUNCTION_FAILED;
  4311. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x111f,
  4312. "Entered %s.\n", __func__);
  4313. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4314. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4315. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4316. mcp->mb[2] = LSW(RQST_TMPLT_SIZE);
  4317. mcp->mb[3] = MSW(RQST_TMPLT_SIZE);
  4318. mcp->out_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4319. mcp->in_mb = MBX_14|MBX_13|MBX_12|MBX_11|MBX_10|MBX_9|MBX_8|
  4320. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4321. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4322. mcp->tov = MBX_TOV_SECONDS;
  4323. rval = qla2x00_mailbox_command(vha, mcp);
  4324. /* Always copy back return mailbox values. */
  4325. if (rval != QLA_SUCCESS) {
  4326. ql_dbg(ql_dbg_mbx, vha, 0x1120,
  4327. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4328. (mcp->mb[1] << 16) | mcp->mb[0],
  4329. (mcp->mb[3] << 16) | mcp->mb[2]);
  4330. } else {
  4331. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1121,
  4332. "Done %s.\n", __func__);
  4333. ha->md_template_size = ((mcp->mb[3] << 16) | mcp->mb[2]);
  4334. if (!ha->md_template_size) {
  4335. ql_dbg(ql_dbg_mbx, vha, 0x1122,
  4336. "Null template size obtained.\n");
  4337. rval = QLA_FUNCTION_FAILED;
  4338. }
  4339. }
  4340. return rval;
  4341. }
  4342. int
  4343. qla82xx_md_get_template(scsi_qla_host_t *vha)
  4344. {
  4345. struct qla_hw_data *ha = vha->hw;
  4346. mbx_cmd_t mc;
  4347. mbx_cmd_t *mcp = &mc;
  4348. int rval = QLA_FUNCTION_FAILED;
  4349. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1123,
  4350. "Entered %s.\n", __func__);
  4351. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4352. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4353. if (!ha->md_tmplt_hdr) {
  4354. ql_log(ql_log_warn, vha, 0x1124,
  4355. "Unable to allocate memory for Minidump template.\n");
  4356. return rval;
  4357. }
  4358. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4359. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4360. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4361. mcp->mb[2] = LSW(RQST_TMPLT);
  4362. mcp->mb[3] = MSW(RQST_TMPLT);
  4363. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma));
  4364. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma));
  4365. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma));
  4366. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma));
  4367. mcp->mb[8] = LSW(ha->md_template_size);
  4368. mcp->mb[9] = MSW(ha->md_template_size);
  4369. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4370. mcp->tov = MBX_TOV_SECONDS;
  4371. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4372. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4373. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4374. rval = qla2x00_mailbox_command(vha, mcp);
  4375. if (rval != QLA_SUCCESS) {
  4376. ql_dbg(ql_dbg_mbx, vha, 0x1125,
  4377. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4378. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4379. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4380. } else
  4381. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1126,
  4382. "Done %s.\n", __func__);
  4383. return rval;
  4384. }
  4385. int
  4386. qla8044_md_get_template(scsi_qla_host_t *vha)
  4387. {
  4388. struct qla_hw_data *ha = vha->hw;
  4389. mbx_cmd_t mc;
  4390. mbx_cmd_t *mcp = &mc;
  4391. int rval = QLA_FUNCTION_FAILED;
  4392. int offset = 0, size = MINIDUMP_SIZE_36K;
  4393. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11f,
  4394. "Entered %s.\n", __func__);
  4395. ha->md_tmplt_hdr = dma_alloc_coherent(&ha->pdev->dev,
  4396. ha->md_template_size, &ha->md_tmplt_hdr_dma, GFP_KERNEL);
  4397. if (!ha->md_tmplt_hdr) {
  4398. ql_log(ql_log_warn, vha, 0xb11b,
  4399. "Unable to allocate memory for Minidump template.\n");
  4400. return rval;
  4401. }
  4402. memset(mcp->mb, 0 , sizeof(mcp->mb));
  4403. while (offset < ha->md_template_size) {
  4404. mcp->mb[0] = LSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4405. mcp->mb[1] = MSW(MBC_DIAGNOSTIC_MINIDUMP_TEMPLATE);
  4406. mcp->mb[2] = LSW(RQST_TMPLT);
  4407. mcp->mb[3] = MSW(RQST_TMPLT);
  4408. mcp->mb[4] = LSW(LSD(ha->md_tmplt_hdr_dma + offset));
  4409. mcp->mb[5] = MSW(LSD(ha->md_tmplt_hdr_dma + offset));
  4410. mcp->mb[6] = LSW(MSD(ha->md_tmplt_hdr_dma + offset));
  4411. mcp->mb[7] = MSW(MSD(ha->md_tmplt_hdr_dma + offset));
  4412. mcp->mb[8] = LSW(size);
  4413. mcp->mb[9] = MSW(size);
  4414. mcp->mb[10] = offset & 0x0000FFFF;
  4415. mcp->mb[11] = offset & 0xFFFF0000;
  4416. mcp->flags = MBX_DMA_OUT|MBX_DMA_IN|IOCTL_CMD;
  4417. mcp->tov = MBX_TOV_SECONDS;
  4418. mcp->out_mb = MBX_11|MBX_10|MBX_9|MBX_8|
  4419. MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4420. mcp->in_mb = MBX_3|MBX_2|MBX_1|MBX_0;
  4421. rval = qla2x00_mailbox_command(vha, mcp);
  4422. if (rval != QLA_SUCCESS) {
  4423. ql_dbg(ql_dbg_mbx, vha, 0xb11c,
  4424. "mailbox command FAILED=0x%x, subcode=%x.\n",
  4425. ((mcp->mb[1] << 16) | mcp->mb[0]),
  4426. ((mcp->mb[3] << 16) | mcp->mb[2]));
  4427. return rval;
  4428. } else
  4429. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0xb11d,
  4430. "Done %s.\n", __func__);
  4431. offset = offset + size;
  4432. }
  4433. return rval;
  4434. }
  4435. int
  4436. qla81xx_set_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4437. {
  4438. int rval;
  4439. struct qla_hw_data *ha = vha->hw;
  4440. mbx_cmd_t mc;
  4441. mbx_cmd_t *mcp = &mc;
  4442. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4443. return QLA_FUNCTION_FAILED;
  4444. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1133,
  4445. "Entered %s.\n", __func__);
  4446. memset(mcp, 0, sizeof(mbx_cmd_t));
  4447. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4448. mcp->mb[1] = led_cfg[0];
  4449. mcp->mb[2] = led_cfg[1];
  4450. if (IS_QLA8031(ha)) {
  4451. mcp->mb[3] = led_cfg[2];
  4452. mcp->mb[4] = led_cfg[3];
  4453. mcp->mb[5] = led_cfg[4];
  4454. mcp->mb[6] = led_cfg[5];
  4455. }
  4456. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4457. if (IS_QLA8031(ha))
  4458. mcp->out_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4459. mcp->in_mb = MBX_0;
  4460. mcp->tov = 30;
  4461. mcp->flags = 0;
  4462. rval = qla2x00_mailbox_command(vha, mcp);
  4463. if (rval != QLA_SUCCESS) {
  4464. ql_dbg(ql_dbg_mbx, vha, 0x1134,
  4465. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4466. } else {
  4467. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1135,
  4468. "Done %s.\n", __func__);
  4469. }
  4470. return rval;
  4471. }
  4472. int
  4473. qla81xx_get_led_config(scsi_qla_host_t *vha, uint16_t *led_cfg)
  4474. {
  4475. int rval;
  4476. struct qla_hw_data *ha = vha->hw;
  4477. mbx_cmd_t mc;
  4478. mbx_cmd_t *mcp = &mc;
  4479. if (!IS_QLA81XX(ha) && !IS_QLA8031(ha))
  4480. return QLA_FUNCTION_FAILED;
  4481. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1136,
  4482. "Entered %s.\n", __func__);
  4483. memset(mcp, 0, sizeof(mbx_cmd_t));
  4484. mcp->mb[0] = MBC_GET_LED_CONFIG;
  4485. mcp->out_mb = MBX_0;
  4486. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4487. if (IS_QLA8031(ha))
  4488. mcp->in_mb |= MBX_6|MBX_5|MBX_4|MBX_3;
  4489. mcp->tov = 30;
  4490. mcp->flags = 0;
  4491. rval = qla2x00_mailbox_command(vha, mcp);
  4492. if (rval != QLA_SUCCESS) {
  4493. ql_dbg(ql_dbg_mbx, vha, 0x1137,
  4494. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4495. } else {
  4496. led_cfg[0] = mcp->mb[1];
  4497. led_cfg[1] = mcp->mb[2];
  4498. if (IS_QLA8031(ha)) {
  4499. led_cfg[2] = mcp->mb[3];
  4500. led_cfg[3] = mcp->mb[4];
  4501. led_cfg[4] = mcp->mb[5];
  4502. led_cfg[5] = mcp->mb[6];
  4503. }
  4504. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1138,
  4505. "Done %s.\n", __func__);
  4506. }
  4507. return rval;
  4508. }
  4509. int
  4510. qla82xx_mbx_beacon_ctl(scsi_qla_host_t *vha, int enable)
  4511. {
  4512. int rval;
  4513. struct qla_hw_data *ha = vha->hw;
  4514. mbx_cmd_t mc;
  4515. mbx_cmd_t *mcp = &mc;
  4516. if (!IS_P3P_TYPE(ha))
  4517. return QLA_FUNCTION_FAILED;
  4518. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1127,
  4519. "Entered %s.\n", __func__);
  4520. memset(mcp, 0, sizeof(mbx_cmd_t));
  4521. mcp->mb[0] = MBC_SET_LED_CONFIG;
  4522. if (enable)
  4523. mcp->mb[7] = 0xE;
  4524. else
  4525. mcp->mb[7] = 0xD;
  4526. mcp->out_mb = MBX_7|MBX_0;
  4527. mcp->in_mb = MBX_0;
  4528. mcp->tov = MBX_TOV_SECONDS;
  4529. mcp->flags = 0;
  4530. rval = qla2x00_mailbox_command(vha, mcp);
  4531. if (rval != QLA_SUCCESS) {
  4532. ql_dbg(ql_dbg_mbx, vha, 0x1128,
  4533. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4534. } else {
  4535. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1129,
  4536. "Done %s.\n", __func__);
  4537. }
  4538. return rval;
  4539. }
  4540. int
  4541. qla83xx_wr_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t data)
  4542. {
  4543. int rval;
  4544. struct qla_hw_data *ha = vha->hw;
  4545. mbx_cmd_t mc;
  4546. mbx_cmd_t *mcp = &mc;
  4547. if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
  4548. return QLA_FUNCTION_FAILED;
  4549. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1130,
  4550. "Entered %s.\n", __func__);
  4551. mcp->mb[0] = MBC_WRITE_REMOTE_REG;
  4552. mcp->mb[1] = LSW(reg);
  4553. mcp->mb[2] = MSW(reg);
  4554. mcp->mb[3] = LSW(data);
  4555. mcp->mb[4] = MSW(data);
  4556. mcp->out_mb = MBX_4|MBX_3|MBX_2|MBX_1|MBX_0;
  4557. mcp->in_mb = MBX_1|MBX_0;
  4558. mcp->tov = MBX_TOV_SECONDS;
  4559. mcp->flags = 0;
  4560. rval = qla2x00_mailbox_command(vha, mcp);
  4561. if (rval != QLA_SUCCESS) {
  4562. ql_dbg(ql_dbg_mbx, vha, 0x1131,
  4563. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4564. } else {
  4565. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x1132,
  4566. "Done %s.\n", __func__);
  4567. }
  4568. return rval;
  4569. }
  4570. int
  4571. qla2x00_port_logout(scsi_qla_host_t *vha, struct fc_port *fcport)
  4572. {
  4573. int rval;
  4574. struct qla_hw_data *ha = vha->hw;
  4575. mbx_cmd_t mc;
  4576. mbx_cmd_t *mcp = &mc;
  4577. if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
  4578. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113b,
  4579. "Implicit LOGO Unsupported.\n");
  4580. return QLA_FUNCTION_FAILED;
  4581. }
  4582. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113c,
  4583. "Entering %s.\n", __func__);
  4584. /* Perform Implicit LOGO. */
  4585. mcp->mb[0] = MBC_PORT_LOGOUT;
  4586. mcp->mb[1] = fcport->loop_id;
  4587. mcp->mb[10] = BIT_15;
  4588. mcp->out_mb = MBX_10|MBX_1|MBX_0;
  4589. mcp->in_mb = MBX_0;
  4590. mcp->tov = MBX_TOV_SECONDS;
  4591. mcp->flags = 0;
  4592. rval = qla2x00_mailbox_command(vha, mcp);
  4593. if (rval != QLA_SUCCESS)
  4594. ql_dbg(ql_dbg_mbx, vha, 0x113d,
  4595. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4596. else
  4597. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x113e,
  4598. "Done %s.\n", __func__);
  4599. return rval;
  4600. }
  4601. int
  4602. qla83xx_rd_reg(scsi_qla_host_t *vha, uint32_t reg, uint32_t *data)
  4603. {
  4604. int rval;
  4605. mbx_cmd_t mc;
  4606. mbx_cmd_t *mcp = &mc;
  4607. struct qla_hw_data *ha = vha->hw;
  4608. unsigned long retry_max_time = jiffies + (2 * HZ);
  4609. if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
  4610. return QLA_FUNCTION_FAILED;
  4611. ql_dbg(ql_dbg_mbx, vha, 0x114b, "Entered %s.\n", __func__);
  4612. retry_rd_reg:
  4613. mcp->mb[0] = MBC_READ_REMOTE_REG;
  4614. mcp->mb[1] = LSW(reg);
  4615. mcp->mb[2] = MSW(reg);
  4616. mcp->out_mb = MBX_2|MBX_1|MBX_0;
  4617. mcp->in_mb = MBX_4|MBX_3|MBX_1|MBX_0;
  4618. mcp->tov = MBX_TOV_SECONDS;
  4619. mcp->flags = 0;
  4620. rval = qla2x00_mailbox_command(vha, mcp);
  4621. if (rval != QLA_SUCCESS) {
  4622. ql_dbg(ql_dbg_mbx, vha, 0x114c,
  4623. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4624. rval, mcp->mb[0], mcp->mb[1]);
  4625. } else {
  4626. *data = (mcp->mb[3] | (mcp->mb[4] << 16));
  4627. if (*data == QLA8XXX_BAD_VALUE) {
  4628. /*
  4629. * During soft-reset CAMRAM register reads might
  4630. * return 0xbad0bad0. So retry for MAX of 2 sec
  4631. * while reading camram registers.
  4632. */
  4633. if (time_after(jiffies, retry_max_time)) {
  4634. ql_dbg(ql_dbg_mbx, vha, 0x1141,
  4635. "Failure to read CAMRAM register. "
  4636. "data=0x%x.\n", *data);
  4637. return QLA_FUNCTION_FAILED;
  4638. }
  4639. msleep(100);
  4640. goto retry_rd_reg;
  4641. }
  4642. ql_dbg(ql_dbg_mbx, vha, 0x1142, "Done %s.\n", __func__);
  4643. }
  4644. return rval;
  4645. }
  4646. int
  4647. qla83xx_restart_nic_firmware(scsi_qla_host_t *vha)
  4648. {
  4649. int rval;
  4650. mbx_cmd_t mc;
  4651. mbx_cmd_t *mcp = &mc;
  4652. struct qla_hw_data *ha = vha->hw;
  4653. if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha))
  4654. return QLA_FUNCTION_FAILED;
  4655. ql_dbg(ql_dbg_mbx, vha, 0x1143, "Entered %s.\n", __func__);
  4656. mcp->mb[0] = MBC_RESTART_NIC_FIRMWARE;
  4657. mcp->out_mb = MBX_0;
  4658. mcp->in_mb = MBX_1|MBX_0;
  4659. mcp->tov = MBX_TOV_SECONDS;
  4660. mcp->flags = 0;
  4661. rval = qla2x00_mailbox_command(vha, mcp);
  4662. if (rval != QLA_SUCCESS) {
  4663. ql_dbg(ql_dbg_mbx, vha, 0x1144,
  4664. "Failed=%x mb[0]=%x mb[1]=%x.\n",
  4665. rval, mcp->mb[0], mcp->mb[1]);
  4666. ha->isp_ops->fw_dump(vha, 0);
  4667. } else {
  4668. ql_dbg(ql_dbg_mbx, vha, 0x1145, "Done %s.\n", __func__);
  4669. }
  4670. return rval;
  4671. }
  4672. int
  4673. qla83xx_access_control(scsi_qla_host_t *vha, uint16_t options,
  4674. uint32_t start_addr, uint32_t end_addr, uint16_t *sector_size)
  4675. {
  4676. int rval;
  4677. mbx_cmd_t mc;
  4678. mbx_cmd_t *mcp = &mc;
  4679. uint8_t subcode = (uint8_t)options;
  4680. struct qla_hw_data *ha = vha->hw;
  4681. if (!IS_QLA8031(ha))
  4682. return QLA_FUNCTION_FAILED;
  4683. ql_dbg(ql_dbg_mbx, vha, 0x1146, "Entered %s.\n", __func__);
  4684. mcp->mb[0] = MBC_SET_ACCESS_CONTROL;
  4685. mcp->mb[1] = options;
  4686. mcp->out_mb = MBX_1|MBX_0;
  4687. if (subcode & BIT_2) {
  4688. mcp->mb[2] = LSW(start_addr);
  4689. mcp->mb[3] = MSW(start_addr);
  4690. mcp->mb[4] = LSW(end_addr);
  4691. mcp->mb[5] = MSW(end_addr);
  4692. mcp->out_mb |= MBX_5|MBX_4|MBX_3|MBX_2;
  4693. }
  4694. mcp->in_mb = MBX_2|MBX_1|MBX_0;
  4695. if (!(subcode & (BIT_2 | BIT_5)))
  4696. mcp->in_mb |= MBX_4|MBX_3;
  4697. mcp->tov = MBX_TOV_SECONDS;
  4698. mcp->flags = 0;
  4699. rval = qla2x00_mailbox_command(vha, mcp);
  4700. if (rval != QLA_SUCCESS) {
  4701. ql_dbg(ql_dbg_mbx, vha, 0x1147,
  4702. "Failed=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[3]=%x mb[4]=%x.\n",
  4703. rval, mcp->mb[0], mcp->mb[1], mcp->mb[2], mcp->mb[3],
  4704. mcp->mb[4]);
  4705. ha->isp_ops->fw_dump(vha, 0);
  4706. } else {
  4707. if (subcode & BIT_5)
  4708. *sector_size = mcp->mb[1];
  4709. else if (subcode & (BIT_6 | BIT_7)) {
  4710. ql_dbg(ql_dbg_mbx, vha, 0x1148,
  4711. "Driver-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4712. } else if (subcode & (BIT_3 | BIT_4)) {
  4713. ql_dbg(ql_dbg_mbx, vha, 0x1149,
  4714. "Flash-lock id=%x%x", mcp->mb[4], mcp->mb[3]);
  4715. }
  4716. ql_dbg(ql_dbg_mbx, vha, 0x114a, "Done %s.\n", __func__);
  4717. }
  4718. return rval;
  4719. }
  4720. int
  4721. qla2x00_dump_mctp_data(scsi_qla_host_t *vha, dma_addr_t req_dma, uint32_t addr,
  4722. uint32_t size)
  4723. {
  4724. int rval;
  4725. mbx_cmd_t mc;
  4726. mbx_cmd_t *mcp = &mc;
  4727. if (!IS_MCTP_CAPABLE(vha->hw))
  4728. return QLA_FUNCTION_FAILED;
  4729. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114f,
  4730. "Entered %s.\n", __func__);
  4731. mcp->mb[0] = MBC_DUMP_RISC_RAM_EXTENDED;
  4732. mcp->mb[1] = LSW(addr);
  4733. mcp->mb[2] = MSW(req_dma);
  4734. mcp->mb[3] = LSW(req_dma);
  4735. mcp->mb[4] = MSW(size);
  4736. mcp->mb[5] = LSW(size);
  4737. mcp->mb[6] = MSW(MSD(req_dma));
  4738. mcp->mb[7] = LSW(MSD(req_dma));
  4739. mcp->mb[8] = MSW(addr);
  4740. /* Setting RAM ID to valid */
  4741. mcp->mb[10] |= BIT_7;
  4742. /* For MCTP RAM ID is 0x40 */
  4743. mcp->mb[10] |= 0x40;
  4744. mcp->out_mb |= MBX_10|MBX_8|MBX_7|MBX_6|MBX_5|MBX_4|MBX_3|MBX_2|MBX_1|
  4745. MBX_0;
  4746. mcp->in_mb = MBX_0;
  4747. mcp->tov = MBX_TOV_SECONDS;
  4748. mcp->flags = 0;
  4749. rval = qla2x00_mailbox_command(vha, mcp);
  4750. if (rval != QLA_SUCCESS) {
  4751. ql_dbg(ql_dbg_mbx, vha, 0x114e,
  4752. "Failed=%x mb[0]=%x.\n", rval, mcp->mb[0]);
  4753. } else {
  4754. ql_dbg(ql_dbg_mbx + ql_dbg_verbose, vha, 0x114d,
  4755. "Done %s.\n", __func__);
  4756. }
  4757. return rval;
  4758. }