wd719x.c 27 KB

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  1. /*
  2. * Driver for Western Digital WD7193, WD7197 and WD7296 SCSI cards
  3. * Copyright 2013 Ondrej Zary
  4. *
  5. * Original driver by
  6. * Aaron Dewell <dewell@woods.net>
  7. * Gaerti <Juergen.Gaertner@mbox.si.uni-hannover.de>
  8. *
  9. * HW documentation available in book:
  10. *
  11. * SPIDER Command Protocol
  12. * by Chandru M. Sippy
  13. * SCSI Storage Products (MCP)
  14. * Western Digital Corporation
  15. * 09-15-95
  16. *
  17. * http://web.archive.org/web/20070717175254/http://sun1.rrzn.uni-hannover.de/gaertner.juergen/wd719x/Linux/Docu/Spider/
  18. */
  19. /*
  20. * Driver workflow:
  21. * 1. SCSI command is transformed to SCB (Spider Control Block) by the
  22. * queuecommand function.
  23. * 2. The address of the SCB is stored in a list to be able to access it, if
  24. * something goes wrong.
  25. * 3. The address of the SCB is written to the Controller, which loads the SCB
  26. * via BM-DMA and processes it.
  27. * 4. After it has finished, it generates an interrupt, and sets registers.
  28. *
  29. * flaws:
  30. * - abort/reset functions
  31. *
  32. * ToDo:
  33. * - tagged queueing
  34. */
  35. #include <linux/interrupt.h>
  36. #include <linux/module.h>
  37. #include <linux/delay.h>
  38. #include <linux/pci.h>
  39. #include <linux/firmware.h>
  40. #include <linux/eeprom_93cx6.h>
  41. #include <scsi/scsi_cmnd.h>
  42. #include <scsi/scsi_device.h>
  43. #include <scsi/scsi_host.h>
  44. #include "wd719x.h"
  45. /* low-level register access */
  46. static inline u8 wd719x_readb(struct wd719x *wd, u8 reg)
  47. {
  48. return ioread8(wd->base + reg);
  49. }
  50. static inline u32 wd719x_readl(struct wd719x *wd, u8 reg)
  51. {
  52. return ioread32(wd->base + reg);
  53. }
  54. static inline void wd719x_writeb(struct wd719x *wd, u8 reg, u8 val)
  55. {
  56. iowrite8(val, wd->base + reg);
  57. }
  58. static inline void wd719x_writew(struct wd719x *wd, u8 reg, u16 val)
  59. {
  60. iowrite16(val, wd->base + reg);
  61. }
  62. static inline void wd719x_writel(struct wd719x *wd, u8 reg, u32 val)
  63. {
  64. iowrite32(val, wd->base + reg);
  65. }
  66. /* wait until the command register is ready */
  67. static inline int wd719x_wait_ready(struct wd719x *wd)
  68. {
  69. int i = 0;
  70. do {
  71. if (wd719x_readb(wd, WD719X_AMR_COMMAND) == WD719X_CMD_READY)
  72. return 0;
  73. udelay(1);
  74. } while (i++ < WD719X_WAIT_FOR_CMD_READY);
  75. dev_err(&wd->pdev->dev, "command register is not ready: 0x%02x\n",
  76. wd719x_readb(wd, WD719X_AMR_COMMAND));
  77. return -ETIMEDOUT;
  78. }
  79. /* poll interrupt status register until command finishes */
  80. static inline int wd719x_wait_done(struct wd719x *wd, int timeout)
  81. {
  82. u8 status;
  83. while (timeout > 0) {
  84. status = wd719x_readb(wd, WD719X_AMR_INT_STATUS);
  85. if (status)
  86. break;
  87. timeout--;
  88. udelay(1);
  89. }
  90. if (timeout <= 0) {
  91. dev_err(&wd->pdev->dev, "direct command timed out\n");
  92. return -ETIMEDOUT;
  93. }
  94. if (status != WD719X_INT_NOERRORS) {
  95. dev_err(&wd->pdev->dev, "direct command failed, status 0x%02x, SUE 0x%02x\n",
  96. status, wd719x_readb(wd, WD719X_AMR_SCB_ERROR));
  97. return -EIO;
  98. }
  99. return 0;
  100. }
  101. static int wd719x_direct_cmd(struct wd719x *wd, u8 opcode, u8 dev, u8 lun,
  102. u8 tag, dma_addr_t data, int timeout)
  103. {
  104. int ret = 0;
  105. /* clear interrupt status register (allow command register to clear) */
  106. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  107. /* Wait for the Command register to become free */
  108. if (wd719x_wait_ready(wd))
  109. return -ETIMEDOUT;
  110. /* make sure we get NO interrupts */
  111. dev |= WD719X_DISABLE_INT;
  112. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, dev);
  113. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_2, lun);
  114. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM_3, tag);
  115. if (data)
  116. wd719x_writel(wd, WD719X_AMR_SCB_IN, data);
  117. /* clear interrupt status register again */
  118. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  119. /* Now, write the command */
  120. wd719x_writeb(wd, WD719X_AMR_COMMAND, opcode);
  121. if (timeout) /* wait for the command to complete */
  122. ret = wd719x_wait_done(wd, timeout);
  123. /* clear interrupt status register (clean up) */
  124. if (opcode != WD719X_CMD_READ_FIRMVER)
  125. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  126. return ret;
  127. }
  128. static void wd719x_destroy(struct wd719x *wd)
  129. {
  130. struct wd719x_scb *scb;
  131. /* stop the RISC */
  132. if (wd719x_direct_cmd(wd, WD719X_CMD_SLEEP, 0, 0, 0, 0,
  133. WD719X_WAIT_FOR_RISC))
  134. dev_warn(&wd->pdev->dev, "RISC sleep command failed\n");
  135. /* disable RISC */
  136. wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
  137. /* free all SCBs */
  138. list_for_each_entry(scb, &wd->active_scbs, list)
  139. pci_free_consistent(wd->pdev, sizeof(struct wd719x_scb), scb,
  140. scb->phys);
  141. list_for_each_entry(scb, &wd->free_scbs, list)
  142. pci_free_consistent(wd->pdev, sizeof(struct wd719x_scb), scb,
  143. scb->phys);
  144. /* free internal buffers */
  145. pci_free_consistent(wd->pdev, wd->fw_size, wd->fw_virt, wd->fw_phys);
  146. wd->fw_virt = NULL;
  147. pci_free_consistent(wd->pdev, WD719X_HASH_TABLE_SIZE, wd->hash_virt,
  148. wd->hash_phys);
  149. wd->hash_virt = NULL;
  150. pci_free_consistent(wd->pdev, sizeof(struct wd719x_host_param),
  151. wd->params, wd->params_phys);
  152. wd->params = NULL;
  153. free_irq(wd->pdev->irq, wd);
  154. }
  155. /* finish a SCSI command, mark SCB (if any) as free, unmap buffers */
  156. static void wd719x_finish_cmd(struct scsi_cmnd *cmd, int result)
  157. {
  158. struct wd719x *wd = shost_priv(cmd->device->host);
  159. struct wd719x_scb *scb = (struct wd719x_scb *) cmd->host_scribble;
  160. if (scb) {
  161. list_move(&scb->list, &wd->free_scbs);
  162. dma_unmap_single(&wd->pdev->dev, cmd->SCp.dma_handle,
  163. SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
  164. scsi_dma_unmap(cmd);
  165. }
  166. cmd->result = result << 16;
  167. cmd->scsi_done(cmd);
  168. }
  169. /* Build a SCB and send it to the card */
  170. static int wd719x_queuecommand(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
  171. {
  172. int i, count_sg;
  173. unsigned long flags;
  174. struct wd719x_scb *scb;
  175. struct wd719x *wd = shost_priv(sh);
  176. dma_addr_t phys;
  177. cmd->host_scribble = NULL;
  178. /* get a free SCB - either from existing ones or allocate a new one */
  179. spin_lock_irqsave(wd->sh->host_lock, flags);
  180. scb = list_first_entry_or_null(&wd->free_scbs, struct wd719x_scb, list);
  181. if (scb) {
  182. list_del(&scb->list);
  183. phys = scb->phys;
  184. } else {
  185. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  186. scb = pci_alloc_consistent(wd->pdev, sizeof(struct wd719x_scb),
  187. &phys);
  188. spin_lock_irqsave(wd->sh->host_lock, flags);
  189. if (!scb) {
  190. dev_err(&wd->pdev->dev, "unable to allocate SCB\n");
  191. wd719x_finish_cmd(cmd, DID_ERROR);
  192. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  193. return 0;
  194. }
  195. }
  196. memset(scb, 0, sizeof(struct wd719x_scb));
  197. list_add(&scb->list, &wd->active_scbs);
  198. scb->phys = phys;
  199. scb->cmd = cmd;
  200. cmd->host_scribble = (char *) scb;
  201. scb->CDB_tag = 0; /* Tagged queueing not supported yet */
  202. scb->devid = cmd->device->id;
  203. scb->lun = cmd->device->lun;
  204. /* copy the command */
  205. memcpy(scb->CDB, cmd->cmnd, cmd->cmd_len);
  206. /* map sense buffer */
  207. scb->sense_buf_length = SCSI_SENSE_BUFFERSIZE;
  208. cmd->SCp.dma_handle = dma_map_single(&wd->pdev->dev, cmd->sense_buffer,
  209. SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
  210. scb->sense_buf = cpu_to_le32(cmd->SCp.dma_handle);
  211. /* request autosense */
  212. scb->SCB_options |= WD719X_SCB_FLAGS_AUTO_REQUEST_SENSE;
  213. /* check direction */
  214. if (cmd->sc_data_direction == DMA_TO_DEVICE)
  215. scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION
  216. | WD719X_SCB_FLAGS_PCI_TO_SCSI;
  217. else if (cmd->sc_data_direction == DMA_FROM_DEVICE)
  218. scb->SCB_options |= WD719X_SCB_FLAGS_CHECK_DIRECTION;
  219. /* Scather/gather */
  220. count_sg = scsi_dma_map(cmd);
  221. if (count_sg < 0) {
  222. wd719x_finish_cmd(cmd, DID_ERROR);
  223. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  224. return 0;
  225. }
  226. BUG_ON(count_sg > WD719X_SG);
  227. if (count_sg) {
  228. struct scatterlist *sg;
  229. scb->data_length = cpu_to_le32(count_sg *
  230. sizeof(struct wd719x_sglist));
  231. scb->data_p = cpu_to_le32(scb->phys +
  232. offsetof(struct wd719x_scb, sg_list));
  233. scsi_for_each_sg(cmd, sg, count_sg, i) {
  234. scb->sg_list[i].ptr = cpu_to_le32(sg_dma_address(sg));
  235. scb->sg_list[i].length = cpu_to_le32(sg_dma_len(sg));
  236. }
  237. scb->SCB_options |= WD719X_SCB_FLAGS_DO_SCATTER_GATHER;
  238. } else { /* zero length */
  239. scb->data_length = 0;
  240. scb->data_p = 0;
  241. }
  242. /* check if the Command register is free */
  243. if (wd719x_readb(wd, WD719X_AMR_COMMAND) != WD719X_CMD_READY) {
  244. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  245. return SCSI_MLQUEUE_HOST_BUSY;
  246. }
  247. /* write pointer to the AMR */
  248. wd719x_writel(wd, WD719X_AMR_SCB_IN, scb->phys);
  249. /* send SCB opcode */
  250. wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_PROCESS_SCB);
  251. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  252. return 0;
  253. }
  254. static int wd719x_chip_init(struct wd719x *wd)
  255. {
  256. int i, ret;
  257. u32 risc_init[3];
  258. const struct firmware *fw_wcs, *fw_risc;
  259. const char fwname_wcs[] = "wd719x-wcs.bin";
  260. const char fwname_risc[] = "wd719x-risc.bin";
  261. memset(wd->hash_virt, 0, WD719X_HASH_TABLE_SIZE);
  262. /* WCS (sequencer) firmware */
  263. ret = request_firmware(&fw_wcs, fwname_wcs, &wd->pdev->dev);
  264. if (ret) {
  265. dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n",
  266. fwname_wcs, ret);
  267. return ret;
  268. }
  269. /* RISC firmware */
  270. ret = request_firmware(&fw_risc, fwname_risc, &wd->pdev->dev);
  271. if (ret) {
  272. dev_err(&wd->pdev->dev, "Unable to load firmware %s: %d\n",
  273. fwname_risc, ret);
  274. release_firmware(fw_wcs);
  275. return ret;
  276. }
  277. wd->fw_size = ALIGN(fw_wcs->size, 4) + fw_risc->size;
  278. if (!wd->fw_virt)
  279. wd->fw_virt = pci_alloc_consistent(wd->pdev, wd->fw_size,
  280. &wd->fw_phys);
  281. if (!wd->fw_virt) {
  282. ret = -ENOMEM;
  283. goto wd719x_init_end;
  284. }
  285. /* make a fresh copy of WCS and RISC code */
  286. memcpy(wd->fw_virt, fw_wcs->data, fw_wcs->size);
  287. memcpy(wd->fw_virt + ALIGN(fw_wcs->size, 4), fw_risc->data,
  288. fw_risc->size);
  289. /* Reset the Spider Chip and adapter itself */
  290. wd719x_writeb(wd, WD719X_PCI_PORT_RESET, WD719X_PCI_RESET);
  291. udelay(WD719X_WAIT_FOR_RISC);
  292. /* Clear PIO mode bits set by BIOS */
  293. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, 0);
  294. /* ensure RISC is not running */
  295. wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, 0);
  296. /* ensure command port is ready */
  297. wd719x_writeb(wd, WD719X_AMR_COMMAND, 0);
  298. if (wd719x_wait_ready(wd)) {
  299. ret = -ETIMEDOUT;
  300. goto wd719x_init_end;
  301. }
  302. /* Transfer the first 2K words of RISC code to kick start the uP */
  303. risc_init[0] = wd->fw_phys; /* WCS FW */
  304. risc_init[1] = wd->fw_phys + ALIGN(fw_wcs->size, 4); /* RISC FW */
  305. risc_init[2] = wd->hash_phys; /* hash table */
  306. /* clear DMA status */
  307. wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3STATUS, 0);
  308. /* address to read firmware from */
  309. wd719x_writel(wd, WD719X_PCI_EXTERNAL_ADDR, risc_init[1]);
  310. /* base address to write firmware to (on card) */
  311. wd719x_writew(wd, WD719X_PCI_INTERNAL_ADDR, WD719X_PRAM_BASE_ADDR);
  312. /* size: first 2K words */
  313. wd719x_writew(wd, WD719X_PCI_DMA_TRANSFER_SIZE, 2048 * 2);
  314. /* start DMA */
  315. wd719x_writeb(wd, WD719X_PCI_CHANNEL2_3CMD, WD719X_START_CHANNEL2_3DMA);
  316. /* wait for DMA to complete */
  317. i = WD719X_WAIT_FOR_RISC;
  318. while (i-- > 0) {
  319. u8 status = wd719x_readb(wd, WD719X_PCI_CHANNEL2_3STATUS);
  320. if (status == WD719X_START_CHANNEL2_3DONE)
  321. break;
  322. if (status == WD719X_START_CHANNEL2_3ABORT) {
  323. dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA aborted\n");
  324. ret = -EIO;
  325. goto wd719x_init_end;
  326. }
  327. udelay(1);
  328. }
  329. if (i < 1) {
  330. dev_warn(&wd->pdev->dev, "RISC bootstrap failed: DMA timeout\n");
  331. ret = -ETIMEDOUT;
  332. goto wd719x_init_end;
  333. }
  334. /* firmware is loaded, now initialize and wake up the RISC */
  335. /* write RISC initialization long words to Spider */
  336. wd719x_writel(wd, WD719X_AMR_SCB_IN, risc_init[0]);
  337. wd719x_writel(wd, WD719X_AMR_SCB_IN + 4, risc_init[1]);
  338. wd719x_writel(wd, WD719X_AMR_SCB_IN + 8, risc_init[2]);
  339. /* disable interrupts during initialization of RISC */
  340. wd719x_writeb(wd, WD719X_AMR_CMD_PARAM, WD719X_DISABLE_INT);
  341. /* issue INITIALIZE RISC comand */
  342. wd719x_writeb(wd, WD719X_AMR_COMMAND, WD719X_CMD_INIT_RISC);
  343. /* enable advanced mode (wake up RISC) */
  344. wd719x_writeb(wd, WD719X_PCI_MODE_SELECT, WD719X_ENABLE_ADVANCE_MODE);
  345. udelay(WD719X_WAIT_FOR_RISC);
  346. ret = wd719x_wait_done(wd, WD719X_WAIT_FOR_RISC);
  347. /* clear interrupt status register */
  348. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  349. if (ret) {
  350. dev_warn(&wd->pdev->dev, "Unable to initialize RISC\n");
  351. goto wd719x_init_end;
  352. }
  353. /* RISC is up and running */
  354. /* Read FW version from RISC */
  355. ret = wd719x_direct_cmd(wd, WD719X_CMD_READ_FIRMVER, 0, 0, 0, 0,
  356. WD719X_WAIT_FOR_RISC);
  357. if (ret) {
  358. dev_warn(&wd->pdev->dev, "Unable to read firmware version\n");
  359. goto wd719x_init_end;
  360. }
  361. dev_info(&wd->pdev->dev, "RISC initialized with firmware version %.2x.%.2x\n",
  362. wd719x_readb(wd, WD719X_AMR_SCB_OUT + 1),
  363. wd719x_readb(wd, WD719X_AMR_SCB_OUT));
  364. /* RESET SCSI bus */
  365. ret = wd719x_direct_cmd(wd, WD719X_CMD_BUSRESET, 0, 0, 0, 0,
  366. WD719X_WAIT_FOR_SCSI_RESET);
  367. if (ret) {
  368. dev_warn(&wd->pdev->dev, "SCSI bus reset failed\n");
  369. goto wd719x_init_end;
  370. }
  371. /* use HostParameter structure to set Spider's Host Parameter Block */
  372. ret = wd719x_direct_cmd(wd, WD719X_CMD_SET_PARAM, 0,
  373. sizeof(struct wd719x_host_param), 0,
  374. wd->params_phys, WD719X_WAIT_FOR_RISC);
  375. if (ret) {
  376. dev_warn(&wd->pdev->dev, "Failed to set HOST PARAMETERS\n");
  377. goto wd719x_init_end;
  378. }
  379. /* initiate SCAM (does nothing if disabled in BIOS) */
  380. /* bug?: we should pass a mask of static IDs which we don't have */
  381. ret = wd719x_direct_cmd(wd, WD719X_CMD_INIT_SCAM, 0, 0, 0, 0,
  382. WD719X_WAIT_FOR_SCSI_RESET);
  383. if (ret) {
  384. dev_warn(&wd->pdev->dev, "SCAM initialization failed\n");
  385. goto wd719x_init_end;
  386. }
  387. /* clear AMR_BIOS_SHARE_INT register */
  388. wd719x_writeb(wd, WD719X_AMR_BIOS_SHARE_INT, 0);
  389. wd719x_init_end:
  390. release_firmware(fw_wcs);
  391. release_firmware(fw_risc);
  392. return ret;
  393. }
  394. static int wd719x_abort(struct scsi_cmnd *cmd)
  395. {
  396. int action, result;
  397. unsigned long flags;
  398. struct wd719x_scb *scb = (struct wd719x_scb *)cmd->host_scribble;
  399. struct wd719x *wd = shost_priv(cmd->device->host);
  400. dev_info(&wd->pdev->dev, "abort command, tag: %x\n", cmd->tag);
  401. action = /*cmd->tag ? WD719X_CMD_ABORT_TAG : */WD719X_CMD_ABORT;
  402. spin_lock_irqsave(wd->sh->host_lock, flags);
  403. result = wd719x_direct_cmd(wd, action, cmd->device->id,
  404. cmd->device->lun, cmd->tag, scb->phys, 0);
  405. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  406. if (result)
  407. return FAILED;
  408. return SUCCESS;
  409. }
  410. static int wd719x_reset(struct scsi_cmnd *cmd, u8 opcode, u8 device)
  411. {
  412. int result;
  413. unsigned long flags;
  414. struct wd719x *wd = shost_priv(cmd->device->host);
  415. dev_info(&wd->pdev->dev, "%s reset requested\n",
  416. (opcode == WD719X_CMD_BUSRESET) ? "bus" : "device");
  417. spin_lock_irqsave(wd->sh->host_lock, flags);
  418. result = wd719x_direct_cmd(wd, opcode, device, 0, 0, 0,
  419. WD719X_WAIT_FOR_SCSI_RESET);
  420. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  421. if (result)
  422. return FAILED;
  423. return SUCCESS;
  424. }
  425. static int wd719x_dev_reset(struct scsi_cmnd *cmd)
  426. {
  427. return wd719x_reset(cmd, WD719X_CMD_RESET, cmd->device->id);
  428. }
  429. static int wd719x_bus_reset(struct scsi_cmnd *cmd)
  430. {
  431. return wd719x_reset(cmd, WD719X_CMD_BUSRESET, 0);
  432. }
  433. static int wd719x_host_reset(struct scsi_cmnd *cmd)
  434. {
  435. struct wd719x *wd = shost_priv(cmd->device->host);
  436. struct wd719x_scb *scb, *tmp;
  437. unsigned long flags;
  438. int result;
  439. dev_info(&wd->pdev->dev, "host reset requested\n");
  440. spin_lock_irqsave(wd->sh->host_lock, flags);
  441. /* Try to reinit the RISC */
  442. if (wd719x_chip_init(wd) == 0)
  443. result = SUCCESS;
  444. else
  445. result = FAILED;
  446. /* flush all SCBs */
  447. list_for_each_entry_safe(scb, tmp, &wd->active_scbs, list) {
  448. struct scsi_cmnd *tmp_cmd = scb->cmd;
  449. wd719x_finish_cmd(tmp_cmd, result);
  450. }
  451. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  452. return result;
  453. }
  454. static int wd719x_biosparam(struct scsi_device *sdev, struct block_device *bdev,
  455. sector_t capacity, int geom[])
  456. {
  457. if (capacity >= 0x200000) {
  458. geom[0] = 255; /* heads */
  459. geom[1] = 63; /* sectors */
  460. } else {
  461. geom[0] = 64; /* heads */
  462. geom[1] = 32; /* sectors */
  463. }
  464. geom[2] = sector_div(capacity, geom[0] * geom[1]); /* cylinders */
  465. return 0;
  466. }
  467. /* process a SCB-completion interrupt */
  468. static inline void wd719x_interrupt_SCB(struct wd719x *wd,
  469. union wd719x_regs regs,
  470. struct wd719x_scb *scb)
  471. {
  472. struct scsi_cmnd *cmd;
  473. int result;
  474. /* now have to find result from card */
  475. switch (regs.bytes.SUE) {
  476. case WD719X_SUE_NOERRORS:
  477. result = DID_OK;
  478. break;
  479. case WD719X_SUE_REJECTED:
  480. dev_err(&wd->pdev->dev, "command rejected\n");
  481. result = DID_ERROR;
  482. break;
  483. case WD719X_SUE_SCBQFULL:
  484. dev_err(&wd->pdev->dev, "SCB queue is full\n");
  485. result = DID_ERROR;
  486. break;
  487. case WD719X_SUE_TERM:
  488. dev_dbg(&wd->pdev->dev, "SCB terminated by direct command\n");
  489. result = DID_ABORT; /* or DID_RESET? */
  490. break;
  491. case WD719X_SUE_CHAN1ABORT:
  492. case WD719X_SUE_CHAN23ABORT:
  493. result = DID_ABORT;
  494. dev_err(&wd->pdev->dev, "DMA abort\n");
  495. break;
  496. case WD719X_SUE_CHAN1PAR:
  497. case WD719X_SUE_CHAN23PAR:
  498. result = DID_PARITY;
  499. dev_err(&wd->pdev->dev, "DMA parity error\n");
  500. break;
  501. case WD719X_SUE_TIMEOUT:
  502. result = DID_TIME_OUT;
  503. dev_dbg(&wd->pdev->dev, "selection timeout\n");
  504. break;
  505. case WD719X_SUE_RESET:
  506. dev_dbg(&wd->pdev->dev, "bus reset occurred\n");
  507. result = DID_RESET;
  508. break;
  509. case WD719X_SUE_BUSERROR:
  510. dev_dbg(&wd->pdev->dev, "SCSI bus error\n");
  511. result = DID_ERROR;
  512. break;
  513. case WD719X_SUE_WRONGWAY:
  514. dev_err(&wd->pdev->dev, "wrong data transfer direction\n");
  515. result = DID_ERROR;
  516. break;
  517. case WD719X_SUE_BADPHASE:
  518. dev_err(&wd->pdev->dev, "invalid SCSI phase\n");
  519. result = DID_ERROR;
  520. break;
  521. case WD719X_SUE_TOOLONG:
  522. dev_err(&wd->pdev->dev, "record too long\n");
  523. result = DID_ERROR;
  524. break;
  525. case WD719X_SUE_BUSFREE:
  526. dev_err(&wd->pdev->dev, "unexpected bus free\n");
  527. result = DID_NO_CONNECT; /* or DID_ERROR ???*/
  528. break;
  529. case WD719X_SUE_ARSDONE:
  530. dev_dbg(&wd->pdev->dev, "auto request sense\n");
  531. if (regs.bytes.SCSI == 0)
  532. result = DID_OK;
  533. else
  534. result = DID_PARITY;
  535. break;
  536. case WD719X_SUE_IGNORED:
  537. dev_err(&wd->pdev->dev, "target id %d ignored command\n",
  538. scb->cmd->device->id);
  539. result = DID_NO_CONNECT;
  540. break;
  541. case WD719X_SUE_WRONGTAGS:
  542. dev_err(&wd->pdev->dev, "reversed tags\n");
  543. result = DID_ERROR;
  544. break;
  545. case WD719X_SUE_BADTAGS:
  546. dev_err(&wd->pdev->dev, "tag type not supported by target\n");
  547. result = DID_ERROR;
  548. break;
  549. case WD719X_SUE_NOSCAMID:
  550. dev_err(&wd->pdev->dev, "no SCAM soft ID available\n");
  551. result = DID_ERROR;
  552. break;
  553. default:
  554. dev_warn(&wd->pdev->dev, "unknown SUE error code: 0x%x\n",
  555. regs.bytes.SUE);
  556. result = DID_ERROR;
  557. break;
  558. }
  559. cmd = scb->cmd;
  560. wd719x_finish_cmd(cmd, result);
  561. }
  562. static irqreturn_t wd719x_interrupt(int irq, void *dev_id)
  563. {
  564. struct wd719x *wd = dev_id;
  565. union wd719x_regs regs;
  566. unsigned long flags;
  567. u32 SCB_out;
  568. spin_lock_irqsave(wd->sh->host_lock, flags);
  569. /* read SCB pointer back from card */
  570. SCB_out = wd719x_readl(wd, WD719X_AMR_SCB_OUT);
  571. /* read all status info at once */
  572. regs.all = cpu_to_le32(wd719x_readl(wd, WD719X_AMR_OP_CODE));
  573. switch (regs.bytes.INT) {
  574. case WD719X_INT_NONE:
  575. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  576. return IRQ_NONE;
  577. case WD719X_INT_LINKNOSTATUS:
  578. dev_err(&wd->pdev->dev, "linked command completed with no status\n");
  579. break;
  580. case WD719X_INT_BADINT:
  581. dev_err(&wd->pdev->dev, "unsolicited interrupt\n");
  582. break;
  583. case WD719X_INT_NOERRORS:
  584. case WD719X_INT_LINKNOERRORS:
  585. case WD719X_INT_ERRORSLOGGED:
  586. case WD719X_INT_SPIDERFAILED:
  587. /* was the cmd completed a direct or SCB command? */
  588. if (regs.bytes.OPC == WD719X_CMD_PROCESS_SCB) {
  589. struct wd719x_scb *scb;
  590. list_for_each_entry(scb, &wd->active_scbs, list)
  591. if (SCB_out == scb->phys)
  592. break;
  593. if (SCB_out == scb->phys)
  594. wd719x_interrupt_SCB(wd, regs, scb);
  595. else
  596. dev_err(&wd->pdev->dev, "card returned invalid SCB pointer\n");
  597. } else
  598. dev_warn(&wd->pdev->dev, "direct command 0x%x completed\n",
  599. regs.bytes.OPC);
  600. break;
  601. case WD719X_INT_PIOREADY:
  602. dev_err(&wd->pdev->dev, "card indicates PIO data ready but we never use PIO\n");
  603. /* interrupt will not be cleared until all data is read */
  604. break;
  605. default:
  606. dev_err(&wd->pdev->dev, "unknown interrupt reason: %d\n",
  607. regs.bytes.INT);
  608. }
  609. /* clear interrupt so another can happen */
  610. wd719x_writeb(wd, WD719X_AMR_INT_STATUS, WD719X_INT_NONE);
  611. spin_unlock_irqrestore(wd->sh->host_lock, flags);
  612. return IRQ_HANDLED;
  613. }
  614. static void wd719x_eeprom_reg_read(struct eeprom_93cx6 *eeprom)
  615. {
  616. struct wd719x *wd = eeprom->data;
  617. u8 reg = wd719x_readb(wd, WD719X_PCI_GPIO_DATA);
  618. eeprom->reg_data_out = reg & WD719X_EE_DO;
  619. }
  620. static void wd719x_eeprom_reg_write(struct eeprom_93cx6 *eeprom)
  621. {
  622. struct wd719x *wd = eeprom->data;
  623. u8 reg = 0;
  624. if (eeprom->reg_data_in)
  625. reg |= WD719X_EE_DI;
  626. if (eeprom->reg_data_clock)
  627. reg |= WD719X_EE_CLK;
  628. if (eeprom->reg_chip_select)
  629. reg |= WD719X_EE_CS;
  630. wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, reg);
  631. }
  632. /* read config from EEPROM so it can be downloaded by the RISC on (re-)init */
  633. static void wd719x_read_eeprom(struct wd719x *wd)
  634. {
  635. struct eeprom_93cx6 eeprom;
  636. u8 gpio;
  637. struct wd719x_eeprom_header header;
  638. eeprom.data = wd;
  639. eeprom.register_read = wd719x_eeprom_reg_read;
  640. eeprom.register_write = wd719x_eeprom_reg_write;
  641. eeprom.width = PCI_EEPROM_WIDTH_93C46;
  642. /* set all outputs to low */
  643. wd719x_writeb(wd, WD719X_PCI_GPIO_DATA, 0);
  644. /* configure GPIO pins */
  645. gpio = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL);
  646. /* GPIO outputs */
  647. gpio &= (~(WD719X_EE_CLK | WD719X_EE_DI | WD719X_EE_CS));
  648. /* GPIO input */
  649. gpio |= WD719X_EE_DO;
  650. wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, gpio);
  651. /* read EEPROM header */
  652. eeprom_93cx6_multireadb(&eeprom, 0, (u8 *)&header, sizeof(header));
  653. if (header.sig1 == 'W' && header.sig2 == 'D')
  654. eeprom_93cx6_multireadb(&eeprom, header.cfg_offset,
  655. (u8 *)wd->params,
  656. sizeof(struct wd719x_host_param));
  657. else { /* default EEPROM values */
  658. dev_warn(&wd->pdev->dev, "EEPROM signature is invalid (0x%02x 0x%02x), using default values\n",
  659. header.sig1, header.sig2);
  660. wd->params->ch_1_th = 0x10; /* 16 DWs = 64 B */
  661. wd->params->scsi_conf = 0x4c; /* 48ma, spue, parity check */
  662. wd->params->own_scsi_id = 0x07; /* ID 7, SCAM disabled */
  663. wd->params->sel_timeout = 0x4d; /* 250 ms */
  664. wd->params->sleep_timer = 0x01;
  665. wd->params->cdb_size = cpu_to_le16(0x5555); /* all 6 B */
  666. wd->params->scsi_pad = 0x1b;
  667. if (wd->type == WD719X_TYPE_7193) /* narrow card - disable */
  668. wd->params->wide = cpu_to_le32(0x00000000);
  669. else /* initiate & respond to WIDE messages */
  670. wd->params->wide = cpu_to_le32(0xffffffff);
  671. wd->params->sync = cpu_to_le32(0xffffffff);
  672. wd->params->soft_mask = 0x00; /* all disabled */
  673. wd->params->unsol_mask = 0x00; /* all disabled */
  674. }
  675. /* disable TAGGED messages */
  676. wd->params->tag_en = cpu_to_le16(0x0000);
  677. }
  678. /* Read card type from GPIO bits 1 and 3 */
  679. static enum wd719x_card_type wd719x_detect_type(struct wd719x *wd)
  680. {
  681. u8 card = wd719x_readb(wd, WD719X_PCI_GPIO_CONTROL);
  682. card |= WD719X_GPIO_ID_BITS;
  683. wd719x_writeb(wd, WD719X_PCI_GPIO_CONTROL, card);
  684. card = wd719x_readb(wd, WD719X_PCI_GPIO_DATA) & WD719X_GPIO_ID_BITS;
  685. switch (card) {
  686. case 0x08:
  687. return WD719X_TYPE_7193;
  688. case 0x02:
  689. return WD719X_TYPE_7197;
  690. case 0x00:
  691. return WD719X_TYPE_7296;
  692. default:
  693. dev_warn(&wd->pdev->dev, "unknown card type 0x%x\n", card);
  694. return WD719X_TYPE_UNKNOWN;
  695. }
  696. }
  697. static int wd719x_board_found(struct Scsi_Host *sh)
  698. {
  699. struct wd719x *wd = shost_priv(sh);
  700. char *card_types[] = { "Unknown card", "WD7193", "WD7197", "WD7296" };
  701. int ret;
  702. INIT_LIST_HEAD(&wd->active_scbs);
  703. INIT_LIST_HEAD(&wd->free_scbs);
  704. sh->base = pci_resource_start(wd->pdev, 0);
  705. wd->type = wd719x_detect_type(wd);
  706. wd->sh = sh;
  707. sh->irq = wd->pdev->irq;
  708. wd->fw_virt = NULL;
  709. /* memory area for host (EEPROM) parameters */
  710. wd->params = pci_alloc_consistent(wd->pdev,
  711. sizeof(struct wd719x_host_param),
  712. &wd->params_phys);
  713. if (!wd->params) {
  714. dev_warn(&wd->pdev->dev, "unable to allocate parameter buffer\n");
  715. return -ENOMEM;
  716. }
  717. /* memory area for the RISC for hash table of outstanding requests */
  718. wd->hash_virt = pci_alloc_consistent(wd->pdev, WD719X_HASH_TABLE_SIZE,
  719. &wd->hash_phys);
  720. if (!wd->hash_virt) {
  721. dev_warn(&wd->pdev->dev, "unable to allocate hash buffer\n");
  722. ret = -ENOMEM;
  723. goto fail_free_params;
  724. }
  725. ret = request_irq(wd->pdev->irq, wd719x_interrupt, IRQF_SHARED,
  726. "wd719x", wd);
  727. if (ret) {
  728. dev_warn(&wd->pdev->dev, "unable to assign IRQ %d\n",
  729. wd->pdev->irq);
  730. goto fail_free_hash;
  731. }
  732. /* read parameters from EEPROM */
  733. wd719x_read_eeprom(wd);
  734. ret = wd719x_chip_init(wd);
  735. if (ret)
  736. goto fail_free_irq;
  737. sh->this_id = wd->params->own_scsi_id & WD719X_EE_SCSI_ID_MASK;
  738. dev_info(&wd->pdev->dev, "%s at I/O 0x%lx, IRQ %u, SCSI ID %d\n",
  739. card_types[wd->type], sh->base, sh->irq, sh->this_id);
  740. return 0;
  741. fail_free_irq:
  742. free_irq(wd->pdev->irq, wd);
  743. fail_free_hash:
  744. pci_free_consistent(wd->pdev, WD719X_HASH_TABLE_SIZE, wd->hash_virt,
  745. wd->hash_phys);
  746. fail_free_params:
  747. pci_free_consistent(wd->pdev, sizeof(struct wd719x_host_param),
  748. wd->params, wd->params_phys);
  749. return ret;
  750. }
  751. static struct scsi_host_template wd719x_template = {
  752. .module = THIS_MODULE,
  753. .name = "Western Digital 719x",
  754. .queuecommand = wd719x_queuecommand,
  755. .eh_abort_handler = wd719x_abort,
  756. .eh_device_reset_handler = wd719x_dev_reset,
  757. .eh_bus_reset_handler = wd719x_bus_reset,
  758. .eh_host_reset_handler = wd719x_host_reset,
  759. .bios_param = wd719x_biosparam,
  760. .proc_name = "wd719x",
  761. .can_queue = 255,
  762. .this_id = 7,
  763. .sg_tablesize = WD719X_SG,
  764. .use_clustering = ENABLE_CLUSTERING,
  765. };
  766. static int wd719x_pci_probe(struct pci_dev *pdev, const struct pci_device_id *d)
  767. {
  768. int err;
  769. struct Scsi_Host *sh;
  770. struct wd719x *wd;
  771. err = pci_enable_device(pdev);
  772. if (err)
  773. goto fail;
  774. if (pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
  775. dev_warn(&pdev->dev, "Unable to set 32-bit DMA mask\n");
  776. goto disable_device;
  777. }
  778. err = pci_request_regions(pdev, "wd719x");
  779. if (err)
  780. goto disable_device;
  781. pci_set_master(pdev);
  782. err = -ENODEV;
  783. if (pci_resource_len(pdev, 0) == 0)
  784. goto release_region;
  785. err = -ENOMEM;
  786. sh = scsi_host_alloc(&wd719x_template, sizeof(struct wd719x));
  787. if (!sh)
  788. goto release_region;
  789. wd = shost_priv(sh);
  790. wd->base = pci_iomap(pdev, 0, 0);
  791. if (!wd->base)
  792. goto free_host;
  793. wd->pdev = pdev;
  794. err = wd719x_board_found(sh);
  795. if (err)
  796. goto unmap;
  797. err = scsi_add_host(sh, &wd->pdev->dev);
  798. if (err)
  799. goto destroy;
  800. scsi_scan_host(sh);
  801. pci_set_drvdata(pdev, sh);
  802. return 0;
  803. destroy:
  804. wd719x_destroy(wd);
  805. unmap:
  806. pci_iounmap(pdev, wd->base);
  807. free_host:
  808. scsi_host_put(sh);
  809. release_region:
  810. pci_release_regions(pdev);
  811. disable_device:
  812. pci_disable_device(pdev);
  813. fail:
  814. return err;
  815. }
  816. static void wd719x_pci_remove(struct pci_dev *pdev)
  817. {
  818. struct Scsi_Host *sh = pci_get_drvdata(pdev);
  819. struct wd719x *wd = shost_priv(sh);
  820. scsi_remove_host(sh);
  821. wd719x_destroy(wd);
  822. pci_iounmap(pdev, wd->base);
  823. pci_release_regions(pdev);
  824. pci_disable_device(pdev);
  825. scsi_host_put(sh);
  826. }
  827. static DEFINE_PCI_DEVICE_TABLE(wd719x_pci_table) = {
  828. { PCI_DEVICE(PCI_VENDOR_ID_WD, 0x3296) },
  829. {}
  830. };
  831. MODULE_DEVICE_TABLE(pci, wd719x_pci_table);
  832. static struct pci_driver wd719x_pci_driver = {
  833. .name = "wd719x",
  834. .id_table = wd719x_pci_table,
  835. .probe = wd719x_pci_probe,
  836. .remove = wd719x_pci_remove,
  837. };
  838. static int __init wd719x_init(void)
  839. {
  840. return pci_register_driver(&wd719x_pci_driver);
  841. }
  842. static void __exit wd719x_exit(void)
  843. {
  844. pci_unregister_driver(&wd719x_pci_driver);
  845. }
  846. module_init(wd719x_init);
  847. module_exit(wd719x_exit);
  848. MODULE_DESCRIPTION("Western Digital WD7193/7197/7296 SCSI driver");
  849. MODULE_AUTHOR("Ondrej Zary, Aaron Dewell, Juergen Gaertner");
  850. MODULE_LICENSE("GPL");
  851. MODULE_FIRMWARE("wd719x-wcs.bin");
  852. MODULE_FIRMWARE("wd719x-risc.bin");