qcom_gsbi.c 6.4 KB

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  1. /*
  2. * Copyright (c) 2014, The Linux foundation. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License rev 2 and
  6. * only rev 2 as published by the free Software foundation.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or fITNESS fOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/module.h>
  17. #include <linux/of.h>
  18. #include <linux/of_platform.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/regmap.h>
  21. #include <linux/mfd/syscon.h>
  22. #include <dt-bindings/soc/qcom,gsbi.h>
  23. #define GSBI_CTRL_REG 0x0000
  24. #define GSBI_PROTOCOL_SHIFT 4
  25. #define MAX_GSBI 12
  26. #define TCSR_ADM_CRCI_BASE 0x70
  27. struct crci_config {
  28. u32 num_rows;
  29. const u32 (*array)[MAX_GSBI];
  30. };
  31. static const u32 crci_ipq8064[][MAX_GSBI] = {
  32. {
  33. 0x000003, 0x00000c, 0x000030, 0x0000c0,
  34. 0x000300, 0x000c00, 0x003000, 0x00c000,
  35. 0x030000, 0x0c0000, 0x300000, 0xc00000
  36. },
  37. {
  38. 0x000003, 0x00000c, 0x000030, 0x0000c0,
  39. 0x000300, 0x000c00, 0x003000, 0x00c000,
  40. 0x030000, 0x0c0000, 0x300000, 0xc00000
  41. },
  42. };
  43. static const struct crci_config config_ipq8064 = {
  44. .num_rows = ARRAY_SIZE(crci_ipq8064),
  45. .array = crci_ipq8064,
  46. };
  47. static const unsigned int crci_apq8064[][MAX_GSBI] = {
  48. {
  49. 0x001800, 0x006000, 0x000030, 0x0000c0,
  50. 0x000300, 0x000400, 0x000000, 0x000000,
  51. 0x000000, 0x000000, 0x000000, 0x000000
  52. },
  53. {
  54. 0x000000, 0x000000, 0x000000, 0x000000,
  55. 0x000000, 0x000020, 0x0000c0, 0x000000,
  56. 0x000000, 0x000000, 0x000000, 0x000000
  57. },
  58. };
  59. static const struct crci_config config_apq8064 = {
  60. .num_rows = ARRAY_SIZE(crci_apq8064),
  61. .array = crci_apq8064,
  62. };
  63. static const unsigned int crci_msm8960[][MAX_GSBI] = {
  64. {
  65. 0x000003, 0x00000c, 0x000030, 0x0000c0,
  66. 0x000300, 0x000400, 0x000000, 0x000000,
  67. 0x000000, 0x000000, 0x000000, 0x000000
  68. },
  69. {
  70. 0x000000, 0x000000, 0x000000, 0x000000,
  71. 0x000000, 0x000020, 0x0000c0, 0x000300,
  72. 0x001800, 0x006000, 0x000000, 0x000000
  73. },
  74. };
  75. static const struct crci_config config_msm8960 = {
  76. .num_rows = ARRAY_SIZE(crci_msm8960),
  77. .array = crci_msm8960,
  78. };
  79. static const unsigned int crci_msm8660[][MAX_GSBI] = {
  80. { /* ADM 0 - B */
  81. 0x000003, 0x00000c, 0x000030, 0x0000c0,
  82. 0x000300, 0x000c00, 0x003000, 0x00c000,
  83. 0x030000, 0x0c0000, 0x300000, 0xc00000
  84. },
  85. { /* ADM 0 - B */
  86. 0x000003, 0x00000c, 0x000030, 0x0000c0,
  87. 0x000300, 0x000c00, 0x003000, 0x00c000,
  88. 0x030000, 0x0c0000, 0x300000, 0xc00000
  89. },
  90. { /* ADM 1 - A */
  91. 0x000003, 0x00000c, 0x000030, 0x0000c0,
  92. 0x000300, 0x000c00, 0x003000, 0x00c000,
  93. 0x030000, 0x0c0000, 0x300000, 0xc00000
  94. },
  95. { /* ADM 1 - B */
  96. 0x000003, 0x00000c, 0x000030, 0x0000c0,
  97. 0x000300, 0x000c00, 0x003000, 0x00c000,
  98. 0x030000, 0x0c0000, 0x300000, 0xc00000
  99. },
  100. };
  101. static const struct crci_config config_msm8660 = {
  102. .num_rows = ARRAY_SIZE(crci_msm8660),
  103. .array = crci_msm8660,
  104. };
  105. struct gsbi_info {
  106. struct clk *hclk;
  107. u32 mode;
  108. u32 crci;
  109. struct regmap *tcsr;
  110. };
  111. static const struct of_device_id tcsr_dt_match[] = {
  112. { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
  113. { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
  114. { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
  115. { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
  116. { },
  117. };
  118. static int gsbi_probe(struct platform_device *pdev)
  119. {
  120. struct device_node *node = pdev->dev.of_node;
  121. struct device_node *tcsr_node;
  122. const struct of_device_id *match;
  123. struct resource *res;
  124. void __iomem *base;
  125. struct gsbi_info *gsbi;
  126. int i, ret;
  127. u32 mask, gsbi_num;
  128. const struct crci_config *config = NULL;
  129. gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
  130. if (!gsbi)
  131. return -ENOMEM;
  132. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  133. base = devm_ioremap_resource(&pdev->dev, res);
  134. if (IS_ERR(base))
  135. return PTR_ERR(base);
  136. /* get the tcsr node and setup the config and regmap */
  137. gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
  138. if (!IS_ERR(gsbi->tcsr)) {
  139. tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
  140. if (tcsr_node) {
  141. match = of_match_node(tcsr_dt_match, tcsr_node);
  142. if (match)
  143. config = match->data;
  144. else
  145. dev_warn(&pdev->dev, "no matching TCSR\n");
  146. of_node_put(tcsr_node);
  147. }
  148. }
  149. if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
  150. dev_err(&pdev->dev, "missing cell-index\n");
  151. return -EINVAL;
  152. }
  153. if (gsbi_num < 1 || gsbi_num > MAX_GSBI) {
  154. dev_err(&pdev->dev, "invalid cell-index\n");
  155. return -EINVAL;
  156. }
  157. if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
  158. dev_err(&pdev->dev, "missing mode configuration\n");
  159. return -EINVAL;
  160. }
  161. /* not required, so default to 0 if not present */
  162. of_property_read_u32(node, "qcom,crci", &gsbi->crci);
  163. dev_info(&pdev->dev, "GSBI port protocol: %d crci: %d\n",
  164. gsbi->mode, gsbi->crci);
  165. gsbi->hclk = devm_clk_get(&pdev->dev, "iface");
  166. if (IS_ERR(gsbi->hclk))
  167. return PTR_ERR(gsbi->hclk);
  168. clk_prepare_enable(gsbi->hclk);
  169. writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
  170. base + GSBI_CTRL_REG);
  171. /*
  172. * modify tcsr to reflect mode and ADM CRCI mux
  173. * Each gsbi contains a pair of bits, one for RX and one for TX
  174. * SPI mode requires both bits cleared, otherwise they are set
  175. */
  176. if (config) {
  177. for (i = 0; i < config->num_rows; i++) {
  178. mask = config->array[i][gsbi_num - 1];
  179. if (gsbi->mode == GSBI_PROT_SPI)
  180. regmap_update_bits(gsbi->tcsr,
  181. TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
  182. else
  183. regmap_update_bits(gsbi->tcsr,
  184. TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
  185. }
  186. }
  187. /* make sure the gsbi control write is not reordered */
  188. wmb();
  189. platform_set_drvdata(pdev, gsbi);
  190. ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
  191. if (ret)
  192. clk_disable_unprepare(gsbi->hclk);
  193. return ret;
  194. }
  195. static int gsbi_remove(struct platform_device *pdev)
  196. {
  197. struct gsbi_info *gsbi = platform_get_drvdata(pdev);
  198. clk_disable_unprepare(gsbi->hclk);
  199. return 0;
  200. }
  201. static const struct of_device_id gsbi_dt_match[] = {
  202. { .compatible = "qcom,gsbi-v1.0.0", },
  203. { },
  204. };
  205. MODULE_DEVICE_TABLE(of, gsbi_dt_match);
  206. static struct platform_driver gsbi_driver = {
  207. .driver = {
  208. .name = "gsbi",
  209. .of_match_table = gsbi_dt_match,
  210. },
  211. .probe = gsbi_probe,
  212. .remove = gsbi_remove,
  213. };
  214. module_platform_driver(gsbi_driver);
  215. MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
  216. MODULE_DESCRIPTION("QCOM GSBI driver");
  217. MODULE_LICENSE("GPL v2");