spi-omap-uwire.c 12 KB

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  1. /*
  2. * MicroWire interface driver for OMAP
  3. *
  4. * Copyright 2003 MontaVista Software Inc. <source@mvista.com>
  5. *
  6. * Ported to 2.6 OMAP uwire interface.
  7. * Copyright (C) 2004 Texas Instruments.
  8. *
  9. * Generalization patches by Juha Yrjola <juha.yrjola@nokia.com>
  10. *
  11. * Copyright (C) 2005 David Brownell (ported to 2.6 SPI interface)
  12. * Copyright (C) 2006 Nokia
  13. *
  14. * Many updates by Imre Deak <imre.deak@nokia.com>
  15. *
  16. * This program is free software; you can redistribute it and/or modify it
  17. * under the terms of the GNU General Public License as published by the
  18. * Free Software Foundation; either version 2 of the License, or (at your
  19. * option) any later version.
  20. *
  21. * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  24. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  25. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31. */
  32. #include <linux/kernel.h>
  33. #include <linux/init.h>
  34. #include <linux/delay.h>
  35. #include <linux/platform_device.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/err.h>
  38. #include <linux/clk.h>
  39. #include <linux/slab.h>
  40. #include <linux/device.h>
  41. #include <linux/spi/spi.h>
  42. #include <linux/spi/spi_bitbang.h>
  43. #include <linux/module.h>
  44. #include <linux/io.h>
  45. #include <mach/hardware.h>
  46. #include <asm/mach-types.h>
  47. #include <mach/mux.h>
  48. #include <mach/omap7xx.h> /* OMAP7XX_IO_CONF registers */
  49. /* FIXME address is now a platform device resource,
  50. * and irqs should show there too...
  51. */
  52. #define UWIRE_BASE_PHYS 0xFFFB3000
  53. /* uWire Registers: */
  54. #define UWIRE_IO_SIZE 0x20
  55. #define UWIRE_TDR 0x00
  56. #define UWIRE_RDR 0x00
  57. #define UWIRE_CSR 0x01
  58. #define UWIRE_SR1 0x02
  59. #define UWIRE_SR2 0x03
  60. #define UWIRE_SR3 0x04
  61. #define UWIRE_SR4 0x05
  62. #define UWIRE_SR5 0x06
  63. /* CSR bits */
  64. #define RDRB (1 << 15)
  65. #define CSRB (1 << 14)
  66. #define START (1 << 13)
  67. #define CS_CMD (1 << 12)
  68. /* SR1 or SR2 bits */
  69. #define UWIRE_READ_FALLING_EDGE 0x0001
  70. #define UWIRE_READ_RISING_EDGE 0x0000
  71. #define UWIRE_WRITE_FALLING_EDGE 0x0000
  72. #define UWIRE_WRITE_RISING_EDGE 0x0002
  73. #define UWIRE_CS_ACTIVE_LOW 0x0000
  74. #define UWIRE_CS_ACTIVE_HIGH 0x0004
  75. #define UWIRE_FREQ_DIV_2 0x0000
  76. #define UWIRE_FREQ_DIV_4 0x0008
  77. #define UWIRE_FREQ_DIV_8 0x0010
  78. #define UWIRE_CHK_READY 0x0020
  79. #define UWIRE_CLK_INVERTED 0x0040
  80. struct uwire_spi {
  81. struct spi_bitbang bitbang;
  82. struct clk *ck;
  83. };
  84. struct uwire_state {
  85. unsigned div1_idx;
  86. };
  87. /* REVISIT compile time constant for idx_shift? */
  88. /*
  89. * Or, put it in a structure which is used throughout the driver;
  90. * that avoids having to issue two loads for each bit of static data.
  91. */
  92. static unsigned int uwire_idx_shift;
  93. static void __iomem *uwire_base;
  94. static inline void uwire_write_reg(int idx, u16 val)
  95. {
  96. __raw_writew(val, uwire_base + (idx << uwire_idx_shift));
  97. }
  98. static inline u16 uwire_read_reg(int idx)
  99. {
  100. return __raw_readw(uwire_base + (idx << uwire_idx_shift));
  101. }
  102. static inline void omap_uwire_configure_mode(u8 cs, unsigned long flags)
  103. {
  104. u16 w, val = 0;
  105. int shift, reg;
  106. if (flags & UWIRE_CLK_INVERTED)
  107. val ^= 0x03;
  108. val = flags & 0x3f;
  109. if (cs & 1)
  110. shift = 6;
  111. else
  112. shift = 0;
  113. if (cs <= 1)
  114. reg = UWIRE_SR1;
  115. else
  116. reg = UWIRE_SR2;
  117. w = uwire_read_reg(reg);
  118. w &= ~(0x3f << shift);
  119. w |= val << shift;
  120. uwire_write_reg(reg, w);
  121. }
  122. static int wait_uwire_csr_flag(u16 mask, u16 val, int might_not_catch)
  123. {
  124. u16 w;
  125. int c = 0;
  126. unsigned long max_jiffies = jiffies + HZ;
  127. for (;;) {
  128. w = uwire_read_reg(UWIRE_CSR);
  129. if ((w & mask) == val)
  130. break;
  131. if (time_after(jiffies, max_jiffies)) {
  132. printk(KERN_ERR "%s: timeout. reg=%#06x "
  133. "mask=%#06x val=%#06x\n",
  134. __func__, w, mask, val);
  135. return -1;
  136. }
  137. c++;
  138. if (might_not_catch && c > 64)
  139. break;
  140. }
  141. return 0;
  142. }
  143. static void uwire_set_clk1_div(int div1_idx)
  144. {
  145. u16 w;
  146. w = uwire_read_reg(UWIRE_SR3);
  147. w &= ~(0x03 << 1);
  148. w |= div1_idx << 1;
  149. uwire_write_reg(UWIRE_SR3, w);
  150. }
  151. static void uwire_chipselect(struct spi_device *spi, int value)
  152. {
  153. struct uwire_state *ust = spi->controller_state;
  154. u16 w;
  155. int old_cs;
  156. BUG_ON(wait_uwire_csr_flag(CSRB, 0, 0));
  157. w = uwire_read_reg(UWIRE_CSR);
  158. old_cs = (w >> 10) & 0x03;
  159. if (value == BITBANG_CS_INACTIVE || old_cs != spi->chip_select) {
  160. /* Deselect this CS, or the previous CS */
  161. w &= ~CS_CMD;
  162. uwire_write_reg(UWIRE_CSR, w);
  163. }
  164. /* activate specfied chipselect */
  165. if (value == BITBANG_CS_ACTIVE) {
  166. uwire_set_clk1_div(ust->div1_idx);
  167. /* invert clock? */
  168. if (spi->mode & SPI_CPOL)
  169. uwire_write_reg(UWIRE_SR4, 1);
  170. else
  171. uwire_write_reg(UWIRE_SR4, 0);
  172. w = spi->chip_select << 10;
  173. w |= CS_CMD;
  174. uwire_write_reg(UWIRE_CSR, w);
  175. }
  176. }
  177. static int uwire_txrx(struct spi_device *spi, struct spi_transfer *t)
  178. {
  179. unsigned len = t->len;
  180. unsigned bits = t->bits_per_word;
  181. unsigned bytes;
  182. u16 val, w;
  183. int status = 0;
  184. if (!t->tx_buf && !t->rx_buf)
  185. return 0;
  186. w = spi->chip_select << 10;
  187. w |= CS_CMD;
  188. if (t->tx_buf) {
  189. const u8 *buf = t->tx_buf;
  190. /* NOTE: DMA could be used for TX transfers */
  191. /* write one or two bytes at a time */
  192. while (len >= 1) {
  193. /* tx bit 15 is first sent; we byteswap multibyte words
  194. * (msb-first) on the way out from memory.
  195. */
  196. val = *buf++;
  197. if (bits > 8) {
  198. bytes = 2;
  199. val |= *buf++ << 8;
  200. } else
  201. bytes = 1;
  202. val <<= 16 - bits;
  203. #ifdef VERBOSE
  204. pr_debug("%s: write-%d =%04x\n",
  205. dev_name(&spi->dev), bits, val);
  206. #endif
  207. if (wait_uwire_csr_flag(CSRB, 0, 0))
  208. goto eio;
  209. uwire_write_reg(UWIRE_TDR, val);
  210. /* start write */
  211. val = START | w | (bits << 5);
  212. uwire_write_reg(UWIRE_CSR, val);
  213. len -= bytes;
  214. /* Wait till write actually starts.
  215. * This is needed with MPU clock 60+ MHz.
  216. * REVISIT: we may not have time to catch it...
  217. */
  218. if (wait_uwire_csr_flag(CSRB, CSRB, 1))
  219. goto eio;
  220. status += bytes;
  221. }
  222. /* REVISIT: save this for later to get more i/o overlap */
  223. if (wait_uwire_csr_flag(CSRB, 0, 0))
  224. goto eio;
  225. } else if (t->rx_buf) {
  226. u8 *buf = t->rx_buf;
  227. /* read one or two bytes at a time */
  228. while (len) {
  229. if (bits > 8) {
  230. bytes = 2;
  231. } else
  232. bytes = 1;
  233. /* start read */
  234. val = START | w | (bits << 0);
  235. uwire_write_reg(UWIRE_CSR, val);
  236. len -= bytes;
  237. /* Wait till read actually starts */
  238. (void) wait_uwire_csr_flag(CSRB, CSRB, 1);
  239. if (wait_uwire_csr_flag(RDRB | CSRB,
  240. RDRB, 0))
  241. goto eio;
  242. /* rx bit 0 is last received; multibyte words will
  243. * be properly byteswapped on the way to memory.
  244. */
  245. val = uwire_read_reg(UWIRE_RDR);
  246. val &= (1 << bits) - 1;
  247. *buf++ = (u8) val;
  248. if (bytes == 2)
  249. *buf++ = val >> 8;
  250. status += bytes;
  251. #ifdef VERBOSE
  252. pr_debug("%s: read-%d =%04x\n",
  253. dev_name(&spi->dev), bits, val);
  254. #endif
  255. }
  256. }
  257. return status;
  258. eio:
  259. return -EIO;
  260. }
  261. static int uwire_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
  262. {
  263. struct uwire_state *ust = spi->controller_state;
  264. struct uwire_spi *uwire;
  265. unsigned flags = 0;
  266. unsigned hz;
  267. unsigned long rate;
  268. int div1_idx;
  269. int div1;
  270. int div2;
  271. int status;
  272. uwire = spi_master_get_devdata(spi->master);
  273. /* mode 0..3, clock inverted separately;
  274. * standard nCS signaling;
  275. * don't treat DI=high as "not ready"
  276. */
  277. if (spi->mode & SPI_CS_HIGH)
  278. flags |= UWIRE_CS_ACTIVE_HIGH;
  279. if (spi->mode & SPI_CPOL)
  280. flags |= UWIRE_CLK_INVERTED;
  281. switch (spi->mode & (SPI_CPOL | SPI_CPHA)) {
  282. case SPI_MODE_0:
  283. case SPI_MODE_3:
  284. flags |= UWIRE_WRITE_FALLING_EDGE | UWIRE_READ_RISING_EDGE;
  285. break;
  286. case SPI_MODE_1:
  287. case SPI_MODE_2:
  288. flags |= UWIRE_WRITE_RISING_EDGE | UWIRE_READ_FALLING_EDGE;
  289. break;
  290. }
  291. /* assume it's already enabled */
  292. rate = clk_get_rate(uwire->ck);
  293. if (t != NULL)
  294. hz = t->speed_hz;
  295. else
  296. hz = spi->max_speed_hz;
  297. if (!hz) {
  298. pr_debug("%s: zero speed?\n", dev_name(&spi->dev));
  299. status = -EINVAL;
  300. goto done;
  301. }
  302. /* F_INT = mpu_xor_clk / DIV1 */
  303. for (div1_idx = 0; div1_idx < 4; div1_idx++) {
  304. switch (div1_idx) {
  305. case 0:
  306. div1 = 2;
  307. break;
  308. case 1:
  309. div1 = 4;
  310. break;
  311. case 2:
  312. div1 = 7;
  313. break;
  314. default:
  315. case 3:
  316. div1 = 10;
  317. break;
  318. }
  319. div2 = (rate / div1 + hz - 1) / hz;
  320. if (div2 <= 8)
  321. break;
  322. }
  323. if (div1_idx == 4) {
  324. pr_debug("%s: lowest clock %ld, need %d\n",
  325. dev_name(&spi->dev), rate / 10 / 8, hz);
  326. status = -EDOM;
  327. goto done;
  328. }
  329. /* we have to cache this and reset in uwire_chipselect as this is a
  330. * global parameter and another uwire device can change it under
  331. * us */
  332. ust->div1_idx = div1_idx;
  333. uwire_set_clk1_div(div1_idx);
  334. rate /= div1;
  335. switch (div2) {
  336. case 0:
  337. case 1:
  338. case 2:
  339. flags |= UWIRE_FREQ_DIV_2;
  340. rate /= 2;
  341. break;
  342. case 3:
  343. case 4:
  344. flags |= UWIRE_FREQ_DIV_4;
  345. rate /= 4;
  346. break;
  347. case 5:
  348. case 6:
  349. case 7:
  350. case 8:
  351. flags |= UWIRE_FREQ_DIV_8;
  352. rate /= 8;
  353. break;
  354. }
  355. omap_uwire_configure_mode(spi->chip_select, flags);
  356. pr_debug("%s: uwire flags %02x, armxor %lu KHz, SCK %lu KHz\n",
  357. __func__, flags,
  358. clk_get_rate(uwire->ck) / 1000,
  359. rate / 1000);
  360. status = 0;
  361. done:
  362. return status;
  363. }
  364. static int uwire_setup(struct spi_device *spi)
  365. {
  366. struct uwire_state *ust = spi->controller_state;
  367. if (ust == NULL) {
  368. ust = kzalloc(sizeof(*ust), GFP_KERNEL);
  369. if (ust == NULL)
  370. return -ENOMEM;
  371. spi->controller_state = ust;
  372. }
  373. return uwire_setup_transfer(spi, NULL);
  374. }
  375. static void uwire_cleanup(struct spi_device *spi)
  376. {
  377. kfree(spi->controller_state);
  378. }
  379. static void uwire_off(struct uwire_spi *uwire)
  380. {
  381. uwire_write_reg(UWIRE_SR3, 0);
  382. clk_disable(uwire->ck);
  383. spi_master_put(uwire->bitbang.master);
  384. }
  385. static int uwire_probe(struct platform_device *pdev)
  386. {
  387. struct spi_master *master;
  388. struct uwire_spi *uwire;
  389. int status;
  390. master = spi_alloc_master(&pdev->dev, sizeof *uwire);
  391. if (!master)
  392. return -ENODEV;
  393. uwire = spi_master_get_devdata(master);
  394. uwire_base = devm_ioremap(&pdev->dev, UWIRE_BASE_PHYS, UWIRE_IO_SIZE);
  395. if (!uwire_base) {
  396. dev_dbg(&pdev->dev, "can't ioremap UWIRE\n");
  397. spi_master_put(master);
  398. return -ENOMEM;
  399. }
  400. platform_set_drvdata(pdev, uwire);
  401. uwire->ck = devm_clk_get(&pdev->dev, "fck");
  402. if (IS_ERR(uwire->ck)) {
  403. status = PTR_ERR(uwire->ck);
  404. dev_dbg(&pdev->dev, "no functional clock?\n");
  405. spi_master_put(master);
  406. return status;
  407. }
  408. clk_enable(uwire->ck);
  409. if (cpu_is_omap7xx())
  410. uwire_idx_shift = 1;
  411. else
  412. uwire_idx_shift = 2;
  413. uwire_write_reg(UWIRE_SR3, 1);
  414. /* the spi->mode bits understood by this driver: */
  415. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
  416. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
  417. master->flags = SPI_MASTER_HALF_DUPLEX;
  418. master->bus_num = 2; /* "official" */
  419. master->num_chipselect = 4;
  420. master->setup = uwire_setup;
  421. master->cleanup = uwire_cleanup;
  422. uwire->bitbang.master = master;
  423. uwire->bitbang.chipselect = uwire_chipselect;
  424. uwire->bitbang.setup_transfer = uwire_setup_transfer;
  425. uwire->bitbang.txrx_bufs = uwire_txrx;
  426. status = spi_bitbang_start(&uwire->bitbang);
  427. if (status < 0) {
  428. uwire_off(uwire);
  429. }
  430. return status;
  431. }
  432. static int uwire_remove(struct platform_device *pdev)
  433. {
  434. struct uwire_spi *uwire = platform_get_drvdata(pdev);
  435. // FIXME remove all child devices, somewhere ...
  436. spi_bitbang_stop(&uwire->bitbang);
  437. uwire_off(uwire);
  438. return 0;
  439. }
  440. /* work with hotplug and coldplug */
  441. MODULE_ALIAS("platform:omap_uwire");
  442. static struct platform_driver uwire_driver = {
  443. .driver = {
  444. .name = "omap_uwire",
  445. },
  446. .probe = uwire_probe,
  447. .remove = uwire_remove,
  448. // suspend ... unuse ck
  449. // resume ... use ck
  450. };
  451. static int __init omap_uwire_init(void)
  452. {
  453. /* FIXME move these into the relevant board init code. also, include
  454. * H3 support; it uses tsc2101 like H2 (on a different chipselect).
  455. */
  456. if (machine_is_omap_h2()) {
  457. /* defaults: W21 SDO, U18 SDI, V19 SCL */
  458. omap_cfg_reg(N14_1610_UWIRE_CS0);
  459. omap_cfg_reg(N15_1610_UWIRE_CS1);
  460. }
  461. if (machine_is_omap_perseus2()) {
  462. /* configure pins: MPU_UW_nSCS1, MPU_UW_SDO, MPU_UW_SCLK */
  463. int val = omap_readl(OMAP7XX_IO_CONF_9) & ~0x00EEE000;
  464. omap_writel(val | 0x00AAA000, OMAP7XX_IO_CONF_9);
  465. }
  466. return platform_driver_register(&uwire_driver);
  467. }
  468. static void __exit omap_uwire_exit(void)
  469. {
  470. platform_driver_unregister(&uwire_driver);
  471. }
  472. subsys_initcall(omap_uwire_init);
  473. module_exit(omap_uwire_exit);
  474. MODULE_LICENSE("GPL");