spi-sun6i.c 12 KB

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  1. /*
  2. * Copyright (C) 2012 - 2014 Allwinner Tech
  3. * Pan Nan <pannan@allwinnertech.com>
  4. *
  5. * Copyright (C) 2014 Maxime Ripard
  6. * Maxime Ripard <maxime.ripard@free-electrons.com>
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/device.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/pm_runtime.h>
  21. #include <linux/reset.h>
  22. #include <linux/spi/spi.h>
  23. #define SUN6I_FIFO_DEPTH 128
  24. #define SUN6I_GBL_CTL_REG 0x04
  25. #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
  26. #define SUN6I_GBL_CTL_MASTER BIT(1)
  27. #define SUN6I_GBL_CTL_TP BIT(7)
  28. #define SUN6I_GBL_CTL_RST BIT(31)
  29. #define SUN6I_TFR_CTL_REG 0x08
  30. #define SUN6I_TFR_CTL_CPHA BIT(0)
  31. #define SUN6I_TFR_CTL_CPOL BIT(1)
  32. #define SUN6I_TFR_CTL_SPOL BIT(2)
  33. #define SUN6I_TFR_CTL_CS_MASK 0x30
  34. #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK)
  35. #define SUN6I_TFR_CTL_CS_MANUAL BIT(6)
  36. #define SUN6I_TFR_CTL_CS_LEVEL BIT(7)
  37. #define SUN6I_TFR_CTL_DHB BIT(8)
  38. #define SUN6I_TFR_CTL_FBS BIT(12)
  39. #define SUN6I_TFR_CTL_XCH BIT(31)
  40. #define SUN6I_INT_CTL_REG 0x10
  41. #define SUN6I_INT_CTL_RF_OVF BIT(8)
  42. #define SUN6I_INT_CTL_TC BIT(12)
  43. #define SUN6I_INT_STA_REG 0x14
  44. #define SUN6I_FIFO_CTL_REG 0x18
  45. #define SUN6I_FIFO_CTL_RF_RST BIT(15)
  46. #define SUN6I_FIFO_CTL_TF_RST BIT(31)
  47. #define SUN6I_FIFO_STA_REG 0x1c
  48. #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f
  49. #define SUN6I_FIFO_STA_RF_CNT_BITS 0
  50. #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f
  51. #define SUN6I_FIFO_STA_TF_CNT_BITS 16
  52. #define SUN6I_CLK_CTL_REG 0x24
  53. #define SUN6I_CLK_CTL_CDR2_MASK 0xff
  54. #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0)
  55. #define SUN6I_CLK_CTL_CDR1_MASK 0xf
  56. #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8)
  57. #define SUN6I_CLK_CTL_DRS BIT(12)
  58. #define SUN6I_BURST_CNT_REG 0x30
  59. #define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff)
  60. #define SUN6I_XMIT_CNT_REG 0x34
  61. #define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
  62. #define SUN6I_BURST_CTL_CNT_REG 0x38
  63. #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff)
  64. #define SUN6I_TXDATA_REG 0x200
  65. #define SUN6I_RXDATA_REG 0x300
  66. struct sun6i_spi {
  67. struct spi_master *master;
  68. void __iomem *base_addr;
  69. struct clk *hclk;
  70. struct clk *mclk;
  71. struct reset_control *rstc;
  72. struct completion done;
  73. const u8 *tx_buf;
  74. u8 *rx_buf;
  75. int len;
  76. };
  77. static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
  78. {
  79. return readl(sspi->base_addr + reg);
  80. }
  81. static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value)
  82. {
  83. writel(value, sspi->base_addr + reg);
  84. }
  85. static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len)
  86. {
  87. u32 reg, cnt;
  88. u8 byte;
  89. /* See how much data is available */
  90. reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG);
  91. reg &= SUN6I_FIFO_STA_RF_CNT_MASK;
  92. cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS;
  93. if (len > cnt)
  94. len = cnt;
  95. while (len--) {
  96. byte = readb(sspi->base_addr + SUN6I_RXDATA_REG);
  97. if (sspi->rx_buf)
  98. *sspi->rx_buf++ = byte;
  99. }
  100. }
  101. static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len)
  102. {
  103. u8 byte;
  104. if (len > sspi->len)
  105. len = sspi->len;
  106. while (len--) {
  107. byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
  108. writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG);
  109. sspi->len--;
  110. }
  111. }
  112. static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
  113. {
  114. struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
  115. u32 reg;
  116. reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
  117. reg &= ~SUN6I_TFR_CTL_CS_MASK;
  118. reg |= SUN6I_TFR_CTL_CS(spi->chip_select);
  119. if (enable)
  120. reg |= SUN6I_TFR_CTL_CS_LEVEL;
  121. else
  122. reg &= ~SUN6I_TFR_CTL_CS_LEVEL;
  123. sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
  124. }
  125. static int sun6i_spi_transfer_one(struct spi_master *master,
  126. struct spi_device *spi,
  127. struct spi_transfer *tfr)
  128. {
  129. struct sun6i_spi *sspi = spi_master_get_devdata(master);
  130. unsigned int mclk_rate, div, timeout;
  131. unsigned int start, end, tx_time;
  132. unsigned int tx_len = 0;
  133. int ret = 0;
  134. u32 reg;
  135. /* We don't support transfer larger than the FIFO */
  136. if (tfr->len > SUN6I_FIFO_DEPTH)
  137. return -EINVAL;
  138. reinit_completion(&sspi->done);
  139. sspi->tx_buf = tfr->tx_buf;
  140. sspi->rx_buf = tfr->rx_buf;
  141. sspi->len = tfr->len;
  142. /* Clear pending interrupts */
  143. sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0);
  144. /* Reset FIFO */
  145. sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG,
  146. SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST);
  147. /*
  148. * Setup the transfer control register: Chip Select,
  149. * polarities, etc.
  150. */
  151. reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
  152. if (spi->mode & SPI_CPOL)
  153. reg |= SUN6I_TFR_CTL_CPOL;
  154. else
  155. reg &= ~SUN6I_TFR_CTL_CPOL;
  156. if (spi->mode & SPI_CPHA)
  157. reg |= SUN6I_TFR_CTL_CPHA;
  158. else
  159. reg &= ~SUN6I_TFR_CTL_CPHA;
  160. if (spi->mode & SPI_LSB_FIRST)
  161. reg |= SUN6I_TFR_CTL_FBS;
  162. else
  163. reg &= ~SUN6I_TFR_CTL_FBS;
  164. /*
  165. * If it's a TX only transfer, we don't want to fill the RX
  166. * FIFO with bogus data
  167. */
  168. if (sspi->rx_buf)
  169. reg &= ~SUN6I_TFR_CTL_DHB;
  170. else
  171. reg |= SUN6I_TFR_CTL_DHB;
  172. /* We want to control the chip select manually */
  173. reg |= SUN6I_TFR_CTL_CS_MANUAL;
  174. sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg);
  175. /* Ensure that we have a parent clock fast enough */
  176. mclk_rate = clk_get_rate(sspi->mclk);
  177. if (mclk_rate < (2 * spi->max_speed_hz)) {
  178. clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz);
  179. mclk_rate = clk_get_rate(sspi->mclk);
  180. }
  181. /*
  182. * Setup clock divider.
  183. *
  184. * We have two choices there. Either we can use the clock
  185. * divide rate 1, which is calculated thanks to this formula:
  186. * SPI_CLK = MOD_CLK / (2 ^ cdr)
  187. * Or we can use CDR2, which is calculated with the formula:
  188. * SPI_CLK = MOD_CLK / (2 * (cdr + 1))
  189. * Wether we use the former or the latter is set through the
  190. * DRS bit.
  191. *
  192. * First try CDR2, and if we can't reach the expected
  193. * frequency, fall back to CDR1.
  194. */
  195. div = mclk_rate / (2 * spi->max_speed_hz);
  196. if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) {
  197. if (div > 0)
  198. div--;
  199. reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS;
  200. } else {
  201. div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz);
  202. reg = SUN6I_CLK_CTL_CDR1(div);
  203. }
  204. sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg);
  205. /* Setup the transfer now... */
  206. if (sspi->tx_buf)
  207. tx_len = tfr->len;
  208. /* Setup the counters */
  209. sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len));
  210. sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len));
  211. sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG,
  212. SUN6I_BURST_CTL_CNT_STC(tx_len));
  213. /* Fill the TX FIFO */
  214. sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
  215. /* Enable the interrupts */
  216. sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
  217. /* Start the transfer */
  218. reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG);
  219. sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH);
  220. tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U);
  221. start = jiffies;
  222. timeout = wait_for_completion_timeout(&sspi->done,
  223. msecs_to_jiffies(tx_time));
  224. end = jiffies;
  225. if (!timeout) {
  226. dev_warn(&master->dev,
  227. "%s: timeout transferring %u bytes@%iHz for %i(%i)ms",
  228. dev_name(&spi->dev), tfr->len, tfr->speed_hz,
  229. jiffies_to_msecs(end - start), tx_time);
  230. ret = -ETIMEDOUT;
  231. goto out;
  232. }
  233. sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
  234. out:
  235. sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
  236. return ret;
  237. }
  238. static irqreturn_t sun6i_spi_handler(int irq, void *dev_id)
  239. {
  240. struct sun6i_spi *sspi = dev_id;
  241. u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG);
  242. /* Transfer complete */
  243. if (status & SUN6I_INT_CTL_TC) {
  244. sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC);
  245. complete(&sspi->done);
  246. return IRQ_HANDLED;
  247. }
  248. return IRQ_NONE;
  249. }
  250. static int sun6i_spi_runtime_resume(struct device *dev)
  251. {
  252. struct spi_master *master = dev_get_drvdata(dev);
  253. struct sun6i_spi *sspi = spi_master_get_devdata(master);
  254. int ret;
  255. ret = clk_prepare_enable(sspi->hclk);
  256. if (ret) {
  257. dev_err(dev, "Couldn't enable AHB clock\n");
  258. goto out;
  259. }
  260. ret = clk_prepare_enable(sspi->mclk);
  261. if (ret) {
  262. dev_err(dev, "Couldn't enable module clock\n");
  263. goto err;
  264. }
  265. ret = reset_control_deassert(sspi->rstc);
  266. if (ret) {
  267. dev_err(dev, "Couldn't deassert the device from reset\n");
  268. goto err2;
  269. }
  270. sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG,
  271. SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP);
  272. return 0;
  273. err2:
  274. clk_disable_unprepare(sspi->mclk);
  275. err:
  276. clk_disable_unprepare(sspi->hclk);
  277. out:
  278. return ret;
  279. }
  280. static int sun6i_spi_runtime_suspend(struct device *dev)
  281. {
  282. struct spi_master *master = dev_get_drvdata(dev);
  283. struct sun6i_spi *sspi = spi_master_get_devdata(master);
  284. reset_control_assert(sspi->rstc);
  285. clk_disable_unprepare(sspi->mclk);
  286. clk_disable_unprepare(sspi->hclk);
  287. return 0;
  288. }
  289. static int sun6i_spi_probe(struct platform_device *pdev)
  290. {
  291. struct spi_master *master;
  292. struct sun6i_spi *sspi;
  293. struct resource *res;
  294. int ret = 0, irq;
  295. master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi));
  296. if (!master) {
  297. dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
  298. return -ENOMEM;
  299. }
  300. platform_set_drvdata(pdev, master);
  301. sspi = spi_master_get_devdata(master);
  302. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  303. sspi->base_addr = devm_ioremap_resource(&pdev->dev, res);
  304. if (IS_ERR(sspi->base_addr)) {
  305. ret = PTR_ERR(sspi->base_addr);
  306. goto err_free_master;
  307. }
  308. irq = platform_get_irq(pdev, 0);
  309. if (irq < 0) {
  310. dev_err(&pdev->dev, "No spi IRQ specified\n");
  311. ret = -ENXIO;
  312. goto err_free_master;
  313. }
  314. ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler,
  315. 0, "sun6i-spi", sspi);
  316. if (ret) {
  317. dev_err(&pdev->dev, "Cannot request IRQ\n");
  318. goto err_free_master;
  319. }
  320. sspi->master = master;
  321. master->set_cs = sun6i_spi_set_cs;
  322. master->transfer_one = sun6i_spi_transfer_one;
  323. master->num_chipselect = 4;
  324. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
  325. master->bits_per_word_mask = SPI_BPW_MASK(8);
  326. master->dev.of_node = pdev->dev.of_node;
  327. master->auto_runtime_pm = true;
  328. sspi->hclk = devm_clk_get(&pdev->dev, "ahb");
  329. if (IS_ERR(sspi->hclk)) {
  330. dev_err(&pdev->dev, "Unable to acquire AHB clock\n");
  331. ret = PTR_ERR(sspi->hclk);
  332. goto err_free_master;
  333. }
  334. sspi->mclk = devm_clk_get(&pdev->dev, "mod");
  335. if (IS_ERR(sspi->mclk)) {
  336. dev_err(&pdev->dev, "Unable to acquire module clock\n");
  337. ret = PTR_ERR(sspi->mclk);
  338. goto err_free_master;
  339. }
  340. init_completion(&sspi->done);
  341. sspi->rstc = devm_reset_control_get(&pdev->dev, NULL);
  342. if (IS_ERR(sspi->rstc)) {
  343. dev_err(&pdev->dev, "Couldn't get reset controller\n");
  344. ret = PTR_ERR(sspi->rstc);
  345. goto err_free_master;
  346. }
  347. /*
  348. * This wake-up/shutdown pattern is to be able to have the
  349. * device woken up, even if runtime_pm is disabled
  350. */
  351. ret = sun6i_spi_runtime_resume(&pdev->dev);
  352. if (ret) {
  353. dev_err(&pdev->dev, "Couldn't resume the device\n");
  354. goto err_free_master;
  355. }
  356. pm_runtime_set_active(&pdev->dev);
  357. pm_runtime_enable(&pdev->dev);
  358. pm_runtime_idle(&pdev->dev);
  359. ret = devm_spi_register_master(&pdev->dev, master);
  360. if (ret) {
  361. dev_err(&pdev->dev, "cannot register SPI master\n");
  362. goto err_pm_disable;
  363. }
  364. return 0;
  365. err_pm_disable:
  366. pm_runtime_disable(&pdev->dev);
  367. sun6i_spi_runtime_suspend(&pdev->dev);
  368. err_free_master:
  369. spi_master_put(master);
  370. return ret;
  371. }
  372. static int sun6i_spi_remove(struct platform_device *pdev)
  373. {
  374. pm_runtime_force_suspend(&pdev->dev);
  375. return 0;
  376. }
  377. static const struct of_device_id sun6i_spi_match[] = {
  378. { .compatible = "allwinner,sun6i-a31-spi", },
  379. {}
  380. };
  381. MODULE_DEVICE_TABLE(of, sun6i_spi_match);
  382. static const struct dev_pm_ops sun6i_spi_pm_ops = {
  383. .runtime_resume = sun6i_spi_runtime_resume,
  384. .runtime_suspend = sun6i_spi_runtime_suspend,
  385. };
  386. static struct platform_driver sun6i_spi_driver = {
  387. .probe = sun6i_spi_probe,
  388. .remove = sun6i_spi_remove,
  389. .driver = {
  390. .name = "sun6i-spi",
  391. .of_match_table = sun6i_spi_match,
  392. .pm = &sun6i_spi_pm_ops,
  393. },
  394. };
  395. module_platform_driver(sun6i_spi_driver);
  396. MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>");
  397. MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
  398. MODULE_DESCRIPTION("Allwinner A31 SPI controller driver");
  399. MODULE_LICENSE("GPL");