spi-zynqmp-gqspi.c 33 KB

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  1. /*
  2. * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
  3. * (master mode only)
  4. *
  5. * Copyright (C) 2009 - 2015 Xilinx, Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published
  9. * by the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include <linux/clk.h>
  13. #include <linux/delay.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/dmaengine.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <linux/of_irq.h>
  20. #include <linux/of_address.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/workqueue.h>
  25. /* Generic QSPI register offsets */
  26. #define GQSPI_CONFIG_OFST 0x00000100
  27. #define GQSPI_ISR_OFST 0x00000104
  28. #define GQSPI_IDR_OFST 0x0000010C
  29. #define GQSPI_IER_OFST 0x00000108
  30. #define GQSPI_IMASK_OFST 0x00000110
  31. #define GQSPI_EN_OFST 0x00000114
  32. #define GQSPI_TXD_OFST 0x0000011C
  33. #define GQSPI_RXD_OFST 0x00000120
  34. #define GQSPI_TX_THRESHOLD_OFST 0x00000128
  35. #define GQSPI_RX_THRESHOLD_OFST 0x0000012C
  36. #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
  37. #define GQSPI_GEN_FIFO_OFST 0x00000140
  38. #define GQSPI_SEL_OFST 0x00000144
  39. #define GQSPI_GF_THRESHOLD_OFST 0x00000150
  40. #define GQSPI_FIFO_CTRL_OFST 0x0000014C
  41. #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
  42. #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
  43. #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
  44. #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
  45. #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
  46. #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
  47. #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
  48. #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
  49. #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
  50. /* GQSPI register bit masks */
  51. #define GQSPI_SEL_MASK 0x00000001
  52. #define GQSPI_EN_MASK 0x00000001
  53. #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
  54. #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
  55. #define GQSPI_IDR_ALL_MASK 0x00000FBE
  56. #define GQSPI_CFG_MODE_EN_MASK 0xC0000000
  57. #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
  58. #define GQSPI_CFG_ENDIAN_MASK 0x04000000
  59. #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
  60. #define GQSPI_CFG_WP_HOLD_MASK 0x00080000
  61. #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
  62. #define GQSPI_CFG_CLK_PHA_MASK 0x00000004
  63. #define GQSPI_CFG_CLK_POL_MASK 0x00000002
  64. #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
  65. #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
  66. #define GQSPI_GENFIFO_DATA_XFER 0x00000100
  67. #define GQSPI_GENFIFO_EXP 0x00000200
  68. #define GQSPI_GENFIFO_MODE_SPI 0x00000400
  69. #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
  70. #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
  71. #define GQSPI_GENFIFO_MODE_MASK 0x00000C00
  72. #define GQSPI_GENFIFO_CS_LOWER 0x00001000
  73. #define GQSPI_GENFIFO_CS_UPPER 0x00002000
  74. #define GQSPI_GENFIFO_BUS_LOWER 0x00004000
  75. #define GQSPI_GENFIFO_BUS_UPPER 0x00008000
  76. #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
  77. #define GQSPI_GENFIFO_BUS_MASK 0x0000C000
  78. #define GQSPI_GENFIFO_TX 0x00010000
  79. #define GQSPI_GENFIFO_RX 0x00020000
  80. #define GQSPI_GENFIFO_STRIPE 0x00040000
  81. #define GQSPI_GENFIFO_POLL 0x00080000
  82. #define GQSPI_GENFIFO_EXP_START 0x00000100
  83. #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
  84. #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
  85. #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
  86. #define GQSPI_ISR_RXEMPTY_MASK 0x00000800
  87. #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
  88. #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
  89. #define GQSPI_ISR_TXEMPTY_MASK 0x00000100
  90. #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
  91. #define GQSPI_ISR_RXFULL_MASK 0x00000020
  92. #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
  93. #define GQSPI_ISR_TXFULL_MASK 0x00000008
  94. #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
  95. #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
  96. #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
  97. #define GQSPI_IER_RXEMPTY_MASK 0x00000800
  98. #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
  99. #define GQSPI_IER_RXNEMPTY_MASK 0x00000010
  100. #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
  101. #define GQSPI_IER_TXEMPTY_MASK 0x00000100
  102. #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
  103. #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
  104. #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
  105. #define GQSPI_ISR_IDR_MASK 0x00000994
  106. #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
  107. #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
  108. #define GQSPI_IRQ_MASK 0x00000980
  109. #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
  110. #define GQSPI_GENFIFO_CS_SETUP 0x4
  111. #define GQSPI_GENFIFO_CS_HOLD 0x3
  112. #define GQSPI_TXD_DEPTH 64
  113. #define GQSPI_RX_FIFO_THRESHOLD 32
  114. #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
  115. #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
  116. #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
  117. GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
  118. #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
  119. #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
  120. #define GQSPI_SELECT_FLASH_CS_LOWER 0x1
  121. #define GQSPI_SELECT_FLASH_CS_UPPER 0x2
  122. #define GQSPI_SELECT_FLASH_CS_BOTH 0x3
  123. #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
  124. #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
  125. #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
  126. #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
  127. #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
  128. #define GQSPI_SELECT_MODE_SPI 0x1
  129. #define GQSPI_SELECT_MODE_DUALSPI 0x2
  130. #define GQSPI_SELECT_MODE_QUADSPI 0x4
  131. #define GQSPI_DMA_UNALIGN 0x3
  132. #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
  133. enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
  134. /**
  135. * struct zynqmp_qspi - Defines qspi driver instance
  136. * @regs: Virtual address of the QSPI controller registers
  137. * @refclk: Pointer to the peripheral clock
  138. * @pclk: Pointer to the APB clock
  139. * @irq: IRQ number
  140. * @dev: Pointer to struct device
  141. * @txbuf: Pointer to the TX buffer
  142. * @rxbuf: Pointer to the RX buffer
  143. * @bytes_to_transfer: Number of bytes left to transfer
  144. * @bytes_to_receive: Number of bytes left to receive
  145. * @genfifocs: Used for chip select
  146. * @genfifobus: Used to select the upper or lower bus
  147. * @dma_rx_bytes: Remaining bytes to receive by DMA mode
  148. * @dma_addr: DMA address after mapping the kernel buffer
  149. * @genfifoentry: Used for storing the genfifoentry instruction.
  150. * @mode: Defines the mode in which QSPI is operating
  151. */
  152. struct zynqmp_qspi {
  153. void __iomem *regs;
  154. struct clk *refclk;
  155. struct clk *pclk;
  156. int irq;
  157. struct device *dev;
  158. const void *txbuf;
  159. void *rxbuf;
  160. int bytes_to_transfer;
  161. int bytes_to_receive;
  162. u32 genfifocs;
  163. u32 genfifobus;
  164. u32 dma_rx_bytes;
  165. dma_addr_t dma_addr;
  166. u32 genfifoentry;
  167. enum mode_type mode;
  168. };
  169. /**
  170. * zynqmp_gqspi_read: For GQSPI controller read operation
  171. * @xqspi: Pointer to the zynqmp_qspi structure
  172. * @offset: Offset from where to read
  173. */
  174. static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
  175. {
  176. return readl_relaxed(xqspi->regs + offset);
  177. }
  178. /**
  179. * zynqmp_gqspi_write: For GQSPI controller write operation
  180. * @xqspi: Pointer to the zynqmp_qspi structure
  181. * @offset: Offset where to write
  182. * @val: Value to be written
  183. */
  184. static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
  185. u32 val)
  186. {
  187. writel_relaxed(val, (xqspi->regs + offset));
  188. }
  189. /**
  190. * zynqmp_gqspi_selectslave: For selection of slave device
  191. * @instanceptr: Pointer to the zynqmp_qspi structure
  192. * @flashcs: For chip select
  193. * @flashbus: To check which bus is selected- upper or lower
  194. */
  195. static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
  196. u8 slavecs, u8 slavebus)
  197. {
  198. /*
  199. * Bus and CS lines selected here will be updated in the instance and
  200. * used for subsequent GENFIFO entries during transfer.
  201. */
  202. /* Choose slave select line */
  203. switch (slavecs) {
  204. case GQSPI_SELECT_FLASH_CS_BOTH:
  205. instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
  206. GQSPI_GENFIFO_CS_UPPER;
  207. break;
  208. case GQSPI_SELECT_FLASH_CS_UPPER:
  209. instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
  210. break;
  211. case GQSPI_SELECT_FLASH_CS_LOWER:
  212. instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
  213. break;
  214. default:
  215. dev_warn(instanceptr->dev, "Invalid slave select\n");
  216. }
  217. /* Choose the bus */
  218. switch (slavebus) {
  219. case GQSPI_SELECT_FLASH_BUS_BOTH:
  220. instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
  221. GQSPI_GENFIFO_BUS_UPPER;
  222. break;
  223. case GQSPI_SELECT_FLASH_BUS_UPPER:
  224. instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
  225. break;
  226. case GQSPI_SELECT_FLASH_BUS_LOWER:
  227. instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
  228. break;
  229. default:
  230. dev_warn(instanceptr->dev, "Invalid slave bus\n");
  231. }
  232. }
  233. /**
  234. * zynqmp_qspi_init_hw: Initialize the hardware
  235. * @xqspi: Pointer to the zynqmp_qspi structure
  236. *
  237. * The default settings of the QSPI controller's configurable parameters on
  238. * reset are
  239. * - Master mode
  240. * - TX threshold set to 1
  241. * - RX threshold set to 1
  242. * - Flash memory interface mode enabled
  243. * This function performs the following actions
  244. * - Disable and clear all the interrupts
  245. * - Enable manual slave select
  246. * - Enable manual start
  247. * - Deselect all the chip select lines
  248. * - Set the little endian mode of TX FIFO and
  249. * - Enable the QSPI controller
  250. */
  251. static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
  252. {
  253. u32 config_reg;
  254. /* Select the GQSPI mode */
  255. zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
  256. /* Clear and disable interrupts */
  257. zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
  258. zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
  259. GQSPI_ISR_WR_TO_CLR_MASK);
  260. /* Clear the DMA STS */
  261. zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
  262. zynqmp_gqspi_read(xqspi,
  263. GQSPI_QSPIDMA_DST_I_STS_OFST));
  264. zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
  265. zynqmp_gqspi_read(xqspi,
  266. GQSPI_QSPIDMA_DST_STS_OFST) |
  267. GQSPI_QSPIDMA_DST_STS_WTC);
  268. zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
  269. zynqmp_gqspi_write(xqspi,
  270. GQSPI_QSPIDMA_DST_I_DIS_OFST,
  271. GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
  272. /* Disable the GQSPI */
  273. zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
  274. config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
  275. config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
  276. /* Manual start */
  277. config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
  278. /* Little endian by default */
  279. config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
  280. /* Disable poll time out */
  281. config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
  282. /* Set hold bit */
  283. config_reg |= GQSPI_CFG_WP_HOLD_MASK;
  284. /* Clear pre-scalar by default */
  285. config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
  286. /* CPHA 0 */
  287. config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
  288. /* CPOL 0 */
  289. config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
  290. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
  291. /* Clear the TX and RX FIFO */
  292. zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
  293. GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
  294. GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
  295. GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
  296. /* Set by default to allow for high frequencies */
  297. zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
  298. zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
  299. GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
  300. /* Reset thresholds */
  301. zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
  302. GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
  303. zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
  304. GQSPI_RX_FIFO_THRESHOLD);
  305. zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
  306. GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
  307. zynqmp_gqspi_selectslave(xqspi,
  308. GQSPI_SELECT_FLASH_CS_LOWER,
  309. GQSPI_SELECT_FLASH_BUS_LOWER);
  310. /* Initialize DMA */
  311. zynqmp_gqspi_write(xqspi,
  312. GQSPI_QSPIDMA_DST_CTRL_OFST,
  313. GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
  314. /* Enable the GQSPI */
  315. zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
  316. }
  317. /**
  318. * zynqmp_qspi_copy_read_data: Copy data to RX buffer
  319. * @xqspi: Pointer to the zynqmp_qspi structure
  320. * @data: The variable where data is stored
  321. * @size: Number of bytes to be copied from data to RX buffer
  322. */
  323. static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
  324. ulong data, u8 size)
  325. {
  326. memcpy(xqspi->rxbuf, &data, size);
  327. xqspi->rxbuf += size;
  328. xqspi->bytes_to_receive -= size;
  329. }
  330. /**
  331. * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer.
  332. * @master: Pointer to the spi_master structure which provides
  333. * information about the controller.
  334. *
  335. * This function enables SPI master controller.
  336. *
  337. * Return: 0 on success; error value otherwise
  338. */
  339. static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
  340. {
  341. struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
  342. int ret;
  343. ret = clk_enable(xqspi->refclk);
  344. if (ret)
  345. goto clk_err;
  346. ret = clk_enable(xqspi->pclk);
  347. if (ret)
  348. goto clk_err;
  349. zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
  350. return 0;
  351. clk_err:
  352. return ret;
  353. }
  354. /**
  355. * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer
  356. * @master: Pointer to the spi_master structure which provides
  357. * information about the controller.
  358. *
  359. * This function disables the SPI master controller.
  360. *
  361. * Return: Always 0
  362. */
  363. static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
  364. {
  365. struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
  366. zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
  367. clk_disable(xqspi->refclk);
  368. clk_disable(xqspi->pclk);
  369. return 0;
  370. }
  371. /**
  372. * zynqmp_qspi_chipselect: Select or deselect the chip select line
  373. * @qspi: Pointer to the spi_device structure
  374. * @is_high: Select(0) or deselect (1) the chip select line
  375. */
  376. static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
  377. {
  378. struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
  379. ulong timeout;
  380. u32 genfifoentry = 0x0, statusreg;
  381. genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
  382. genfifoentry |= xqspi->genfifobus;
  383. if (!is_high) {
  384. genfifoentry |= xqspi->genfifocs;
  385. genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
  386. } else {
  387. genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
  388. }
  389. zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
  390. /* Dummy generic FIFO entry */
  391. zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
  392. /* Manually start the generic FIFO command */
  393. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
  394. zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
  395. GQSPI_CFG_START_GEN_FIFO_MASK);
  396. timeout = jiffies + msecs_to_jiffies(1000);
  397. /* Wait until the generic FIFO command is empty */
  398. do {
  399. statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
  400. if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
  401. (statusreg & GQSPI_ISR_TXEMPTY_MASK))
  402. break;
  403. else
  404. cpu_relax();
  405. } while (!time_after_eq(jiffies, timeout));
  406. if (time_after_eq(jiffies, timeout))
  407. dev_err(xqspi->dev, "Chip select timed out\n");
  408. }
  409. /**
  410. * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified
  411. * transfer
  412. * @qspi: Pointer to the spi_device structure
  413. * @transfer: Pointer to the spi_transfer structure which provides
  414. * information about next transfer setup parameters
  415. *
  416. * Sets the operational mode of QSPI controller for the next QSPI transfer and
  417. * sets the requested clock frequency.
  418. *
  419. * Return: Always 0
  420. *
  421. * Note:
  422. * If the requested frequency is not an exact match with what can be
  423. * obtained using the pre-scalar value, the driver sets the clock
  424. * frequency which is lower than the requested frequency (maximum lower)
  425. * for the transfer.
  426. *
  427. * If the requested frequency is higher or lower than that is supported
  428. * by the QSPI controller the driver will set the highest or lowest
  429. * frequency supported by controller.
  430. */
  431. static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
  432. struct spi_transfer *transfer)
  433. {
  434. struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
  435. ulong clk_rate;
  436. u32 config_reg, req_hz, baud_rate_val = 0;
  437. if (transfer)
  438. req_hz = transfer->speed_hz;
  439. else
  440. req_hz = qspi->max_speed_hz;
  441. /* Set the clock frequency */
  442. /* If req_hz == 0, default to lowest speed */
  443. clk_rate = clk_get_rate(xqspi->refclk);
  444. while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
  445. (clk_rate /
  446. (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
  447. baud_rate_val++;
  448. config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
  449. /* Set the QSPI clock phase and clock polarity */
  450. config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
  451. if (qspi->mode & SPI_CPHA)
  452. config_reg |= GQSPI_CFG_CLK_PHA_MASK;
  453. if (qspi->mode & SPI_CPOL)
  454. config_reg |= GQSPI_CFG_CLK_POL_MASK;
  455. config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
  456. config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
  457. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
  458. return 0;
  459. }
  460. /**
  461. * zynqmp_qspi_setup: Configure the QSPI controller
  462. * @qspi: Pointer to the spi_device structure
  463. *
  464. * Sets the operational mode of QSPI controller for the next QSPI transfer,
  465. * baud rate and divisor value to setup the requested qspi clock.
  466. *
  467. * Return: 0 on success; error value otherwise.
  468. */
  469. static int zynqmp_qspi_setup(struct spi_device *qspi)
  470. {
  471. if (qspi->master->busy)
  472. return -EBUSY;
  473. return 0;
  474. }
  475. /**
  476. * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in
  477. * the FIFO or the bytes required to be
  478. * transmitted.
  479. * @xqspi: Pointer to the zynqmp_qspi structure
  480. * @size: Number of bytes to be copied from TX buffer to TX FIFO
  481. */
  482. static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
  483. {
  484. u32 count = 0, intermediate;
  485. while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
  486. memcpy(&intermediate, xqspi->txbuf, 4);
  487. zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
  488. if (xqspi->bytes_to_transfer >= 4) {
  489. xqspi->txbuf += 4;
  490. xqspi->bytes_to_transfer -= 4;
  491. } else {
  492. xqspi->txbuf += xqspi->bytes_to_transfer;
  493. xqspi->bytes_to_transfer = 0;
  494. }
  495. count++;
  496. }
  497. }
  498. /**
  499. * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in
  500. * the FIFO.
  501. * @xqspi: Pointer to the zynqmp_qspi structure
  502. * @size: Number of bytes to be copied from RX buffer to RX FIFO
  503. */
  504. static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
  505. {
  506. ulong data;
  507. int count = 0;
  508. while ((count < size) && (xqspi->bytes_to_receive > 0)) {
  509. if (xqspi->bytes_to_receive >= 4) {
  510. (*(u32 *) xqspi->rxbuf) =
  511. zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
  512. xqspi->rxbuf += 4;
  513. xqspi->bytes_to_receive -= 4;
  514. count += 4;
  515. } else {
  516. data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
  517. count += xqspi->bytes_to_receive;
  518. zynqmp_qspi_copy_read_data(xqspi, data,
  519. xqspi->bytes_to_receive);
  520. xqspi->bytes_to_receive = 0;
  521. }
  522. }
  523. }
  524. /**
  525. * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI
  526. * controller
  527. * @xqspi: zynqmp_qspi instance pointer
  528. *
  529. * This function handles DMA interrupt only.
  530. */
  531. static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
  532. {
  533. u32 config_reg, genfifoentry;
  534. dma_unmap_single(xqspi->dev, xqspi->dma_addr,
  535. xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
  536. xqspi->rxbuf += xqspi->dma_rx_bytes;
  537. xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
  538. xqspi->dma_rx_bytes = 0;
  539. /* Disabling the DMA interrupts */
  540. zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
  541. GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
  542. if (xqspi->bytes_to_receive > 0) {
  543. /* Switch to IO mode,for remaining bytes to receive */
  544. config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
  545. config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
  546. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
  547. /* Initiate the transfer of remaining bytes */
  548. genfifoentry = xqspi->genfifoentry;
  549. genfifoentry |= xqspi->bytes_to_receive;
  550. zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
  551. /* Dummy generic FIFO entry */
  552. zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
  553. /* Manual start */
  554. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
  555. (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
  556. GQSPI_CFG_START_GEN_FIFO_MASK));
  557. /* Enable the RX interrupts for IO mode */
  558. zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
  559. GQSPI_IER_GENFIFOEMPTY_MASK |
  560. GQSPI_IER_RXNEMPTY_MASK |
  561. GQSPI_IER_RXEMPTY_MASK);
  562. }
  563. }
  564. /**
  565. * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller
  566. * @irq: IRQ number
  567. * @dev_id: Pointer to the xqspi structure
  568. *
  569. * This function handles TX empty only.
  570. * On TX empty interrupt this function reads the received data from RX FIFO
  571. * and fills the TX FIFO if there is any data remaining to be transferred.
  572. *
  573. * Return: IRQ_HANDLED when interrupt is handled
  574. * IRQ_NONE otherwise.
  575. */
  576. static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
  577. {
  578. struct spi_master *master = dev_id;
  579. struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
  580. int ret = IRQ_NONE;
  581. u32 status, mask, dma_status = 0;
  582. status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
  583. zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
  584. mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
  585. /* Read and clear DMA status */
  586. if (xqspi->mode == GQSPI_MODE_DMA) {
  587. dma_status =
  588. zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
  589. zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
  590. dma_status);
  591. }
  592. if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
  593. zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
  594. ret = IRQ_HANDLED;
  595. }
  596. if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
  597. zynqmp_process_dma_irq(xqspi);
  598. ret = IRQ_HANDLED;
  599. } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
  600. (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
  601. zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
  602. ret = IRQ_HANDLED;
  603. }
  604. if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
  605. && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
  606. zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
  607. spi_finalize_current_transfer(master);
  608. ret = IRQ_HANDLED;
  609. }
  610. return ret;
  611. }
  612. /**
  613. * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4.
  614. * @xqspi: xqspi is a pointer to the GQSPI instance
  615. * @spimode: spimode - SPI or DUAL or QUAD.
  616. * Return: Mask to set desired SPI mode in GENFIFO entry.
  617. */
  618. static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
  619. u8 spimode)
  620. {
  621. u32 mask = 0;
  622. switch (spimode) {
  623. case GQSPI_SELECT_MODE_DUALSPI:
  624. mask = GQSPI_GENFIFO_MODE_DUALSPI;
  625. break;
  626. case GQSPI_SELECT_MODE_QUADSPI:
  627. mask = GQSPI_GENFIFO_MODE_QUADSPI;
  628. break;
  629. case GQSPI_SELECT_MODE_SPI:
  630. mask = GQSPI_GENFIFO_MODE_SPI;
  631. break;
  632. default:
  633. dev_warn(xqspi->dev, "Invalid SPI mode\n");
  634. }
  635. return mask;
  636. }
  637. /**
  638. * zynq_qspi_setuprxdma: This function sets up the RX DMA operation
  639. * @xqspi: xqspi is a pointer to the GQSPI instance.
  640. */
  641. static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
  642. {
  643. u32 rx_bytes, rx_rem, config_reg;
  644. dma_addr_t addr;
  645. u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
  646. if ((xqspi->bytes_to_receive < 8) ||
  647. ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
  648. /* Setting to IO mode */
  649. config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
  650. config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
  651. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
  652. xqspi->mode = GQSPI_MODE_IO;
  653. xqspi->dma_rx_bytes = 0;
  654. return;
  655. }
  656. rx_rem = xqspi->bytes_to_receive % 4;
  657. rx_bytes = (xqspi->bytes_to_receive - rx_rem);
  658. addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
  659. rx_bytes, DMA_FROM_DEVICE);
  660. if (dma_mapping_error(xqspi->dev, addr))
  661. dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
  662. xqspi->dma_rx_bytes = rx_bytes;
  663. xqspi->dma_addr = addr;
  664. zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
  665. (u32)(addr & 0xffffffff));
  666. addr = ((addr >> 16) >> 16);
  667. zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
  668. ((u32)addr) & 0xfff);
  669. /* Enabling the DMA mode */
  670. config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
  671. config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
  672. config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
  673. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
  674. /* Switch to DMA mode */
  675. xqspi->mode = GQSPI_MODE_DMA;
  676. /* Write the number of bytes to transfer */
  677. zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
  678. }
  679. /**
  680. * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in
  681. * the transfer and sets up the GENFIFO entries,
  682. * TX FIFO as required.
  683. * @xqspi: xqspi is a pointer to the GQSPI instance.
  684. * @transfer: It is a pointer to the structure containing transfer data.
  685. * @genfifoentry: genfifoentry is pointer to the variable in which
  686. * GENFIFO mask is returned to calling function
  687. */
  688. static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
  689. struct spi_transfer *transfer,
  690. u32 *genfifoentry)
  691. {
  692. u32 config_reg;
  693. /* Transmit */
  694. if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
  695. /* Setup data to be TXed */
  696. *genfifoentry &= ~GQSPI_GENFIFO_RX;
  697. *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
  698. *genfifoentry |= GQSPI_GENFIFO_TX;
  699. *genfifoentry |=
  700. zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
  701. xqspi->bytes_to_transfer = transfer->len;
  702. if (xqspi->mode == GQSPI_MODE_DMA) {
  703. config_reg = zynqmp_gqspi_read(xqspi,
  704. GQSPI_CONFIG_OFST);
  705. config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
  706. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
  707. config_reg);
  708. xqspi->mode = GQSPI_MODE_IO;
  709. }
  710. zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
  711. /* Discard RX data */
  712. xqspi->bytes_to_receive = 0;
  713. } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
  714. /* Receive */
  715. /* TX auto fill */
  716. *genfifoentry &= ~GQSPI_GENFIFO_TX;
  717. /* Setup RX */
  718. *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
  719. *genfifoentry |= GQSPI_GENFIFO_RX;
  720. *genfifoentry |=
  721. zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
  722. xqspi->bytes_to_transfer = 0;
  723. xqspi->bytes_to_receive = transfer->len;
  724. zynq_qspi_setuprxdma(xqspi);
  725. }
  726. }
  727. /**
  728. * zynqmp_qspi_start_transfer: Initiates the QSPI transfer
  729. * @master: Pointer to the spi_master structure which provides
  730. * information about the controller.
  731. * @qspi: Pointer to the spi_device structure
  732. * @transfer: Pointer to the spi_transfer structure which provide information
  733. * about next transfer parameters
  734. *
  735. * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
  736. * transfer to be completed.
  737. *
  738. * Return: Number of bytes transferred in the last transfer
  739. */
  740. static int zynqmp_qspi_start_transfer(struct spi_master *master,
  741. struct spi_device *qspi,
  742. struct spi_transfer *transfer)
  743. {
  744. struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
  745. u32 genfifoentry = 0x0, transfer_len;
  746. xqspi->txbuf = transfer->tx_buf;
  747. xqspi->rxbuf = transfer->rx_buf;
  748. zynqmp_qspi_setup_transfer(qspi, transfer);
  749. genfifoentry |= xqspi->genfifocs;
  750. genfifoentry |= xqspi->genfifobus;
  751. zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
  752. if (xqspi->mode == GQSPI_MODE_DMA)
  753. transfer_len = xqspi->dma_rx_bytes;
  754. else
  755. transfer_len = transfer->len;
  756. xqspi->genfifoentry = genfifoentry;
  757. if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
  758. genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
  759. genfifoentry |= transfer_len;
  760. zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
  761. } else {
  762. int tempcount = transfer_len;
  763. u32 exponent = 8; /* 2^8 = 256 */
  764. u8 imm_data = tempcount & 0xFF;
  765. tempcount &= ~(tempcount & 0xFF);
  766. /* Immediate entry */
  767. if (tempcount != 0) {
  768. /* Exponent entries */
  769. genfifoentry |= GQSPI_GENFIFO_EXP;
  770. while (tempcount != 0) {
  771. if (tempcount & GQSPI_GENFIFO_EXP_START) {
  772. genfifoentry &=
  773. ~GQSPI_GENFIFO_IMM_DATA_MASK;
  774. genfifoentry |= exponent;
  775. zynqmp_gqspi_write(xqspi,
  776. GQSPI_GEN_FIFO_OFST,
  777. genfifoentry);
  778. }
  779. tempcount = tempcount >> 1;
  780. exponent++;
  781. }
  782. }
  783. if (imm_data != 0) {
  784. genfifoentry &= ~GQSPI_GENFIFO_EXP;
  785. genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
  786. genfifoentry |= (u8) (imm_data & 0xFF);
  787. zynqmp_gqspi_write(xqspi,
  788. GQSPI_GEN_FIFO_OFST, genfifoentry);
  789. }
  790. }
  791. if ((xqspi->mode == GQSPI_MODE_IO) &&
  792. (xqspi->rxbuf != NULL)) {
  793. /* Dummy generic FIFO entry */
  794. zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
  795. }
  796. /* Since we are using manual mode */
  797. zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
  798. zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
  799. GQSPI_CFG_START_GEN_FIFO_MASK);
  800. if (xqspi->txbuf != NULL)
  801. /* Enable interrupts for TX */
  802. zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
  803. GQSPI_IER_TXEMPTY_MASK |
  804. GQSPI_IER_GENFIFOEMPTY_MASK |
  805. GQSPI_IER_TXNOT_FULL_MASK);
  806. if (xqspi->rxbuf != NULL) {
  807. /* Enable interrupts for RX */
  808. if (xqspi->mode == GQSPI_MODE_DMA) {
  809. /* Enable DMA interrupts */
  810. zynqmp_gqspi_write(xqspi,
  811. GQSPI_QSPIDMA_DST_I_EN_OFST,
  812. GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
  813. } else {
  814. zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
  815. GQSPI_IER_GENFIFOEMPTY_MASK |
  816. GQSPI_IER_RXNEMPTY_MASK |
  817. GQSPI_IER_RXEMPTY_MASK);
  818. }
  819. }
  820. return transfer->len;
  821. }
  822. /**
  823. * zynqmp_qspi_suspend: Suspend method for the QSPI driver
  824. * @_dev: Address of the platform_device structure
  825. *
  826. * This function stops the QSPI driver queue and disables the QSPI controller
  827. *
  828. * Return: Always 0
  829. */
  830. static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
  831. {
  832. struct platform_device *pdev = container_of(dev,
  833. struct platform_device,
  834. dev);
  835. struct spi_master *master = platform_get_drvdata(pdev);
  836. spi_master_suspend(master);
  837. zynqmp_unprepare_transfer_hardware(master);
  838. return 0;
  839. }
  840. /**
  841. * zynqmp_qspi_resume: Resume method for the QSPI driver
  842. * @dev: Address of the platform_device structure
  843. *
  844. * The function starts the QSPI driver queue and initializes the QSPI
  845. * controller
  846. *
  847. * Return: 0 on success; error value otherwise
  848. */
  849. static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
  850. {
  851. struct platform_device *pdev = container_of(dev,
  852. struct platform_device,
  853. dev);
  854. struct spi_master *master = platform_get_drvdata(pdev);
  855. struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
  856. int ret = 0;
  857. ret = clk_enable(xqspi->pclk);
  858. if (ret) {
  859. dev_err(dev, "Cannot enable APB clock.\n");
  860. return ret;
  861. }
  862. ret = clk_enable(xqspi->refclk);
  863. if (ret) {
  864. dev_err(dev, "Cannot enable device clock.\n");
  865. clk_disable(xqspi->pclk);
  866. return ret;
  867. }
  868. spi_master_resume(master);
  869. return 0;
  870. }
  871. static SIMPLE_DEV_PM_OPS(zynqmp_qspi_dev_pm_ops, zynqmp_qspi_suspend,
  872. zynqmp_qspi_resume);
  873. /**
  874. * zynqmp_qspi_probe: Probe method for the QSPI driver
  875. * @pdev: Pointer to the platform_device structure
  876. *
  877. * This function initializes the driver data structures and the hardware.
  878. *
  879. * Return: 0 on success; error value otherwise
  880. */
  881. static int zynqmp_qspi_probe(struct platform_device *pdev)
  882. {
  883. int ret = 0;
  884. struct spi_master *master;
  885. struct zynqmp_qspi *xqspi;
  886. struct resource *res;
  887. struct device *dev = &pdev->dev;
  888. master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
  889. if (!master)
  890. return -ENOMEM;
  891. xqspi = spi_master_get_devdata(master);
  892. master->dev.of_node = pdev->dev.of_node;
  893. platform_set_drvdata(pdev, master);
  894. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  895. xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
  896. if (IS_ERR(xqspi->regs)) {
  897. ret = PTR_ERR(xqspi->regs);
  898. goto remove_master;
  899. }
  900. xqspi->dev = dev;
  901. xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
  902. if (IS_ERR(xqspi->pclk)) {
  903. dev_err(dev, "pclk clock not found.\n");
  904. ret = PTR_ERR(xqspi->pclk);
  905. goto remove_master;
  906. }
  907. ret = clk_prepare_enable(xqspi->pclk);
  908. if (ret) {
  909. dev_err(dev, "Unable to enable APB clock.\n");
  910. goto remove_master;
  911. }
  912. xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
  913. if (IS_ERR(xqspi->refclk)) {
  914. dev_err(dev, "ref_clk clock not found.\n");
  915. ret = PTR_ERR(xqspi->refclk);
  916. goto clk_dis_pclk;
  917. }
  918. ret = clk_prepare_enable(xqspi->refclk);
  919. if (ret) {
  920. dev_err(dev, "Unable to enable device clock.\n");
  921. goto clk_dis_pclk;
  922. }
  923. /* QSPI controller initializations */
  924. zynqmp_qspi_init_hw(xqspi);
  925. xqspi->irq = platform_get_irq(pdev, 0);
  926. if (xqspi->irq <= 0) {
  927. ret = -ENXIO;
  928. dev_err(dev, "irq resource not found\n");
  929. goto clk_dis_all;
  930. }
  931. ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
  932. 0, pdev->name, master);
  933. if (ret != 0) {
  934. ret = -ENXIO;
  935. dev_err(dev, "request_irq failed\n");
  936. goto clk_dis_all;
  937. }
  938. master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
  939. master->setup = zynqmp_qspi_setup;
  940. master->set_cs = zynqmp_qspi_chipselect;
  941. master->transfer_one = zynqmp_qspi_start_transfer;
  942. master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
  943. master->unprepare_transfer_hardware =
  944. zynqmp_unprepare_transfer_hardware;
  945. master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
  946. master->bits_per_word_mask = SPI_BPW_MASK(8);
  947. master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
  948. SPI_TX_DUAL | SPI_TX_QUAD;
  949. if (master->dev.parent == NULL)
  950. master->dev.parent = &master->dev;
  951. ret = spi_register_master(master);
  952. if (ret)
  953. goto clk_dis_all;
  954. return 0;
  955. clk_dis_all:
  956. clk_disable_unprepare(xqspi->refclk);
  957. clk_dis_pclk:
  958. clk_disable_unprepare(xqspi->pclk);
  959. remove_master:
  960. spi_master_put(master);
  961. return ret;
  962. }
  963. /**
  964. * zynqmp_qspi_remove: Remove method for the QSPI driver
  965. * @pdev: Pointer to the platform_device structure
  966. *
  967. * This function is called if a device is physically removed from the system or
  968. * if the driver module is being unloaded. It frees all resources allocated to
  969. * the device.
  970. *
  971. * Return: 0 Always
  972. */
  973. static int zynqmp_qspi_remove(struct platform_device *pdev)
  974. {
  975. struct spi_master *master = platform_get_drvdata(pdev);
  976. struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
  977. zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
  978. clk_disable_unprepare(xqspi->refclk);
  979. clk_disable_unprepare(xqspi->pclk);
  980. spi_unregister_master(master);
  981. return 0;
  982. }
  983. static const struct of_device_id zynqmp_qspi_of_match[] = {
  984. { .compatible = "xlnx,zynqmp-qspi-1.0", },
  985. { /* End of table */ }
  986. };
  987. MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
  988. static struct platform_driver zynqmp_qspi_driver = {
  989. .probe = zynqmp_qspi_probe,
  990. .remove = zynqmp_qspi_remove,
  991. .driver = {
  992. .name = "zynqmp-qspi",
  993. .of_match_table = zynqmp_qspi_of_match,
  994. .pm = &zynqmp_qspi_dev_pm_ops,
  995. },
  996. };
  997. module_platform_driver(zynqmp_qspi_driver);
  998. MODULE_AUTHOR("Xilinx, Inc.");
  999. MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
  1000. MODULE_LICENSE("GPL");