ad9832.c 9.2 KB

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  1. /*
  2. * AD9832 SPI DDS driver
  3. *
  4. * Copyright 2011 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2.
  7. */
  8. #include <linux/device.h>
  9. #include <linux/kernel.h>
  10. #include <linux/slab.h>
  11. #include <linux/sysfs.h>
  12. #include <linux/spi/spi.h>
  13. #include <linux/regulator/consumer.h>
  14. #include <linux/err.h>
  15. #include <linux/module.h>
  16. #include <asm/div64.h>
  17. #include <linux/iio/iio.h>
  18. #include <linux/iio/sysfs.h>
  19. #include "dds.h"
  20. #include "ad9832.h"
  21. static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
  22. {
  23. unsigned long long freqreg = (u64)fout *
  24. (u64)((u64)1L << AD9832_FREQ_BITS);
  25. do_div(freqreg, mclk);
  26. return freqreg;
  27. }
  28. static int ad9832_write_frequency(struct ad9832_state *st,
  29. unsigned addr, unsigned long fout)
  30. {
  31. unsigned long regval;
  32. if (fout > (st->mclk / 2))
  33. return -EINVAL;
  34. regval = ad9832_calc_freqreg(st->mclk, fout);
  35. st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
  36. (addr << ADD_SHIFT) |
  37. ((regval >> 24) & 0xFF));
  38. st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
  39. ((addr - 1) << ADD_SHIFT) |
  40. ((regval >> 16) & 0xFF));
  41. st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
  42. ((addr - 2) << ADD_SHIFT) |
  43. ((regval >> 8) & 0xFF));
  44. st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
  45. ((addr - 3) << ADD_SHIFT) |
  46. ((regval >> 0) & 0xFF));
  47. return spi_sync(st->spi, &st->freq_msg);
  48. }
  49. static int ad9832_write_phase(struct ad9832_state *st,
  50. unsigned long addr, unsigned long phase)
  51. {
  52. if (phase > BIT(AD9832_PHASE_BITS))
  53. return -EINVAL;
  54. st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
  55. (addr << ADD_SHIFT) |
  56. ((phase >> 8) & 0xFF));
  57. st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
  58. ((addr - 1) << ADD_SHIFT) |
  59. (phase & 0xFF));
  60. return spi_sync(st->spi, &st->phase_msg);
  61. }
  62. static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
  63. const char *buf, size_t len)
  64. {
  65. struct iio_dev *indio_dev = dev_to_iio_dev(dev);
  66. struct ad9832_state *st = iio_priv(indio_dev);
  67. struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
  68. int ret;
  69. unsigned long val;
  70. ret = kstrtoul(buf, 10, &val);
  71. if (ret)
  72. goto error_ret;
  73. mutex_lock(&indio_dev->mlock);
  74. switch ((u32)this_attr->address) {
  75. case AD9832_FREQ0HM:
  76. case AD9832_FREQ1HM:
  77. ret = ad9832_write_frequency(st, this_attr->address, val);
  78. break;
  79. case AD9832_PHASE0H:
  80. case AD9832_PHASE1H:
  81. case AD9832_PHASE2H:
  82. case AD9832_PHASE3H:
  83. ret = ad9832_write_phase(st, this_attr->address, val);
  84. break;
  85. case AD9832_PINCTRL_EN:
  86. if (val)
  87. st->ctrl_ss &= ~AD9832_SELSRC;
  88. else
  89. st->ctrl_ss |= AD9832_SELSRC;
  90. st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
  91. st->ctrl_ss);
  92. ret = spi_sync(st->spi, &st->msg);
  93. break;
  94. case AD9832_FREQ_SYM:
  95. if (val == 1) {
  96. st->ctrl_fp |= AD9832_FREQ;
  97. } else if (val == 0) {
  98. st->ctrl_fp &= ~AD9832_FREQ;
  99. } else {
  100. ret = -EINVAL;
  101. break;
  102. }
  103. st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
  104. st->ctrl_fp);
  105. ret = spi_sync(st->spi, &st->msg);
  106. break;
  107. case AD9832_PHASE_SYM:
  108. if (val > 3) {
  109. ret = -EINVAL;
  110. break;
  111. }
  112. st->ctrl_fp &= ~AD9832_PHASE(3);
  113. st->ctrl_fp |= AD9832_PHASE(val);
  114. st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
  115. st->ctrl_fp);
  116. ret = spi_sync(st->spi, &st->msg);
  117. break;
  118. case AD9832_OUTPUT_EN:
  119. if (val)
  120. st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
  121. AD9832_CLR);
  122. else
  123. st->ctrl_src |= AD9832_RESET;
  124. st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
  125. st->ctrl_src);
  126. ret = spi_sync(st->spi, &st->msg);
  127. break;
  128. default:
  129. ret = -ENODEV;
  130. }
  131. mutex_unlock(&indio_dev->mlock);
  132. error_ret:
  133. return ret ? ret : len;
  134. }
  135. /**
  136. * see dds.h for further information
  137. */
  138. static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
  139. static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
  140. static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
  141. static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
  142. static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
  143. static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
  144. static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
  145. static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
  146. static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
  147. ad9832_write, AD9832_PHASE_SYM);
  148. static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
  149. static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
  150. ad9832_write, AD9832_PINCTRL_EN);
  151. static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
  152. ad9832_write, AD9832_OUTPUT_EN);
  153. static struct attribute *ad9832_attributes[] = {
  154. &iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
  155. &iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
  156. &iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
  157. &iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
  158. &iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
  159. &iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
  160. &iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
  161. &iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
  162. &iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
  163. &iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
  164. &iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
  165. &iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
  166. NULL,
  167. };
  168. static const struct attribute_group ad9832_attribute_group = {
  169. .attrs = ad9832_attributes,
  170. };
  171. static const struct iio_info ad9832_info = {
  172. .attrs = &ad9832_attribute_group,
  173. .driver_module = THIS_MODULE,
  174. };
  175. static int ad9832_probe(struct spi_device *spi)
  176. {
  177. struct ad9832_platform_data *pdata = spi->dev.platform_data;
  178. struct iio_dev *indio_dev;
  179. struct ad9832_state *st;
  180. struct regulator *reg;
  181. int ret;
  182. if (!pdata) {
  183. dev_dbg(&spi->dev, "no platform data?\n");
  184. return -ENODEV;
  185. }
  186. reg = devm_regulator_get(&spi->dev, "vcc");
  187. if (!IS_ERR(reg)) {
  188. ret = regulator_enable(reg);
  189. if (ret)
  190. return ret;
  191. }
  192. indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
  193. if (!indio_dev) {
  194. ret = -ENOMEM;
  195. goto error_disable_reg;
  196. }
  197. spi_set_drvdata(spi, indio_dev);
  198. st = iio_priv(indio_dev);
  199. st->reg = reg;
  200. st->mclk = pdata->mclk;
  201. st->spi = spi;
  202. indio_dev->dev.parent = &spi->dev;
  203. indio_dev->name = spi_get_device_id(spi)->name;
  204. indio_dev->info = &ad9832_info;
  205. indio_dev->modes = INDIO_DIRECT_MODE;
  206. /* Setup default messages */
  207. st->xfer.tx_buf = &st->data;
  208. st->xfer.len = 2;
  209. spi_message_init(&st->msg);
  210. spi_message_add_tail(&st->xfer, &st->msg);
  211. st->freq_xfer[0].tx_buf = &st->freq_data[0];
  212. st->freq_xfer[0].len = 2;
  213. st->freq_xfer[0].cs_change = 1;
  214. st->freq_xfer[1].tx_buf = &st->freq_data[1];
  215. st->freq_xfer[1].len = 2;
  216. st->freq_xfer[1].cs_change = 1;
  217. st->freq_xfer[2].tx_buf = &st->freq_data[2];
  218. st->freq_xfer[2].len = 2;
  219. st->freq_xfer[2].cs_change = 1;
  220. st->freq_xfer[3].tx_buf = &st->freq_data[3];
  221. st->freq_xfer[3].len = 2;
  222. spi_message_init(&st->freq_msg);
  223. spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
  224. spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
  225. spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
  226. spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
  227. st->phase_xfer[0].tx_buf = &st->phase_data[0];
  228. st->phase_xfer[0].len = 2;
  229. st->phase_xfer[0].cs_change = 1;
  230. st->phase_xfer[1].tx_buf = &st->phase_data[1];
  231. st->phase_xfer[1].len = 2;
  232. spi_message_init(&st->phase_msg);
  233. spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
  234. spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
  235. st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
  236. st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
  237. st->ctrl_src);
  238. ret = spi_sync(st->spi, &st->msg);
  239. if (ret) {
  240. dev_err(&spi->dev, "device init failed\n");
  241. goto error_disable_reg;
  242. }
  243. ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
  244. if (ret)
  245. goto error_disable_reg;
  246. ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
  247. if (ret)
  248. goto error_disable_reg;
  249. ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
  250. if (ret)
  251. goto error_disable_reg;
  252. ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
  253. if (ret)
  254. goto error_disable_reg;
  255. ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
  256. if (ret)
  257. goto error_disable_reg;
  258. ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
  259. if (ret)
  260. goto error_disable_reg;
  261. ret = iio_device_register(indio_dev);
  262. if (ret)
  263. goto error_disable_reg;
  264. return 0;
  265. error_disable_reg:
  266. if (!IS_ERR(reg))
  267. regulator_disable(reg);
  268. return ret;
  269. }
  270. static int ad9832_remove(struct spi_device *spi)
  271. {
  272. struct iio_dev *indio_dev = spi_get_drvdata(spi);
  273. struct ad9832_state *st = iio_priv(indio_dev);
  274. iio_device_unregister(indio_dev);
  275. if (!IS_ERR(st->reg))
  276. regulator_disable(st->reg);
  277. return 0;
  278. }
  279. static const struct spi_device_id ad9832_id[] = {
  280. {"ad9832", 0},
  281. {"ad9835", 0},
  282. {}
  283. };
  284. MODULE_DEVICE_TABLE(spi, ad9832_id);
  285. static struct spi_driver ad9832_driver = {
  286. .driver = {
  287. .name = "ad9832",
  288. },
  289. .probe = ad9832_probe,
  290. .remove = ad9832_remove,
  291. .id_table = ad9832_id,
  292. };
  293. module_spi_driver(ad9832_driver);
  294. MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
  295. MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
  296. MODULE_LICENSE("GPL v2");