dim2_hdm.c 24 KB

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  1. /*
  2. * dim2_hdm.c - MediaLB DIM2 Hardware Dependent Module
  3. *
  4. * Copyright (C) 2015, Microchip Technology Germany II GmbH & Co. KG
  5. *
  6. * This program is distributed in the hope that it will be useful,
  7. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  8. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  9. * GNU General Public License for more details.
  10. *
  11. * This file is licensed under GPLv2.
  12. */
  13. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14. #include <linux/module.h>
  15. #include <linux/printk.h>
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/slab.h>
  21. #include <linux/io.h>
  22. #include <linux/dma-mapping.h>
  23. #include <linux/sched.h>
  24. #include <linux/kthread.h>
  25. #include <mostcore.h>
  26. #include <networking.h>
  27. #include "dim2_hal.h"
  28. #include "dim2_hdm.h"
  29. #include "dim2_errors.h"
  30. #include "dim2_sysfs.h"
  31. #define DMA_CHANNELS (32 - 1) /* channel 0 is a system channel */
  32. #define MAX_BUFFERS_PACKET 32
  33. #define MAX_BUFFERS_STREAMING 32
  34. #define MAX_BUF_SIZE_PACKET 2048
  35. #define MAX_BUF_SIZE_STREAMING (8 * 1024)
  36. /* command line parameter to select clock speed */
  37. static char *clock_speed;
  38. module_param(clock_speed, charp, 0);
  39. MODULE_PARM_DESC(clock_speed, "MediaLB Clock Speed");
  40. /*
  41. * #############################################################################
  42. *
  43. * The define below activates an utility function used by HAL-simu
  44. * for calling DIM interrupt handler.
  45. * It is used only for TEST PURPOSE and shall be commented before release.
  46. *
  47. * #############################################################################
  48. */
  49. /* #define ENABLE_HDM_TEST */
  50. static DEFINE_SPINLOCK(dim_lock);
  51. static void dim2_tasklet_fn(unsigned long data);
  52. static DECLARE_TASKLET(dim2_tasklet, dim2_tasklet_fn, 0);
  53. /**
  54. * struct hdm_channel - private structure to keep channel specific data
  55. * @is_initialized: identifier to know whether the channel is initialized
  56. * @ch: HAL specific channel data
  57. * @pending_list: list to keep MBO's before starting transfer
  58. * @started_list: list to keep MBO's after starting transfer
  59. * @direction: channel direction (TX or RX)
  60. * @data_type: channel data type
  61. */
  62. struct hdm_channel {
  63. char name[sizeof "caNNN"];
  64. bool is_initialized;
  65. struct dim_channel ch;
  66. struct list_head pending_list; /* before DIM_EnqueueBuffer() */
  67. struct list_head started_list; /* after DIM_EnqueueBuffer() */
  68. enum most_channel_direction direction;
  69. enum most_channel_data_type data_type;
  70. };
  71. /**
  72. * struct dim2_hdm - private structure to keep interface specific data
  73. * @hch: an array of channel specific data
  74. * @most_iface: most interface structure
  75. * @capabilities: an array of channel capability data
  76. * @io_base: I/O register base address
  77. * @irq_ahb0: dim2 AHB0 irq number
  78. * @clk_speed: user selectable (through command line parameter) clock speed
  79. * @netinfo_task: thread to deliver network status
  80. * @netinfo_waitq: waitq for the thread to sleep
  81. * @deliver_netinfo: to identify whether network status received
  82. * @mac_addrs: INIC mac address
  83. * @link_state: network link state
  84. * @atx_idx: index of async tx channel
  85. */
  86. struct dim2_hdm {
  87. struct hdm_channel hch[DMA_CHANNELS];
  88. struct most_channel_capability capabilities[DMA_CHANNELS];
  89. struct most_interface most_iface;
  90. char name[16 + sizeof "dim2-"];
  91. void *io_base;
  92. unsigned int irq_ahb0;
  93. int clk_speed;
  94. struct task_struct *netinfo_task;
  95. wait_queue_head_t netinfo_waitq;
  96. int deliver_netinfo;
  97. unsigned char mac_addrs[6];
  98. unsigned char link_state;
  99. int atx_idx;
  100. struct medialb_bus bus;
  101. };
  102. #define iface_to_hdm(iface) container_of(iface, struct dim2_hdm, most_iface)
  103. /* Macro to identify a network status message */
  104. #define PACKET_IS_NET_INFO(p) \
  105. (((p)[1] == 0x18) && ((p)[2] == 0x05) && ((p)[3] == 0x0C) && \
  106. ((p)[13] == 0x3C) && ((p)[14] == 0x00) && ((p)[15] == 0x0A))
  107. #if defined(ENABLE_HDM_TEST)
  108. static struct dim2_hdm *test_dev;
  109. #endif
  110. bool dim2_sysfs_get_state_cb(void)
  111. {
  112. bool state;
  113. unsigned long flags;
  114. spin_lock_irqsave(&dim_lock, flags);
  115. state = DIM_GetLockState();
  116. spin_unlock_irqrestore(&dim_lock, flags);
  117. return state;
  118. }
  119. /**
  120. * DIMCB_IoRead - callback from HAL to read an I/O register
  121. * @ptr32: register address
  122. */
  123. u32 DIMCB_IoRead(u32 *ptr32)
  124. {
  125. return __raw_readl(ptr32);
  126. }
  127. /**
  128. * DIMCB_IoWrite - callback from HAL to write value to an I/O register
  129. * @ptr32: register address
  130. * @value: value to write
  131. */
  132. void DIMCB_IoWrite(u32 *ptr32, u32 value)
  133. {
  134. __raw_writel(value, ptr32);
  135. }
  136. /**
  137. * DIMCB_OnError - callback from HAL to report miscommunication between
  138. * HDM and HAL
  139. * @error_id: Error ID
  140. * @error_message: Error message. Some text in a free format
  141. */
  142. void DIMCB_OnError(u8 error_id, const char *error_message)
  143. {
  144. pr_err("DIMCB_OnError: error_id - %d, error_message - %s\n", error_id,
  145. error_message);
  146. }
  147. /**
  148. * startup_dim - initialize the dim2 interface
  149. * @pdev: platform device
  150. *
  151. * Get the value of command line parameter "clock_speed" if given or use the
  152. * default value, enable the clock and PLL, and initialize the dim2 interface.
  153. */
  154. static int startup_dim(struct platform_device *pdev)
  155. {
  156. struct dim2_hdm *dev = platform_get_drvdata(pdev);
  157. struct dim2_platform_data *pdata = pdev->dev.platform_data;
  158. u8 hal_ret;
  159. dev->clk_speed = -1;
  160. if (clock_speed) {
  161. if (!strcmp(clock_speed, "256fs"))
  162. dev->clk_speed = CLK_256FS;
  163. else if (!strcmp(clock_speed, "512fs"))
  164. dev->clk_speed = CLK_512FS;
  165. else if (!strcmp(clock_speed, "1024fs"))
  166. dev->clk_speed = CLK_1024FS;
  167. else if (!strcmp(clock_speed, "2048fs"))
  168. dev->clk_speed = CLK_2048FS;
  169. else if (!strcmp(clock_speed, "3072fs"))
  170. dev->clk_speed = CLK_3072FS;
  171. else if (!strcmp(clock_speed, "4096fs"))
  172. dev->clk_speed = CLK_4096FS;
  173. else if (!strcmp(clock_speed, "6144fs"))
  174. dev->clk_speed = CLK_6144FS;
  175. else if (!strcmp(clock_speed, "8192fs"))
  176. dev->clk_speed = CLK_8192FS;
  177. }
  178. if (dev->clk_speed == -1) {
  179. pr_info("Bad or missing clock speed parameter, using default value: 3072fs\n");
  180. dev->clk_speed = CLK_3072FS;
  181. } else {
  182. pr_info("Selected clock speed: %s\n", clock_speed);
  183. }
  184. if (pdata && pdata->init) {
  185. int ret = pdata->init(pdata, dev->io_base, dev->clk_speed);
  186. if (ret)
  187. return ret;
  188. }
  189. hal_ret = DIM_Startup(dev->io_base, dev->clk_speed);
  190. if (hal_ret != DIM_NO_ERROR) {
  191. pr_err("DIM_Startup failed: %d\n", hal_ret);
  192. if (pdata && pdata->destroy)
  193. pdata->destroy(pdata);
  194. return -ENODEV;
  195. }
  196. return 0;
  197. }
  198. /**
  199. * try_start_dim_transfer - try to transfer a buffer on a channel
  200. * @hdm_ch: channel specific data
  201. *
  202. * Transfer a buffer from pending_list if the channel is ready
  203. */
  204. static int try_start_dim_transfer(struct hdm_channel *hdm_ch)
  205. {
  206. u16 buf_size;
  207. struct list_head *head = &hdm_ch->pending_list;
  208. struct mbo *mbo;
  209. unsigned long flags;
  210. struct dim_ch_state_t st;
  211. BUG_ON(!hdm_ch);
  212. BUG_ON(!hdm_ch->is_initialized);
  213. spin_lock_irqsave(&dim_lock, flags);
  214. if (list_empty(head)) {
  215. spin_unlock_irqrestore(&dim_lock, flags);
  216. return -EAGAIN;
  217. }
  218. if (!DIM_GetChannelState(&hdm_ch->ch, &st)->ready) {
  219. spin_unlock_irqrestore(&dim_lock, flags);
  220. return -EAGAIN;
  221. }
  222. mbo = list_entry(head->next, struct mbo, list);
  223. buf_size = mbo->buffer_length;
  224. BUG_ON(mbo->bus_address == 0);
  225. if (!DIM_EnqueueBuffer(&hdm_ch->ch, mbo->bus_address, buf_size)) {
  226. list_del(head->next);
  227. spin_unlock_irqrestore(&dim_lock, flags);
  228. mbo->processed_length = 0;
  229. mbo->status = MBO_E_INVAL;
  230. mbo->complete(mbo);
  231. return -EFAULT;
  232. }
  233. list_move_tail(head->next, &hdm_ch->started_list);
  234. spin_unlock_irqrestore(&dim_lock, flags);
  235. return 0;
  236. }
  237. /**
  238. * deliver_netinfo_thread - thread to deliver network status to mostcore
  239. * @data: private data
  240. *
  241. * Wait for network status and deliver it to mostcore once it is received
  242. */
  243. static int deliver_netinfo_thread(void *data)
  244. {
  245. struct dim2_hdm *dev = data;
  246. while (!kthread_should_stop()) {
  247. wait_event_interruptible(dev->netinfo_waitq,
  248. dev->deliver_netinfo ||
  249. kthread_should_stop());
  250. if (dev->deliver_netinfo) {
  251. dev->deliver_netinfo--;
  252. most_deliver_netinfo(&dev->most_iface, dev->link_state,
  253. dev->mac_addrs);
  254. }
  255. }
  256. return 0;
  257. }
  258. /**
  259. * retrieve_netinfo - retrieve network status from received buffer
  260. * @dev: private data
  261. * @mbo: received MBO
  262. *
  263. * Parse the message in buffer and get node address, link state, MAC address.
  264. * Wake up a thread to deliver this status to mostcore
  265. */
  266. static void retrieve_netinfo(struct dim2_hdm *dev, struct mbo *mbo)
  267. {
  268. u8 *data = mbo->virt_address;
  269. u8 *mac = dev->mac_addrs;
  270. pr_info("Node Address: 0x%03x\n", (u16)data[16] << 8 | data[17]);
  271. dev->link_state = data[18];
  272. pr_info("NIState: %d\n", dev->link_state);
  273. memcpy(mac, data + 19, 6);
  274. pr_info("MAC address: %02X:%02X:%02X:%02X:%02X:%02X\n",
  275. mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
  276. dev->deliver_netinfo++;
  277. wake_up_interruptible(&dev->netinfo_waitq);
  278. }
  279. /**
  280. * service_done_flag - handle completed buffers
  281. * @dev: private data
  282. * @ch_idx: channel index
  283. *
  284. * Return back the completed buffers to mostcore, using completion callback
  285. */
  286. static void service_done_flag(struct dim2_hdm *dev, int ch_idx)
  287. {
  288. struct hdm_channel *hdm_ch = dev->hch + ch_idx;
  289. struct dim_ch_state_t st;
  290. struct list_head *head;
  291. struct mbo *mbo;
  292. int done_buffers;
  293. unsigned long flags;
  294. u8 *data;
  295. BUG_ON(!hdm_ch);
  296. BUG_ON(!hdm_ch->is_initialized);
  297. spin_lock_irqsave(&dim_lock, flags);
  298. done_buffers = DIM_GetChannelState(&hdm_ch->ch, &st)->done_buffers;
  299. if (!done_buffers) {
  300. spin_unlock_irqrestore(&dim_lock, flags);
  301. return;
  302. }
  303. if (!DIM_DetachBuffers(&hdm_ch->ch, done_buffers)) {
  304. spin_unlock_irqrestore(&dim_lock, flags);
  305. return;
  306. }
  307. spin_unlock_irqrestore(&dim_lock, flags);
  308. head = &hdm_ch->started_list;
  309. while (done_buffers) {
  310. spin_lock_irqsave(&dim_lock, flags);
  311. if (list_empty(head)) {
  312. spin_unlock_irqrestore(&dim_lock, flags);
  313. pr_crit("hard error: started_mbo list is empty whereas DIM2 has sent buffers\n");
  314. break;
  315. }
  316. mbo = list_entry(head->next, struct mbo, list);
  317. list_del(head->next);
  318. spin_unlock_irqrestore(&dim_lock, flags);
  319. data = mbo->virt_address;
  320. if (hdm_ch->data_type == MOST_CH_ASYNC &&
  321. hdm_ch->direction == MOST_CH_RX &&
  322. PACKET_IS_NET_INFO(data)) {
  323. retrieve_netinfo(dev, mbo);
  324. spin_lock_irqsave(&dim_lock, flags);
  325. list_add_tail(&mbo->list, &hdm_ch->pending_list);
  326. spin_unlock_irqrestore(&dim_lock, flags);
  327. } else {
  328. if (hdm_ch->data_type == MOST_CH_CONTROL ||
  329. hdm_ch->data_type == MOST_CH_ASYNC) {
  330. u32 const data_size =
  331. (u32)data[0] * 256 + data[1] + 2;
  332. mbo->processed_length =
  333. min_t(u32, data_size,
  334. mbo->buffer_length);
  335. } else {
  336. mbo->processed_length = mbo->buffer_length;
  337. }
  338. mbo->status = MBO_SUCCESS;
  339. mbo->complete(mbo);
  340. }
  341. done_buffers--;
  342. }
  343. }
  344. static struct dim_channel **get_active_channels(struct dim2_hdm *dev,
  345. struct dim_channel **buffer)
  346. {
  347. int idx = 0;
  348. int ch_idx;
  349. for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
  350. if (dev->hch[ch_idx].is_initialized)
  351. buffer[idx++] = &dev->hch[ch_idx].ch;
  352. }
  353. buffer[idx++] = NULL;
  354. return buffer;
  355. }
  356. /**
  357. * dim2_tasklet_fn - tasklet function
  358. * @data: private data
  359. *
  360. * Service each initialized channel, if needed
  361. */
  362. static void dim2_tasklet_fn(unsigned long data)
  363. {
  364. struct dim2_hdm *dev = (struct dim2_hdm *)data;
  365. unsigned long flags;
  366. int ch_idx;
  367. for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
  368. if (!dev->hch[ch_idx].is_initialized)
  369. continue;
  370. spin_lock_irqsave(&dim_lock, flags);
  371. DIM_ServiceChannel(&dev->hch[ch_idx].ch);
  372. spin_unlock_irqrestore(&dim_lock, flags);
  373. service_done_flag(dev, ch_idx);
  374. while (!try_start_dim_transfer(dev->hch + ch_idx))
  375. continue;
  376. }
  377. }
  378. /**
  379. * dim2_ahb_isr - interrupt service routine
  380. * @irq: irq number
  381. * @_dev: private data
  382. *
  383. * Acknowledge the interrupt and schedule a tasklet to service channels.
  384. * Return IRQ_HANDLED.
  385. */
  386. static irqreturn_t dim2_ahb_isr(int irq, void *_dev)
  387. {
  388. struct dim2_hdm *dev = _dev;
  389. struct dim_channel *buffer[DMA_CHANNELS + 1];
  390. unsigned long flags;
  391. spin_lock_irqsave(&dim_lock, flags);
  392. DIM_ServiceIrq(get_active_channels(dev, buffer));
  393. spin_unlock_irqrestore(&dim_lock, flags);
  394. #if !defined(ENABLE_HDM_TEST)
  395. dim2_tasklet.data = (unsigned long)dev;
  396. tasklet_schedule(&dim2_tasklet);
  397. #else
  398. dim2_tasklet_fn((unsigned long)dev);
  399. #endif
  400. return IRQ_HANDLED;
  401. }
  402. #if defined(ENABLE_HDM_TEST)
  403. /*
  404. * Utility function used by HAL-simu for calling DIM interrupt handler.
  405. * It is used only for TEST PURPOSE.
  406. */
  407. void raise_dim_interrupt(void)
  408. {
  409. (void)dim2_ahb_isr(0, test_dev);
  410. }
  411. #endif
  412. /**
  413. * complete_all_mbos - complete MBO's in a list
  414. * @head: list head
  415. *
  416. * Delete all the entries in list and return back MBO's to mostcore using
  417. * completion call back.
  418. */
  419. static void complete_all_mbos(struct list_head *head)
  420. {
  421. unsigned long flags;
  422. struct mbo *mbo;
  423. for (;;) {
  424. spin_lock_irqsave(&dim_lock, flags);
  425. if (list_empty(head)) {
  426. spin_unlock_irqrestore(&dim_lock, flags);
  427. break;
  428. }
  429. mbo = list_entry(head->next, struct mbo, list);
  430. list_del(head->next);
  431. spin_unlock_irqrestore(&dim_lock, flags);
  432. mbo->processed_length = 0;
  433. mbo->status = MBO_E_CLOSE;
  434. mbo->complete(mbo);
  435. }
  436. }
  437. /**
  438. * configure_channel - initialize a channel
  439. * @iface: interface the channel belongs to
  440. * @channel: channel to be configured
  441. * @channel_config: structure that holds the configuration information
  442. *
  443. * Receives configuration information from mostcore and initialize
  444. * the corresponding channel. Return 0 on success, negative on failure.
  445. */
  446. static int configure_channel(struct most_interface *most_iface, int ch_idx,
  447. struct most_channel_config *ccfg)
  448. {
  449. struct dim2_hdm *dev = iface_to_hdm(most_iface);
  450. bool const is_tx = ccfg->direction == MOST_CH_TX;
  451. u16 const sub_size = ccfg->subbuffer_size;
  452. u16 const buf_size = ccfg->buffer_size;
  453. u16 new_size;
  454. unsigned long flags;
  455. u8 hal_ret;
  456. int const ch_addr = ch_idx * 2 + 2;
  457. struct hdm_channel *const hdm_ch = dev->hch + ch_idx;
  458. BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
  459. if (hdm_ch->is_initialized)
  460. return -EPERM;
  461. switch (ccfg->data_type) {
  462. case MOST_CH_CONTROL:
  463. new_size = DIM_NormCtrlAsyncBufferSize(buf_size);
  464. if (new_size == 0) {
  465. pr_err("%s: too small buffer size\n", hdm_ch->name);
  466. return -EINVAL;
  467. }
  468. ccfg->buffer_size = new_size;
  469. if (new_size != buf_size)
  470. pr_warn("%s: fixed buffer size (%d -> %d)\n",
  471. hdm_ch->name, buf_size, new_size);
  472. spin_lock_irqsave(&dim_lock, flags);
  473. hal_ret = DIM_InitControl(&hdm_ch->ch, is_tx, ch_addr,
  474. buf_size);
  475. break;
  476. case MOST_CH_ASYNC:
  477. new_size = DIM_NormCtrlAsyncBufferSize(buf_size);
  478. if (new_size == 0) {
  479. pr_err("%s: too small buffer size\n", hdm_ch->name);
  480. return -EINVAL;
  481. }
  482. ccfg->buffer_size = new_size;
  483. if (new_size != buf_size)
  484. pr_warn("%s: fixed buffer size (%d -> %d)\n",
  485. hdm_ch->name, buf_size, new_size);
  486. spin_lock_irqsave(&dim_lock, flags);
  487. hal_ret = DIM_InitAsync(&hdm_ch->ch, is_tx, ch_addr, buf_size);
  488. break;
  489. case MOST_CH_ISOC_AVP:
  490. new_size = DIM_NormIsocBufferSize(buf_size, sub_size);
  491. if (new_size == 0) {
  492. pr_err("%s: invalid sub-buffer size or too small buffer size\n",
  493. hdm_ch->name);
  494. return -EINVAL;
  495. }
  496. ccfg->buffer_size = new_size;
  497. if (new_size != buf_size)
  498. pr_warn("%s: fixed buffer size (%d -> %d)\n",
  499. hdm_ch->name, buf_size, new_size);
  500. spin_lock_irqsave(&dim_lock, flags);
  501. hal_ret = DIM_InitIsoc(&hdm_ch->ch, is_tx, ch_addr, sub_size);
  502. break;
  503. case MOST_CH_SYNC:
  504. new_size = DIM_NormSyncBufferSize(buf_size, sub_size);
  505. if (new_size == 0) {
  506. pr_err("%s: invalid sub-buffer size or too small buffer size\n",
  507. hdm_ch->name);
  508. return -EINVAL;
  509. }
  510. ccfg->buffer_size = new_size;
  511. if (new_size != buf_size)
  512. pr_warn("%s: fixed buffer size (%d -> %d)\n",
  513. hdm_ch->name, buf_size, new_size);
  514. spin_lock_irqsave(&dim_lock, flags);
  515. hal_ret = DIM_InitSync(&hdm_ch->ch, is_tx, ch_addr, sub_size);
  516. break;
  517. default:
  518. pr_err("%s: configure failed, bad channel type: %d\n",
  519. hdm_ch->name, ccfg->data_type);
  520. return -EINVAL;
  521. }
  522. if (hal_ret != DIM_NO_ERROR) {
  523. spin_unlock_irqrestore(&dim_lock, flags);
  524. pr_err("%s: configure failed (%d), type: %d, is_tx: %d\n",
  525. hdm_ch->name, hal_ret, ccfg->data_type, (int)is_tx);
  526. return -ENODEV;
  527. }
  528. hdm_ch->data_type = ccfg->data_type;
  529. hdm_ch->direction = ccfg->direction;
  530. hdm_ch->is_initialized = true;
  531. if (hdm_ch->data_type == MOST_CH_ASYNC &&
  532. hdm_ch->direction == MOST_CH_TX &&
  533. dev->atx_idx < 0)
  534. dev->atx_idx = ch_idx;
  535. spin_unlock_irqrestore(&dim_lock, flags);
  536. return 0;
  537. }
  538. /**
  539. * enqueue - enqueue a buffer for data transfer
  540. * @iface: intended interface
  541. * @channel: ID of the channel the buffer is intended for
  542. * @mbo: pointer to the buffer object
  543. *
  544. * Push the buffer into pending_list and try to transfer one buffer from
  545. * pending_list. Return 0 on success, negative on failure.
  546. */
  547. static int enqueue(struct most_interface *most_iface, int ch_idx,
  548. struct mbo *mbo)
  549. {
  550. struct dim2_hdm *dev = iface_to_hdm(most_iface);
  551. struct hdm_channel *hdm_ch = dev->hch + ch_idx;
  552. unsigned long flags;
  553. BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
  554. if (!hdm_ch->is_initialized)
  555. return -EPERM;
  556. if (mbo->bus_address == 0)
  557. return -EFAULT;
  558. spin_lock_irqsave(&dim_lock, flags);
  559. list_add_tail(&mbo->list, &hdm_ch->pending_list);
  560. spin_unlock_irqrestore(&dim_lock, flags);
  561. (void)try_start_dim_transfer(hdm_ch);
  562. return 0;
  563. }
  564. /**
  565. * request_netinfo - triggers retrieving of network info
  566. * @iface: pointer to the interface
  567. * @channel_id: corresponding channel ID
  568. *
  569. * Send a command to INIC which triggers retrieving of network info by means of
  570. * "Message exchange over MDP/MEP". Return 0 on success, negative on failure.
  571. */
  572. static void request_netinfo(struct most_interface *most_iface, int ch_idx)
  573. {
  574. struct dim2_hdm *dev = iface_to_hdm(most_iface);
  575. struct mbo *mbo;
  576. u8 *data;
  577. if (dev->atx_idx < 0) {
  578. pr_err("Async Tx Not initialized\n");
  579. return;
  580. }
  581. mbo = most_get_mbo(&dev->most_iface, dev->atx_idx, NULL);
  582. if (!mbo)
  583. return;
  584. mbo->buffer_length = 5;
  585. data = mbo->virt_address;
  586. data[0] = 0x00; /* PML High byte */
  587. data[1] = 0x03; /* PML Low byte */
  588. data[2] = 0x02; /* PMHL */
  589. data[3] = 0x08; /* FPH */
  590. data[4] = 0x40; /* FMF (FIFO cmd msg - Triggers NAOverMDP) */
  591. most_submit_mbo(mbo);
  592. }
  593. /**
  594. * poison_channel - poison buffers of a channel
  595. * @iface: pointer to the interface the channel to be poisoned belongs to
  596. * @channel_id: corresponding channel ID
  597. *
  598. * Destroy a channel and complete all the buffers in both started_list &
  599. * pending_list. Return 0 on success, negative on failure.
  600. */
  601. static int poison_channel(struct most_interface *most_iface, int ch_idx)
  602. {
  603. struct dim2_hdm *dev = iface_to_hdm(most_iface);
  604. struct hdm_channel *hdm_ch = dev->hch + ch_idx;
  605. unsigned long flags;
  606. u8 hal_ret;
  607. int ret = 0;
  608. BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
  609. if (!hdm_ch->is_initialized)
  610. return -EPERM;
  611. spin_lock_irqsave(&dim_lock, flags);
  612. hal_ret = DIM_DestroyChannel(&hdm_ch->ch);
  613. hdm_ch->is_initialized = false;
  614. if (ch_idx == dev->atx_idx)
  615. dev->atx_idx = -1;
  616. spin_unlock_irqrestore(&dim_lock, flags);
  617. if (hal_ret != DIM_NO_ERROR) {
  618. pr_err("HAL Failed to close channel %s\n", hdm_ch->name);
  619. ret = -EFAULT;
  620. }
  621. complete_all_mbos(&hdm_ch->started_list);
  622. complete_all_mbos(&hdm_ch->pending_list);
  623. return ret;
  624. }
  625. /*
  626. * dim2_probe - dim2 probe handler
  627. * @pdev: platform device structure
  628. *
  629. * Register the dim2 interface with mostcore and initialize it.
  630. * Return 0 on success, negative on failure.
  631. */
  632. static int dim2_probe(struct platform_device *pdev)
  633. {
  634. struct dim2_hdm *dev;
  635. struct resource *res;
  636. int ret, i;
  637. struct kobject *kobj;
  638. dev = kzalloc(sizeof(*dev), GFP_KERNEL);
  639. if (!dev)
  640. return -ENOMEM;
  641. dev->atx_idx = -1;
  642. platform_set_drvdata(pdev, dev);
  643. #if defined(ENABLE_HDM_TEST)
  644. test_dev = dev;
  645. #else
  646. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  647. if (!res) {
  648. pr_err("no memory region defined\n");
  649. ret = -ENOENT;
  650. goto err_free_dev;
  651. }
  652. if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
  653. pr_err("failed to request mem region\n");
  654. ret = -EBUSY;
  655. goto err_free_dev;
  656. }
  657. dev->io_base = ioremap(res->start, resource_size(res));
  658. if (!dev->io_base) {
  659. pr_err("failed to ioremap\n");
  660. ret = -ENOMEM;
  661. goto err_release_mem;
  662. }
  663. ret = platform_get_irq(pdev, 0);
  664. if (ret < 0) {
  665. pr_err("failed to get irq\n");
  666. goto err_unmap_io;
  667. }
  668. dev->irq_ahb0 = ret;
  669. ret = request_irq(dev->irq_ahb0, dim2_ahb_isr, 0, "mlb_ahb0", dev);
  670. if (ret) {
  671. pr_err("failed to request IRQ: %d, err: %d\n",
  672. dev->irq_ahb0, ret);
  673. goto err_unmap_io;
  674. }
  675. #endif
  676. init_waitqueue_head(&dev->netinfo_waitq);
  677. dev->deliver_netinfo = 0;
  678. dev->netinfo_task = kthread_run(&deliver_netinfo_thread, (void *)dev,
  679. "dim2_netinfo");
  680. if (IS_ERR(dev->netinfo_task)) {
  681. ret = PTR_ERR(dev->netinfo_task);
  682. goto err_free_irq;
  683. }
  684. for (i = 0; i < DMA_CHANNELS; i++) {
  685. struct most_channel_capability *cap = dev->capabilities + i;
  686. struct hdm_channel *hdm_ch = dev->hch + i;
  687. INIT_LIST_HEAD(&hdm_ch->pending_list);
  688. INIT_LIST_HEAD(&hdm_ch->started_list);
  689. hdm_ch->is_initialized = false;
  690. snprintf(hdm_ch->name, sizeof(hdm_ch->name), "ca%d", i * 2 + 2);
  691. cap->name_suffix = hdm_ch->name;
  692. cap->direction = MOST_CH_RX | MOST_CH_TX;
  693. cap->data_type = MOST_CH_CONTROL | MOST_CH_ASYNC |
  694. MOST_CH_ISOC_AVP | MOST_CH_SYNC;
  695. cap->num_buffers_packet = MAX_BUFFERS_PACKET;
  696. cap->buffer_size_packet = MAX_BUF_SIZE_PACKET;
  697. cap->num_buffers_streaming = MAX_BUFFERS_STREAMING;
  698. cap->buffer_size_streaming = MAX_BUF_SIZE_STREAMING;
  699. }
  700. {
  701. const char *fmt;
  702. if (sizeof(res->start) == sizeof(long long))
  703. fmt = "dim2-%016llx";
  704. else if (sizeof(res->start) == sizeof(long))
  705. fmt = "dim2-%016lx";
  706. else
  707. fmt = "dim2-%016x";
  708. snprintf(dev->name, sizeof(dev->name), fmt, res->start);
  709. }
  710. dev->most_iface.interface = ITYPE_MEDIALB_DIM2;
  711. dev->most_iface.description = dev->name;
  712. dev->most_iface.num_channels = DMA_CHANNELS;
  713. dev->most_iface.channel_vector = dev->capabilities;
  714. dev->most_iface.configure = configure_channel;
  715. dev->most_iface.enqueue = enqueue;
  716. dev->most_iface.poison_channel = poison_channel;
  717. dev->most_iface.request_netinfo = request_netinfo;
  718. kobj = most_register_interface(&dev->most_iface);
  719. if (IS_ERR(kobj)) {
  720. ret = PTR_ERR(kobj);
  721. pr_err("failed to register MOST interface\n");
  722. goto err_stop_thread;
  723. }
  724. ret = dim2_sysfs_probe(&dev->bus, kobj);
  725. if (ret)
  726. goto err_unreg_iface;
  727. ret = startup_dim(pdev);
  728. if (ret) {
  729. pr_err("failed to initialize DIM2\n");
  730. goto err_destroy_bus;
  731. }
  732. return 0;
  733. err_destroy_bus:
  734. dim2_sysfs_destroy(&dev->bus);
  735. err_unreg_iface:
  736. most_deregister_interface(&dev->most_iface);
  737. err_stop_thread:
  738. kthread_stop(dev->netinfo_task);
  739. err_free_irq:
  740. #if !defined(ENABLE_HDM_TEST)
  741. free_irq(dev->irq_ahb0, dev);
  742. err_unmap_io:
  743. iounmap(dev->io_base);
  744. err_release_mem:
  745. release_mem_region(res->start, resource_size(res));
  746. err_free_dev:
  747. #endif
  748. kfree(dev);
  749. return ret;
  750. }
  751. /**
  752. * dim2_remove - dim2 remove handler
  753. * @pdev: platform device structure
  754. *
  755. * Unregister the interface from mostcore
  756. */
  757. static int dim2_remove(struct platform_device *pdev)
  758. {
  759. struct dim2_hdm *dev = platform_get_drvdata(pdev);
  760. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  761. struct dim2_platform_data *pdata = pdev->dev.platform_data;
  762. unsigned long flags;
  763. spin_lock_irqsave(&dim_lock, flags);
  764. DIM_Shutdown();
  765. spin_unlock_irqrestore(&dim_lock, flags);
  766. if (pdata && pdata->destroy)
  767. pdata->destroy(pdata);
  768. dim2_sysfs_destroy(&dev->bus);
  769. most_deregister_interface(&dev->most_iface);
  770. kthread_stop(dev->netinfo_task);
  771. #if !defined(ENABLE_HDM_TEST)
  772. free_irq(dev->irq_ahb0, dev);
  773. iounmap(dev->io_base);
  774. release_mem_region(res->start, resource_size(res));
  775. #endif
  776. kfree(dev);
  777. platform_set_drvdata(pdev, NULL);
  778. /*
  779. * break link to local platform_device_id struct
  780. * to prevent crash by unload platform device module
  781. */
  782. pdev->id_entry = NULL;
  783. return 0;
  784. }
  785. static struct platform_device_id dim2_id[] = {
  786. { "medialb_dim2" },
  787. { }, /* Terminating entry */
  788. };
  789. MODULE_DEVICE_TABLE(platform, dim2_id);
  790. static struct platform_driver dim2_driver = {
  791. .probe = dim2_probe,
  792. .remove = dim2_remove,
  793. .id_table = dim2_id,
  794. .driver = {
  795. .name = "hdm_dim2",
  796. },
  797. };
  798. module_platform_driver(dim2_driver);
  799. MODULE_AUTHOR("Jain Roy Ambi <JainRoy.Ambi@microchip.com>");
  800. MODULE_AUTHOR("Andrey Shvetsov <andrey.shvetsov@k2l.de>");
  801. MODULE_DESCRIPTION("MediaLB DIM2 Hardware Dependent Module");
  802. MODULE_LICENSE("GPL");