nvec.c 26 KB

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  1. /*
  2. * NVEC: NVIDIA compliant embedded controller interface
  3. *
  4. * Copyright (C) 2011 The AC100 Kernel Team <ac100@lists.lauchpad.net>
  5. *
  6. * Authors: Pierre-Hugues Husson <phhusson@free.fr>
  7. * Ilya Petrov <ilya.muromec@gmail.com>
  8. * Marc Dietrich <marvin24@gmx.de>
  9. * Julian Andres Klode <jak@jak-linux.org>
  10. *
  11. * This file is subject to the terms and conditions of the GNU General Public
  12. * License. See the file "COPYING" in the main directory of this archive
  13. * for more details.
  14. *
  15. */
  16. /* #define DEBUG */
  17. #include <linux/kernel.h>
  18. #include <linux/module.h>
  19. #include <linux/atomic.h>
  20. #include <linux/clk.h>
  21. #include <linux/completion.h>
  22. #include <linux/delay.h>
  23. #include <linux/err.h>
  24. #include <linux/gpio.h>
  25. #include <linux/interrupt.h>
  26. #include <linux/io.h>
  27. #include <linux/irq.h>
  28. #include <linux/of.h>
  29. #include <linux/of_gpio.h>
  30. #include <linux/list.h>
  31. #include <linux/mfd/core.h>
  32. #include <linux/mutex.h>
  33. #include <linux/notifier.h>
  34. #include <linux/slab.h>
  35. #include <linux/spinlock.h>
  36. #include <linux/workqueue.h>
  37. #include "nvec.h"
  38. #define I2C_CNFG 0x00
  39. #define I2C_CNFG_PACKET_MODE_EN (1<<10)
  40. #define I2C_CNFG_NEW_MASTER_SFM (1<<11)
  41. #define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
  42. #define I2C_SL_CNFG 0x20
  43. #define I2C_SL_NEWSL (1<<2)
  44. #define I2C_SL_NACK (1<<1)
  45. #define I2C_SL_RESP (1<<0)
  46. #define I2C_SL_IRQ (1<<3)
  47. #define END_TRANS (1<<4)
  48. #define RCVD (1<<2)
  49. #define RNW (1<<1)
  50. #define I2C_SL_RCVD 0x24
  51. #define I2C_SL_STATUS 0x28
  52. #define I2C_SL_ADDR1 0x2c
  53. #define I2C_SL_ADDR2 0x30
  54. #define I2C_SL_DELAY_COUNT 0x3c
  55. /**
  56. * enum nvec_msg_category - Message categories for nvec_msg_alloc()
  57. * @NVEC_MSG_RX: The message is an incoming message (from EC)
  58. * @NVEC_MSG_TX: The message is an outgoing message (to EC)
  59. */
  60. enum nvec_msg_category {
  61. NVEC_MSG_RX,
  62. NVEC_MSG_TX,
  63. };
  64. enum nvec_sleep_subcmds {
  65. GLOBAL_EVENTS,
  66. AP_PWR_DOWN,
  67. AP_SUSPEND,
  68. };
  69. #define CNF_EVENT_REPORTING 0x01
  70. #define GET_FIRMWARE_VERSION 0x15
  71. #define LID_SWITCH BIT(1)
  72. #define PWR_BUTTON BIT(15)
  73. static struct nvec_chip *nvec_power_handle;
  74. static const struct mfd_cell nvec_devices[] = {
  75. {
  76. .name = "nvec-kbd",
  77. },
  78. {
  79. .name = "nvec-mouse",
  80. },
  81. {
  82. .name = "nvec-power",
  83. .id = 0,
  84. },
  85. {
  86. .name = "nvec-power",
  87. .id = 1,
  88. },
  89. {
  90. .name = "nvec-paz00",
  91. },
  92. };
  93. /**
  94. * nvec_register_notifier - Register a notifier with nvec
  95. * @nvec: A &struct nvec_chip
  96. * @nb: The notifier block to register
  97. *
  98. * Registers a notifier with @nvec. The notifier will be added to an atomic
  99. * notifier chain that is called for all received messages except those that
  100. * correspond to a request initiated by nvec_write_sync().
  101. */
  102. int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb,
  103. unsigned int events)
  104. {
  105. return atomic_notifier_chain_register(&nvec->notifier_list, nb);
  106. }
  107. EXPORT_SYMBOL_GPL(nvec_register_notifier);
  108. /**
  109. * nvec_unregister_notifier - Unregister a notifier with nvec
  110. * @nvec: A &struct nvec_chip
  111. * @nb: The notifier block to unregister
  112. *
  113. * Unregisters a notifier with @nvec. The notifier will be removed from the
  114. * atomic notifier chain.
  115. */
  116. int nvec_unregister_notifier(struct nvec_chip *nvec, struct notifier_block *nb)
  117. {
  118. return atomic_notifier_chain_unregister(&nvec->notifier_list, nb);
  119. }
  120. EXPORT_SYMBOL_GPL(nvec_unregister_notifier);
  121. /**
  122. * nvec_status_notifier - The final notifier
  123. *
  124. * Prints a message about control events not handled in the notifier
  125. * chain.
  126. */
  127. static int nvec_status_notifier(struct notifier_block *nb,
  128. unsigned long event_type, void *data)
  129. {
  130. struct nvec_chip *nvec = container_of(nb, struct nvec_chip,
  131. nvec_status_notifier);
  132. unsigned char *msg = (unsigned char *)data;
  133. if (event_type != NVEC_CNTL)
  134. return NOTIFY_DONE;
  135. dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type);
  136. print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1,
  137. msg, msg[1] + 2, true);
  138. return NOTIFY_OK;
  139. }
  140. /**
  141. * nvec_msg_alloc:
  142. * @nvec: A &struct nvec_chip
  143. * @category: Pool category, see &enum nvec_msg_category
  144. *
  145. * Allocate a single &struct nvec_msg object from the message pool of
  146. * @nvec. The result shall be passed to nvec_msg_free() if no longer
  147. * used.
  148. *
  149. * Outgoing messages are placed in the upper 75% of the pool, keeping the
  150. * lower 25% available for RX buffers only. The reason is to prevent a
  151. * situation where all buffers are full and a message is thus endlessly
  152. * retried because the response could never be processed.
  153. */
  154. static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec,
  155. enum nvec_msg_category category)
  156. {
  157. int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0;
  158. for (; i < NVEC_POOL_SIZE; i++) {
  159. if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) {
  160. dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i);
  161. return &nvec->msg_pool[i];
  162. }
  163. }
  164. dev_err(nvec->dev, "could not allocate %s buffer\n",
  165. (category == NVEC_MSG_TX) ? "TX" : "RX");
  166. return NULL;
  167. }
  168. /**
  169. * nvec_msg_free:
  170. * @nvec: A &struct nvec_chip
  171. * @msg: A message (must be allocated by nvec_msg_alloc() and belong to @nvec)
  172. *
  173. * Free the given message
  174. */
  175. void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg)
  176. {
  177. if (msg != &nvec->tx_scratch)
  178. dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool);
  179. atomic_set(&msg->used, 0);
  180. }
  181. EXPORT_SYMBOL_GPL(nvec_msg_free);
  182. /**
  183. * nvec_msg_is_event - Return %true if @msg is an event
  184. * @msg: A message
  185. */
  186. static bool nvec_msg_is_event(struct nvec_msg *msg)
  187. {
  188. return msg->data[0] >> 7;
  189. }
  190. /**
  191. * nvec_msg_size - Get the size of a message
  192. * @msg: The message to get the size for
  193. *
  194. * This only works for received messages, not for outgoing messages.
  195. */
  196. static size_t nvec_msg_size(struct nvec_msg *msg)
  197. {
  198. bool is_event = nvec_msg_is_event(msg);
  199. int event_length = (msg->data[0] & 0x60) >> 5;
  200. /* for variable size, payload size in byte 1 + count (1) + cmd (1) */
  201. if (!is_event || event_length == NVEC_VAR_SIZE)
  202. return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0;
  203. else if (event_length == NVEC_2BYTES)
  204. return 2;
  205. else if (event_length == NVEC_3BYTES)
  206. return 3;
  207. return 0;
  208. }
  209. /**
  210. * nvec_gpio_set_value - Set the GPIO value
  211. * @nvec: A &struct nvec_chip
  212. * @value: The value to write (0 or 1)
  213. *
  214. * Like gpio_set_value(), but generating debugging information
  215. */
  216. static void nvec_gpio_set_value(struct nvec_chip *nvec, int value)
  217. {
  218. dev_dbg(nvec->dev, "GPIO changed from %u to %u\n",
  219. gpio_get_value(nvec->gpio), value);
  220. gpio_set_value(nvec->gpio, value);
  221. }
  222. /**
  223. * nvec_write_async - Asynchronously write a message to NVEC
  224. * @nvec: An nvec_chip instance
  225. * @data: The message data, starting with the request type
  226. * @size: The size of @data
  227. *
  228. * Queue a single message to be transferred to the embedded controller
  229. * and return immediately.
  230. *
  231. * Returns: 0 on success, a negative error code on failure. If a failure
  232. * occurred, the nvec driver may print an error.
  233. */
  234. int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data,
  235. short size)
  236. {
  237. struct nvec_msg *msg;
  238. unsigned long flags;
  239. msg = nvec_msg_alloc(nvec, NVEC_MSG_TX);
  240. if (msg == NULL)
  241. return -ENOMEM;
  242. msg->data[0] = size;
  243. memcpy(msg->data + 1, data, size);
  244. msg->size = size + 1;
  245. spin_lock_irqsave(&nvec->tx_lock, flags);
  246. list_add_tail(&msg->node, &nvec->tx_data);
  247. spin_unlock_irqrestore(&nvec->tx_lock, flags);
  248. schedule_work(&nvec->tx_work);
  249. return 0;
  250. }
  251. EXPORT_SYMBOL(nvec_write_async);
  252. /**
  253. * nvec_write_sync - Write a message to nvec and read the response
  254. * @nvec: An &struct nvec_chip
  255. * @data: The data to write
  256. * @size: The size of @data
  257. *
  258. * This is similar to nvec_write_async(), but waits for the
  259. * request to be answered before returning. This function
  260. * uses a mutex and can thus not be called from e.g.
  261. * interrupt handlers.
  262. *
  263. * Returns: A pointer to the response message on success,
  264. * %NULL on failure. Free with nvec_msg_free() once no longer
  265. * used.
  266. */
  267. struct nvec_msg *nvec_write_sync(struct nvec_chip *nvec,
  268. const unsigned char *data, short size)
  269. {
  270. struct nvec_msg *msg;
  271. mutex_lock(&nvec->sync_write_mutex);
  272. nvec->sync_write_pending = (data[1] << 8) + data[0];
  273. if (nvec_write_async(nvec, data, size) < 0) {
  274. mutex_unlock(&nvec->sync_write_mutex);
  275. return NULL;
  276. }
  277. dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n",
  278. nvec->sync_write_pending);
  279. if (!(wait_for_completion_timeout(&nvec->sync_write,
  280. msecs_to_jiffies(2000)))) {
  281. dev_warn(nvec->dev, "timeout waiting for sync write to complete\n");
  282. mutex_unlock(&nvec->sync_write_mutex);
  283. return NULL;
  284. }
  285. dev_dbg(nvec->dev, "nvec_sync_write: pong!\n");
  286. msg = nvec->last_sync_msg;
  287. mutex_unlock(&nvec->sync_write_mutex);
  288. return msg;
  289. }
  290. EXPORT_SYMBOL(nvec_write_sync);
  291. /**
  292. * nvec_toggle_global_events - enables or disables global event reporting
  293. * @nvec: nvec handle
  294. * @state: true for enable, false for disable
  295. *
  296. * This switches on/off global event reports by the embedded controller.
  297. */
  298. static void nvec_toggle_global_events(struct nvec_chip *nvec, bool state)
  299. {
  300. unsigned char global_events[] = { NVEC_SLEEP, GLOBAL_EVENTS, state };
  301. nvec_write_async(nvec, global_events, 3);
  302. }
  303. /**
  304. * nvec_event_mask - fill the command string with event bitfield
  305. * ev: points to event command string
  306. * mask: bit to insert into the event mask
  307. *
  308. * Configure event command expects a 32 bit bitfield which describes
  309. * which events to enable. The bitfield has the following structure
  310. * (from highest byte to lowest):
  311. * system state bits 7-0
  312. * system state bits 15-8
  313. * oem system state bits 7-0
  314. * oem system state bits 15-8
  315. */
  316. static void nvec_event_mask(char *ev, u32 mask)
  317. {
  318. ev[3] = mask >> 16 & 0xff;
  319. ev[4] = mask >> 24 & 0xff;
  320. ev[5] = mask >> 0 & 0xff;
  321. ev[6] = mask >> 8 & 0xff;
  322. }
  323. /**
  324. * nvec_request_master - Process outgoing messages
  325. * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
  326. *
  327. * Processes all outgoing requests by sending the request and awaiting the
  328. * response, then continuing with the next request. Once a request has a
  329. * matching response, it will be freed and removed from the list.
  330. */
  331. static void nvec_request_master(struct work_struct *work)
  332. {
  333. struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work);
  334. unsigned long flags;
  335. long err;
  336. struct nvec_msg *msg;
  337. spin_lock_irqsave(&nvec->tx_lock, flags);
  338. while (!list_empty(&nvec->tx_data)) {
  339. msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node);
  340. spin_unlock_irqrestore(&nvec->tx_lock, flags);
  341. nvec_gpio_set_value(nvec, 0);
  342. err = wait_for_completion_interruptible_timeout(
  343. &nvec->ec_transfer, msecs_to_jiffies(5000));
  344. if (err == 0) {
  345. dev_warn(nvec->dev, "timeout waiting for ec transfer\n");
  346. nvec_gpio_set_value(nvec, 1);
  347. msg->pos = 0;
  348. }
  349. spin_lock_irqsave(&nvec->tx_lock, flags);
  350. if (err > 0) {
  351. list_del_init(&msg->node);
  352. nvec_msg_free(nvec, msg);
  353. }
  354. }
  355. spin_unlock_irqrestore(&nvec->tx_lock, flags);
  356. }
  357. /**
  358. * parse_msg - Print some information and call the notifiers on an RX message
  359. * @nvec: A &struct nvec_chip
  360. * @msg: A message received by @nvec
  361. *
  362. * Paarse some pieces of the message and then call the chain of notifiers
  363. * registered via nvec_register_notifier.
  364. */
  365. static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg)
  366. {
  367. if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) {
  368. dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data);
  369. return -EINVAL;
  370. }
  371. if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5)
  372. print_hex_dump(KERN_WARNING, "ec system event ",
  373. DUMP_PREFIX_NONE, 16, 1, msg->data,
  374. msg->data[1] + 2, true);
  375. atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f,
  376. msg->data);
  377. return 0;
  378. }
  379. /**
  380. * nvec_dispatch - Process messages received from the EC
  381. * @work: A &struct work_struct (the tx_worker member of &struct nvec_chip)
  382. *
  383. * Process messages previously received from the EC and put into the RX
  384. * queue of the &struct nvec_chip instance associated with @work.
  385. */
  386. static void nvec_dispatch(struct work_struct *work)
  387. {
  388. struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work);
  389. unsigned long flags;
  390. struct nvec_msg *msg;
  391. spin_lock_irqsave(&nvec->rx_lock, flags);
  392. while (!list_empty(&nvec->rx_data)) {
  393. msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node);
  394. list_del_init(&msg->node);
  395. spin_unlock_irqrestore(&nvec->rx_lock, flags);
  396. if (nvec->sync_write_pending ==
  397. (msg->data[2] << 8) + msg->data[0]) {
  398. dev_dbg(nvec->dev, "sync write completed!\n");
  399. nvec->sync_write_pending = 0;
  400. nvec->last_sync_msg = msg;
  401. complete(&nvec->sync_write);
  402. } else {
  403. parse_msg(nvec, msg);
  404. nvec_msg_free(nvec, msg);
  405. }
  406. spin_lock_irqsave(&nvec->rx_lock, flags);
  407. }
  408. spin_unlock_irqrestore(&nvec->rx_lock, flags);
  409. }
  410. /**
  411. * nvec_tx_completed - Complete the current transfer
  412. * @nvec: A &struct nvec_chip
  413. *
  414. * This is called when we have received an END_TRANS on a TX transfer.
  415. */
  416. static void nvec_tx_completed(struct nvec_chip *nvec)
  417. {
  418. /* We got an END_TRANS, let's skip this, maybe there's an event */
  419. if (nvec->tx->pos != nvec->tx->size) {
  420. dev_err(nvec->dev, "premature END_TRANS, resending\n");
  421. nvec->tx->pos = 0;
  422. nvec_gpio_set_value(nvec, 0);
  423. } else {
  424. nvec->state = 0;
  425. }
  426. }
  427. /**
  428. * nvec_rx_completed - Complete the current transfer
  429. * @nvec: A &struct nvec_chip
  430. *
  431. * This is called when we have received an END_TRANS on a RX transfer.
  432. */
  433. static void nvec_rx_completed(struct nvec_chip *nvec)
  434. {
  435. if (nvec->rx->pos != nvec_msg_size(nvec->rx)) {
  436. dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n",
  437. (uint) nvec_msg_size(nvec->rx),
  438. (uint) nvec->rx->pos);
  439. nvec_msg_free(nvec, nvec->rx);
  440. nvec->state = 0;
  441. /* Battery quirk - Often incomplete, and likes to crash */
  442. if (nvec->rx->data[0] == NVEC_BAT)
  443. complete(&nvec->ec_transfer);
  444. return;
  445. }
  446. spin_lock(&nvec->rx_lock);
  447. /* add the received data to the work list
  448. and move the ring buffer pointer to the next entry */
  449. list_add_tail(&nvec->rx->node, &nvec->rx_data);
  450. spin_unlock(&nvec->rx_lock);
  451. nvec->state = 0;
  452. if (!nvec_msg_is_event(nvec->rx))
  453. complete(&nvec->ec_transfer);
  454. schedule_work(&nvec->rx_work);
  455. }
  456. /**
  457. * nvec_invalid_flags - Send an error message about invalid flags and jump
  458. * @nvec: The nvec device
  459. * @status: The status flags
  460. * @reset: Whether we shall jump to state 0.
  461. */
  462. static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status,
  463. bool reset)
  464. {
  465. dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n",
  466. status, nvec->state);
  467. if (reset)
  468. nvec->state = 0;
  469. }
  470. /**
  471. * nvec_tx_set - Set the message to transfer (nvec->tx)
  472. * @nvec: A &struct nvec_chip
  473. *
  474. * Gets the first entry from the tx_data list of @nvec and sets the
  475. * tx member to it. If the tx_data list is empty, this uses the
  476. * tx_scratch message to send a no operation message.
  477. */
  478. static void nvec_tx_set(struct nvec_chip *nvec)
  479. {
  480. spin_lock(&nvec->tx_lock);
  481. if (list_empty(&nvec->tx_data)) {
  482. dev_err(nvec->dev, "empty tx - sending no-op\n");
  483. memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3);
  484. nvec->tx_scratch.size = 3;
  485. nvec->tx_scratch.pos = 0;
  486. nvec->tx = &nvec->tx_scratch;
  487. list_add_tail(&nvec->tx->node, &nvec->tx_data);
  488. } else {
  489. nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg,
  490. node);
  491. nvec->tx->pos = 0;
  492. }
  493. spin_unlock(&nvec->tx_lock);
  494. dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n",
  495. (uint)nvec->tx->size, nvec->tx->data[1]);
  496. }
  497. /**
  498. * nvec_interrupt - Interrupt handler
  499. * @irq: The IRQ
  500. * @dev: The nvec device
  501. *
  502. * Interrupt handler that fills our RX buffers and empties our TX
  503. * buffers. This uses a finite state machine with ridiculous amounts
  504. * of error checking, in order to be fairly reliable.
  505. */
  506. static irqreturn_t nvec_interrupt(int irq, void *dev)
  507. {
  508. unsigned long status;
  509. unsigned int received = 0;
  510. unsigned char to_send = 0xff;
  511. const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW;
  512. struct nvec_chip *nvec = dev;
  513. unsigned int state = nvec->state;
  514. status = readl(nvec->base + I2C_SL_STATUS);
  515. /* Filter out some errors */
  516. if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) {
  517. dev_err(nvec->dev, "unexpected irq mask %lx\n", status);
  518. return IRQ_HANDLED;
  519. }
  520. if ((status & I2C_SL_IRQ) == 0) {
  521. dev_err(nvec->dev, "Spurious IRQ\n");
  522. return IRQ_HANDLED;
  523. }
  524. /* The EC did not request a read, so it send us something, read it */
  525. if ((status & RNW) == 0) {
  526. received = readl(nvec->base + I2C_SL_RCVD);
  527. if (status & RCVD)
  528. writel(0, nvec->base + I2C_SL_RCVD);
  529. }
  530. if (status == (I2C_SL_IRQ | RCVD))
  531. nvec->state = 0;
  532. switch (nvec->state) {
  533. case 0: /* Verify that its a transfer start, the rest later */
  534. if (status != (I2C_SL_IRQ | RCVD))
  535. nvec_invalid_flags(nvec, status, false);
  536. break;
  537. case 1: /* command byte */
  538. if (status != I2C_SL_IRQ) {
  539. nvec_invalid_flags(nvec, status, true);
  540. } else {
  541. nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX);
  542. /* Should not happen in a normal world */
  543. if (unlikely(nvec->rx == NULL)) {
  544. nvec->state = 0;
  545. break;
  546. }
  547. nvec->rx->data[0] = received;
  548. nvec->rx->pos = 1;
  549. nvec->state = 2;
  550. }
  551. break;
  552. case 2: /* first byte after command */
  553. if (status == (I2C_SL_IRQ | RNW | RCVD)) {
  554. udelay(33);
  555. if (nvec->rx->data[0] != 0x01) {
  556. dev_err(nvec->dev,
  557. "Read without prior read command\n");
  558. nvec->state = 0;
  559. break;
  560. }
  561. nvec_msg_free(nvec, nvec->rx);
  562. nvec->state = 3;
  563. nvec_tx_set(nvec);
  564. BUG_ON(nvec->tx->size < 1);
  565. to_send = nvec->tx->data[0];
  566. nvec->tx->pos = 1;
  567. } else if (status == (I2C_SL_IRQ)) {
  568. BUG_ON(nvec->rx == NULL);
  569. nvec->rx->data[1] = received;
  570. nvec->rx->pos = 2;
  571. nvec->state = 4;
  572. } else {
  573. nvec_invalid_flags(nvec, status, true);
  574. }
  575. break;
  576. case 3: /* EC does a block read, we transmit data */
  577. if (status & END_TRANS) {
  578. nvec_tx_completed(nvec);
  579. } else if ((status & RNW) == 0 || (status & RCVD)) {
  580. nvec_invalid_flags(nvec, status, true);
  581. } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) {
  582. to_send = nvec->tx->data[nvec->tx->pos++];
  583. } else {
  584. dev_err(nvec->dev, "tx buffer underflow on %p (%u > %u)\n",
  585. nvec->tx,
  586. (uint) (nvec->tx ? nvec->tx->pos : 0),
  587. (uint) (nvec->tx ? nvec->tx->size : 0));
  588. nvec->state = 0;
  589. }
  590. break;
  591. case 4: /* EC does some write, we read the data */
  592. if ((status & (END_TRANS | RNW)) == END_TRANS)
  593. nvec_rx_completed(nvec);
  594. else if (status & (RNW | RCVD))
  595. nvec_invalid_flags(nvec, status, true);
  596. else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE)
  597. nvec->rx->data[nvec->rx->pos++] = received;
  598. else
  599. dev_err(nvec->dev,
  600. "RX buffer overflow on %p: Trying to write byte %u of %u\n",
  601. nvec->rx, nvec->rx ? nvec->rx->pos : 0,
  602. NVEC_MSG_SIZE);
  603. break;
  604. default:
  605. nvec->state = 0;
  606. }
  607. /* If we are told that a new transfer starts, verify it */
  608. if ((status & (RCVD | RNW)) == RCVD) {
  609. if (received != nvec->i2c_addr)
  610. dev_err(nvec->dev,
  611. "received address 0x%02x, expected 0x%02x\n",
  612. received, nvec->i2c_addr);
  613. nvec->state = 1;
  614. }
  615. /* Send data if requested, but not on end of transmission */
  616. if ((status & (RNW | END_TRANS)) == RNW)
  617. writel(to_send, nvec->base + I2C_SL_RCVD);
  618. /* If we have send the first byte */
  619. if (status == (I2C_SL_IRQ | RNW | RCVD))
  620. nvec_gpio_set_value(nvec, 1);
  621. dev_dbg(nvec->dev,
  622. "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n",
  623. (status & RNW) == 0 ? "received" : "R=",
  624. received,
  625. (status & (RNW | END_TRANS)) ? "sent" : "S=",
  626. to_send,
  627. state,
  628. status & END_TRANS ? " END_TRANS" : "",
  629. status & RCVD ? " RCVD" : "",
  630. status & RNW ? " RNW" : "");
  631. /*
  632. * TODO: A correct fix needs to be found for this.
  633. *
  634. * We experience less incomplete messages with this delay than without
  635. * it, but we don't know why. Help is appreciated.
  636. */
  637. udelay(100);
  638. return IRQ_HANDLED;
  639. }
  640. static void tegra_init_i2c_slave(struct nvec_chip *nvec)
  641. {
  642. u32 val;
  643. clk_prepare_enable(nvec->i2c_clk);
  644. reset_control_assert(nvec->rst);
  645. udelay(2);
  646. reset_control_deassert(nvec->rst);
  647. val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
  648. (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
  649. writel(val, nvec->base + I2C_CNFG);
  650. clk_set_rate(nvec->i2c_clk, 8 * 80000);
  651. writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG);
  652. writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT);
  653. writel(nvec->i2c_addr>>1, nvec->base + I2C_SL_ADDR1);
  654. writel(0, nvec->base + I2C_SL_ADDR2);
  655. enable_irq(nvec->irq);
  656. }
  657. #ifdef CONFIG_PM_SLEEP
  658. static void nvec_disable_i2c_slave(struct nvec_chip *nvec)
  659. {
  660. disable_irq(nvec->irq);
  661. writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
  662. clk_disable_unprepare(nvec->i2c_clk);
  663. }
  664. #endif
  665. static void nvec_power_off(void)
  666. {
  667. char ap_pwr_down[] = { NVEC_SLEEP, AP_PWR_DOWN };
  668. nvec_toggle_global_events(nvec_power_handle, false);
  669. nvec_write_async(nvec_power_handle, ap_pwr_down, 2);
  670. }
  671. /*
  672. * Parse common device tree data
  673. */
  674. static int nvec_i2c_parse_dt_pdata(struct nvec_chip *nvec)
  675. {
  676. nvec->gpio = of_get_named_gpio(nvec->dev->of_node, "request-gpios", 0);
  677. if (nvec->gpio < 0) {
  678. dev_err(nvec->dev, "no gpio specified");
  679. return -ENODEV;
  680. }
  681. if (of_property_read_u32(nvec->dev->of_node, "slave-addr",
  682. &nvec->i2c_addr)) {
  683. dev_err(nvec->dev, "no i2c address specified");
  684. return -ENODEV;
  685. }
  686. return 0;
  687. }
  688. static int tegra_nvec_probe(struct platform_device *pdev)
  689. {
  690. int err, ret;
  691. struct clk *i2c_clk;
  692. struct nvec_chip *nvec;
  693. struct nvec_msg *msg;
  694. struct resource *res;
  695. void __iomem *base;
  696. char get_firmware_version[] = { NVEC_CNTL, GET_FIRMWARE_VERSION },
  697. unmute_speakers[] = { NVEC_OEM0, 0x10, 0x59, 0x95 },
  698. enable_event[7] = { NVEC_SYS, CNF_EVENT_REPORTING, true };
  699. if (!pdev->dev.of_node) {
  700. dev_err(&pdev->dev, "must be instantiated using device tree\n");
  701. return -ENODEV;
  702. }
  703. nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL);
  704. if (!nvec)
  705. return -ENOMEM;
  706. platform_set_drvdata(pdev, nvec);
  707. nvec->dev = &pdev->dev;
  708. err = nvec_i2c_parse_dt_pdata(nvec);
  709. if (err < 0)
  710. return err;
  711. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  712. base = devm_ioremap_resource(&pdev->dev, res);
  713. if (IS_ERR(base))
  714. return PTR_ERR(base);
  715. nvec->irq = platform_get_irq(pdev, 0);
  716. if (nvec->irq < 0) {
  717. dev_err(&pdev->dev, "no irq resource?\n");
  718. return -ENODEV;
  719. }
  720. i2c_clk = devm_clk_get(&pdev->dev, "div-clk");
  721. if (IS_ERR(i2c_clk)) {
  722. dev_err(nvec->dev, "failed to get controller clock\n");
  723. return -ENODEV;
  724. }
  725. nvec->rst = devm_reset_control_get(&pdev->dev, "i2c");
  726. if (IS_ERR(nvec->rst)) {
  727. dev_err(nvec->dev, "failed to get controller reset\n");
  728. return PTR_ERR(nvec->rst);
  729. }
  730. nvec->base = base;
  731. nvec->i2c_clk = i2c_clk;
  732. nvec->rx = &nvec->msg_pool[0];
  733. ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list);
  734. init_completion(&nvec->sync_write);
  735. init_completion(&nvec->ec_transfer);
  736. mutex_init(&nvec->sync_write_mutex);
  737. spin_lock_init(&nvec->tx_lock);
  738. spin_lock_init(&nvec->rx_lock);
  739. INIT_LIST_HEAD(&nvec->rx_data);
  740. INIT_LIST_HEAD(&nvec->tx_data);
  741. INIT_WORK(&nvec->rx_work, nvec_dispatch);
  742. INIT_WORK(&nvec->tx_work, nvec_request_master);
  743. err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH,
  744. "nvec gpio");
  745. if (err < 0) {
  746. dev_err(nvec->dev, "couldn't request gpio\n");
  747. return -ENODEV;
  748. }
  749. err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0,
  750. "nvec", nvec);
  751. if (err) {
  752. dev_err(nvec->dev, "couldn't request irq\n");
  753. return -ENODEV;
  754. }
  755. disable_irq(nvec->irq);
  756. tegra_init_i2c_slave(nvec);
  757. /* enable event reporting */
  758. nvec_toggle_global_events(nvec, true);
  759. nvec->nvec_status_notifier.notifier_call = nvec_status_notifier;
  760. nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0);
  761. nvec_power_handle = nvec;
  762. pm_power_off = nvec_power_off;
  763. /* Get Firmware Version */
  764. msg = nvec_write_sync(nvec, get_firmware_version, 2);
  765. if (msg) {
  766. dev_warn(nvec->dev, "ec firmware version %02x.%02x.%02x / %02x\n",
  767. msg->data[4], msg->data[5], msg->data[6], msg->data[7]);
  768. nvec_msg_free(nvec, msg);
  769. }
  770. ret = mfd_add_devices(nvec->dev, 0, nvec_devices,
  771. ARRAY_SIZE(nvec_devices), NULL, 0, NULL);
  772. if (ret)
  773. dev_err(nvec->dev, "error adding subdevices\n");
  774. /* unmute speakers? */
  775. nvec_write_async(nvec, unmute_speakers, 4);
  776. /* enable lid switch event */
  777. nvec_event_mask(enable_event, LID_SWITCH);
  778. nvec_write_async(nvec, enable_event, 7);
  779. /* enable power button event */
  780. nvec_event_mask(enable_event, PWR_BUTTON);
  781. nvec_write_async(nvec, enable_event, 7);
  782. return 0;
  783. }
  784. static int tegra_nvec_remove(struct platform_device *pdev)
  785. {
  786. struct nvec_chip *nvec = platform_get_drvdata(pdev);
  787. nvec_toggle_global_events(nvec, false);
  788. mfd_remove_devices(nvec->dev);
  789. nvec_unregister_notifier(nvec, &nvec->nvec_status_notifier);
  790. cancel_work_sync(&nvec->rx_work);
  791. cancel_work_sync(&nvec->tx_work);
  792. /* FIXME: needs check whether nvec is responsible for power off */
  793. pm_power_off = NULL;
  794. return 0;
  795. }
  796. #ifdef CONFIG_PM_SLEEP
  797. static int nvec_suspend(struct device *dev)
  798. {
  799. struct platform_device *pdev = to_platform_device(dev);
  800. struct nvec_chip *nvec = platform_get_drvdata(pdev);
  801. struct nvec_msg *msg;
  802. char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND };
  803. dev_dbg(nvec->dev, "suspending\n");
  804. /* keep these sync or you'll break suspend */
  805. nvec_toggle_global_events(nvec, false);
  806. msg = nvec_write_sync(nvec, ap_suspend, sizeof(ap_suspend));
  807. nvec_msg_free(nvec, msg);
  808. nvec_disable_i2c_slave(nvec);
  809. return 0;
  810. }
  811. static int nvec_resume(struct device *dev)
  812. {
  813. struct platform_device *pdev = to_platform_device(dev);
  814. struct nvec_chip *nvec = platform_get_drvdata(pdev);
  815. dev_dbg(nvec->dev, "resuming\n");
  816. tegra_init_i2c_slave(nvec);
  817. nvec_toggle_global_events(nvec, true);
  818. return 0;
  819. }
  820. #endif
  821. static SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume);
  822. /* Match table for of_platform binding */
  823. static const struct of_device_id nvidia_nvec_of_match[] = {
  824. { .compatible = "nvidia,nvec", },
  825. {},
  826. };
  827. MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match);
  828. static struct platform_driver nvec_device_driver = {
  829. .probe = tegra_nvec_probe,
  830. .remove = tegra_nvec_remove,
  831. .driver = {
  832. .name = "nvec",
  833. .pm = &nvec_pm_ops,
  834. .of_match_table = nvidia_nvec_of_match,
  835. }
  836. };
  837. module_platform_driver(nvec_device_driver);
  838. MODULE_ALIAS("platform:nvec");
  839. MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface");
  840. MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>");
  841. MODULE_LICENSE("GPL");