r819xU_cmdpkt.h 4.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191
  1. #ifndef R819XUSB_CMDPKT_H
  2. #define R819XUSB_CMDPKT_H
  3. /* Different command packet have dedicated message length and definition. */
  4. #define CMPK_RX_TX_FB_SIZE sizeof(cmpk_txfb_t) /* 20 */
  5. #define CMPK_TX_SET_CONFIG_SIZE sizeof(cmpk_set_cfg_t) /* 16 */
  6. #define CMPK_BOTH_QUERY_CONFIG_SIZE sizeof(cmpk_set_cfg_t) /* 16 */
  7. #define CMPK_RX_TX_STS_SIZE sizeof(cmpk_tx_status_t)
  8. #define CMPK_RX_DBG_MSG_SIZE sizeof(cmpk_rx_dbginfo_t)
  9. #define CMPK_TX_RAHIS_SIZE sizeof(cmpk_tx_rahis_t)
  10. /* 2008/05/08 amy For USB constant. */
  11. #define ISR_TxBcnOk BIT(27) /* Transmit Beacon OK */
  12. #define ISR_TxBcnErr BIT(26) /* Transmit Beacon Error */
  13. #define ISR_BcnTimerIntr BIT(13) /* Beacon Timer Interrupt */
  14. /* Define element ID of command packet. */
  15. /*------------------------------Define structure----------------------------*/
  16. /* Define different command packet structure. */
  17. /* 1. RX side: TX feedback packet. */
  18. typedef struct tag_cmd_pkt_tx_feedback {
  19. /* DWORD 0 */
  20. u8 element_id; /* Command packet type. */
  21. u8 length; /* Command packet length. */
  22. /* Change tx feedback info field. */
  23. /*------TX Feedback Info Field */
  24. u8 TID:4;
  25. u8 fail_reason:3;
  26. u8 tok:1; /* Transmit ok. */
  27. u8 reserve1:4;
  28. u8 pkt_type:2;
  29. u8 bandwidth:1;
  30. u8 qos_pkt:1;
  31. /* DWORD 1 */
  32. u8 reserve2;
  33. /*------TX Feedback Info Field */
  34. u8 retry_cnt;
  35. u16 pkt_id;
  36. /* DWORD 3 */
  37. u16 seq_num;
  38. u8 s_rate; /* Start rate. */
  39. u8 f_rate; /* Final rate. */
  40. /* DWORD 4 */
  41. u8 s_rts_rate;
  42. u8 f_rts_rate;
  43. u16 pkt_length;
  44. /* DWORD 5 */
  45. u16 reserve3;
  46. u16 duration;
  47. } cmpk_txfb_t;
  48. /* 2. RX side: Interrupt status packet. It includes Beacon State,
  49. * Beacon Timer Interrupt and other useful informations in MAC ISR Reg. */
  50. typedef struct tag_cmd_pkt_interrupt_status {
  51. u8 element_id; /* Command packet type. */
  52. u8 length; /* Command packet length. */
  53. u16 reserve;
  54. u32 interrupt_status; /* Interrupt Status. */
  55. } cmpk_intr_sta_t;
  56. /* 3. TX side: Set configuration packet. */
  57. typedef struct tag_cmd_pkt_set_configuration {
  58. u8 element_id; /* Command packet type. */
  59. u8 length; /* Command packet length. */
  60. u16 reserve1;
  61. /* Configuration info. */
  62. u8 cfg_reserve1:3;
  63. u8 cfg_size:2;
  64. u8 cfg_type:2;
  65. u8 cfg_action:1;
  66. u8 cfg_reserve2;
  67. u8 cfg_page:4;
  68. u8 cfg_reserve3:4;
  69. u8 cfg_offset;
  70. u32 value;
  71. u32 mask;
  72. } cmpk_set_cfg_t;
  73. /* 4. Both side : TX/RX query configuraton packet. The query structure is the
  74. same as set configuration. */
  75. #define cmpk_query_cfg_t cmpk_set_cfg_t
  76. /* 5. Multi packet feedback status. */
  77. typedef struct tag_tx_stats_feedback {
  78. /* For endian transfer --> Driver will not the same as
  79. firmware structure. */
  80. /* DW 0 */
  81. u16 reserve1;
  82. u8 length; /* Command packet length */
  83. u8 element_id; /* Command packet type */
  84. /* DW 1 */
  85. u16 txfail; /* Tx fail count */
  86. u16 txok; /* Tx ok count */
  87. /* DW 2 */
  88. u16 txmcok; /* Tx multicast */
  89. u16 txretry; /* Tx retry count */
  90. /* DW 3 */
  91. u16 txucok; /* Tx unicast */
  92. u16 txbcok; /* Tx broadcast */
  93. /* DW 4 */
  94. u16 txbcfail;
  95. u16 txmcfail;
  96. /* DW 5 */
  97. u16 reserve2;
  98. u16 txucfail;
  99. /* DW 6-8 */
  100. u32 txmclength;
  101. u32 txbclength;
  102. u32 txuclength;
  103. /* DW 9 */
  104. u16 reserve3_23;
  105. u8 reserve3_1;
  106. u8 rate;
  107. } __packed cmpk_tx_status_t;
  108. /* 6. Debug feedback message. */
  109. /* Define RX debug message */
  110. typedef struct tag_rx_debug_message_feedback {
  111. /* For endian transfer --> for driver */
  112. /* DW 0 */
  113. u16 reserve1;
  114. u8 length; /* Command packet length */
  115. u8 element_id; /* Command packet type */
  116. /* DW 1-?? */
  117. /* Variable debug message. */
  118. } cmpk_rx_dbginfo_t;
  119. /* Define transmit rate history. For big endian format. */
  120. typedef struct tag_tx_rate_history {
  121. /* For endian transfer --> for driver */
  122. /* DW 0 */
  123. u8 element_id; /* Command packet type */
  124. u8 length; /* Command packet length */
  125. u16 reserved1;
  126. /* DW 1-2 CCK rate counter */
  127. u16 cck[4];
  128. /* DW 3-6 */
  129. u16 ofdm[8];
  130. /* DW 7-14 BW=0 SG=0
  131. * DW 15-22 BW=1 SG=0
  132. * DW 23-30 BW=0 SG=1
  133. * DW 31-38 BW=1 SG=1
  134. */
  135. u16 ht_mcs[4][16];
  136. } __packed cmpk_tx_rahis_t;
  137. typedef enum tag_command_packet_directories {
  138. RX_TX_FEEDBACK = 0,
  139. RX_INTERRUPT_STATUS = 1,
  140. TX_SET_CONFIG = 2,
  141. BOTH_QUERY_CONFIG = 3,
  142. RX_TX_STATUS = 4,
  143. RX_DBGINFO_FEEDBACK = 5,
  144. RX_TX_PER_PKT_FEEDBACK = 6,
  145. RX_TX_RATE_HISTORY = 7,
  146. RX_CMD_ELE_MAX
  147. } cmpk_element_e;
  148. typedef enum _rt_status {
  149. RT_STATUS_SUCCESS,
  150. RT_STATUS_FAILURE,
  151. RT_STATUS_PENDING,
  152. RT_STATUS_RESOURCE
  153. } rt_status, *prt_status;
  154. u32 cmpk_message_handle_rx(struct net_device *dev,
  155. struct ieee80211_rx_stats *pstats);
  156. rt_status SendTxCommandPacket(struct net_device *dev,
  157. void *pData, u32 DataLen);
  158. #endif