r819xU_phy.h 3.1 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091
  1. #ifndef _R819XU_PHY_H
  2. #define _R819XU_PHY_H
  3. /* Channel switch: The size of command tables for switch channel */
  4. #define MAX_PRECMD_CNT 16
  5. #define MAX_RFDEPENDCMD_CNT 16
  6. #define MAX_POSTCMD_CNT 16
  7. typedef enum _SwChnlCmdID {
  8. CmdID_End,
  9. CmdID_SetTxPowerLevel,
  10. CmdID_BBRegWrite10,
  11. CmdID_WritePortUlong,
  12. CmdID_WritePortUshort,
  13. CmdID_WritePortUchar,
  14. CmdID_RF_WriteReg,
  15. } SwChnlCmdID;
  16. /* -----------------------Define structure---------------------- */
  17. /* 1. Switch channel related */
  18. typedef struct _SwChnlCmd {
  19. SwChnlCmdID CmdID;
  20. u32 Para1;
  21. u32 Para2;
  22. u32 msDelay;
  23. } __packed SwChnlCmd;
  24. extern u32 rtl819XMACPHY_Array_PG[];
  25. extern u32 rtl819XPHY_REG_1T2RArray[];
  26. extern u32 rtl819XAGCTAB_Array[];
  27. extern u32 rtl819XRadioA_Array[];
  28. extern u32 rtl819XRadioB_Array[];
  29. extern u32 rtl819XRadioC_Array[];
  30. extern u32 rtl819XRadioD_Array[];
  31. typedef enum _HW90_BLOCK {
  32. HW90_BLOCK_MAC = 0,
  33. HW90_BLOCK_PHY0 = 1,
  34. HW90_BLOCK_PHY1 = 2,
  35. HW90_BLOCK_RF = 3,
  36. HW90_BLOCK_MAXIMUM = 4, /* Never use this */
  37. } HW90_BLOCK_E, *PHW90_BLOCK_E;
  38. typedef enum _RF90_RADIO_PATH {
  39. RF90_PATH_A = 0, /* Radio Path A */
  40. RF90_PATH_B = 1, /* Radio Path B */
  41. RF90_PATH_C = 2, /* Radio Path C */
  42. RF90_PATH_D = 3, /* Radio Path D */
  43. RF90_PATH_MAX /* Max RF number 92 support */
  44. } RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
  45. #define bMaskByte0 0xff
  46. #define bMaskByte1 0xff00
  47. #define bMaskByte2 0xff0000
  48. #define bMaskByte3 0xff000000
  49. #define bMaskHWord 0xffff0000
  50. #define bMaskLWord 0x0000ffff
  51. #define bMaskDWord 0xffffffff
  52. u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath);
  53. void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr,
  54. u32 bitmask, u32 data);
  55. u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask);
  56. void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
  57. u32 reg_addr, u32 bitmask, u32 data);
  58. u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
  59. u32 reg_addr, u32 bitmask);
  60. void rtl8192_phy_configmac(struct net_device *dev);
  61. void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType);
  62. u8 rtl8192_phy_checkBBAndRF(struct net_device *dev,
  63. HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
  64. void rtl8192_BBConfig(struct net_device *dev);
  65. void rtl8192_phy_getTxPower(struct net_device *dev);
  66. void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel);
  67. void rtl8192_phy_RFConfig(struct net_device *dev);
  68. void rtl8192_phy_updateInitGain(struct net_device *dev);
  69. u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
  70. RF90_RADIO_PATH_E eRFPath);
  71. u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel);
  72. void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
  73. HT_EXTCHNL_OFFSET offset);
  74. void rtl8192_SwChnl_WorkItem(struct net_device *dev);
  75. void rtl8192_SetBWModeWorkItem(struct net_device *dev);
  76. bool rtl8192_SetRFPowerState(struct net_device *dev,
  77. RT_RF_POWER_STATE eRFPowerState);
  78. void InitialGain819xUsb(struct net_device *dev, u8 Operation);
  79. void InitialGainOperateWorkItemCallBack(struct work_struct *work);
  80. #endif