rockchip_thermal.c 21 KB

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  1. /*
  2. * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
  3. *
  4. * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
  5. * Caesar Wang <wxt@rock-chips.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms and conditions of the GNU General Public License,
  9. * version 2, as published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. */
  16. #include <linux/clk.h>
  17. #include <linux/delay.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/reset.h>
  26. #include <linux/thermal.h>
  27. #include <linux/pinctrl/consumer.h>
  28. /**
  29. * If the temperature over a period of time High,
  30. * the resulting TSHUT gave CRU module,let it reset the entire chip,
  31. * or via GPIO give PMIC.
  32. */
  33. enum tshut_mode {
  34. TSHUT_MODE_CRU = 0,
  35. TSHUT_MODE_GPIO,
  36. };
  37. /**
  38. * the system Temperature Sensors tshut(tshut) polarity
  39. * the bit 8 is tshut polarity.
  40. * 0: low active, 1: high active
  41. */
  42. enum tshut_polarity {
  43. TSHUT_LOW_ACTIVE = 0,
  44. TSHUT_HIGH_ACTIVE,
  45. };
  46. /**
  47. * The system has two Temperature Sensors.
  48. * sensor0 is for CPU, and sensor1 is for GPU.
  49. */
  50. enum sensor_id {
  51. SENSOR_CPU = 0,
  52. SENSOR_GPU,
  53. };
  54. /**
  55. * The conversion table has the adc value and temperature.
  56. * ADC_DECREMENT is the adc value decremnet.(e.g. v2_code_table)
  57. * ADC_INCREMNET is the adc value incremnet.(e.g. v3_code_table)
  58. */
  59. enum adc_sort_mode {
  60. ADC_DECREMENT = 0,
  61. ADC_INCREMENT,
  62. };
  63. /**
  64. * The max sensors is two in rockchip SoCs.
  65. * Two sensors: CPU and GPU sensor.
  66. */
  67. #define SOC_MAX_SENSORS 2
  68. struct chip_tsadc_table {
  69. const struct tsadc_table *id;
  70. /* the array table size*/
  71. unsigned int length;
  72. /* that analogic mask data */
  73. u32 data_mask;
  74. /* the sort mode is adc value that increment or decrement in table */
  75. enum adc_sort_mode mode;
  76. };
  77. struct rockchip_tsadc_chip {
  78. /* The sensor id of chip correspond to the ADC channel */
  79. int chn_id[SOC_MAX_SENSORS];
  80. int chn_num;
  81. /* The hardware-controlled tshut property */
  82. int tshut_temp;
  83. enum tshut_mode tshut_mode;
  84. enum tshut_polarity tshut_polarity;
  85. /* Chip-wide methods */
  86. void (*initialize)(void __iomem *reg, enum tshut_polarity p);
  87. void (*irq_ack)(void __iomem *reg);
  88. void (*control)(void __iomem *reg, bool on);
  89. /* Per-sensor methods */
  90. int (*get_temp)(struct chip_tsadc_table table,
  91. int chn, void __iomem *reg, int *temp);
  92. void (*set_tshut_temp)(struct chip_tsadc_table table,
  93. int chn, void __iomem *reg, int temp);
  94. void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
  95. /* Per-table methods */
  96. struct chip_tsadc_table table;
  97. };
  98. struct rockchip_thermal_sensor {
  99. struct rockchip_thermal_data *thermal;
  100. struct thermal_zone_device *tzd;
  101. int id;
  102. };
  103. struct rockchip_thermal_data {
  104. const struct rockchip_tsadc_chip *chip;
  105. struct platform_device *pdev;
  106. struct reset_control *reset;
  107. struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
  108. struct clk *clk;
  109. struct clk *pclk;
  110. void __iomem *regs;
  111. int tshut_temp;
  112. enum tshut_mode tshut_mode;
  113. enum tshut_polarity tshut_polarity;
  114. };
  115. /* TSADC Sensor info define: */
  116. #define TSADCV2_AUTO_CON 0x04
  117. #define TSADCV2_INT_EN 0x08
  118. #define TSADCV2_INT_PD 0x0c
  119. #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
  120. #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
  121. #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
  122. #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
  123. #define TSADCV2_AUTO_PERIOD 0x68
  124. #define TSADCV2_AUTO_PERIOD_HT 0x6c
  125. #define TSADCV2_AUTO_EN BIT(0)
  126. #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
  127. #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
  128. #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
  129. #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
  130. #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
  131. #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
  132. #define TSADCV2_DATA_MASK 0xfff
  133. #define TSADCV3_DATA_MASK 0x3ff
  134. #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
  135. #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
  136. #define TSADCV2_AUTO_PERIOD_TIME 250 /* msec */
  137. #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* msec */
  138. struct tsadc_table {
  139. u32 code;
  140. int temp;
  141. };
  142. static const struct tsadc_table v2_code_table[] = {
  143. {TSADCV2_DATA_MASK, -40000},
  144. {3800, -40000},
  145. {3792, -35000},
  146. {3783, -30000},
  147. {3774, -25000},
  148. {3765, -20000},
  149. {3756, -15000},
  150. {3747, -10000},
  151. {3737, -5000},
  152. {3728, 0},
  153. {3718, 5000},
  154. {3708, 10000},
  155. {3698, 15000},
  156. {3688, 20000},
  157. {3678, 25000},
  158. {3667, 30000},
  159. {3656, 35000},
  160. {3645, 40000},
  161. {3634, 45000},
  162. {3623, 50000},
  163. {3611, 55000},
  164. {3600, 60000},
  165. {3588, 65000},
  166. {3575, 70000},
  167. {3563, 75000},
  168. {3550, 80000},
  169. {3537, 85000},
  170. {3524, 90000},
  171. {3510, 95000},
  172. {3496, 100000},
  173. {3482, 105000},
  174. {3467, 110000},
  175. {3452, 115000},
  176. {3437, 120000},
  177. {3421, 125000},
  178. };
  179. static const struct tsadc_table v3_code_table[] = {
  180. {0, -40000},
  181. {106, -40000},
  182. {108, -35000},
  183. {110, -30000},
  184. {112, -25000},
  185. {114, -20000},
  186. {116, -15000},
  187. {118, -10000},
  188. {120, -5000},
  189. {122, 0},
  190. {124, 5000},
  191. {126, 10000},
  192. {128, 15000},
  193. {130, 20000},
  194. {132, 25000},
  195. {134, 30000},
  196. {136, 35000},
  197. {138, 40000},
  198. {140, 45000},
  199. {142, 50000},
  200. {144, 55000},
  201. {146, 60000},
  202. {148, 65000},
  203. {150, 70000},
  204. {152, 75000},
  205. {154, 80000},
  206. {156, 85000},
  207. {158, 90000},
  208. {160, 95000},
  209. {162, 100000},
  210. {163, 105000},
  211. {165, 110000},
  212. {167, 115000},
  213. {169, 120000},
  214. {171, 125000},
  215. {TSADCV3_DATA_MASK, 125000},
  216. };
  217. static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table,
  218. int temp)
  219. {
  220. int high, low, mid;
  221. low = 0;
  222. high = table.length - 1;
  223. mid = (high + low) / 2;
  224. if (temp < table.id[low].temp || temp > table.id[high].temp)
  225. return 0;
  226. while (low <= high) {
  227. if (temp == table.id[mid].temp)
  228. return table.id[mid].code;
  229. else if (temp < table.id[mid].temp)
  230. high = mid - 1;
  231. else
  232. low = mid + 1;
  233. mid = (low + high) / 2;
  234. }
  235. return 0;
  236. }
  237. static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code,
  238. int *temp)
  239. {
  240. unsigned int low = 1;
  241. unsigned int high = table.length - 1;
  242. unsigned int mid = (low + high) / 2;
  243. unsigned int num;
  244. unsigned long denom;
  245. WARN_ON(table.length < 2);
  246. switch (table.mode) {
  247. case ADC_DECREMENT:
  248. code &= table.data_mask;
  249. if (code < table.id[high].code)
  250. return -EAGAIN; /* Incorrect reading */
  251. while (low <= high) {
  252. if (code >= table.id[mid].code &&
  253. code < table.id[mid - 1].code)
  254. break;
  255. else if (code < table.id[mid].code)
  256. low = mid + 1;
  257. else
  258. high = mid - 1;
  259. mid = (low + high) / 2;
  260. }
  261. break;
  262. case ADC_INCREMENT:
  263. code &= table.data_mask;
  264. if (code < table.id[low].code)
  265. return -EAGAIN; /* Incorrect reading */
  266. while (low <= high) {
  267. if (code >= table.id[mid - 1].code &&
  268. code < table.id[mid].code)
  269. break;
  270. else if (code > table.id[mid].code)
  271. low = mid + 1;
  272. else
  273. high = mid - 1;
  274. mid = (low + high) / 2;
  275. }
  276. break;
  277. default:
  278. pr_err("Invalid the conversion table\n");
  279. }
  280. /*
  281. * The 5C granularity provided by the table is too much. Let's
  282. * assume that the relationship between sensor readings and
  283. * temperature between 2 table entries is linear and interpolate
  284. * to produce less granular result.
  285. */
  286. num = table.id[mid].temp - v2_code_table[mid - 1].temp;
  287. num *= abs(table.id[mid - 1].code - code);
  288. denom = abs(table.id[mid - 1].code - table.id[mid].code);
  289. *temp = table.id[mid - 1].temp + (num / denom);
  290. return 0;
  291. }
  292. /**
  293. * rk_tsadcv2_initialize - initialize TASDC Controller.
  294. *
  295. * (1) Set TSADC_V2_AUTO_PERIOD:
  296. * Configure the interleave between every two accessing of
  297. * TSADC in normal operation.
  298. *
  299. * (2) Set TSADCV2_AUTO_PERIOD_HT:
  300. * Configure the interleave between every two accessing of
  301. * TSADC after the temperature is higher than COM_SHUT or COM_INT.
  302. *
  303. * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
  304. * If the temperature is higher than COMP_INT or COMP_SHUT for
  305. * "debounce" times, TSADC controller will generate interrupt or TSHUT.
  306. */
  307. static void rk_tsadcv2_initialize(void __iomem *regs,
  308. enum tshut_polarity tshut_polarity)
  309. {
  310. if (tshut_polarity == TSHUT_HIGH_ACTIVE)
  311. writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  312. regs + TSADCV2_AUTO_CON);
  313. else
  314. writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
  315. regs + TSADCV2_AUTO_CON);
  316. writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
  317. writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
  318. regs + TSADCV2_HIGHT_INT_DEBOUNCE);
  319. writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
  320. regs + TSADCV2_AUTO_PERIOD_HT);
  321. writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
  322. regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
  323. }
  324. static void rk_tsadcv2_irq_ack(void __iomem *regs)
  325. {
  326. u32 val;
  327. val = readl_relaxed(regs + TSADCV2_INT_PD);
  328. writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
  329. }
  330. static void rk_tsadcv2_control(void __iomem *regs, bool enable)
  331. {
  332. u32 val;
  333. val = readl_relaxed(regs + TSADCV2_AUTO_CON);
  334. if (enable)
  335. val |= TSADCV2_AUTO_EN;
  336. else
  337. val &= ~TSADCV2_AUTO_EN;
  338. writel_relaxed(val, regs + TSADCV2_AUTO_CON);
  339. }
  340. static int rk_tsadcv2_get_temp(struct chip_tsadc_table table,
  341. int chn, void __iomem *regs, int *temp)
  342. {
  343. u32 val;
  344. val = readl_relaxed(regs + TSADCV2_DATA(chn));
  345. return rk_tsadcv2_code_to_temp(table, val, temp);
  346. }
  347. static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table,
  348. int chn, void __iomem *regs, int temp)
  349. {
  350. u32 tshut_value, val;
  351. tshut_value = rk_tsadcv2_temp_to_code(table, temp);
  352. writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
  353. /* TSHUT will be valid */
  354. val = readl_relaxed(regs + TSADCV2_AUTO_CON);
  355. writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
  356. }
  357. static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
  358. enum tshut_mode mode)
  359. {
  360. u32 val;
  361. val = readl_relaxed(regs + TSADCV2_INT_EN);
  362. if (mode == TSHUT_MODE_GPIO) {
  363. val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
  364. val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
  365. } else {
  366. val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
  367. val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
  368. }
  369. writel_relaxed(val, regs + TSADCV2_INT_EN);
  370. }
  371. static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
  372. .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
  373. .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
  374. .chn_num = 2, /* two channels for tsadc */
  375. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  376. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  377. .tshut_temp = 95000,
  378. .initialize = rk_tsadcv2_initialize,
  379. .irq_ack = rk_tsadcv2_irq_ack,
  380. .control = rk_tsadcv2_control,
  381. .get_temp = rk_tsadcv2_get_temp,
  382. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  383. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  384. .table = {
  385. .id = v2_code_table,
  386. .length = ARRAY_SIZE(v2_code_table),
  387. .data_mask = TSADCV2_DATA_MASK,
  388. .mode = ADC_DECREMENT,
  389. },
  390. };
  391. static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
  392. .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
  393. .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
  394. .chn_num = 2, /* two channels for tsadc */
  395. .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
  396. .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
  397. .tshut_temp = 95000,
  398. .initialize = rk_tsadcv2_initialize,
  399. .irq_ack = rk_tsadcv2_irq_ack,
  400. .control = rk_tsadcv2_control,
  401. .get_temp = rk_tsadcv2_get_temp,
  402. .set_tshut_temp = rk_tsadcv2_tshut_temp,
  403. .set_tshut_mode = rk_tsadcv2_tshut_mode,
  404. .table = {
  405. .id = v3_code_table,
  406. .length = ARRAY_SIZE(v3_code_table),
  407. .data_mask = TSADCV3_DATA_MASK,
  408. .mode = ADC_INCREMENT,
  409. },
  410. };
  411. static const struct of_device_id of_rockchip_thermal_match[] = {
  412. {
  413. .compatible = "rockchip,rk3288-tsadc",
  414. .data = (void *)&rk3288_tsadc_data,
  415. },
  416. {
  417. .compatible = "rockchip,rk3368-tsadc",
  418. .data = (void *)&rk3368_tsadc_data,
  419. },
  420. { /* end */ },
  421. };
  422. MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
  423. static void
  424. rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
  425. {
  426. struct thermal_zone_device *tzd = sensor->tzd;
  427. tzd->ops->set_mode(tzd,
  428. on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
  429. }
  430. static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
  431. {
  432. struct rockchip_thermal_data *thermal = dev;
  433. int i;
  434. dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
  435. thermal->chip->irq_ack(thermal->regs);
  436. for (i = 0; i < thermal->chip->chn_num; i++)
  437. thermal_zone_device_update(thermal->sensors[i].tzd);
  438. return IRQ_HANDLED;
  439. }
  440. static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
  441. {
  442. struct rockchip_thermal_sensor *sensor = _sensor;
  443. struct rockchip_thermal_data *thermal = sensor->thermal;
  444. const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
  445. int retval;
  446. retval = tsadc->get_temp(tsadc->table,
  447. sensor->id, thermal->regs, out_temp);
  448. dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
  449. sensor->id, *out_temp, retval);
  450. return retval;
  451. }
  452. static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
  453. .get_temp = rockchip_thermal_get_temp,
  454. };
  455. static int rockchip_configure_from_dt(struct device *dev,
  456. struct device_node *np,
  457. struct rockchip_thermal_data *thermal)
  458. {
  459. u32 shut_temp, tshut_mode, tshut_polarity;
  460. if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
  461. dev_warn(dev,
  462. "Missing tshut temp property, using default %d\n",
  463. thermal->chip->tshut_temp);
  464. thermal->tshut_temp = thermal->chip->tshut_temp;
  465. } else {
  466. if (shut_temp > INT_MAX) {
  467. dev_err(dev, "Invalid tshut temperature specified: %d\n",
  468. shut_temp);
  469. return -ERANGE;
  470. }
  471. thermal->tshut_temp = shut_temp;
  472. }
  473. if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
  474. dev_warn(dev,
  475. "Missing tshut mode property, using default (%s)\n",
  476. thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
  477. "gpio" : "cru");
  478. thermal->tshut_mode = thermal->chip->tshut_mode;
  479. } else {
  480. thermal->tshut_mode = tshut_mode;
  481. }
  482. if (thermal->tshut_mode > 1) {
  483. dev_err(dev, "Invalid tshut mode specified: %d\n",
  484. thermal->tshut_mode);
  485. return -EINVAL;
  486. }
  487. if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
  488. &tshut_polarity)) {
  489. dev_warn(dev,
  490. "Missing tshut-polarity property, using default (%s)\n",
  491. thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
  492. "low" : "high");
  493. thermal->tshut_polarity = thermal->chip->tshut_polarity;
  494. } else {
  495. thermal->tshut_polarity = tshut_polarity;
  496. }
  497. if (thermal->tshut_polarity > 1) {
  498. dev_err(dev, "Invalid tshut-polarity specified: %d\n",
  499. thermal->tshut_polarity);
  500. return -EINVAL;
  501. }
  502. return 0;
  503. }
  504. static int
  505. rockchip_thermal_register_sensor(struct platform_device *pdev,
  506. struct rockchip_thermal_data *thermal,
  507. struct rockchip_thermal_sensor *sensor,
  508. int id)
  509. {
  510. const struct rockchip_tsadc_chip *tsadc = thermal->chip;
  511. int error;
  512. tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
  513. tsadc->set_tshut_temp(tsadc->table, id, thermal->regs,
  514. thermal->tshut_temp);
  515. sensor->thermal = thermal;
  516. sensor->id = id;
  517. sensor->tzd = thermal_zone_of_sensor_register(&pdev->dev, id, sensor,
  518. &rockchip_of_thermal_ops);
  519. if (IS_ERR(sensor->tzd)) {
  520. error = PTR_ERR(sensor->tzd);
  521. dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
  522. id, error);
  523. return error;
  524. }
  525. return 0;
  526. }
  527. /*
  528. * Reset TSADC Controller, reset all tsadc registers.
  529. */
  530. static void rockchip_thermal_reset_controller(struct reset_control *reset)
  531. {
  532. reset_control_assert(reset);
  533. usleep_range(10, 20);
  534. reset_control_deassert(reset);
  535. }
  536. static int rockchip_thermal_probe(struct platform_device *pdev)
  537. {
  538. struct device_node *np = pdev->dev.of_node;
  539. struct rockchip_thermal_data *thermal;
  540. const struct of_device_id *match;
  541. struct resource *res;
  542. int irq;
  543. int i, j;
  544. int error;
  545. match = of_match_node(of_rockchip_thermal_match, np);
  546. if (!match)
  547. return -ENXIO;
  548. irq = platform_get_irq(pdev, 0);
  549. if (irq < 0) {
  550. dev_err(&pdev->dev, "no irq resource?\n");
  551. return -EINVAL;
  552. }
  553. thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
  554. GFP_KERNEL);
  555. if (!thermal)
  556. return -ENOMEM;
  557. thermal->pdev = pdev;
  558. thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
  559. if (!thermal->chip)
  560. return -EINVAL;
  561. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  562. thermal->regs = devm_ioremap_resource(&pdev->dev, res);
  563. if (IS_ERR(thermal->regs))
  564. return PTR_ERR(thermal->regs);
  565. thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
  566. if (IS_ERR(thermal->reset)) {
  567. error = PTR_ERR(thermal->reset);
  568. dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
  569. return error;
  570. }
  571. thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
  572. if (IS_ERR(thermal->clk)) {
  573. error = PTR_ERR(thermal->clk);
  574. dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
  575. return error;
  576. }
  577. thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
  578. if (IS_ERR(thermal->pclk)) {
  579. error = PTR_ERR(thermal->pclk);
  580. dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
  581. error);
  582. return error;
  583. }
  584. error = clk_prepare_enable(thermal->clk);
  585. if (error) {
  586. dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
  587. error);
  588. return error;
  589. }
  590. error = clk_prepare_enable(thermal->pclk);
  591. if (error) {
  592. dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
  593. goto err_disable_clk;
  594. }
  595. rockchip_thermal_reset_controller(thermal->reset);
  596. error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
  597. if (error) {
  598. dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
  599. error);
  600. goto err_disable_pclk;
  601. }
  602. thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
  603. for (i = 0; i < thermal->chip->chn_num; i++) {
  604. error = rockchip_thermal_register_sensor(pdev, thermal,
  605. &thermal->sensors[i],
  606. thermal->chip->chn_id[i]);
  607. if (error) {
  608. dev_err(&pdev->dev,
  609. "failed to register sensor[%d] : error = %d\n",
  610. i, error);
  611. for (j = 0; j < i; j++)
  612. thermal_zone_of_sensor_unregister(&pdev->dev,
  613. thermal->sensors[j].tzd);
  614. goto err_disable_pclk;
  615. }
  616. }
  617. error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
  618. &rockchip_thermal_alarm_irq_thread,
  619. IRQF_ONESHOT,
  620. "rockchip_thermal", thermal);
  621. if (error) {
  622. dev_err(&pdev->dev,
  623. "failed to request tsadc irq: %d\n", error);
  624. goto err_unregister_sensor;
  625. }
  626. thermal->chip->control(thermal->regs, true);
  627. for (i = 0; i < thermal->chip->chn_num; i++)
  628. rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
  629. platform_set_drvdata(pdev, thermal);
  630. return 0;
  631. err_unregister_sensor:
  632. while (i--)
  633. thermal_zone_of_sensor_unregister(&pdev->dev,
  634. thermal->sensors[i].tzd);
  635. err_disable_pclk:
  636. clk_disable_unprepare(thermal->pclk);
  637. err_disable_clk:
  638. clk_disable_unprepare(thermal->clk);
  639. return error;
  640. }
  641. static int rockchip_thermal_remove(struct platform_device *pdev)
  642. {
  643. struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
  644. int i;
  645. for (i = 0; i < thermal->chip->chn_num; i++) {
  646. struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
  647. rockchip_thermal_toggle_sensor(sensor, false);
  648. thermal_zone_of_sensor_unregister(&pdev->dev, sensor->tzd);
  649. }
  650. thermal->chip->control(thermal->regs, false);
  651. clk_disable_unprepare(thermal->pclk);
  652. clk_disable_unprepare(thermal->clk);
  653. return 0;
  654. }
  655. static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
  656. {
  657. struct platform_device *pdev = to_platform_device(dev);
  658. struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
  659. int i;
  660. for (i = 0; i < thermal->chip->chn_num; i++)
  661. rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
  662. thermal->chip->control(thermal->regs, false);
  663. clk_disable(thermal->pclk);
  664. clk_disable(thermal->clk);
  665. pinctrl_pm_select_sleep_state(dev);
  666. return 0;
  667. }
  668. static int __maybe_unused rockchip_thermal_resume(struct device *dev)
  669. {
  670. struct platform_device *pdev = to_platform_device(dev);
  671. struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
  672. int i;
  673. int error;
  674. error = clk_enable(thermal->clk);
  675. if (error)
  676. return error;
  677. error = clk_enable(thermal->pclk);
  678. if (error)
  679. return error;
  680. rockchip_thermal_reset_controller(thermal->reset);
  681. thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
  682. for (i = 0; i < thermal->chip->chn_num; i++) {
  683. int id = thermal->sensors[i].id;
  684. thermal->chip->set_tshut_mode(id, thermal->regs,
  685. thermal->tshut_mode);
  686. thermal->chip->set_tshut_temp(thermal->chip->table,
  687. id, thermal->regs,
  688. thermal->tshut_temp);
  689. }
  690. thermal->chip->control(thermal->regs, true);
  691. for (i = 0; i < thermal->chip->chn_num; i++)
  692. rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
  693. pinctrl_pm_select_default_state(dev);
  694. return 0;
  695. }
  696. static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
  697. rockchip_thermal_suspend, rockchip_thermal_resume);
  698. static struct platform_driver rockchip_thermal_driver = {
  699. .driver = {
  700. .name = "rockchip-thermal",
  701. .pm = &rockchip_thermal_pm_ops,
  702. .of_match_table = of_rockchip_thermal_match,
  703. },
  704. .probe = rockchip_thermal_probe,
  705. .remove = rockchip_thermal_remove,
  706. };
  707. module_platform_driver(rockchip_thermal_driver);
  708. MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
  709. MODULE_AUTHOR("Rockchip, Inc.");
  710. MODULE_LICENSE("GPL v2");
  711. MODULE_ALIAS("platform:rockchip-thermal");