otg_fsm.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815
  1. /*
  2. * otg_fsm.c - ChipIdea USB IP core OTG FSM driver
  3. *
  4. * Copyright (C) 2014 Freescale Semiconductor, Inc.
  5. *
  6. * Author: Jun Li
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. /*
  13. * This file mainly handles OTG fsm, it includes OTG fsm operations
  14. * for HNP and SRP.
  15. *
  16. * TODO List
  17. * - ADP
  18. * - OTG test device
  19. */
  20. #include <linux/usb/otg.h>
  21. #include <linux/usb/gadget.h>
  22. #include <linux/usb/hcd.h>
  23. #include <linux/usb/chipidea.h>
  24. #include <linux/regulator/consumer.h>
  25. #include "ci.h"
  26. #include "bits.h"
  27. #include "otg.h"
  28. #include "otg_fsm.h"
  29. /* Add for otg: interact with user space app */
  30. static ssize_t
  31. get_a_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  32. {
  33. char *next;
  34. unsigned size, t;
  35. struct ci_hdrc *ci = dev_get_drvdata(dev);
  36. next = buf;
  37. size = PAGE_SIZE;
  38. t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_req);
  39. size -= t;
  40. next += t;
  41. return PAGE_SIZE - size;
  42. }
  43. static ssize_t
  44. set_a_bus_req(struct device *dev, struct device_attribute *attr,
  45. const char *buf, size_t count)
  46. {
  47. struct ci_hdrc *ci = dev_get_drvdata(dev);
  48. if (count > 2)
  49. return -1;
  50. mutex_lock(&ci->fsm.lock);
  51. if (buf[0] == '0') {
  52. ci->fsm.a_bus_req = 0;
  53. } else if (buf[0] == '1') {
  54. /* If a_bus_drop is TRUE, a_bus_req can't be set */
  55. if (ci->fsm.a_bus_drop) {
  56. mutex_unlock(&ci->fsm.lock);
  57. return count;
  58. }
  59. ci->fsm.a_bus_req = 1;
  60. }
  61. ci_otg_queue_work(ci);
  62. mutex_unlock(&ci->fsm.lock);
  63. return count;
  64. }
  65. static DEVICE_ATTR(a_bus_req, S_IRUGO | S_IWUSR, get_a_bus_req, set_a_bus_req);
  66. static ssize_t
  67. get_a_bus_drop(struct device *dev, struct device_attribute *attr, char *buf)
  68. {
  69. char *next;
  70. unsigned size, t;
  71. struct ci_hdrc *ci = dev_get_drvdata(dev);
  72. next = buf;
  73. size = PAGE_SIZE;
  74. t = scnprintf(next, size, "%d\n", ci->fsm.a_bus_drop);
  75. size -= t;
  76. next += t;
  77. return PAGE_SIZE - size;
  78. }
  79. static ssize_t
  80. set_a_bus_drop(struct device *dev, struct device_attribute *attr,
  81. const char *buf, size_t count)
  82. {
  83. struct ci_hdrc *ci = dev_get_drvdata(dev);
  84. if (count > 2)
  85. return -1;
  86. mutex_lock(&ci->fsm.lock);
  87. if (buf[0] == '0') {
  88. ci->fsm.a_bus_drop = 0;
  89. } else if (buf[0] == '1') {
  90. ci->fsm.a_bus_drop = 1;
  91. ci->fsm.a_bus_req = 0;
  92. }
  93. ci_otg_queue_work(ci);
  94. mutex_unlock(&ci->fsm.lock);
  95. return count;
  96. }
  97. static DEVICE_ATTR(a_bus_drop, S_IRUGO | S_IWUSR, get_a_bus_drop,
  98. set_a_bus_drop);
  99. static ssize_t
  100. get_b_bus_req(struct device *dev, struct device_attribute *attr, char *buf)
  101. {
  102. char *next;
  103. unsigned size, t;
  104. struct ci_hdrc *ci = dev_get_drvdata(dev);
  105. next = buf;
  106. size = PAGE_SIZE;
  107. t = scnprintf(next, size, "%d\n", ci->fsm.b_bus_req);
  108. size -= t;
  109. next += t;
  110. return PAGE_SIZE - size;
  111. }
  112. static ssize_t
  113. set_b_bus_req(struct device *dev, struct device_attribute *attr,
  114. const char *buf, size_t count)
  115. {
  116. struct ci_hdrc *ci = dev_get_drvdata(dev);
  117. if (count > 2)
  118. return -1;
  119. mutex_lock(&ci->fsm.lock);
  120. if (buf[0] == '0')
  121. ci->fsm.b_bus_req = 0;
  122. else if (buf[0] == '1')
  123. ci->fsm.b_bus_req = 1;
  124. ci_otg_queue_work(ci);
  125. mutex_unlock(&ci->fsm.lock);
  126. return count;
  127. }
  128. static DEVICE_ATTR(b_bus_req, S_IRUGO | S_IWUSR, get_b_bus_req, set_b_bus_req);
  129. static ssize_t
  130. set_a_clr_err(struct device *dev, struct device_attribute *attr,
  131. const char *buf, size_t count)
  132. {
  133. struct ci_hdrc *ci = dev_get_drvdata(dev);
  134. if (count > 2)
  135. return -1;
  136. mutex_lock(&ci->fsm.lock);
  137. if (buf[0] == '1')
  138. ci->fsm.a_clr_err = 1;
  139. ci_otg_queue_work(ci);
  140. mutex_unlock(&ci->fsm.lock);
  141. return count;
  142. }
  143. static DEVICE_ATTR(a_clr_err, S_IWUSR, NULL, set_a_clr_err);
  144. static struct attribute *inputs_attrs[] = {
  145. &dev_attr_a_bus_req.attr,
  146. &dev_attr_a_bus_drop.attr,
  147. &dev_attr_b_bus_req.attr,
  148. &dev_attr_a_clr_err.attr,
  149. NULL,
  150. };
  151. static struct attribute_group inputs_attr_group = {
  152. .name = "inputs",
  153. .attrs = inputs_attrs,
  154. };
  155. /*
  156. * Keep this list in the same order as timers indexed
  157. * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h
  158. */
  159. static unsigned otg_timer_ms[] = {
  160. TA_WAIT_VRISE,
  161. TA_WAIT_VFALL,
  162. TA_WAIT_BCON,
  163. TA_AIDL_BDIS,
  164. TB_ASE0_BRST,
  165. TA_BIDL_ADIS,
  166. TB_SE0_SRP,
  167. TB_SRP_FAIL,
  168. 0,
  169. TB_DATA_PLS,
  170. TB_SSEND_SRP,
  171. };
  172. /*
  173. * Add timer to active timer list
  174. */
  175. static void ci_otg_add_timer(struct ci_hdrc *ci, enum otg_fsm_timer t)
  176. {
  177. unsigned long flags, timer_sec, timer_nsec;
  178. if (t >= NUM_OTG_FSM_TIMERS)
  179. return;
  180. spin_lock_irqsave(&ci->lock, flags);
  181. timer_sec = otg_timer_ms[t] / MSEC_PER_SEC;
  182. timer_nsec = (otg_timer_ms[t] % MSEC_PER_SEC) * NSEC_PER_MSEC;
  183. ci->hr_timeouts[t] = ktime_add(ktime_get(),
  184. ktime_set(timer_sec, timer_nsec));
  185. ci->enabled_otg_timer_bits |= (1 << t);
  186. if ((ci->next_otg_timer == NUM_OTG_FSM_TIMERS) ||
  187. (ci->hr_timeouts[ci->next_otg_timer].tv64 >
  188. ci->hr_timeouts[t].tv64)) {
  189. ci->next_otg_timer = t;
  190. hrtimer_start_range_ns(&ci->otg_fsm_hrtimer,
  191. ci->hr_timeouts[t], NSEC_PER_MSEC,
  192. HRTIMER_MODE_ABS);
  193. }
  194. spin_unlock_irqrestore(&ci->lock, flags);
  195. }
  196. /*
  197. * Remove timer from active timer list
  198. */
  199. static void ci_otg_del_timer(struct ci_hdrc *ci, enum otg_fsm_timer t)
  200. {
  201. unsigned long flags, enabled_timer_bits;
  202. enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS;
  203. if ((t >= NUM_OTG_FSM_TIMERS) ||
  204. !(ci->enabled_otg_timer_bits & (1 << t)))
  205. return;
  206. spin_lock_irqsave(&ci->lock, flags);
  207. ci->enabled_otg_timer_bits &= ~(1 << t);
  208. if (ci->next_otg_timer == t) {
  209. if (ci->enabled_otg_timer_bits == 0) {
  210. /* No enabled timers after delete it */
  211. hrtimer_cancel(&ci->otg_fsm_hrtimer);
  212. ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
  213. } else {
  214. /* Find the next timer */
  215. enabled_timer_bits = ci->enabled_otg_timer_bits;
  216. for_each_set_bit(cur_timer, &enabled_timer_bits,
  217. NUM_OTG_FSM_TIMERS) {
  218. if ((next_timer == NUM_OTG_FSM_TIMERS) ||
  219. (ci->hr_timeouts[next_timer].tv64 <
  220. ci->hr_timeouts[cur_timer].tv64))
  221. next_timer = cur_timer;
  222. }
  223. }
  224. }
  225. if (next_timer != NUM_OTG_FSM_TIMERS) {
  226. ci->next_otg_timer = next_timer;
  227. hrtimer_start_range_ns(&ci->otg_fsm_hrtimer,
  228. ci->hr_timeouts[next_timer], NSEC_PER_MSEC,
  229. HRTIMER_MODE_ABS);
  230. }
  231. spin_unlock_irqrestore(&ci->lock, flags);
  232. }
  233. /* OTG FSM timer handlers */
  234. static int a_wait_vrise_tmout(struct ci_hdrc *ci)
  235. {
  236. ci->fsm.a_wait_vrise_tmout = 1;
  237. return 0;
  238. }
  239. static int a_wait_vfall_tmout(struct ci_hdrc *ci)
  240. {
  241. ci->fsm.a_wait_vfall_tmout = 1;
  242. return 0;
  243. }
  244. static int a_wait_bcon_tmout(struct ci_hdrc *ci)
  245. {
  246. ci->fsm.a_wait_bcon_tmout = 1;
  247. return 0;
  248. }
  249. static int a_aidl_bdis_tmout(struct ci_hdrc *ci)
  250. {
  251. ci->fsm.a_aidl_bdis_tmout = 1;
  252. return 0;
  253. }
  254. static int b_ase0_brst_tmout(struct ci_hdrc *ci)
  255. {
  256. ci->fsm.b_ase0_brst_tmout = 1;
  257. return 0;
  258. }
  259. static int a_bidl_adis_tmout(struct ci_hdrc *ci)
  260. {
  261. ci->fsm.a_bidl_adis_tmout = 1;
  262. return 0;
  263. }
  264. static int b_se0_srp_tmout(struct ci_hdrc *ci)
  265. {
  266. ci->fsm.b_se0_srp = 1;
  267. return 0;
  268. }
  269. static int b_srp_fail_tmout(struct ci_hdrc *ci)
  270. {
  271. ci->fsm.b_srp_done = 1;
  272. return 1;
  273. }
  274. static int b_data_pls_tmout(struct ci_hdrc *ci)
  275. {
  276. ci->fsm.b_srp_done = 1;
  277. ci->fsm.b_bus_req = 0;
  278. if (ci->fsm.power_up)
  279. ci->fsm.power_up = 0;
  280. hw_write_otgsc(ci, OTGSC_HABA, 0);
  281. pm_runtime_put(ci->dev);
  282. return 0;
  283. }
  284. static int b_ssend_srp_tmout(struct ci_hdrc *ci)
  285. {
  286. ci->fsm.b_ssend_srp = 1;
  287. /* only vbus fall below B_sess_vld in b_idle state */
  288. if (ci->fsm.otg->state == OTG_STATE_B_IDLE)
  289. return 0;
  290. else
  291. return 1;
  292. }
  293. /*
  294. * Keep this list in the same order as timers indexed
  295. * by enum otg_fsm_timer in include/linux/usb/otg-fsm.h
  296. */
  297. static int (*otg_timer_handlers[])(struct ci_hdrc *) = {
  298. a_wait_vrise_tmout, /* A_WAIT_VRISE */
  299. a_wait_vfall_tmout, /* A_WAIT_VFALL */
  300. a_wait_bcon_tmout, /* A_WAIT_BCON */
  301. a_aidl_bdis_tmout, /* A_AIDL_BDIS */
  302. b_ase0_brst_tmout, /* B_ASE0_BRST */
  303. a_bidl_adis_tmout, /* A_BIDL_ADIS */
  304. b_se0_srp_tmout, /* B_SE0_SRP */
  305. b_srp_fail_tmout, /* B_SRP_FAIL */
  306. NULL, /* A_WAIT_ENUM */
  307. b_data_pls_tmout, /* B_DATA_PLS */
  308. b_ssend_srp_tmout, /* B_SSEND_SRP */
  309. };
  310. /*
  311. * Enable the next nearest enabled timer if have
  312. */
  313. static enum hrtimer_restart ci_otg_hrtimer_func(struct hrtimer *t)
  314. {
  315. struct ci_hdrc *ci = container_of(t, struct ci_hdrc, otg_fsm_hrtimer);
  316. ktime_t now, *timeout;
  317. unsigned long enabled_timer_bits;
  318. unsigned long flags;
  319. enum otg_fsm_timer cur_timer, next_timer = NUM_OTG_FSM_TIMERS;
  320. int ret = -EINVAL;
  321. spin_lock_irqsave(&ci->lock, flags);
  322. enabled_timer_bits = ci->enabled_otg_timer_bits;
  323. ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
  324. now = ktime_get();
  325. for_each_set_bit(cur_timer, &enabled_timer_bits, NUM_OTG_FSM_TIMERS) {
  326. if (now.tv64 >= ci->hr_timeouts[cur_timer].tv64) {
  327. ci->enabled_otg_timer_bits &= ~(1 << cur_timer);
  328. if (otg_timer_handlers[cur_timer])
  329. ret = otg_timer_handlers[cur_timer](ci);
  330. } else {
  331. if ((next_timer == NUM_OTG_FSM_TIMERS) ||
  332. (ci->hr_timeouts[cur_timer].tv64 <
  333. ci->hr_timeouts[next_timer].tv64))
  334. next_timer = cur_timer;
  335. }
  336. }
  337. /* Enable the next nearest timer */
  338. if (next_timer < NUM_OTG_FSM_TIMERS) {
  339. timeout = &ci->hr_timeouts[next_timer];
  340. hrtimer_start_range_ns(&ci->otg_fsm_hrtimer, *timeout,
  341. NSEC_PER_MSEC, HRTIMER_MODE_ABS);
  342. ci->next_otg_timer = next_timer;
  343. }
  344. spin_unlock_irqrestore(&ci->lock, flags);
  345. if (!ret)
  346. ci_otg_queue_work(ci);
  347. return HRTIMER_NORESTART;
  348. }
  349. /* Initialize timers */
  350. static int ci_otg_init_timers(struct ci_hdrc *ci)
  351. {
  352. hrtimer_init(&ci->otg_fsm_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_ABS);
  353. ci->otg_fsm_hrtimer.function = ci_otg_hrtimer_func;
  354. return 0;
  355. }
  356. /* -------------------------------------------------------------*/
  357. /* Operations that will be called from OTG Finite State Machine */
  358. /* -------------------------------------------------------------*/
  359. static void ci_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
  360. {
  361. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  362. if (t < NUM_OTG_FSM_TIMERS)
  363. ci_otg_add_timer(ci, t);
  364. return;
  365. }
  366. static void ci_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
  367. {
  368. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  369. if (t < NUM_OTG_FSM_TIMERS)
  370. ci_otg_del_timer(ci, t);
  371. return;
  372. }
  373. /*
  374. * A-device drive vbus: turn on vbus regulator and enable port power
  375. * Data pulse irq should be disabled while vbus is on.
  376. */
  377. static void ci_otg_drv_vbus(struct otg_fsm *fsm, int on)
  378. {
  379. int ret;
  380. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  381. if (on) {
  382. /* Enable power power */
  383. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
  384. PORTSC_PP);
  385. if (ci->platdata->reg_vbus) {
  386. ret = regulator_enable(ci->platdata->reg_vbus);
  387. if (ret) {
  388. dev_err(ci->dev,
  389. "Failed to enable vbus regulator, ret=%d\n",
  390. ret);
  391. return;
  392. }
  393. }
  394. /* Disable data pulse irq */
  395. hw_write_otgsc(ci, OTGSC_DPIE, 0);
  396. fsm->a_srp_det = 0;
  397. fsm->power_up = 0;
  398. } else {
  399. if (ci->platdata->reg_vbus)
  400. regulator_disable(ci->platdata->reg_vbus);
  401. fsm->a_bus_drop = 1;
  402. fsm->a_bus_req = 0;
  403. }
  404. }
  405. /*
  406. * Control data line by Run Stop bit.
  407. */
  408. static void ci_otg_loc_conn(struct otg_fsm *fsm, int on)
  409. {
  410. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  411. if (on)
  412. hw_write(ci, OP_USBCMD, USBCMD_RS, USBCMD_RS);
  413. else
  414. hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
  415. }
  416. /*
  417. * Generate SOF by host.
  418. * This is controlled through suspend/resume the port.
  419. * In host mode, controller will automatically send SOF.
  420. * Suspend will block the data on the port.
  421. */
  422. static void ci_otg_loc_sof(struct otg_fsm *fsm, int on)
  423. {
  424. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  425. if (on)
  426. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_FPR,
  427. PORTSC_FPR);
  428. else
  429. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_SUSP,
  430. PORTSC_SUSP);
  431. }
  432. /*
  433. * Start SRP pulsing by data-line pulsing,
  434. * no v-bus pulsing followed
  435. */
  436. static void ci_otg_start_pulse(struct otg_fsm *fsm)
  437. {
  438. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  439. /* Hardware Assistant Data pulse */
  440. hw_write_otgsc(ci, OTGSC_HADP, OTGSC_HADP);
  441. pm_runtime_get(ci->dev);
  442. ci_otg_add_timer(ci, B_DATA_PLS);
  443. }
  444. static int ci_otg_start_host(struct otg_fsm *fsm, int on)
  445. {
  446. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  447. if (on) {
  448. ci_role_stop(ci);
  449. ci_role_start(ci, CI_ROLE_HOST);
  450. } else {
  451. ci_role_stop(ci);
  452. ci_role_start(ci, CI_ROLE_GADGET);
  453. }
  454. return 0;
  455. }
  456. static int ci_otg_start_gadget(struct otg_fsm *fsm, int on)
  457. {
  458. struct ci_hdrc *ci = container_of(fsm, struct ci_hdrc, fsm);
  459. if (on)
  460. usb_gadget_vbus_connect(&ci->gadget);
  461. else
  462. usb_gadget_vbus_disconnect(&ci->gadget);
  463. return 0;
  464. }
  465. static struct otg_fsm_ops ci_otg_ops = {
  466. .drv_vbus = ci_otg_drv_vbus,
  467. .loc_conn = ci_otg_loc_conn,
  468. .loc_sof = ci_otg_loc_sof,
  469. .start_pulse = ci_otg_start_pulse,
  470. .add_timer = ci_otg_fsm_add_timer,
  471. .del_timer = ci_otg_fsm_del_timer,
  472. .start_host = ci_otg_start_host,
  473. .start_gadget = ci_otg_start_gadget,
  474. };
  475. int ci_otg_fsm_work(struct ci_hdrc *ci)
  476. {
  477. /*
  478. * Don't do fsm transition for B device
  479. * when there is no gadget class driver
  480. */
  481. if (ci->fsm.id && !(ci->driver) &&
  482. ci->fsm.otg->state < OTG_STATE_A_IDLE)
  483. return 0;
  484. pm_runtime_get_sync(ci->dev);
  485. if (otg_statemachine(&ci->fsm)) {
  486. if (ci->fsm.otg->state == OTG_STATE_A_IDLE) {
  487. /*
  488. * Further state change for cases:
  489. * a_idle to b_idle; or
  490. * a_idle to a_wait_vrise due to ID change(1->0), so
  491. * B-dev becomes A-dev can try to start new session
  492. * consequently; or
  493. * a_idle to a_wait_vrise when power up
  494. */
  495. if ((ci->fsm.id) || (ci->id_event) ||
  496. (ci->fsm.power_up)) {
  497. ci_otg_queue_work(ci);
  498. } else {
  499. /* Enable data pulse irq */
  500. hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS |
  501. PORTSC_PP, 0);
  502. hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
  503. hw_write_otgsc(ci, OTGSC_DPIE, OTGSC_DPIE);
  504. }
  505. if (ci->id_event)
  506. ci->id_event = false;
  507. } else if (ci->fsm.otg->state == OTG_STATE_B_IDLE) {
  508. if (ci->fsm.b_sess_vld) {
  509. ci->fsm.power_up = 0;
  510. /*
  511. * Further transite to b_periphearl state
  512. * when register gadget driver with vbus on
  513. */
  514. ci_otg_queue_work(ci);
  515. }
  516. } else if (ci->fsm.otg->state == OTG_STATE_A_HOST) {
  517. pm_runtime_mark_last_busy(ci->dev);
  518. pm_runtime_put_autosuspend(ci->dev);
  519. return 0;
  520. }
  521. }
  522. pm_runtime_put_sync(ci->dev);
  523. return 0;
  524. }
  525. /*
  526. * Update fsm variables in each state if catching expected interrupts,
  527. * called by otg fsm isr.
  528. */
  529. static void ci_otg_fsm_event(struct ci_hdrc *ci)
  530. {
  531. u32 intr_sts, otg_bsess_vld, port_conn;
  532. struct otg_fsm *fsm = &ci->fsm;
  533. intr_sts = hw_read_intr_status(ci);
  534. otg_bsess_vld = hw_read_otgsc(ci, OTGSC_BSV);
  535. port_conn = hw_read(ci, OP_PORTSC, PORTSC_CCS);
  536. switch (ci->fsm.otg->state) {
  537. case OTG_STATE_A_WAIT_BCON:
  538. if (port_conn) {
  539. fsm->b_conn = 1;
  540. fsm->a_bus_req = 1;
  541. ci_otg_queue_work(ci);
  542. }
  543. break;
  544. case OTG_STATE_B_IDLE:
  545. if (otg_bsess_vld && (intr_sts & USBi_PCI) && port_conn) {
  546. fsm->b_sess_vld = 1;
  547. ci_otg_queue_work(ci);
  548. }
  549. break;
  550. case OTG_STATE_B_PERIPHERAL:
  551. if ((intr_sts & USBi_SLI) && port_conn && otg_bsess_vld) {
  552. fsm->a_bus_suspend = 1;
  553. ci_otg_queue_work(ci);
  554. } else if (intr_sts & USBi_PCI) {
  555. if (fsm->a_bus_suspend == 1)
  556. fsm->a_bus_suspend = 0;
  557. }
  558. break;
  559. case OTG_STATE_B_HOST:
  560. if ((intr_sts & USBi_PCI) && !port_conn) {
  561. fsm->a_conn = 0;
  562. fsm->b_bus_req = 0;
  563. ci_otg_queue_work(ci);
  564. }
  565. break;
  566. case OTG_STATE_A_PERIPHERAL:
  567. if (intr_sts & USBi_SLI) {
  568. fsm->b_bus_suspend = 1;
  569. /*
  570. * Init a timer to know how long this suspend
  571. * will continue, if time out, indicates B no longer
  572. * wants to be host role
  573. */
  574. ci_otg_add_timer(ci, A_BIDL_ADIS);
  575. }
  576. if (intr_sts & USBi_URI)
  577. ci_otg_del_timer(ci, A_BIDL_ADIS);
  578. if (intr_sts & USBi_PCI) {
  579. if (fsm->b_bus_suspend == 1) {
  580. ci_otg_del_timer(ci, A_BIDL_ADIS);
  581. fsm->b_bus_suspend = 0;
  582. }
  583. }
  584. break;
  585. case OTG_STATE_A_SUSPEND:
  586. if ((intr_sts & USBi_PCI) && !port_conn) {
  587. fsm->b_conn = 0;
  588. /* if gadget driver is binded */
  589. if (ci->driver) {
  590. /* A device to be peripheral mode */
  591. ci->gadget.is_a_peripheral = 1;
  592. }
  593. ci_otg_queue_work(ci);
  594. }
  595. break;
  596. case OTG_STATE_A_HOST:
  597. if ((intr_sts & USBi_PCI) && !port_conn) {
  598. fsm->b_conn = 0;
  599. ci_otg_queue_work(ci);
  600. }
  601. break;
  602. case OTG_STATE_B_WAIT_ACON:
  603. if ((intr_sts & USBi_PCI) && port_conn) {
  604. fsm->a_conn = 1;
  605. ci_otg_queue_work(ci);
  606. }
  607. break;
  608. default:
  609. break;
  610. }
  611. }
  612. /*
  613. * ci_otg_irq - otg fsm related irq handling
  614. * and also update otg fsm variable by monitoring usb host and udc
  615. * state change interrupts.
  616. * @ci: ci_hdrc
  617. */
  618. irqreturn_t ci_otg_fsm_irq(struct ci_hdrc *ci)
  619. {
  620. irqreturn_t retval = IRQ_NONE;
  621. u32 otgsc, otg_int_src = 0;
  622. struct otg_fsm *fsm = &ci->fsm;
  623. otgsc = hw_read_otgsc(ci, ~0);
  624. otg_int_src = otgsc & OTGSC_INT_STATUS_BITS & (otgsc >> 8);
  625. fsm->id = (otgsc & OTGSC_ID) ? 1 : 0;
  626. if (otg_int_src) {
  627. if (otg_int_src & OTGSC_DPIS) {
  628. hw_write_otgsc(ci, OTGSC_DPIS, OTGSC_DPIS);
  629. fsm->a_srp_det = 1;
  630. fsm->a_bus_drop = 0;
  631. } else if (otg_int_src & OTGSC_IDIS) {
  632. hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
  633. if (fsm->id == 0) {
  634. fsm->a_bus_drop = 0;
  635. fsm->a_bus_req = 1;
  636. ci->id_event = true;
  637. }
  638. } else if (otg_int_src & OTGSC_BSVIS) {
  639. hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
  640. if (otgsc & OTGSC_BSV) {
  641. fsm->b_sess_vld = 1;
  642. ci_otg_del_timer(ci, B_SSEND_SRP);
  643. ci_otg_del_timer(ci, B_SRP_FAIL);
  644. fsm->b_ssend_srp = 0;
  645. } else {
  646. fsm->b_sess_vld = 0;
  647. if (fsm->id)
  648. ci_otg_add_timer(ci, B_SSEND_SRP);
  649. }
  650. } else if (otg_int_src & OTGSC_AVVIS) {
  651. hw_write_otgsc(ci, OTGSC_AVVIS, OTGSC_AVVIS);
  652. if (otgsc & OTGSC_AVV) {
  653. fsm->a_vbus_vld = 1;
  654. } else {
  655. fsm->a_vbus_vld = 0;
  656. fsm->b_conn = 0;
  657. }
  658. }
  659. ci_otg_queue_work(ci);
  660. return IRQ_HANDLED;
  661. }
  662. ci_otg_fsm_event(ci);
  663. return retval;
  664. }
  665. void ci_hdrc_otg_fsm_start(struct ci_hdrc *ci)
  666. {
  667. ci_otg_queue_work(ci);
  668. }
  669. int ci_hdrc_otg_fsm_init(struct ci_hdrc *ci)
  670. {
  671. int retval = 0;
  672. if (ci->phy)
  673. ci->otg.phy = ci->phy;
  674. else
  675. ci->otg.usb_phy = ci->usb_phy;
  676. ci->otg.gadget = &ci->gadget;
  677. ci->fsm.otg = &ci->otg;
  678. ci->fsm.power_up = 1;
  679. ci->fsm.id = hw_read_otgsc(ci, OTGSC_ID) ? 1 : 0;
  680. ci->fsm.otg->state = OTG_STATE_UNDEFINED;
  681. ci->fsm.ops = &ci_otg_ops;
  682. mutex_init(&ci->fsm.lock);
  683. retval = ci_otg_init_timers(ci);
  684. if (retval) {
  685. dev_err(ci->dev, "Couldn't init OTG timers\n");
  686. return retval;
  687. }
  688. ci->enabled_otg_timer_bits = 0;
  689. ci->next_otg_timer = NUM_OTG_FSM_TIMERS;
  690. retval = sysfs_create_group(&ci->dev->kobj, &inputs_attr_group);
  691. if (retval < 0) {
  692. dev_dbg(ci->dev,
  693. "Can't register sysfs attr group: %d\n", retval);
  694. return retval;
  695. }
  696. /* Enable A vbus valid irq */
  697. hw_write_otgsc(ci, OTGSC_AVVIE, OTGSC_AVVIE);
  698. if (ci->fsm.id) {
  699. ci->fsm.b_ssend_srp =
  700. hw_read_otgsc(ci, OTGSC_BSV) ? 0 : 1;
  701. ci->fsm.b_sess_vld =
  702. hw_read_otgsc(ci, OTGSC_BSV) ? 1 : 0;
  703. /* Enable BSV irq */
  704. hw_write_otgsc(ci, OTGSC_BSVIE, OTGSC_BSVIE);
  705. }
  706. return 0;
  707. }
  708. void ci_hdrc_otg_fsm_remove(struct ci_hdrc *ci)
  709. {
  710. sysfs_remove_group(&ci->dev->kobj, &inputs_attr_group);
  711. }